Lines Matching refs:rdn
145 int rdn[4];
602 cvmx_nand_state[chip].rdn[0] = 0;
603 cvmx_nand_state[chip].rdn[1] = 6; /* Trp, RE# pulse width*/
604 cvmx_nand_state[chip].rdn[2] = 7; /* Treh, RE# high hold time */
605 cvmx_nand_state[chip].rdn[3] = 0;
836 * @param rdn
841 cvmx_nand_status_t cvmx_nand_set_timing(int chip, int tim_mult, int tim_par[8], int clen[4], int alen[4], int rdn[4], int wrn[2])
859 cvmx_nand_state[chip].rdn[i] = rdn[i];
1283 cmd.rd.rdn1 = cvmx_nand_state[chip].rdn[0];
1284 cmd.rd.rdn2 = cvmx_nand_state[chip].rdn[1];
1285 cmd.rd.rdn3 = cvmx_nand_state[chip].rdn[2];
1286 cmd.rd.rdn4 = cvmx_nand_state[chip].rdn[3];