contrib/octeon-sdk/cvmx-nand.c

415     cvmx_nand_cmd_t cmd;
420     memset(&cmd,  0,  sizeof(cmd));
421     cmd.wait.two = 2;
422     cmd.wait.r_b=0;
423     cmd.wait.n = 2;
430     if (cvmx_nand_submit(cmd))
432     if (cvmx_nand_submit(cmd))
434     if (cvmx_nand_submit(cmd))
436     if (cvmx_nand_submit(cmd))
438     cmd.wait.r_b=1; /* Now wait for busy to be de-asserted */
439     if (cvmx_nand_submit(cmd))
887  * @param cmd    Command to submit
891 cvmx_nand_status_t cvmx_nand_submit(cvmx_nand_cmd_t cmd)
894     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)cmd.u64[0]);
895     CVMX_NAND_LOG_PARAM("0x%llx", (ULL)cmd.u64[1]);
896     CVMX_NAND_LOG_PARAM("%s", cvmx_nand_opcode_labels[cmd.s.op_code]);
897     switch (cmd.s.op_code)
911             cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[1]);
915             if (cmd.ale.adr_byte_num < 5)
919                 cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[1]);
926                 cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[1]);
927                 cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[0]);
934             cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[1]);
935             cvmx_write_csr(CVMX_NDF_CMD, cmd.u64[0]);
1010     cvmx_nand_cmd_t cmd;
1015     memset(&cmd,  0,  sizeof(cmd));
1016     cmd.set_tm_par.one = 1;
1017     cmd.set_tm_par.tim_mult = cvmx_nand_state[chip].tim_mult;
1019     cmd.set_tm_par.tim_par1 = cvmx_nand_state[chip].tim_par[1];
1020     cmd.set_tm_par.tim_par2 = cvmx_nand_state[chip].tim_par[2];
1021     cmd.set_tm_par.tim_par3 = cvmx_nand_state[chip].tim_par[3];
1022     cmd.set_tm_par.tim_par4 = cvmx_nand_state[chip].tim_par[4];
1023     cmd.set_tm_par.tim_par5 = cvmx_nand_state[chip].tim_par[5];
1024     cmd.set_tm_par.tim_par6 = cvmx_nand_state[chip].tim_par[6];
1025     cmd.set_tm_par.tim_par7 = cvmx_nand_state[chip].tim_par[7];
1026     result = cvmx_nand_submit(cmd);
1031     memset(&cmd,  0,  sizeof(cmd));
1032     cmd.bus_acq.fifteen = 15;
1033     cmd.bus_acq.one = 1;
1034     result = cvmx_nand_submit(cmd);
1039     memset(&cmd,  0,  sizeof(cmd));
1040     cmd.chip_en.chip = chip;
1041     cmd.chip_en.one = 1;
1042     cmd.chip_en.three = 3;
1043     cmd.chip_en.width = (cvmx_nand_state[chip].flags & CVMX_NAND_STATE_16BIT) ? 2 : 1;
1044     result = cvmx_nand_submit(cmd);
1053     memset(&cmd,  0,  sizeof(cmd));
1054     cmd.wait.two = 2;
1055     cmd.wait.n = 1;
1056     if (cvmx_nand_submit(cmd))
1060     memset(&cmd,  0,  sizeof(cmd));
1061     cmd.cle.cmd_data = cmd_data;
1062     cmd.cle.clen1 = cvmx_nand_state[chip].clen[0];
1063     cmd.cle.clen2 = cvmx_nand_state[chip].clen[1];
1064     cmd.cle.clen3 = cvmx_nand_state[chip].clen[2];
1065     cmd.cle.four = 4;
1066     result = cvmx_nand_submit(cmd);
1073         memset(&cmd,  0,  sizeof(cmd));
1074         cmd.ale.adr_byte_num = num_address_cycles;
1077             cmd.ale.adr_bytes_l = nand_address;
1078             cmd.ale.adr_bytes_h = nand_address >> 32;
1086             cmd.ale.adr_bytes_l = column + (row << column_shift);
1087             cmd.ale.adr_bytes_h = row >> (32 - column_shift);
1089         cmd.ale.alen1 = cvmx_nand_state[chip].alen[0];
1090         cmd.ale.alen2 = cvmx_nand_state[chip].alen[1];
1091         cmd.ale.alen3 = cvmx_nand_state[chip].alen[2];
1092         cmd.ale.alen4 = cvmx_nand_state[chip].alen[3];
1093         cmd.ale.five = 5;
1094         result = cvmx_nand_submit(cmd);
1102         memset(&cmd,  0,  sizeof(cmd));
1103         cmd.cle.cmd_data = cmd_data2;
1104         cmd.cle.clen1 = cvmx_nand_state[chip].clen[0];
1105         cmd.cle.clen2 = cvmx_nand_state[chip].clen[1];
1106         cmd.cle.clen3 = cvmx_nand_state[chip].clen[2];
1107         cmd.cle.four = 4;
1108         result = cvmx_nand_submit(cmd);
1125     cvmx_nand_cmd_t cmd;
1130     memset(&cmd,  0,  sizeof(cmd));
1131     cmd.chip_dis.three = 3;
1132     result = cvmx_nand_submit(cmd);
1137     memset(&cmd,  0,  sizeof(cmd));
1138     cmd.bus_rel.fifteen = 15;
1139     result = cvmx_nand_submit(cmd);
1232     cvmx_nand_cmd_t cmd;
1268     memset(&cmd,  0,  sizeof(cmd));
1269     cmd.wait.two = 2;
1270     cmd.wait.n=4;
1271     if (cvmx_nand_submit(cmd))
1273     if (cvmx_nand_submit(cmd))
1277     memset(&cmd,  0,  sizeof(cmd));
1278     cmd.rd.data_bytes = buffer_length;
1280         cmd.rd.nine = 10;  /* READ_EDO command is required for ONFI timing modes 4 and 5 */
1282         cmd.rd.nine = 9;
1283     cmd.rd.rdn1 = cvmx_nand_state[chip].rdn[0];
1284     cmd.rd.rdn2 = cvmx_nand_state[chip].rdn[1];
1285     cmd.rd.rdn3 = cvmx_nand_state[chip].rdn[2];
1286     cmd.rd.rdn4 = cvmx_nand_state[chip].rdn[3];
1287     if (cvmx_nand_submit(cmd))
1375     cvmx_nand_cmd_t cmd;
1410     memset(&cmd,  0,  sizeof(cmd));
1411     cmd.wr.data_bytes = buffer_length;
1412     cmd.wr.eight = 8;
1413     cmd.wr.wrn1 = cvmx_nand_state[chip].wrn[0];
1414     cmd.wr.wrn2 = cvmx_nand_state[chip].wrn[1];
1415     if (cvmx_nand_submit(cmd))
1419     memset(&cmd,  0,  sizeof(cmd));
1420     cmd.cle.cmd_data = NAND_COMMAND_PROGRAM_FIN;
1421     cmd.cle.clen1 = cvmx_nand_state[chip].clen[0];
1422     cmd.cle.clen2 = cvmx_nand_state[chip].clen[1];
1423     cmd.cle.clen3 = cvmx_nand_state[chip].clen[2];
1424     cmd.cle.four = 4;
1425     if (cvmx_nand_submit(cmd))