contrib/octeon-sdk/cvmx-mixx-defs.h

56 static inline uint64_t CVMX_MIXX_BIST(unsigned long offset)
59 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
60 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
61 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
62 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
63 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
64 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
65 		cvmx_warn("CVMX_MIXX_BIST(%lu) is invalid on this chip\n", offset);
66 	return CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048;
69 #define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048)
72 static inline uint64_t CVMX_MIXX_CTL(unsigned long offset)
75 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
76 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
77 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
78 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
79 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
80 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
81 		cvmx_warn("CVMX_MIXX_CTL(%lu) is invalid on this chip\n", offset);
82 	return CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048;
85 #define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048)
88 static inline uint64_t CVMX_MIXX_INTENA(unsigned long offset)
91 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
92 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
93 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
94 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
95 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
96 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
97 		cvmx_warn("CVMX_MIXX_INTENA(%lu) is invalid on this chip\n", offset);
98 	return CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048;
101 #define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048)
104 static inline uint64_t CVMX_MIXX_IRCNT(unsigned long offset)
107 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
108 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
109 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
110 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
111 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
112 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
113 		cvmx_warn("CVMX_MIXX_IRCNT(%lu) is invalid on this chip\n", offset);
114 	return CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048;
117 #define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048)
120 static inline uint64_t CVMX_MIXX_IRHWM(unsigned long offset)
123 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
124 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
125 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
126 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
127 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
128 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
129 		cvmx_warn("CVMX_MIXX_IRHWM(%lu) is invalid on this chip\n", offset);
130 	return CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048;
133 #define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048)
136 static inline uint64_t CVMX_MIXX_IRING1(unsigned long offset)
139 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
140 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
141 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
142 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
143 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
144 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
145 		cvmx_warn("CVMX_MIXX_IRING1(%lu) is invalid on this chip\n", offset);
146 	return CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048;
149 #define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048)
152 static inline uint64_t CVMX_MIXX_IRING2(unsigned long offset)
155 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
156 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
157 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
158 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
159 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
160 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
161 		cvmx_warn("CVMX_MIXX_IRING2(%lu) is invalid on this chip\n", offset);
162 	return CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048;
165 #define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048)
168 static inline uint64_t CVMX_MIXX_ISR(unsigned long offset)
171 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
172 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
173 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
174 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
175 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
176 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
177 		cvmx_warn("CVMX_MIXX_ISR(%lu) is invalid on this chip\n", offset);
178 	return CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048;
181 #define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048)
184 static inline uint64_t CVMX_MIXX_ORCNT(unsigned long offset)
187 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
188 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
189 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
190 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
191 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
192 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
193 		cvmx_warn("CVMX_MIXX_ORCNT(%lu) is invalid on this chip\n", offset);
194 	return CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048;
197 #define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048)
200 static inline uint64_t CVMX_MIXX_ORHWM(unsigned long offset)
203 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
204 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
205 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
206 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
207 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
208 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
209 		cvmx_warn("CVMX_MIXX_ORHWM(%lu) is invalid on this chip\n", offset);
210 	return CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048;
213 #define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048)
216 static inline uint64_t CVMX_MIXX_ORING1(unsigned long offset)
219 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
220 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
221 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
222 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
223 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
224 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
225 		cvmx_warn("CVMX_MIXX_ORING1(%lu) is invalid on this chip\n", offset);
226 	return CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048;
229 #define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048)
232 static inline uint64_t CVMX_MIXX_ORING2(unsigned long offset)
235 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
236 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
237 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
238 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
239 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
240 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
241 		cvmx_warn("CVMX_MIXX_ORING2(%lu) is invalid on this chip\n", offset);
242 	return CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048;
245 #define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048)
248 static inline uint64_t CVMX_MIXX_REMCNT(unsigned long offset)
251 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
252 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0))) ||
253 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
254 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
255 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
256 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
257 		cvmx_warn("CVMX_MIXX_REMCNT(%lu) is invalid on this chip\n", offset);
258 	return CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048;
261 #define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048)
264 static inline uint64_t CVMX_MIXX_TSCTL(unsigned long offset)
267 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
268 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
269 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
270 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
271 		cvmx_warn("CVMX_MIXX_TSCTL(%lu) is invalid on this chip\n", offset);
272 	return CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048;
275 #define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048)
278 static inline uint64_t CVMX_MIXX_TSTAMP(unsigned long offset)
281 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
282 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
283 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
284 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset == 0)))))
285 		cvmx_warn("CVMX_MIXX_TSTAMP(%lu) is invalid on this chip\n", offset);
286 	return CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048;
289 #define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048)