Lines Matching refs:offset
68 static inline uint64_t CVMX_MIO_BOOT_DMA_CFGX(unsigned long offset)
71 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
72 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
73 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
74 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
75 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
76 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
77 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
78 cvmx_warn("CVMX_MIO_BOOT_DMA_CFGX(%lu) is invalid on this chip\n", offset);
79 return CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8;
82 #define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8)
85 static inline uint64_t CVMX_MIO_BOOT_DMA_INTX(unsigned long offset)
88 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
89 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
90 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
91 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
92 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
93 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
94 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
95 cvmx_warn("CVMX_MIO_BOOT_DMA_INTX(%lu) is invalid on this chip\n", offset);
96 return CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8;
99 #define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8)
102 static inline uint64_t CVMX_MIO_BOOT_DMA_INT_ENX(unsigned long offset)
105 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
107 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
108 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
109 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
110 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
111 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
112 cvmx_warn("CVMX_MIO_BOOT_DMA_INT_ENX(%lu) is invalid on this chip\n", offset);
113 return CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8;
116 #define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8)
119 static inline uint64_t CVMX_MIO_BOOT_DMA_TIMX(unsigned long offset)
122 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
123 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 2))) ||
124 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
125 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
126 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
127 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
128 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
129 cvmx_warn("CVMX_MIO_BOOT_DMA_TIMX(%lu) is invalid on this chip\n", offset);
130 return CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8;
133 #define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8)
139 static inline uint64_t CVMX_MIO_BOOT_LOC_CFGX(unsigned long offset)
142 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
143 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
144 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
145 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
146 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
147 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
148 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
149 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
150 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
151 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
152 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
153 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
154 cvmx_warn("CVMX_MIO_BOOT_LOC_CFGX(%lu) is invalid on this chip\n", offset);
155 return CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8;
158 #define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8)
173 static inline uint64_t CVMX_MIO_BOOT_REG_CFGX(unsigned long offset)
176 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
177 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
178 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
179 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
180 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
181 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
182 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
183 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
184 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
185 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
186 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
187 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
188 cvmx_warn("CVMX_MIO_BOOT_REG_CFGX(%lu) is invalid on this chip\n", offset);
189 return CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8;
192 #define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8)
195 static inline uint64_t CVMX_MIO_BOOT_REG_TIMX(unsigned long offset)
198 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
199 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
200 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
201 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
202 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
203 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
204 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
205 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
206 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
207 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
208 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
209 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
210 cvmx_warn("CVMX_MIO_BOOT_REG_TIMX(%lu) is invalid on this chip\n", offset);
211 return CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8;
214 #define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8)
295 static inline uint64_t CVMX_MIO_EMM_MODEX(unsigned long offset)
298 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
299 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
300 cvmx_warn("CVMX_MIO_EMM_MODEX(%lu) is invalid on this chip\n", offset);
301 return CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8;
304 #define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8)
395 static inline uint64_t CVMX_MIO_FUS_BNK_DATX(unsigned long offset)
398 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 3))) ||
399 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
400 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
401 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))) ||
402 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
403 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
404 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
405 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
406 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
407 cvmx_warn("CVMX_MIO_FUS_BNK_DATX(%lu) is invalid on this chip\n", offset);
408 return CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8;
411 #define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8)
764 static inline uint64_t CVMX_MIO_QLMX_CFG(unsigned long offset)
767 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 2))) ||
768 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 2))) ||
769 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 4))) ||
770 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
771 cvmx_warn("CVMX_MIO_QLMX_CFG(%lu) is invalid on this chip\n", offset);
772 return CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8;
775 #define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8)
811 static inline uint64_t CVMX_MIO_RST_CNTLX(unsigned long offset)
814 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
815 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
816 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
817 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
818 cvmx_warn("CVMX_MIO_RST_CNTLX(%lu) is invalid on this chip\n", offset);
819 return CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8;
822 #define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8)
825 static inline uint64_t CVMX_MIO_RST_CTLX(unsigned long offset)
828 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
829 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
830 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
831 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
832 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
833 cvmx_warn("CVMX_MIO_RST_CTLX(%lu) is invalid on this chip\n", offset);
834 return CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8;
837 #define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8)
873 static inline uint64_t CVMX_MIO_TWSX_INT(unsigned long offset)
876 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
877 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
878 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
879 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
880 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
881 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
882 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
883 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
884 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
885 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
886 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
887 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
888 cvmx_warn("CVMX_MIO_TWSX_INT(%lu) is invalid on this chip\n", offset);
889 return CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512;
892 #define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512)
895 static inline uint64_t CVMX_MIO_TWSX_SW_TWSI(unsigned long offset)
898 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
899 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
900 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
901 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
902 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
903 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
904 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
905 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
906 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
907 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
908 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
909 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
910 cvmx_warn("CVMX_MIO_TWSX_SW_TWSI(%lu) is invalid on this chip\n", offset);
911 return CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512;
914 #define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512)
917 static inline uint64_t CVMX_MIO_TWSX_SW_TWSI_EXT(unsigned long offset)
920 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
921 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
922 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
923 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
924 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
925 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
926 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
927 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
928 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
929 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
930 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
931 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
932 cvmx_warn("CVMX_MIO_TWSX_SW_TWSI_EXT(%lu) is invalid on this chip\n", offset);
933 return CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512;
936 #define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512)
939 static inline uint64_t CVMX_MIO_TWSX_TWSI_SW(unsigned long offset)
942 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
943 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset == 0))) ||
944 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset == 0))) ||
945 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset == 0))) ||
946 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
947 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
948 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset == 0))) ||
949 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
950 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
951 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
952 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
953 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
954 cvmx_warn("CVMX_MIO_TWSX_TWSI_SW(%lu) is invalid on this chip\n", offset);
955 return CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512;
958 #define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512)
1236 static inline uint64_t CVMX_MIO_UARTX_DLH(unsigned long offset)
1239 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1241 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1242 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1243 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1244 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1245 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1246 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1247 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1248 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1249 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1250 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1251 cvmx_warn("CVMX_MIO_UARTX_DLH(%lu) is invalid on this chip\n", offset);
1252 return CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024;
1255 #define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024)
1258 static inline uint64_t CVMX_MIO_UARTX_DLL(unsigned long offset)
1261 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1262 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1263 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1264 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1265 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1266 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1267 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1268 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1269 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1270 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1271 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1272 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1273 cvmx_warn("CVMX_MIO_UARTX_DLL(%lu) is invalid on this chip\n", offset);
1274 return CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024;
1277 #define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024)
1280 static inline uint64_t CVMX_MIO_UARTX_FAR(unsigned long offset)
1283 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1284 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1285 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1286 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1287 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1288 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1289 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1290 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1291 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1292 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1293 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1294 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1295 cvmx_warn("CVMX_MIO_UARTX_FAR(%lu) is invalid on this chip\n", offset);
1296 return CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024;
1299 #define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024)
1302 static inline uint64_t CVMX_MIO_UARTX_FCR(unsigned long offset)
1305 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1306 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1307 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1308 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1309 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1310 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1311 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1312 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1313 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1314 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1315 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1316 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1317 cvmx_warn("CVMX_MIO_UARTX_FCR(%lu) is invalid on this chip\n", offset);
1318 return CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024;
1321 #define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024)
1324 static inline uint64_t CVMX_MIO_UARTX_HTX(unsigned long offset)
1327 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1328 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1329 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1330 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1331 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1332 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1333 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1334 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1335 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1336 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1337 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1338 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1339 cvmx_warn("CVMX_MIO_UARTX_HTX(%lu) is invalid on this chip\n", offset);
1340 return CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024;
1343 #define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024)
1346 static inline uint64_t CVMX_MIO_UARTX_IER(unsigned long offset)
1349 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1350 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1351 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1352 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1353 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1354 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1355 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1356 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1357 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1358 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1359 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1360 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1361 cvmx_warn("CVMX_MIO_UARTX_IER(%lu) is invalid on this chip\n", offset);
1362 return CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024;
1365 #define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024)
1368 static inline uint64_t CVMX_MIO_UARTX_IIR(unsigned long offset)
1371 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1372 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1373 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1374 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1375 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1376 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1377 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1378 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1379 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1380 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1381 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1382 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1383 cvmx_warn("CVMX_MIO_UARTX_IIR(%lu) is invalid on this chip\n", offset);
1384 return CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024;
1387 #define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024)
1390 static inline uint64_t CVMX_MIO_UARTX_LCR(unsigned long offset)
1393 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1394 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1395 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1396 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1397 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1398 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1399 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1400 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1401 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1402 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1403 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1404 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1405 cvmx_warn("CVMX_MIO_UARTX_LCR(%lu) is invalid on this chip\n", offset);
1406 return CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024;
1409 #define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024)
1412 static inline uint64_t CVMX_MIO_UARTX_LSR(unsigned long offset)
1415 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1416 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1417 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1418 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1419 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1420 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1421 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1422 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1423 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1424 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1425 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1426 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1427 cvmx_warn("CVMX_MIO_UARTX_LSR(%lu) is invalid on this chip\n", offset);
1428 return CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024;
1431 #define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024)
1434 static inline uint64_t CVMX_MIO_UARTX_MCR(unsigned long offset)
1437 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1438 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1439 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1440 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1441 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1442 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1443 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1444 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1445 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1446 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1447 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1448 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1449 cvmx_warn("CVMX_MIO_UARTX_MCR(%lu) is invalid on this chip\n", offset);
1450 return CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024;
1453 #define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024)
1456 static inline uint64_t CVMX_MIO_UARTX_MSR(unsigned long offset)
1459 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1460 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1461 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1462 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1463 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1464 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1465 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1466 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1467 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1468 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1469 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1470 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1471 cvmx_warn("CVMX_MIO_UARTX_MSR(%lu) is invalid on this chip\n", offset);
1472 return CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024;
1475 #define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024)
1478 static inline uint64_t CVMX_MIO_UARTX_RBR(unsigned long offset)
1481 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1482 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1483 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1484 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1485 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1486 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1487 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1488 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1489 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1490 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1491 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1492 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1493 cvmx_warn("CVMX_MIO_UARTX_RBR(%lu) is invalid on this chip\n", offset);
1494 return CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024;
1497 #define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024)
1500 static inline uint64_t CVMX_MIO_UARTX_RFL(unsigned long offset)
1503 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1504 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1505 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1506 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1507 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1508 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1509 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1510 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1511 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1512 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1513 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1514 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1515 cvmx_warn("CVMX_MIO_UARTX_RFL(%lu) is invalid on this chip\n", offset);
1516 return CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024;
1519 #define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024)
1522 static inline uint64_t CVMX_MIO_UARTX_RFW(unsigned long offset)
1525 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1526 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1527 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1528 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1529 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1530 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1531 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1532 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1533 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1534 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1535 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1536 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1537 cvmx_warn("CVMX_MIO_UARTX_RFW(%lu) is invalid on this chip\n", offset);
1538 return CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024;
1541 #define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024)
1544 static inline uint64_t CVMX_MIO_UARTX_SBCR(unsigned long offset)
1547 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1548 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1549 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1550 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1551 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1552 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1553 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1554 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1555 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1556 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1557 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1558 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1559 cvmx_warn("CVMX_MIO_UARTX_SBCR(%lu) is invalid on this chip\n", offset);
1560 return CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024;
1563 #define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024)
1566 static inline uint64_t CVMX_MIO_UARTX_SCR(unsigned long offset)
1569 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1570 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1571 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1572 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1573 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1574 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1575 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1576 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1577 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1578 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1579 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1580 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1581 cvmx_warn("CVMX_MIO_UARTX_SCR(%lu) is invalid on this chip\n", offset);
1582 return CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024;
1585 #define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024)
1588 static inline uint64_t CVMX_MIO_UARTX_SFE(unsigned long offset)
1591 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1592 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1593 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1594 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1595 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1596 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1597 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1598 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1599 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1600 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1601 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1602 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1603 cvmx_warn("CVMX_MIO_UARTX_SFE(%lu) is invalid on this chip\n", offset);
1604 return CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024;
1607 #define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024)
1610 static inline uint64_t CVMX_MIO_UARTX_SRR(unsigned long offset)
1613 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1614 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1615 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1616 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1617 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1618 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1619 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1620 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1621 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1622 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1623 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1624 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1625 cvmx_warn("CVMX_MIO_UARTX_SRR(%lu) is invalid on this chip\n", offset);
1626 return CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024;
1629 #define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024)
1632 static inline uint64_t CVMX_MIO_UARTX_SRT(unsigned long offset)
1635 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1636 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1637 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1638 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1639 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1640 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1641 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1642 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1643 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1644 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1645 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1646 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1647 cvmx_warn("CVMX_MIO_UARTX_SRT(%lu) is invalid on this chip\n", offset);
1648 return CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024;
1651 #define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024)
1654 static inline uint64_t CVMX_MIO_UARTX_SRTS(unsigned long offset)
1657 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1658 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1659 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1660 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1661 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1662 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1663 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1664 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1665 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1666 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1667 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1668 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1669 cvmx_warn("CVMX_MIO_UARTX_SRTS(%lu) is invalid on this chip\n", offset);
1670 return CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024;
1673 #define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024)
1676 static inline uint64_t CVMX_MIO_UARTX_STT(unsigned long offset)
1679 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1680 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1681 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1682 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1683 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1684 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1685 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1686 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1687 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1688 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1689 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1690 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1691 cvmx_warn("CVMX_MIO_UARTX_STT(%lu) is invalid on this chip\n", offset);
1692 return CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024;
1695 #define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024)
1698 static inline uint64_t CVMX_MIO_UARTX_TFL(unsigned long offset)
1701 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1702 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1703 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1704 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1705 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1706 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1707 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1708 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1709 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1710 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1711 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1712 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1713 cvmx_warn("CVMX_MIO_UARTX_TFL(%lu) is invalid on this chip\n", offset);
1714 return CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024;
1717 #define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024)
1720 static inline uint64_t CVMX_MIO_UARTX_TFR(unsigned long offset)
1723 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1724 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1725 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1726 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1727 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1728 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1729 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1730 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1731 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1732 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1733 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1734 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1735 cvmx_warn("CVMX_MIO_UARTX_TFR(%lu) is invalid on this chip\n", offset);
1736 return CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024;
1739 #define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024)
1742 static inline uint64_t CVMX_MIO_UARTX_THR(unsigned long offset)
1745 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1746 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1747 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1748 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1749 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1750 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1751 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1752 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1753 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1754 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1755 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1756 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1757 cvmx_warn("CVMX_MIO_UARTX_THR(%lu) is invalid on this chip\n", offset);
1758 return CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024;
1761 #define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024)
1764 static inline uint64_t CVMX_MIO_UARTX_USR(unsigned long offset)
1767 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 1))) ||
1768 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
1769 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 1))) ||
1770 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
1771 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 1))) ||
1772 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 1))) ||
1773 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 1))) ||
1774 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
1775 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
1776 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
1777 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
1778 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
1779 cvmx_warn("CVMX_MIO_UARTX_USR(%lu) is invalid on this chip\n", offset);
1780 return CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024;
1783 #define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024)
2816 MIO_EMM_BUF_DAT. Wraps after last offset of last data buffer. */
2819 uint64_t offset : 6; /**< Specify the 8B data buffer offset for the next access to
2822 uint64_t offset : 6;
2898 uint64_t offset : 6; /**< Debug only. Specify the number of 8 byte transfers in the
2913 uint64_t offset : 6;
3601 uint64_t pll_off : 4; /**< Fuse information - core pll offset
3602 Used to compute the base offset for the core pll.
3603 the offset will be (PLL_OFF ^ 8)
3629 uint64_t pll_off : 4; /**< Fuse information - core pll offset
3630 Used to compute the base offset for the core pll.
3631 the offset will be (PLL_OFF ^ 8)