contrib/octeon-sdk/cvmx-mdio.h

325 static inline void __cvmx_mdio_set_clause45_mode(int bus_id)
329     smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
332     cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
335 static inline void __cvmx_mdio_set_clause22_mode(int bus_id)
339     smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id));
341     cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64);
349  * @param bus_id SMI/MDIO bus to read
354 static inline cvmx_smix_rd_dat_t __cvmx_mdio_read_rd_dat(int bus_id)
362         smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id));
372  * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
379 static inline int cvmx_mdio_read(int bus_id, int phy_id, int location)
385 	BUG_ON(bus_id > 3 || bus_id < 0);
387 	bus = octeon_mdiobuses[bus_id];
401         __cvmx_mdio_set_clause22_mode(bus_id);
407     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
409     smi_rd = __cvmx_mdio_read_rd_dat(bus_id);
422  * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
431 static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val)
437 	BUG_ON(bus_id > 3 || bus_id < 0);
439 	bus = octeon_mdiobuses[bus_id];
453         __cvmx_mdio_set_clause22_mode(bus_id);
457     cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
463     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
465     if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
478  * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
487 static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, int location)
496     __cvmx_mdio_set_clause45_mode(bus_id);
500     cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
506     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
508     if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
511         cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   TIME OUT(address)\n", bus_id, phy_id, device, location);
519     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
521     smi_rd = __cvmx_mdio_read_rd_dat(bus_id);
524         cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   TIME OUT(data)\n", bus_id, phy_id, device, location);
532         cvmx_dprintf ("cvmx_mdio_45_read: bus_id %d phy_id %2d device %2d register %2d   INVALID READ\n", bus_id, phy_id, device, location);
541  * @param bus_id   MDIO bus number. Zero on most chips, but some chips (ex CN56XX)
551 static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, int location,
560     __cvmx_mdio_set_clause45_mode(bus_id);
564     cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
570     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
572     if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),
578     cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64);
584     cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64);
586     if (CVMX_WAIT_FOR_FIELD64(CVMX_SMIX_WR_DAT(bus_id),