contrib/octeon-sdk/cvmx-ipd-defs.h

60 static inline uint64_t CVMX_IPD_BPIDX_MBUF_TH(unsigned long offset)
63 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
64 		cvmx_warn("CVMX_IPD_BPIDX_MBUF_TH(%lu) is invalid on this chip\n", offset);
65 	return CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8;
68 #define CVMX_IPD_BPIDX_MBUF_TH(offset) (CVMX_ADD_IO_SEG(0x00014F0000002000ull) + ((offset) & 63) * 8)
71 static inline uint64_t CVMX_IPD_BPID_BP_COUNTERX(unsigned long offset)
74 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 63)))))
75 		cvmx_warn("CVMX_IPD_BPID_BP_COUNTERX(%lu) is invalid on this chip\n", offset);
76 	return CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8;
79 #define CVMX_IPD_BPID_BP_COUNTERX(offset) (CVMX_ADD_IO_SEG(0x00014F0000003000ull) + ((offset) & 63) * 8)
209 static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT(unsigned long offset)
212 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) ||
213 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
214 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
215 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
216 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) ||
217 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
218 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
219 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
220 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) ||
221 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
222 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35))))))
223 		cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT(%lu) is invalid on this chip\n", offset);
224 	return CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8;
227 #define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000028ull) + ((offset) & 63) * 8)
230 static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT2(unsigned long offset)
233 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) ||
234 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
235 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 36) && (offset <= 39)))) ||
236 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39)))) ||
237 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 36) && (offset <= 39)))) ||
238 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 36) && (offset <= 39))))))
239 		cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT2(%lu) is invalid on this chip\n", offset);
240 	return CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36;
243 #define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) (CVMX_ADD_IO_SEG(0x00014F0000000368ull) + ((offset) & 63) * 8 - 8*36)
246 static inline uint64_t CVMX_IPD_PORTX_BP_PAGE_CNT3(unsigned long offset)
249 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 40) && (offset <= 47)))) ||
250 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
251 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 41)) || ((offset >= 44) && (offset <= 47)))) ||
252 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 40) && (offset <= 47))))))
253 		cvmx_warn("CVMX_IPD_PORTX_BP_PAGE_CNT3(%lu) is invalid on this chip\n", offset);
254 	return CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40;
257 #define CVMX_IPD_PORTX_BP_PAGE_CNT3(offset) (CVMX_ADD_IO_SEG(0x00014F00000003D0ull) + ((offset) & 63) * 8 - 8*40)
260 static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(unsigned long offset)
263 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && (((offset >= 36) && (offset <= 39)))) ||
264 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && (((offset >= 36) && (offset <= 39)))) ||
265 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 36) && (offset <= 39)))) ||
266 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 36) && (offset <= 39)))) ||
267 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 36) && (offset <= 39)))) ||
268 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 36) && (offset <= 39))))))
269 		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(%lu) is invalid on this chip\n", offset);
270 	return CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36;
273 #define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000388ull) + ((offset) & 63) * 8 - 8*36)
276 static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(unsigned long offset)
279 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 40) && (offset <= 43)))) ||
280 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && (((offset >= 40) && (offset <= 43)))) ||
281 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 40) && (offset <= 43)))) ||
282 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 40) && (offset <= 43))))))
283 		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(%lu) is invalid on this chip\n", offset);
284 	return CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40;
287 #define CVMX_IPD_PORT_BP_COUNTERS3_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000003B0ull) + ((offset) & 63) * 8 - 8*40)
290 static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(unsigned long offset)
293 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 44) && (offset <= 47)))) ||
294 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 44) && (offset <= 47)))) ||
295 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 44) && (offset <= 47))))))
296 		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(%lu) is invalid on this chip\n", offset);
297 	return CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44;
300 #define CVMX_IPD_PORT_BP_COUNTERS4_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000410ull) + ((offset) & 63) * 8 - 8*44)
303 static inline uint64_t CVMX_IPD_PORT_BP_COUNTERS_PAIRX(unsigned long offset)
306 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 2) || (offset == 32))) ||
307 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
308 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 35))) ||
309 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 2) || ((offset >= 32) && (offset <= 33)))) ||
310 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) ||
311 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
312 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 35))) ||
313 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
314 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3) || ((offset >= 32) && (offset <= 35)))) ||
315 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35)))) ||
316 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3) || ((offset >= 16) && (offset <= 19)) || ((offset >= 32) && (offset <= 35))))))
317 		cvmx_warn("CVMX_IPD_PORT_BP_COUNTERS_PAIRX(%lu) is invalid on this chip\n", offset);
318 	return CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8;
321 #define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) (CVMX_ADD_IO_SEG(0x00014F00000001B8ull) + ((offset) & 63) * 8)
335 static inline uint64_t CVMX_IPD_PORT_QOS_INTX(unsigned long offset)
338 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) ||
339 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
340 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) ||
341 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5))) ||
342 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) ||
343 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
344 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5)))))
345 		cvmx_warn("CVMX_IPD_PORT_QOS_INTX(%lu) is invalid on this chip\n", offset);
346 	return CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8;
349 #define CVMX_IPD_PORT_QOS_INTX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000808ull) + ((offset) & 7) * 8)
352 static inline uint64_t CVMX_IPD_PORT_QOS_INT_ENBX(unsigned long offset)
355 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset == 0) || (offset == 4))) ||
356 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset == 0) || (offset == 2) || (offset == 4))) ||
357 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) ||
358 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset == 0) || (offset == 4) || (offset == 5))) ||
359 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5))) ||
360 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
361 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset == 0) || (offset == 2) || (offset == 4) || (offset == 5)))))
362 		cvmx_warn("CVMX_IPD_PORT_QOS_INT_ENBX(%lu) is invalid on this chip\n", offset);
363 	return CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8;
366 #define CVMX_IPD_PORT_QOS_INT_ENBX(offset) (CVMX_ADD_IO_SEG(0x00014F0000000848ull) + ((offset) & 7) * 8)
369 static inline uint64_t CVMX_IPD_PORT_QOS_X_CNT(unsigned long offset)
372 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 319)))) ||
373 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 319)))) ||
374 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 383)))) ||
375 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 31) || ((offset >= 256) && (offset <= 351)))) ||
376 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 335)) || ((offset >= 352) && (offset <= 383)))) ||
377 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 511))) ||
378 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 31) || ((offset >= 128) && (offset <= 159)) || ((offset >= 256) && (offset <= 383))))))
379 		cvmx_warn("CVMX_IPD_PORT_QOS_X_CNT(%lu) is invalid on this chip\n", offset);
380 	return CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8;
383 #define CVMX_IPD_PORT_QOS_X_CNT(offset) (CVMX_ADD_IO_SEG(0x00014F0000000888ull) + ((offset) & 511) * 8)
439 static inline uint64_t CVMX_IPD_QOSX_RED_MARKS(unsigned long offset)
442 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
443 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
444 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
445 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
446 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
447 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
448 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
449 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
450 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
451 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
452 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
453 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
454 		cvmx_warn("CVMX_IPD_QOSX_RED_MARKS(%lu) is invalid on this chip\n", offset);
455 	return CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8;
458 #define CVMX_IPD_QOSX_RED_MARKS(offset) (CVMX_ADD_IO_SEG(0x00014F0000000178ull) + ((offset) & 7) * 8)
514 static inline uint64_t CVMX_IPD_RED_QUEX_PARAM(unsigned long offset)
517 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
518 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
519 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
520 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
521 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
522 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
523 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
524 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
525 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
526 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
527 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7))) ||
528 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
529 		cvmx_warn("CVMX_IPD_RED_QUEX_PARAM(%lu) is invalid on this chip\n", offset);
530 	return CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8;
533 #define CVMX_IPD_RED_QUEX_PARAM(offset) (CVMX_ADD_IO_SEG(0x00014F00000002E0ull) + ((offset) & 7) * 8)