Lines Matching refs:offset
155 static inline uint64_t CVMX_ILK_RXX_CFG0(unsigned long offset)
158 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
159 cvmx_warn("CVMX_ILK_RXX_CFG0(%lu) is invalid on this chip\n", offset);
160 return CVMX_ADD_IO_SEG(0x0001180014020000ull) + ((offset) & 1) * 16384;
163 #define CVMX_ILK_RXX_CFG0(offset) (CVMX_ADD_IO_SEG(0x0001180014020000ull) + ((offset) & 1) * 16384)
166 static inline uint64_t CVMX_ILK_RXX_CFG1(unsigned long offset)
169 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
170 cvmx_warn("CVMX_ILK_RXX_CFG1(%lu) is invalid on this chip\n", offset);
171 return CVMX_ADD_IO_SEG(0x0001180014020008ull) + ((offset) & 1) * 16384;
174 #define CVMX_ILK_RXX_CFG1(offset) (CVMX_ADD_IO_SEG(0x0001180014020008ull) + ((offset) & 1) * 16384)
177 static inline uint64_t CVMX_ILK_RXX_FLOW_CTL0(unsigned long offset)
180 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
181 cvmx_warn("CVMX_ILK_RXX_FLOW_CTL0(%lu) is invalid on this chip\n", offset);
182 return CVMX_ADD_IO_SEG(0x0001180014020090ull) + ((offset) & 1) * 16384;
185 #define CVMX_ILK_RXX_FLOW_CTL0(offset) (CVMX_ADD_IO_SEG(0x0001180014020090ull) + ((offset) & 1) * 16384)
188 static inline uint64_t CVMX_ILK_RXX_FLOW_CTL1(unsigned long offset)
191 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
192 cvmx_warn("CVMX_ILK_RXX_FLOW_CTL1(%lu) is invalid on this chip\n", offset);
193 return CVMX_ADD_IO_SEG(0x0001180014020098ull) + ((offset) & 1) * 16384;
196 #define CVMX_ILK_RXX_FLOW_CTL1(offset) (CVMX_ADD_IO_SEG(0x0001180014020098ull) + ((offset) & 1) * 16384)
199 static inline uint64_t CVMX_ILK_RXX_IDX_CAL(unsigned long offset)
202 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
203 cvmx_warn("CVMX_ILK_RXX_IDX_CAL(%lu) is invalid on this chip\n", offset);
204 return CVMX_ADD_IO_SEG(0x00011800140200A0ull) + ((offset) & 1) * 16384;
207 #define CVMX_ILK_RXX_IDX_CAL(offset) (CVMX_ADD_IO_SEG(0x00011800140200A0ull) + ((offset) & 1) * 16384)
210 static inline uint64_t CVMX_ILK_RXX_IDX_STAT0(unsigned long offset)
213 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
214 cvmx_warn("CVMX_ILK_RXX_IDX_STAT0(%lu) is invalid on this chip\n", offset);
215 return CVMX_ADD_IO_SEG(0x0001180014020070ull) + ((offset) & 1) * 16384;
218 #define CVMX_ILK_RXX_IDX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014020070ull) + ((offset) & 1) * 16384)
221 static inline uint64_t CVMX_ILK_RXX_IDX_STAT1(unsigned long offset)
224 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
225 cvmx_warn("CVMX_ILK_RXX_IDX_STAT1(%lu) is invalid on this chip\n", offset);
226 return CVMX_ADD_IO_SEG(0x0001180014020078ull) + ((offset) & 1) * 16384;
229 #define CVMX_ILK_RXX_IDX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014020078ull) + ((offset) & 1) * 16384)
232 static inline uint64_t CVMX_ILK_RXX_INT(unsigned long offset)
235 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
236 cvmx_warn("CVMX_ILK_RXX_INT(%lu) is invalid on this chip\n", offset);
237 return CVMX_ADD_IO_SEG(0x0001180014020010ull) + ((offset) & 1) * 16384;
240 #define CVMX_ILK_RXX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180014020010ull) + ((offset) & 1) * 16384)
243 static inline uint64_t CVMX_ILK_RXX_INT_EN(unsigned long offset)
246 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
247 cvmx_warn("CVMX_ILK_RXX_INT_EN(%lu) is invalid on this chip\n", offset);
248 return CVMX_ADD_IO_SEG(0x0001180014020018ull) + ((offset) & 1) * 16384;
251 #define CVMX_ILK_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x0001180014020018ull) + ((offset) & 1) * 16384)
254 static inline uint64_t CVMX_ILK_RXX_JABBER(unsigned long offset)
257 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
258 cvmx_warn("CVMX_ILK_RXX_JABBER(%lu) is invalid on this chip\n", offset);
259 return CVMX_ADD_IO_SEG(0x00011800140200B8ull) + ((offset) & 1) * 16384;
262 #define CVMX_ILK_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800140200B8ull) + ((offset) & 1) * 16384)
265 static inline uint64_t CVMX_ILK_RXX_MEM_CAL0(unsigned long offset)
268 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
269 cvmx_warn("CVMX_ILK_RXX_MEM_CAL0(%lu) is invalid on this chip\n", offset);
270 return CVMX_ADD_IO_SEG(0x00011800140200A8ull) + ((offset) & 1) * 16384;
273 #define CVMX_ILK_RXX_MEM_CAL0(offset) (CVMX_ADD_IO_SEG(0x00011800140200A8ull) + ((offset) & 1) * 16384)
276 static inline uint64_t CVMX_ILK_RXX_MEM_CAL1(unsigned long offset)
279 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
280 cvmx_warn("CVMX_ILK_RXX_MEM_CAL1(%lu) is invalid on this chip\n", offset);
281 return CVMX_ADD_IO_SEG(0x00011800140200B0ull) + ((offset) & 1) * 16384;
284 #define CVMX_ILK_RXX_MEM_CAL1(offset) (CVMX_ADD_IO_SEG(0x00011800140200B0ull) + ((offset) & 1) * 16384)
287 static inline uint64_t CVMX_ILK_RXX_MEM_STAT0(unsigned long offset)
290 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
291 cvmx_warn("CVMX_ILK_RXX_MEM_STAT0(%lu) is invalid on this chip\n", offset);
292 return CVMX_ADD_IO_SEG(0x0001180014020080ull) + ((offset) & 1) * 16384;
295 #define CVMX_ILK_RXX_MEM_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014020080ull) + ((offset) & 1) * 16384)
298 static inline uint64_t CVMX_ILK_RXX_MEM_STAT1(unsigned long offset)
301 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
302 cvmx_warn("CVMX_ILK_RXX_MEM_STAT1(%lu) is invalid on this chip\n", offset);
303 return CVMX_ADD_IO_SEG(0x0001180014020088ull) + ((offset) & 1) * 16384;
306 #define CVMX_ILK_RXX_MEM_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014020088ull) + ((offset) & 1) * 16384)
309 static inline uint64_t CVMX_ILK_RXX_RID(unsigned long offset)
312 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
313 cvmx_warn("CVMX_ILK_RXX_RID(%lu) is invalid on this chip\n", offset);
314 return CVMX_ADD_IO_SEG(0x00011800140200C0ull) + ((offset) & 1) * 16384;
317 #define CVMX_ILK_RXX_RID(offset) (CVMX_ADD_IO_SEG(0x00011800140200C0ull) + ((offset) & 1) * 16384)
320 static inline uint64_t CVMX_ILK_RXX_STAT0(unsigned long offset)
323 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
324 cvmx_warn("CVMX_ILK_RXX_STAT0(%lu) is invalid on this chip\n", offset);
325 return CVMX_ADD_IO_SEG(0x0001180014020020ull) + ((offset) & 1) * 16384;
328 #define CVMX_ILK_RXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014020020ull) + ((offset) & 1) * 16384)
331 static inline uint64_t CVMX_ILK_RXX_STAT1(unsigned long offset)
334 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
335 cvmx_warn("CVMX_ILK_RXX_STAT1(%lu) is invalid on this chip\n", offset);
336 return CVMX_ADD_IO_SEG(0x0001180014020028ull) + ((offset) & 1) * 16384;
339 #define CVMX_ILK_RXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014020028ull) + ((offset) & 1) * 16384)
342 static inline uint64_t CVMX_ILK_RXX_STAT2(unsigned long offset)
345 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
346 cvmx_warn("CVMX_ILK_RXX_STAT2(%lu) is invalid on this chip\n", offset);
347 return CVMX_ADD_IO_SEG(0x0001180014020030ull) + ((offset) & 1) * 16384;
350 #define CVMX_ILK_RXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x0001180014020030ull) + ((offset) & 1) * 16384)
353 static inline uint64_t CVMX_ILK_RXX_STAT3(unsigned long offset)
356 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
357 cvmx_warn("CVMX_ILK_RXX_STAT3(%lu) is invalid on this chip\n", offset);
358 return CVMX_ADD_IO_SEG(0x0001180014020038ull) + ((offset) & 1) * 16384;
361 #define CVMX_ILK_RXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x0001180014020038ull) + ((offset) & 1) * 16384)
364 static inline uint64_t CVMX_ILK_RXX_STAT4(unsigned long offset)
367 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
368 cvmx_warn("CVMX_ILK_RXX_STAT4(%lu) is invalid on this chip\n", offset);
369 return CVMX_ADD_IO_SEG(0x0001180014020040ull) + ((offset) & 1) * 16384;
372 #define CVMX_ILK_RXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x0001180014020040ull) + ((offset) & 1) * 16384)
375 static inline uint64_t CVMX_ILK_RXX_STAT5(unsigned long offset)
378 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
379 cvmx_warn("CVMX_ILK_RXX_STAT5(%lu) is invalid on this chip\n", offset);
380 return CVMX_ADD_IO_SEG(0x0001180014020048ull) + ((offset) & 1) * 16384;
383 #define CVMX_ILK_RXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x0001180014020048ull) + ((offset) & 1) * 16384)
386 static inline uint64_t CVMX_ILK_RXX_STAT6(unsigned long offset)
389 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
390 cvmx_warn("CVMX_ILK_RXX_STAT6(%lu) is invalid on this chip\n", offset);
391 return CVMX_ADD_IO_SEG(0x0001180014020050ull) + ((offset) & 1) * 16384;
394 #define CVMX_ILK_RXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x0001180014020050ull) + ((offset) & 1) * 16384)
397 static inline uint64_t CVMX_ILK_RXX_STAT7(unsigned long offset)
400 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
401 cvmx_warn("CVMX_ILK_RXX_STAT7(%lu) is invalid on this chip\n", offset);
402 return CVMX_ADD_IO_SEG(0x0001180014020058ull) + ((offset) & 1) * 16384;
405 #define CVMX_ILK_RXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x0001180014020058ull) + ((offset) & 1) * 16384)
408 static inline uint64_t CVMX_ILK_RXX_STAT8(unsigned long offset)
411 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
412 cvmx_warn("CVMX_ILK_RXX_STAT8(%lu) is invalid on this chip\n", offset);
413 return CVMX_ADD_IO_SEG(0x0001180014020060ull) + ((offset) & 1) * 16384;
416 #define CVMX_ILK_RXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x0001180014020060ull) + ((offset) & 1) * 16384)
419 static inline uint64_t CVMX_ILK_RXX_STAT9(unsigned long offset)
422 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
423 cvmx_warn("CVMX_ILK_RXX_STAT9(%lu) is invalid on this chip\n", offset);
424 return CVMX_ADD_IO_SEG(0x0001180014020068ull) + ((offset) & 1) * 16384;
427 #define CVMX_ILK_RXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x0001180014020068ull) + ((offset) & 1) * 16384)
430 static inline uint64_t CVMX_ILK_RX_LNEX_CFG(unsigned long offset)
433 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
434 cvmx_warn("CVMX_ILK_RX_LNEX_CFG(%lu) is invalid on this chip\n", offset);
435 return CVMX_ADD_IO_SEG(0x0001180014038000ull) + ((offset) & 7) * 1024;
438 #define CVMX_ILK_RX_LNEX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180014038000ull) + ((offset) & 7) * 1024)
441 static inline uint64_t CVMX_ILK_RX_LNEX_INT(unsigned long offset)
444 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
445 cvmx_warn("CVMX_ILK_RX_LNEX_INT(%lu) is invalid on this chip\n", offset);
446 return CVMX_ADD_IO_SEG(0x0001180014038008ull) + ((offset) & 7) * 1024;
449 #define CVMX_ILK_RX_LNEX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180014038008ull) + ((offset) & 7) * 1024)
452 static inline uint64_t CVMX_ILK_RX_LNEX_INT_EN(unsigned long offset)
455 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
456 cvmx_warn("CVMX_ILK_RX_LNEX_INT_EN(%lu) is invalid on this chip\n", offset);
457 return CVMX_ADD_IO_SEG(0x0001180014038010ull) + ((offset) & 7) * 1024;
460 #define CVMX_ILK_RX_LNEX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x0001180014038010ull) + ((offset) & 7) * 1024)
463 static inline uint64_t CVMX_ILK_RX_LNEX_STAT0(unsigned long offset)
466 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
467 cvmx_warn("CVMX_ILK_RX_LNEX_STAT0(%lu) is invalid on this chip\n", offset);
468 return CVMX_ADD_IO_SEG(0x0001180014038018ull) + ((offset) & 7) * 1024;
471 #define CVMX_ILK_RX_LNEX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014038018ull) + ((offset) & 7) * 1024)
474 static inline uint64_t CVMX_ILK_RX_LNEX_STAT1(unsigned long offset)
477 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
478 cvmx_warn("CVMX_ILK_RX_LNEX_STAT1(%lu) is invalid on this chip\n", offset);
479 return CVMX_ADD_IO_SEG(0x0001180014038020ull) + ((offset) & 7) * 1024;
482 #define CVMX_ILK_RX_LNEX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014038020ull) + ((offset) & 7) * 1024)
485 static inline uint64_t CVMX_ILK_RX_LNEX_STAT2(unsigned long offset)
488 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
489 cvmx_warn("CVMX_ILK_RX_LNEX_STAT2(%lu) is invalid on this chip\n", offset);
490 return CVMX_ADD_IO_SEG(0x0001180014038028ull) + ((offset) & 7) * 1024;
493 #define CVMX_ILK_RX_LNEX_STAT2(offset) (CVMX_ADD_IO_SEG(0x0001180014038028ull) + ((offset) & 7) * 1024)
496 static inline uint64_t CVMX_ILK_RX_LNEX_STAT3(unsigned long offset)
499 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
500 cvmx_warn("CVMX_ILK_RX_LNEX_STAT3(%lu) is invalid on this chip\n", offset);
501 return CVMX_ADD_IO_SEG(0x0001180014038030ull) + ((offset) & 7) * 1024;
504 #define CVMX_ILK_RX_LNEX_STAT3(offset) (CVMX_ADD_IO_SEG(0x0001180014038030ull) + ((offset) & 7) * 1024)
507 static inline uint64_t CVMX_ILK_RX_LNEX_STAT4(unsigned long offset)
510 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
511 cvmx_warn("CVMX_ILK_RX_LNEX_STAT4(%lu) is invalid on this chip\n", offset);
512 return CVMX_ADD_IO_SEG(0x0001180014038038ull) + ((offset) & 7) * 1024;
515 #define CVMX_ILK_RX_LNEX_STAT4(offset) (CVMX_ADD_IO_SEG(0x0001180014038038ull) + ((offset) & 7) * 1024)
518 static inline uint64_t CVMX_ILK_RX_LNEX_STAT5(unsigned long offset)
521 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
522 cvmx_warn("CVMX_ILK_RX_LNEX_STAT5(%lu) is invalid on this chip\n", offset);
523 return CVMX_ADD_IO_SEG(0x0001180014038040ull) + ((offset) & 7) * 1024;
526 #define CVMX_ILK_RX_LNEX_STAT5(offset) (CVMX_ADD_IO_SEG(0x0001180014038040ull) + ((offset) & 7) * 1024)
529 static inline uint64_t CVMX_ILK_RX_LNEX_STAT6(unsigned long offset)
532 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
533 cvmx_warn("CVMX_ILK_RX_LNEX_STAT6(%lu) is invalid on this chip\n", offset);
534 return CVMX_ADD_IO_SEG(0x0001180014038048ull) + ((offset) & 7) * 1024;
537 #define CVMX_ILK_RX_LNEX_STAT6(offset) (CVMX_ADD_IO_SEG(0x0001180014038048ull) + ((offset) & 7) * 1024)
540 static inline uint64_t CVMX_ILK_RX_LNEX_STAT7(unsigned long offset)
543 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
544 cvmx_warn("CVMX_ILK_RX_LNEX_STAT7(%lu) is invalid on this chip\n", offset);
545 return CVMX_ADD_IO_SEG(0x0001180014038050ull) + ((offset) & 7) * 1024;
548 #define CVMX_ILK_RX_LNEX_STAT7(offset) (CVMX_ADD_IO_SEG(0x0001180014038050ull) + ((offset) & 7) * 1024)
551 static inline uint64_t CVMX_ILK_RX_LNEX_STAT8(unsigned long offset)
554 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
555 cvmx_warn("CVMX_ILK_RX_LNEX_STAT8(%lu) is invalid on this chip\n", offset);
556 return CVMX_ADD_IO_SEG(0x0001180014038058ull) + ((offset) & 7) * 1024;
559 #define CVMX_ILK_RX_LNEX_STAT8(offset) (CVMX_ADD_IO_SEG(0x0001180014038058ull) + ((offset) & 7) * 1024)
562 static inline uint64_t CVMX_ILK_RX_LNEX_STAT9(unsigned long offset)
565 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 7)))))
566 cvmx_warn("CVMX_ILK_RX_LNEX_STAT9(%lu) is invalid on this chip\n", offset);
567 return CVMX_ADD_IO_SEG(0x0001180014038060ull) + ((offset) & 7) * 1024;
570 #define CVMX_ILK_RX_LNEX_STAT9(offset) (CVMX_ADD_IO_SEG(0x0001180014038060ull) + ((offset) & 7) * 1024)
584 static inline uint64_t CVMX_ILK_TXX_CFG0(unsigned long offset)
587 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
588 cvmx_warn("CVMX_ILK_TXX_CFG0(%lu) is invalid on this chip\n", offset);
589 return CVMX_ADD_IO_SEG(0x0001180014010000ull) + ((offset) & 1) * 16384;
592 #define CVMX_ILK_TXX_CFG0(offset) (CVMX_ADD_IO_SEG(0x0001180014010000ull) + ((offset) & 1) * 16384)
595 static inline uint64_t CVMX_ILK_TXX_CFG1(unsigned long offset)
598 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
599 cvmx_warn("CVMX_ILK_TXX_CFG1(%lu) is invalid on this chip\n", offset);
600 return CVMX_ADD_IO_SEG(0x0001180014010008ull) + ((offset) & 1) * 16384;
603 #define CVMX_ILK_TXX_CFG1(offset) (CVMX_ADD_IO_SEG(0x0001180014010008ull) + ((offset) & 1) * 16384)
606 static inline uint64_t CVMX_ILK_TXX_DBG(unsigned long offset)
609 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
610 cvmx_warn("CVMX_ILK_TXX_DBG(%lu) is invalid on this chip\n", offset);
611 return CVMX_ADD_IO_SEG(0x0001180014010070ull) + ((offset) & 1) * 16384;
614 #define CVMX_ILK_TXX_DBG(offset) (CVMX_ADD_IO_SEG(0x0001180014010070ull) + ((offset) & 1) * 16384)
617 static inline uint64_t CVMX_ILK_TXX_FLOW_CTL0(unsigned long offset)
620 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
621 cvmx_warn("CVMX_ILK_TXX_FLOW_CTL0(%lu) is invalid on this chip\n", offset);
622 return CVMX_ADD_IO_SEG(0x0001180014010048ull) + ((offset) & 1) * 16384;
625 #define CVMX_ILK_TXX_FLOW_CTL0(offset) (CVMX_ADD_IO_SEG(0x0001180014010048ull) + ((offset) & 1) * 16384)
628 static inline uint64_t CVMX_ILK_TXX_FLOW_CTL1(unsigned long offset)
631 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
632 cvmx_warn("CVMX_ILK_TXX_FLOW_CTL1(%lu) is invalid on this chip\n", offset);
633 return CVMX_ADD_IO_SEG(0x0001180014010050ull) + ((offset) & 1) * 16384;
636 #define CVMX_ILK_TXX_FLOW_CTL1(offset) (CVMX_ADD_IO_SEG(0x0001180014010050ull) + ((offset) & 1) * 16384)
639 static inline uint64_t CVMX_ILK_TXX_IDX_CAL(unsigned long offset)
642 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
643 cvmx_warn("CVMX_ILK_TXX_IDX_CAL(%lu) is invalid on this chip\n", offset);
644 return CVMX_ADD_IO_SEG(0x0001180014010058ull) + ((offset) & 1) * 16384;
647 #define CVMX_ILK_TXX_IDX_CAL(offset) (CVMX_ADD_IO_SEG(0x0001180014010058ull) + ((offset) & 1) * 16384)
650 static inline uint64_t CVMX_ILK_TXX_IDX_PMAP(unsigned long offset)
653 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
654 cvmx_warn("CVMX_ILK_TXX_IDX_PMAP(%lu) is invalid on this chip\n", offset);
655 return CVMX_ADD_IO_SEG(0x0001180014010010ull) + ((offset) & 1) * 16384;
658 #define CVMX_ILK_TXX_IDX_PMAP(offset) (CVMX_ADD_IO_SEG(0x0001180014010010ull) + ((offset) & 1) * 16384)
661 static inline uint64_t CVMX_ILK_TXX_IDX_STAT0(unsigned long offset)
664 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
665 cvmx_warn("CVMX_ILK_TXX_IDX_STAT0(%lu) is invalid on this chip\n", offset);
666 return CVMX_ADD_IO_SEG(0x0001180014010020ull) + ((offset) & 1) * 16384;
669 #define CVMX_ILK_TXX_IDX_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014010020ull) + ((offset) & 1) * 16384)
672 static inline uint64_t CVMX_ILK_TXX_IDX_STAT1(unsigned long offset)
675 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
676 cvmx_warn("CVMX_ILK_TXX_IDX_STAT1(%lu) is invalid on this chip\n", offset);
677 return CVMX_ADD_IO_SEG(0x0001180014010028ull) + ((offset) & 1) * 16384;
680 #define CVMX_ILK_TXX_IDX_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014010028ull) + ((offset) & 1) * 16384)
683 static inline uint64_t CVMX_ILK_TXX_INT(unsigned long offset)
686 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
687 cvmx_warn("CVMX_ILK_TXX_INT(%lu) is invalid on this chip\n", offset);
688 return CVMX_ADD_IO_SEG(0x0001180014010078ull) + ((offset) & 1) * 16384;
691 #define CVMX_ILK_TXX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180014010078ull) + ((offset) & 1) * 16384)
694 static inline uint64_t CVMX_ILK_TXX_INT_EN(unsigned long offset)
697 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
698 cvmx_warn("CVMX_ILK_TXX_INT_EN(%lu) is invalid on this chip\n", offset);
699 return CVMX_ADD_IO_SEG(0x0001180014010080ull) + ((offset) & 1) * 16384;
702 #define CVMX_ILK_TXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x0001180014010080ull) + ((offset) & 1) * 16384)
705 static inline uint64_t CVMX_ILK_TXX_MEM_CAL0(unsigned long offset)
708 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
709 cvmx_warn("CVMX_ILK_TXX_MEM_CAL0(%lu) is invalid on this chip\n", offset);
710 return CVMX_ADD_IO_SEG(0x0001180014010060ull) + ((offset) & 1) * 16384;
713 #define CVMX_ILK_TXX_MEM_CAL0(offset) (CVMX_ADD_IO_SEG(0x0001180014010060ull) + ((offset) & 1) * 16384)
716 static inline uint64_t CVMX_ILK_TXX_MEM_CAL1(unsigned long offset)
719 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
720 cvmx_warn("CVMX_ILK_TXX_MEM_CAL1(%lu) is invalid on this chip\n", offset);
721 return CVMX_ADD_IO_SEG(0x0001180014010068ull) + ((offset) & 1) * 16384;
724 #define CVMX_ILK_TXX_MEM_CAL1(offset) (CVMX_ADD_IO_SEG(0x0001180014010068ull) + ((offset) & 1) * 16384)
727 static inline uint64_t CVMX_ILK_TXX_MEM_PMAP(unsigned long offset)
730 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
731 cvmx_warn("CVMX_ILK_TXX_MEM_PMAP(%lu) is invalid on this chip\n", offset);
732 return CVMX_ADD_IO_SEG(0x0001180014010018ull) + ((offset) & 1) * 16384;
735 #define CVMX_ILK_TXX_MEM_PMAP(offset) (CVMX_ADD_IO_SEG(0x0001180014010018ull) + ((offset) & 1) * 16384)
738 static inline uint64_t CVMX_ILK_TXX_MEM_STAT0(unsigned long offset)
741 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
742 cvmx_warn("CVMX_ILK_TXX_MEM_STAT0(%lu) is invalid on this chip\n", offset);
743 return CVMX_ADD_IO_SEG(0x0001180014010030ull) + ((offset) & 1) * 16384;
746 #define CVMX_ILK_TXX_MEM_STAT0(offset) (CVMX_ADD_IO_SEG(0x0001180014010030ull) + ((offset) & 1) * 16384)
749 static inline uint64_t CVMX_ILK_TXX_MEM_STAT1(unsigned long offset)
752 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
753 cvmx_warn("CVMX_ILK_TXX_MEM_STAT1(%lu) is invalid on this chip\n", offset);
754 return CVMX_ADD_IO_SEG(0x0001180014010038ull) + ((offset) & 1) * 16384;
757 #define CVMX_ILK_TXX_MEM_STAT1(offset) (CVMX_ADD_IO_SEG(0x0001180014010038ull) + ((offset) & 1) * 16384)
760 static inline uint64_t CVMX_ILK_TXX_PIPE(unsigned long offset)
763 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
764 cvmx_warn("CVMX_ILK_TXX_PIPE(%lu) is invalid on this chip\n", offset);
765 return CVMX_ADD_IO_SEG(0x0001180014010088ull) + ((offset) & 1) * 16384;
768 #define CVMX_ILK_TXX_PIPE(offset) (CVMX_ADD_IO_SEG(0x0001180014010088ull) + ((offset) & 1) * 16384)
771 static inline uint64_t CVMX_ILK_TXX_RMATCH(unsigned long offset)
774 (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1)))))
775 cvmx_warn("CVMX_ILK_TXX_RMATCH(%lu) is invalid on this chip\n", offset);
776 return CVMX_ADD_IO_SEG(0x0001180014010040ull) + ((offset) & 1) * 16384;
779 #define CVMX_ILK_TXX_RMATCH(offset) (CVMX_ADD_IO_SEG(0x0001180014010040ull) + ((offset) & 1) * 16384)