contrib/octeon-sdk/cvmx-gpio-defs.h

56 static inline uint64_t CVMX_GPIO_BIT_CFGX(unsigned long offset)
59 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
60 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
61 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
62 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
63 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
64 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
65 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
66 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
67 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
68 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
69 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 15))) ||
70 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
71 		cvmx_warn("CVMX_GPIO_BIT_CFGX(%lu) is invalid on this chip\n", offset);
72 	return CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8;
75 #define CVMX_GPIO_BIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000800ull) + ((offset) & 15) * 8)
89 static inline uint64_t CVMX_GPIO_CLK_GENX(unsigned long offset)
92 	      (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
93 	      (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 3))) ||
94 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
95 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 3))) ||
96 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 3))) ||
97 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 3))) ||
98 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
99 		cvmx_warn("CVMX_GPIO_CLK_GENX(%lu) is invalid on this chip\n", offset);
100 	return CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8;
103 #define CVMX_GPIO_CLK_GENX(offset) (CVMX_ADD_IO_SEG(0x00010700000008C0ull) + ((offset) & 3) * 8)
106 static inline uint64_t CVMX_GPIO_CLK_QLMX(unsigned long offset)
109 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 1))) ||
110 	      (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 1))) ||
111 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 1))) ||
112 	      (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((offset <= 1))) ||
113 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 1)))))
114 		cvmx_warn("CVMX_GPIO_CLK_QLMX(%lu) is invalid on this chip\n", offset);
115 	return CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8;
118 #define CVMX_GPIO_CLK_QLMX(offset) (CVMX_ADD_IO_SEG(0x00010700000008E0ull) + ((offset) & 1) * 8)
169 static inline uint64_t CVMX_GPIO_XBIT_CFGX(unsigned long offset)
172 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 16) && (offset <= 23)))) ||
173 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 16) && (offset <= 23)))) ||
174 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 16) && (offset <= 23)))) ||
175 	      (OCTEON_IS_MODEL(OCTEON_CN61XX) && (((offset >= 16) && (offset <= 19)))) ||
176 	      (OCTEON_IS_MODEL(OCTEON_CN66XX) && (((offset >= 16) && (offset <= 19)))) ||
177 	      (OCTEON_IS_MODEL(OCTEON_CNF71XX) && (((offset >= 16) && (offset <= 19))))))
178 		cvmx_warn("CVMX_GPIO_XBIT_CFGX(%lu) is invalid on this chip\n", offset);
179 	return CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16;
182 #define CVMX_GPIO_XBIT_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001070000000900ull) + ((offset) & 31) * 8 - 8*16)