Lines Matching refs:offset
112 static inline uint64_t CVMX_GMXX_BPID_MAPX(unsigned long offset, unsigned long block_id)
115 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 15)) && ((block_id <= 4))))))
116 cvmx_warn("CVMX_GMXX_BPID_MAPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
117 return CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8;
120 #define CVMX_GMXX_BPID_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 15) + ((block_id) & 7) * 0x200000ull) * 8)
268 static inline uint64_t CVMX_GMXX_PRTX_CBFC_CTL(unsigned long offset, unsigned long block_id)
274 if (((offset == 0)) && ((block_id == 0)))
280 if (((offset == 0)) && ((block_id <= 1)))
284 if (((offset == 0)) && ((block_id <= 4)))
288 cvmx_warn("CVMX_GMXX_PRTX_CBFC_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
291 static inline uint64_t CVMX_GMXX_PRTX_CFG(unsigned long offset, unsigned long block_id)
295 if (((offset <= 1)) && ((block_id == 0)))
296 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
300 if (((offset <= 2)) && ((block_id == 0)))
301 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
305 if (((offset <= 3)) && ((block_id == 0)))
306 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
313 if (((offset <= 3)) && ((block_id <= 1)))
314 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
317 if (((offset <= 2)) && ((block_id == 0)))
318 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
321 if (((offset <= 3)) && ((block_id <= 4)))
322 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
325 cvmx_warn("CVMX_GMXX_PRTX_CFG (%lu, %lu) not supported on this chip\n", offset, block_id);
326 return CVMX_ADD_IO_SEG(0x0001180008000010ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
339 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM0(unsigned long offset, unsigned long block_id)
345 if (((offset <= 3)) && ((block_id == 0)))
346 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
350 if (((offset <= 2)) && ((block_id == 0)))
351 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
358 if (((offset <= 3)) && ((block_id <= 1)))
359 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
362 if (((offset <= 2)) && ((block_id == 0)))
363 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
366 if (((offset <= 3)) && ((block_id <= 4)))
367 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
370 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM0 (%lu, %lu) not supported on this chip\n", offset, block_id);
371 return CVMX_ADD_IO_SEG(0x0001180008000180ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
373 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM1(unsigned long offset, unsigned long block_id)
379 if (((offset <= 3)) && ((block_id == 0)))
380 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
384 if (((offset <= 2)) && ((block_id == 0)))
385 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
392 if (((offset <= 3)) && ((block_id <= 1)))
393 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
396 if (((offset <= 2)) && ((block_id == 0)))
397 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
400 if (((offset <= 3)) && ((block_id <= 4)))
401 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
404 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM1 (%lu, %lu) not supported on this chip\n", offset, block_id);
405 return CVMX_ADD_IO_SEG(0x0001180008000188ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
407 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM2(unsigned long offset, unsigned long block_id)
413 if (((offset <= 3)) && ((block_id == 0)))
414 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
418 if (((offset <= 2)) && ((block_id == 0)))
419 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
426 if (((offset <= 3)) && ((block_id <= 1)))
427 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
430 if (((offset <= 2)) && ((block_id == 0)))
431 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
434 if (((offset <= 3)) && ((block_id <= 4)))
435 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
438 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM2 (%lu, %lu) not supported on this chip\n", offset, block_id);
439 return CVMX_ADD_IO_SEG(0x0001180008000190ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
441 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM3(unsigned long offset, unsigned long block_id)
447 if (((offset <= 3)) && ((block_id == 0)))
448 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
452 if (((offset <= 2)) && ((block_id == 0)))
453 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
460 if (((offset <= 3)) && ((block_id <= 1)))
461 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
464 if (((offset <= 2)) && ((block_id == 0)))
465 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
468 if (((offset <= 3)) && ((block_id <= 4)))
469 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
472 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM3 (%lu, %lu) not supported on this chip\n", offset, block_id);
473 return CVMX_ADD_IO_SEG(0x0001180008000198ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
475 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM4(unsigned long offset, unsigned long block_id)
481 if (((offset <= 3)) && ((block_id == 0)))
482 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
486 if (((offset <= 2)) && ((block_id == 0)))
487 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
494 if (((offset <= 3)) && ((block_id <= 1)))
495 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
498 if (((offset <= 2)) && ((block_id == 0)))
499 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
502 if (((offset <= 3)) && ((block_id <= 4)))
503 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
506 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM4 (%lu, %lu) not supported on this chip\n", offset, block_id);
507 return CVMX_ADD_IO_SEG(0x00011800080001A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
509 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM5(unsigned long offset, unsigned long block_id)
515 if (((offset <= 3)) && ((block_id == 0)))
516 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
520 if (((offset <= 2)) && ((block_id == 0)))
521 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
528 if (((offset <= 3)) && ((block_id <= 1)))
529 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
532 if (((offset <= 2)) && ((block_id == 0)))
533 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
536 if (((offset <= 3)) && ((block_id <= 4)))
537 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
540 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM5 (%lu, %lu) not supported on this chip\n", offset, block_id);
541 return CVMX_ADD_IO_SEG(0x00011800080001A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
543 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_ALL_EN(unsigned long offset, unsigned long block_id)
548 if (((offset <= 3)) && ((block_id <= 1)))
549 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
552 if (((offset <= 1)) && ((block_id == 0)))
553 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
556 if (((offset <= 3)) && ((block_id <= 4)))
557 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
560 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_ALL_EN (%lu, %lu) not supported on this chip\n", offset, block_id);
561 return CVMX_ADD_IO_SEG(0x0001180008000110ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
563 static inline uint64_t CVMX_GMXX_RXX_ADR_CAM_EN(unsigned long offset, unsigned long block_id)
567 if (((offset <= 1)) && ((block_id == 0)))
568 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
572 if (((offset <= 2)) && ((block_id == 0)))
573 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
577 if (((offset <= 3)) && ((block_id == 0)))
578 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
585 if (((offset <= 3)) && ((block_id <= 1)))
586 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
589 if (((offset <= 2)) && ((block_id == 0)))
590 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
593 if (((offset <= 3)) && ((block_id <= 4)))
594 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
597 cvmx_warn("CVMX_GMXX_RXX_ADR_CAM_EN (%lu, %lu) not supported on this chip\n", offset, block_id);
598 return CVMX_ADD_IO_SEG(0x0001180008000108ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
600 static inline uint64_t CVMX_GMXX_RXX_ADR_CTL(unsigned long offset, unsigned long block_id)
604 if (((offset <= 1)) && ((block_id == 0)))
605 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
609 if (((offset <= 2)) && ((block_id == 0)))
610 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
614 if (((offset <= 3)) && ((block_id == 0)))
615 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
622 if (((offset <= 3)) && ((block_id <= 1)))
623 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
626 if (((offset <= 2)) && ((block_id == 0)))
627 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
630 if (((offset <= 3)) && ((block_id <= 4)))
631 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
634 cvmx_warn("CVMX_GMXX_RXX_ADR_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
635 return CVMX_ADD_IO_SEG(0x0001180008000100ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
637 static inline uint64_t CVMX_GMXX_RXX_DECISION(unsigned long offset, unsigned long block_id)
641 if (((offset <= 1)) && ((block_id == 0)))
642 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
646 if (((offset <= 2)) && ((block_id == 0)))
647 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
651 if (((offset <= 3)) && ((block_id == 0)))
652 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
659 if (((offset <= 3)) && ((block_id <= 1)))
660 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
663 if (((offset <= 2)) && ((block_id == 0)))
664 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
667 if (((offset <= 3)) && ((block_id <= 4)))
668 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
671 cvmx_warn("CVMX_GMXX_RXX_DECISION (%lu, %lu) not supported on this chip\n", offset, block_id);
672 return CVMX_ADD_IO_SEG(0x0001180008000040ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
674 static inline uint64_t CVMX_GMXX_RXX_FRM_CHK(unsigned long offset, unsigned long block_id)
678 if (((offset <= 1)) && ((block_id == 0)))
679 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
683 if (((offset <= 2)) && ((block_id == 0)))
684 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
688 if (((offset <= 3)) && ((block_id == 0)))
689 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
696 if (((offset <= 3)) && ((block_id <= 1)))
697 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
700 if (((offset <= 2)) && ((block_id == 0)))
701 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
704 if (((offset <= 3)) && ((block_id <= 4)))
705 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
708 cvmx_warn("CVMX_GMXX_RXX_FRM_CHK (%lu, %lu) not supported on this chip\n", offset, block_id);
709 return CVMX_ADD_IO_SEG(0x0001180008000020ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
711 static inline uint64_t CVMX_GMXX_RXX_FRM_CTL(unsigned long offset, unsigned long block_id)
715 if (((offset <= 1)) && ((block_id == 0)))
716 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
720 if (((offset <= 2)) && ((block_id == 0)))
721 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
725 if (((offset <= 3)) && ((block_id == 0)))
726 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
733 if (((offset <= 3)) && ((block_id <= 1)))
734 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
737 if (((offset <= 2)) && ((block_id == 0)))
738 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
741 if (((offset <= 3)) && ((block_id <= 4)))
742 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
745 cvmx_warn("CVMX_GMXX_RXX_FRM_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
746 return CVMX_ADD_IO_SEG(0x0001180008000018ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
749 static inline uint64_t CVMX_GMXX_RXX_FRM_MAX(unsigned long offset, unsigned long block_id)
752 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
753 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
754 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
755 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
756 cvmx_warn("CVMX_GMXX_RXX_FRM_MAX(%lu,%lu) is invalid on this chip\n", offset, block_id);
757 return CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
760 #define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000030ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
763 static inline uint64_t CVMX_GMXX_RXX_FRM_MIN(unsigned long offset, unsigned long block_id)
766 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
767 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
768 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
769 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
770 cvmx_warn("CVMX_GMXX_RXX_FRM_MIN(%lu,%lu) is invalid on this chip\n", offset, block_id);
771 return CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
774 #define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000028ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
776 static inline uint64_t CVMX_GMXX_RXX_IFG(unsigned long offset, unsigned long block_id)
780 if (((offset <= 1)) && ((block_id == 0)))
781 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
785 if (((offset <= 2)) && ((block_id == 0)))
786 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
790 if (((offset <= 3)) && ((block_id == 0)))
791 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
798 if (((offset <= 3)) && ((block_id <= 1)))
799 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
802 if (((offset <= 2)) && ((block_id == 0)))
803 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
806 if (((offset <= 3)) && ((block_id <= 4)))
807 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
810 cvmx_warn("CVMX_GMXX_RXX_IFG (%lu, %lu) not supported on this chip\n", offset, block_id);
811 return CVMX_ADD_IO_SEG(0x0001180008000058ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
813 static inline uint64_t CVMX_GMXX_RXX_INT_EN(unsigned long offset, unsigned long block_id)
817 if (((offset <= 1)) && ((block_id == 0)))
818 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
822 if (((offset <= 2)) && ((block_id == 0)))
823 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
827 if (((offset <= 3)) && ((block_id == 0)))
828 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
835 if (((offset <= 3)) && ((block_id <= 1)))
836 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
839 if (((offset <= 2)) && ((block_id == 0)))
840 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
843 if (((offset <= 3)) && ((block_id <= 4)))
844 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
847 cvmx_warn("CVMX_GMXX_RXX_INT_EN (%lu, %lu) not supported on this chip\n", offset, block_id);
848 return CVMX_ADD_IO_SEG(0x0001180008000008ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
850 static inline uint64_t CVMX_GMXX_RXX_INT_REG(unsigned long offset, unsigned long block_id)
854 if (((offset <= 1)) && ((block_id == 0)))
855 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
859 if (((offset <= 2)) && ((block_id == 0)))
860 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
864 if (((offset <= 3)) && ((block_id == 0)))
865 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
872 if (((offset <= 3)) && ((block_id <= 1)))
873 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
876 if (((offset <= 2)) && ((block_id == 0)))
877 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
880 if (((offset <= 3)) && ((block_id <= 4)))
881 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
884 cvmx_warn("CVMX_GMXX_RXX_INT_REG (%lu, %lu) not supported on this chip\n", offset, block_id);
885 return CVMX_ADD_IO_SEG(0x0001180008000000ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
887 static inline uint64_t CVMX_GMXX_RXX_JABBER(unsigned long offset, unsigned long block_id)
891 if (((offset <= 1)) && ((block_id == 0)))
892 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
896 if (((offset <= 2)) && ((block_id == 0)))
897 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
901 if (((offset <= 3)) && ((block_id == 0)))
902 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
909 if (((offset <= 3)) && ((block_id <= 1)))
910 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
913 if (((offset <= 2)) && ((block_id == 0)))
914 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
917 if (((offset <= 3)) && ((block_id <= 4)))
918 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
921 cvmx_warn("CVMX_GMXX_RXX_JABBER (%lu, %lu) not supported on this chip\n", offset, block_id);
922 return CVMX_ADD_IO_SEG(0x0001180008000038ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
924 static inline uint64_t CVMX_GMXX_RXX_PAUSE_DROP_TIME(unsigned long offset, unsigned long block_id)
928 if (((offset <= 1)) && ((block_id == 0)))
929 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
932 if (((offset <= 3)) && ((block_id == 0)))
933 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
936 if (((offset <= 2)) && ((block_id == 0)))
937 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
943 if (((offset <= 3)) && ((block_id <= 1)))
944 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
947 if (((offset <= 3)) && ((block_id == 0)))
948 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
951 if (((offset <= 3)) && ((block_id <= 4)))
952 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
955 cvmx_warn("CVMX_GMXX_RXX_PAUSE_DROP_TIME (%lu, %lu) not supported on this chip\n", offset, block_id);
956 return CVMX_ADD_IO_SEG(0x0001180008000068ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
959 static inline uint64_t CVMX_GMXX_RXX_RX_INBND(unsigned long offset, unsigned long block_id)
962 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
963 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
964 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
965 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
966 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
967 cvmx_warn("CVMX_GMXX_RXX_RX_INBND(%lu,%lu) is invalid on this chip\n", offset, block_id);
968 return CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
971 #define CVMX_GMXX_RXX_RX_INBND(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000060ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
973 static inline uint64_t CVMX_GMXX_RXX_STATS_CTL(unsigned long offset, unsigned long block_id)
977 if (((offset <= 1)) && ((block_id == 0)))
978 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
982 if (((offset <= 2)) && ((block_id == 0)))
983 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
987 if (((offset <= 3)) && ((block_id == 0)))
988 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
995 if (((offset <= 3)) && ((block_id <= 1)))
996 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
999 if (((offset <= 2)) && ((block_id == 0)))
1000 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1003 if (((offset <= 3)) && ((block_id <= 4)))
1004 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1007 cvmx_warn("CVMX_GMXX_RXX_STATS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
1008 return CVMX_ADD_IO_SEG(0x0001180008000050ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1010 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS(unsigned long offset, unsigned long block_id)
1014 if (((offset <= 1)) && ((block_id == 0)))
1015 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1019 if (((offset <= 2)) && ((block_id == 0)))
1020 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1024 if (((offset <= 3)) && ((block_id == 0)))
1025 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1032 if (((offset <= 3)) && ((block_id <= 1)))
1033 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1036 if (((offset <= 2)) && ((block_id == 0)))
1037 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1040 if (((offset <= 3)) && ((block_id <= 4)))
1041 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1044 cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS (%lu, %lu) not supported on this chip\n", offset, block_id);
1045 return CVMX_ADD_IO_SEG(0x0001180008000088ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1047 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_CTL(unsigned long offset, unsigned long block_id)
1051 if (((offset <= 1)) && ((block_id == 0)))
1052 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1056 if (((offset <= 2)) && ((block_id == 0)))
1057 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1061 if (((offset <= 3)) && ((block_id == 0)))
1062 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1069 if (((offset <= 3)) && ((block_id <= 1)))
1070 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1073 if (((offset <= 2)) && ((block_id == 0)))
1074 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1077 if (((offset <= 3)) && ((block_id <= 4)))
1078 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1081 cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
1082 return CVMX_ADD_IO_SEG(0x0001180008000098ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1084 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DMAC(unsigned long offset, unsigned long block_id)
1088 if (((offset <= 1)) && ((block_id == 0)))
1089 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1093 if (((offset <= 2)) && ((block_id == 0)))
1094 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1098 if (((offset <= 3)) && ((block_id == 0)))
1099 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1106 if (((offset <= 3)) && ((block_id <= 1)))
1107 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1110 if (((offset <= 2)) && ((block_id == 0)))
1111 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1114 if (((offset <= 3)) && ((block_id <= 4)))
1115 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1118 cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DMAC (%lu, %lu) not supported on this chip\n", offset, block_id);
1119 return CVMX_ADD_IO_SEG(0x00011800080000A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1121 static inline uint64_t CVMX_GMXX_RXX_STATS_OCTS_DRP(unsigned long offset, unsigned long block_id)
1125 if (((offset <= 1)) && ((block_id == 0)))
1126 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1130 if (((offset <= 2)) && ((block_id == 0)))
1131 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1135 if (((offset <= 3)) && ((block_id == 0)))
1136 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1143 if (((offset <= 3)) && ((block_id <= 1)))
1144 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1147 if (((offset <= 2)) && ((block_id == 0)))
1148 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1151 if (((offset <= 3)) && ((block_id <= 4)))
1152 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1155 cvmx_warn("CVMX_GMXX_RXX_STATS_OCTS_DRP (%lu, %lu) not supported on this chip\n", offset, block_id);
1156 return CVMX_ADD_IO_SEG(0x00011800080000B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1158 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS(unsigned long offset, unsigned long block_id)
1162 if (((offset <= 1)) && ((block_id == 0)))
1163 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1167 if (((offset <= 2)) && ((block_id == 0)))
1168 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1172 if (((offset <= 3)) && ((block_id == 0)))
1173 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1180 if (((offset <= 3)) && ((block_id <= 1)))
1181 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1184 if (((offset <= 2)) && ((block_id == 0)))
1185 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1188 if (((offset <= 3)) && ((block_id <= 4)))
1189 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1192 cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS (%lu, %lu) not supported on this chip\n", offset, block_id);
1193 return CVMX_ADD_IO_SEG(0x0001180008000080ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1195 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_BAD(unsigned long offset, unsigned long block_id)
1199 if (((offset <= 1)) && ((block_id == 0)))
1200 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1204 if (((offset <= 2)) && ((block_id == 0)))
1205 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1209 if (((offset <= 3)) && ((block_id == 0)))
1210 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1217 if (((offset <= 3)) && ((block_id <= 1)))
1218 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1221 if (((offset <= 2)) && ((block_id == 0)))
1222 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1225 if (((offset <= 3)) && ((block_id <= 4)))
1226 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1229 cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_BAD (%lu, %lu) not supported on this chip\n", offset, block_id);
1230 return CVMX_ADD_IO_SEG(0x00011800080000C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1232 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_CTL(unsigned long offset, unsigned long block_id)
1236 if (((offset <= 1)) && ((block_id == 0)))
1237 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1241 if (((offset <= 2)) && ((block_id == 0)))
1242 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1246 if (((offset <= 3)) && ((block_id == 0)))
1247 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1254 if (((offset <= 3)) && ((block_id <= 1)))
1255 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1258 if (((offset <= 2)) && ((block_id == 0)))
1259 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1262 if (((offset <= 3)) && ((block_id <= 4)))
1263 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1266 cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
1267 return CVMX_ADD_IO_SEG(0x0001180008000090ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1269 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DMAC(unsigned long offset, unsigned long block_id)
1273 if (((offset <= 1)) && ((block_id == 0)))
1274 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1278 if (((offset <= 2)) && ((block_id == 0)))
1279 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1283 if (((offset <= 3)) && ((block_id == 0)))
1284 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1291 if (((offset <= 3)) && ((block_id <= 1)))
1292 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1295 if (((offset <= 2)) && ((block_id == 0)))
1296 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1299 if (((offset <= 3)) && ((block_id <= 4)))
1300 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1303 cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DMAC (%lu, %lu) not supported on this chip\n", offset, block_id);
1304 return CVMX_ADD_IO_SEG(0x00011800080000A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1306 static inline uint64_t CVMX_GMXX_RXX_STATS_PKTS_DRP(unsigned long offset, unsigned long block_id)
1310 if (((offset <= 1)) && ((block_id == 0)))
1311 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1315 if (((offset <= 2)) && ((block_id == 0)))
1316 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1320 if (((offset <= 3)) && ((block_id == 0)))
1321 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1328 if (((offset <= 3)) && ((block_id <= 1)))
1329 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1332 if (((offset <= 2)) && ((block_id == 0)))
1333 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1336 if (((offset <= 3)) && ((block_id <= 4)))
1337 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1340 cvmx_warn("CVMX_GMXX_RXX_STATS_PKTS_DRP (%lu, %lu) not supported on this chip\n", offset, block_id);
1341 return CVMX_ADD_IO_SEG(0x00011800080000B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1343 static inline uint64_t CVMX_GMXX_RXX_UDD_SKP(unsigned long offset, unsigned long block_id)
1347 if (((offset <= 1)) && ((block_id == 0)))
1348 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1352 if (((offset <= 2)) && ((block_id == 0)))
1353 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1357 if (((offset <= 3)) && ((block_id == 0)))
1358 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1365 if (((offset <= 3)) && ((block_id <= 1)))
1366 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1369 if (((offset <= 2)) && ((block_id == 0)))
1370 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1373 if (((offset <= 3)) && ((block_id <= 4)))
1374 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1377 cvmx_warn("CVMX_GMXX_RXX_UDD_SKP (%lu, %lu) not supported on this chip\n", offset, block_id);
1378 return CVMX_ADD_IO_SEG(0x0001180008000048ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1380 static inline uint64_t CVMX_GMXX_RX_BP_DROPX(unsigned long offset, unsigned long block_id)
1384 if (((offset <= 1)) && ((block_id == 0)))
1385 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
1389 if (((offset <= 2)) && ((block_id == 0)))
1390 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
1394 if (((offset <= 3)) && ((block_id == 0)))
1395 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
1402 if (((offset <= 3)) && ((block_id <= 1)))
1403 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
1406 if (((offset <= 2)) && ((block_id == 0)))
1407 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
1410 if (((offset <= 3)) && ((block_id <= 4)))
1411 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8;
1414 cvmx_warn("CVMX_GMXX_RX_BP_DROPX (%lu, %lu) not supported on this chip\n", offset, block_id);
1415 return CVMX_ADD_IO_SEG(0x0001180008000420ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
1417 static inline uint64_t CVMX_GMXX_RX_BP_OFFX(unsigned long offset, unsigned long block_id)
1421 if (((offset <= 1)) && ((block_id == 0)))
1422 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
1426 if (((offset <= 2)) && ((block_id == 0)))
1427 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
1431 if (((offset <= 3)) && ((block_id == 0)))
1432 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
1439 if (((offset <= 3)) && ((block_id <= 1)))
1440 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
1443 if (((offset <= 2)) && ((block_id == 0)))
1444 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
1447 if (((offset <= 3)) && ((block_id <= 4)))
1448 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8;
1451 cvmx_warn("CVMX_GMXX_RX_BP_OFFX (%lu, %lu) not supported on this chip\n", offset, block_id);
1452 return CVMX_ADD_IO_SEG(0x0001180008000460ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
1454 static inline uint64_t CVMX_GMXX_RX_BP_ONX(unsigned long offset, unsigned long block_id)
1458 if (((offset <= 1)) && ((block_id == 0)))
1459 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
1463 if (((offset <= 2)) && ((block_id == 0)))
1464 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
1468 if (((offset <= 3)) && ((block_id == 0)))
1469 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x1000000ull) * 8;
1476 if (((offset <= 3)) && ((block_id <= 1)))
1477 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
1480 if (((offset <= 2)) && ((block_id == 0)))
1481 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 8;
1484 if (((offset <= 3)) && ((block_id <= 4)))
1485 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 3) + ((block_id) & 7) * 0x200000ull) * 8;
1488 cvmx_warn("CVMX_GMXX_RX_BP_ONX (%lu, %lu) not supported on this chip\n", offset, block_id);
1489 return CVMX_ADD_IO_SEG(0x0001180008000440ull) + (((offset) & 1) + ((block_id) & 0) * 0x1000000ull) * 8;
1527 static inline uint64_t CVMX_GMXX_RX_PASS_MAPX(unsigned long offset, unsigned long block_id)
1530 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 15)) && ((block_id <= 1)))) ||
1531 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 15)) && ((block_id <= 1))))))
1532 cvmx_warn("CVMX_GMXX_RX_PASS_MAPX(%lu,%lu) is invalid on this chip\n", offset, block_id);
1533 return CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8;
1536 #define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000600ull) + (((offset) & 15) + ((block_id) & 1) * 0x1000000ull) * 8)
1653 static inline uint64_t CVMX_GMXX_SMACX(unsigned long offset, unsigned long block_id)
1657 if (((offset <= 1)) && ((block_id == 0)))
1658 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1662 if (((offset <= 2)) && ((block_id == 0)))
1663 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1667 if (((offset <= 3)) && ((block_id == 0)))
1668 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1675 if (((offset <= 3)) && ((block_id <= 1)))
1676 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1679 if (((offset <= 2)) && ((block_id == 0)))
1680 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1683 if (((offset <= 3)) && ((block_id <= 4)))
1684 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1687 cvmx_warn("CVMX_GMXX_SMACX (%lu, %lu) not supported on this chip\n", offset, block_id);
1688 return CVMX_ADD_IO_SEG(0x0001180008000230ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1757 static inline uint64_t CVMX_GMXX_TXX_APPEND(unsigned long offset, unsigned long block_id)
1761 if (((offset <= 1)) && ((block_id == 0)))
1762 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1766 if (((offset <= 2)) && ((block_id == 0)))
1767 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1771 if (((offset <= 3)) && ((block_id == 0)))
1772 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1779 if (((offset <= 3)) && ((block_id <= 1)))
1780 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1783 if (((offset <= 2)) && ((block_id == 0)))
1784 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1787 if (((offset <= 3)) && ((block_id <= 4)))
1788 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1791 cvmx_warn("CVMX_GMXX_TXX_APPEND (%lu, %lu) not supported on this chip\n", offset, block_id);
1792 return CVMX_ADD_IO_SEG(0x0001180008000218ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1794 static inline uint64_t CVMX_GMXX_TXX_BURST(unsigned long offset, unsigned long block_id)
1798 if (((offset <= 1)) && ((block_id == 0)))
1799 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1803 if (((offset <= 2)) && ((block_id == 0)))
1804 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1808 if (((offset <= 3)) && ((block_id == 0)))
1809 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1816 if (((offset <= 3)) && ((block_id <= 1)))
1817 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1820 if (((offset <= 2)) && ((block_id == 0)))
1821 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1824 if (((offset <= 3)) && ((block_id <= 4)))
1825 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1828 cvmx_warn("CVMX_GMXX_TXX_BURST (%lu, %lu) not supported on this chip\n", offset, block_id);
1829 return CVMX_ADD_IO_SEG(0x0001180008000228ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1831 static inline uint64_t CVMX_GMXX_TXX_CBFC_XOFF(unsigned long offset, unsigned long block_id)
1837 if (((offset == 0)) && ((block_id == 0)))
1843 if (((offset == 0)) && ((block_id <= 1)))
1847 if (((offset == 0)) && ((block_id <= 4)))
1851 cvmx_warn("CVMX_GMXX_TXX_CBFC_XOFF (%lu, %lu) not supported on this chip\n", offset, block_id);
1854 static inline uint64_t CVMX_GMXX_TXX_CBFC_XON(unsigned long offset, unsigned long block_id)
1860 if (((offset == 0)) && ((block_id == 0)))
1866 if (((offset == 0)) && ((block_id <= 1)))
1870 if (((offset == 0)) && ((block_id <= 4)))
1874 cvmx_warn("CVMX_GMXX_TXX_CBFC_XON (%lu, %lu) not supported on this chip\n", offset, block_id);
1878 static inline uint64_t CVMX_GMXX_TXX_CLK(unsigned long offset, unsigned long block_id)
1881 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1882 (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1883 (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
1884 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
1885 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
1886 cvmx_warn("CVMX_GMXX_TXX_CLK(%lu,%lu) is invalid on this chip\n", offset, block_id);
1887 return CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1890 #define CVMX_GMXX_TXX_CLK(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000208ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048)
1892 static inline uint64_t CVMX_GMXX_TXX_CTL(unsigned long offset, unsigned long block_id)
1896 if (((offset <= 1)) && ((block_id == 0)))
1897 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1901 if (((offset <= 2)) && ((block_id == 0)))
1902 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1906 if (((offset <= 3)) && ((block_id == 0)))
1907 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1914 if (((offset <= 3)) && ((block_id <= 1)))
1915 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1918 if (((offset <= 2)) && ((block_id == 0)))
1919 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1922 if (((offset <= 3)) && ((block_id <= 4)))
1923 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1926 cvmx_warn("CVMX_GMXX_TXX_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
1927 return CVMX_ADD_IO_SEG(0x0001180008000270ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1929 static inline uint64_t CVMX_GMXX_TXX_MIN_PKT(unsigned long offset, unsigned long block_id)
1933 if (((offset <= 1)) && ((block_id == 0)))
1934 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1938 if (((offset <= 2)) && ((block_id == 0)))
1939 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1943 if (((offset <= 3)) && ((block_id == 0)))
1944 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1951 if (((offset <= 3)) && ((block_id <= 1)))
1952 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1955 if (((offset <= 2)) && ((block_id == 0)))
1956 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1959 if (((offset <= 3)) && ((block_id <= 4)))
1960 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
1963 cvmx_warn("CVMX_GMXX_TXX_MIN_PKT (%lu, %lu) not supported on this chip\n", offset, block_id);
1964 return CVMX_ADD_IO_SEG(0x0001180008000240ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1966 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(unsigned long offset, unsigned long block_id)
1970 if (((offset <= 1)) && ((block_id == 0)))
1971 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
1975 if (((offset <= 2)) && ((block_id == 0)))
1976 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1980 if (((offset <= 3)) && ((block_id == 0)))
1981 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
1988 if (((offset <= 3)) && ((block_id <= 1)))
1989 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
1992 if (((offset <= 2)) && ((block_id == 0)))
1993 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
1996 if (((offset <= 3)) && ((block_id <= 4)))
1997 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2000 cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL (%lu, %lu) not supported on this chip\n", offset, block_id);
2001 return CVMX_ADD_IO_SEG(0x0001180008000248ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2003 static inline uint64_t CVMX_GMXX_TXX_PAUSE_PKT_TIME(unsigned long offset, unsigned long block_id)
2007 if (((offset <= 1)) && ((block_id == 0)))
2008 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2012 if (((offset <= 2)) && ((block_id == 0)))
2013 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2017 if (((offset <= 3)) && ((block_id == 0)))
2018 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2025 if (((offset <= 3)) && ((block_id <= 1)))
2026 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2029 if (((offset <= 2)) && ((block_id == 0)))
2030 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2033 if (((offset <= 3)) && ((block_id <= 4)))
2034 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2037 cvmx_warn("CVMX_GMXX_TXX_PAUSE_PKT_TIME (%lu, %lu) not supported on this chip\n", offset, block_id);
2038 return CVMX_ADD_IO_SEG(0x0001180008000238ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2040 static inline uint64_t CVMX_GMXX_TXX_PAUSE_TOGO(unsigned long offset, unsigned long block_id)
2044 if (((offset <= 1)) && ((block_id == 0)))
2045 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2049 if (((offset <= 2)) && ((block_id == 0)))
2050 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2054 if (((offset <= 3)) && ((block_id == 0)))
2055 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2062 if (((offset <= 3)) && ((block_id <= 1)))
2063 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2066 if (((offset <= 2)) && ((block_id == 0)))
2067 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2070 if (((offset <= 3)) && ((block_id <= 4)))
2071 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2074 cvmx_warn("CVMX_GMXX_TXX_PAUSE_TOGO (%lu, %lu) not supported on this chip\n", offset, block_id);
2075 return CVMX_ADD_IO_SEG(0x0001180008000258ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2077 static inline uint64_t CVMX_GMXX_TXX_PAUSE_ZERO(unsigned long offset, unsigned long block_id)
2081 if (((offset <= 1)) && ((block_id == 0)))
2082 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2086 if (((offset <= 2)) && ((block_id == 0)))
2087 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2091 if (((offset <= 3)) && ((block_id == 0)))
2092 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2099 if (((offset <= 3)) && ((block_id <= 1)))
2100 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2103 if (((offset <= 2)) && ((block_id == 0)))
2104 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2107 if (((offset <= 3)) && ((block_id <= 4)))
2108 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2111 cvmx_warn("CVMX_GMXX_TXX_PAUSE_ZERO (%lu, %lu) not supported on this chip\n", offset, block_id);
2112 return CVMX_ADD_IO_SEG(0x0001180008000260ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2115 static inline uint64_t CVMX_GMXX_TXX_PIPE(unsigned long offset, unsigned long block_id)
2118 (OCTEON_IS_MODEL(OCTEON_CN68XX) && (((offset <= 3)) && ((block_id <= 4))))))
2119 cvmx_warn("CVMX_GMXX_TXX_PIPE(%lu,%lu) is invalid on this chip\n", offset, block_id);
2120 return CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2123 #define CVMX_GMXX_TXX_PIPE(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000310ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048)
2125 static inline uint64_t CVMX_GMXX_TXX_SGMII_CTL(unsigned long offset, unsigned long block_id)
2129 if (((offset <= 1)) && ((block_id == 0)))
2130 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2134 if (((offset <= 3)) && ((block_id == 0)))
2135 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2140 if (((offset <= 3)) && ((block_id <= 1)))
2141 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2144 if (((offset <= 3)) && ((block_id <= 4)))
2145 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2148 cvmx_warn("CVMX_GMXX_TXX_SGMII_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
2149 return CVMX_ADD_IO_SEG(0x0001180008000300ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2151 static inline uint64_t CVMX_GMXX_TXX_SLOT(unsigned long offset, unsigned long block_id)
2155 if (((offset <= 1)) && ((block_id == 0)))
2156 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2160 if (((offset <= 2)) && ((block_id == 0)))
2161 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2165 if (((offset <= 3)) && ((block_id == 0)))
2166 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2173 if (((offset <= 3)) && ((block_id <= 1)))
2174 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2177 if (((offset <= 2)) && ((block_id == 0)))
2178 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2181 if (((offset <= 3)) && ((block_id <= 4)))
2182 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2185 cvmx_warn("CVMX_GMXX_TXX_SLOT (%lu, %lu) not supported on this chip\n", offset, block_id);
2186 return CVMX_ADD_IO_SEG(0x0001180008000220ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2188 static inline uint64_t CVMX_GMXX_TXX_SOFT_PAUSE(unsigned long offset, unsigned long block_id)
2192 if (((offset <= 1)) && ((block_id == 0)))
2193 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2197 if (((offset <= 2)) && ((block_id == 0)))
2198 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2202 if (((offset <= 3)) && ((block_id == 0)))
2203 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2210 if (((offset <= 3)) && ((block_id <= 1)))
2211 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2214 if (((offset <= 2)) && ((block_id == 0)))
2215 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2218 if (((offset <= 3)) && ((block_id <= 4)))
2219 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2222 cvmx_warn("CVMX_GMXX_TXX_SOFT_PAUSE (%lu, %lu) not supported on this chip\n", offset, block_id);
2223 return CVMX_ADD_IO_SEG(0x0001180008000250ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2225 static inline uint64_t CVMX_GMXX_TXX_STAT0(unsigned long offset, unsigned long block_id)
2229 if (((offset <= 1)) && ((block_id == 0)))
2230 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2234 if (((offset <= 2)) && ((block_id == 0)))
2235 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2239 if (((offset <= 3)) && ((block_id == 0)))
2240 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2247 if (((offset <= 3)) && ((block_id <= 1)))
2248 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2251 if (((offset <= 2)) && ((block_id == 0)))
2252 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2255 if (((offset <= 3)) && ((block_id <= 4)))
2256 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2259 cvmx_warn("CVMX_GMXX_TXX_STAT0 (%lu, %lu) not supported on this chip\n", offset, block_id);
2260 return CVMX_ADD_IO_SEG(0x0001180008000280ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2262 static inline uint64_t CVMX_GMXX_TXX_STAT1(unsigned long offset, unsigned long block_id)
2266 if (((offset <= 1)) && ((block_id == 0)))
2267 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2271 if (((offset <= 2)) && ((block_id == 0)))
2272 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2276 if (((offset <= 3)) && ((block_id == 0)))
2277 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2284 if (((offset <= 3)) && ((block_id <= 1)))
2285 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2288 if (((offset <= 2)) && ((block_id == 0)))
2289 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2292 if (((offset <= 3)) && ((block_id <= 4)))
2293 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2296 cvmx_warn("CVMX_GMXX_TXX_STAT1 (%lu, %lu) not supported on this chip\n", offset, block_id);
2297 return CVMX_ADD_IO_SEG(0x0001180008000288ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2299 static inline uint64_t CVMX_GMXX_TXX_STAT2(unsigned long offset, unsigned long block_id)
2303 if (((offset <= 1)) && ((block_id == 0)))
2304 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2308 if (((offset <= 2)) && ((block_id == 0)))
2309 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2313 if (((offset <= 3)) && ((block_id == 0)))
2314 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2321 if (((offset <= 3)) && ((block_id <= 1)))
2322 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2325 if (((offset <= 2)) && ((block_id == 0)))
2326 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2329 if (((offset <= 3)) && ((block_id <= 4)))
2330 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2333 cvmx_warn("CVMX_GMXX_TXX_STAT2 (%lu, %lu) not supported on this chip\n", offset, block_id);
2334 return CVMX_ADD_IO_SEG(0x0001180008000290ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2336 static inline uint64_t CVMX_GMXX_TXX_STAT3(unsigned long offset, unsigned long block_id)
2340 if (((offset <= 1)) && ((block_id == 0)))
2341 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2345 if (((offset <= 2)) && ((block_id == 0)))
2346 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2350 if (((offset <= 3)) && ((block_id == 0)))
2351 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2358 if (((offset <= 3)) && ((block_id <= 1)))
2359 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2362 if (((offset <= 2)) && ((block_id == 0)))
2363 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2366 if (((offset <= 3)) && ((block_id <= 4)))
2367 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2370 cvmx_warn("CVMX_GMXX_TXX_STAT3 (%lu, %lu) not supported on this chip\n", offset, block_id);
2371 return CVMX_ADD_IO_SEG(0x0001180008000298ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2373 static inline uint64_t CVMX_GMXX_TXX_STAT4(unsigned long offset, unsigned long block_id)
2377 if (((offset <= 1)) && ((block_id == 0)))
2378 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2382 if (((offset <= 2)) && ((block_id == 0)))
2383 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2387 if (((offset <= 3)) && ((block_id == 0)))
2388 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2395 if (((offset <= 3)) && ((block_id <= 1)))
2396 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2399 if (((offset <= 2)) && ((block_id == 0)))
2400 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2403 if (((offset <= 3)) && ((block_id <= 4)))
2404 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2407 cvmx_warn("CVMX_GMXX_TXX_STAT4 (%lu, %lu) not supported on this chip\n", offset, block_id);
2408 return CVMX_ADD_IO_SEG(0x00011800080002A0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2410 static inline uint64_t CVMX_GMXX_TXX_STAT5(unsigned long offset, unsigned long block_id)
2414 if (((offset <= 1)) && ((block_id == 0)))
2415 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2419 if (((offset <= 2)) && ((block_id == 0)))
2420 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2424 if (((offset <= 3)) && ((block_id == 0)))
2425 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2432 if (((offset <= 3)) && ((block_id <= 1)))
2433 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2436 if (((offset <= 2)) && ((block_id == 0)))
2437 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2440 if (((offset <= 3)) && ((block_id <= 4)))
2441 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2444 cvmx_warn("CVMX_GMXX_TXX_STAT5 (%lu, %lu) not supported on this chip\n", offset, block_id);
2445 return CVMX_ADD_IO_SEG(0x00011800080002A8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2447 static inline uint64_t CVMX_GMXX_TXX_STAT6(unsigned long offset, unsigned long block_id)
2451 if (((offset <= 1)) && ((block_id == 0)))
2452 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2456 if (((offset <= 2)) && ((block_id == 0)))
2457 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2461 if (((offset <= 3)) && ((block_id == 0)))
2462 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2469 if (((offset <= 3)) && ((block_id <= 1)))
2470 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2473 if (((offset <= 2)) && ((block_id == 0)))
2474 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2477 if (((offset <= 3)) && ((block_id <= 4)))
2478 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2481 cvmx_warn("CVMX_GMXX_TXX_STAT6 (%lu, %lu) not supported on this chip\n", offset, block_id);
2482 return CVMX_ADD_IO_SEG(0x00011800080002B0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2484 static inline uint64_t CVMX_GMXX_TXX_STAT7(unsigned long offset, unsigned long block_id)
2488 if (((offset <= 1)) && ((block_id == 0)))
2489 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2493 if (((offset <= 2)) && ((block_id == 0)))
2494 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2498 if (((offset <= 3)) && ((block_id == 0)))
2499 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2506 if (((offset <= 3)) && ((block_id <= 1)))
2507 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2510 if (((offset <= 2)) && ((block_id == 0)))
2511 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2514 if (((offset <= 3)) && ((block_id <= 4)))
2515 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2518 cvmx_warn("CVMX_GMXX_TXX_STAT7 (%lu, %lu) not supported on this chip\n", offset, block_id);
2519 return CVMX_ADD_IO_SEG(0x00011800080002B8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2521 static inline uint64_t CVMX_GMXX_TXX_STAT8(unsigned long offset, unsigned long block_id)
2525 if (((offset <= 1)) && ((block_id == 0)))
2526 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2530 if (((offset <= 2)) && ((block_id == 0)))
2531 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2535 if (((offset <= 3)) && ((block_id == 0)))
2536 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2543 if (((offset <= 3)) && ((block_id <= 1)))
2544 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2547 if (((offset <= 2)) && ((block_id == 0)))
2548 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2551 if (((offset <= 3)) && ((block_id <= 4)))
2552 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2555 cvmx_warn("CVMX_GMXX_TXX_STAT8 (%lu, %lu) not supported on this chip\n", offset, block_id);
2556 return CVMX_ADD_IO_SEG(0x00011800080002C0ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2558 static inline uint64_t CVMX_GMXX_TXX_STAT9(unsigned long offset, unsigned long block_id)
2562 if (((offset <= 1)) && ((block_id == 0)))
2563 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2567 if (((offset <= 2)) && ((block_id == 0)))
2568 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2572 if (((offset <= 3)) && ((block_id == 0)))
2573 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2580 if (((offset <= 3)) && ((block_id <= 1)))
2581 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2584 if (((offset <= 2)) && ((block_id == 0)))
2585 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2588 if (((offset <= 3)) && ((block_id <= 4)))
2589 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2592 cvmx_warn("CVMX_GMXX_TXX_STAT9 (%lu, %lu) not supported on this chip\n", offset, block_id);
2593 return CVMX_ADD_IO_SEG(0x00011800080002C8ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2595 static inline uint64_t CVMX_GMXX_TXX_STATS_CTL(unsigned long offset, unsigned long block_id)
2599 if (((offset <= 1)) && ((block_id == 0)))
2600 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2604 if (((offset <= 2)) && ((block_id == 0)))
2605 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2609 if (((offset <= 3)) && ((block_id == 0)))
2610 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2617 if (((offset <= 3)) && ((block_id <= 1)))
2618 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2621 if (((offset <= 2)) && ((block_id == 0)))
2622 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2625 if (((offset <= 3)) && ((block_id <= 4)))
2626 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2629 cvmx_warn("CVMX_GMXX_TXX_STATS_CTL (%lu, %lu) not supported on this chip\n", offset, block_id);
2630 return CVMX_ADD_IO_SEG(0x0001180008000268ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2632 static inline uint64_t CVMX_GMXX_TXX_THRESH(unsigned long offset, unsigned long block_id)
2636 if (((offset <= 1)) && ((block_id == 0)))
2637 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2641 if (((offset <= 2)) && ((block_id == 0)))
2642 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2646 if (((offset <= 3)) && ((block_id == 0)))
2647 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x10000ull) * 2048;
2654 if (((offset <= 3)) && ((block_id <= 1)))
2655 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 1) * 0x10000ull) * 2048;
2658 if (((offset <= 2)) && ((block_id == 0)))
2659 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 2048;
2662 if (((offset <= 3)) && ((block_id <= 4)))
2663 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 3) + ((block_id) & 7) * 0x2000ull) * 2048;
2666 cvmx_warn("CVMX_GMXX_TXX_THRESH (%lu, %lu) not supported on this chip\n", offset, block_id);
2667 return CVMX_ADD_IO_SEG(0x0001180008000210ull) + (((offset) & 1) + ((block_id) & 0) * 0x10000ull) * 2048;
2698 static inline uint64_t CVMX_GMXX_TX_CLK_MSKX(unsigned long offset, unsigned long block_id)
2701 (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 1)) && ((block_id == 0)))) ||
2702 (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 1)) && ((block_id == 0))))))
2703 cvmx_warn("CVMX_GMXX_TX_CLK_MSKX(%lu,%lu) is invalid on this chip\n", offset, block_id);
2704 return CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8;
2707 #define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000780ull) + (((offset) & 1) + ((block_id) & 0) * 0x0ull) * 8)
3100 static inline uint64_t CVMX_GMXX_TX_SPI_ROUNDX(unsigned long offset, unsigned long block_id)
3103 (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 31)) && ((block_id <= 1))))))
3104 cvmx_warn("CVMX_GMXX_TX_SPI_ROUNDX(%lu,%lu) is invalid on this chip\n", offset, block_id);
3105 return CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8;
3108 #define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) (CVMX_ADD_IO_SEG(0x0001180008000680ull) + (((offset) & 31) + ((block_id) & 1) * 0x1000000ull) * 8)