Lines Matching refs:mbox
2332 uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */
2338 uint64_t mbox : 2;
2378 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2384 uint64_t mbox : 2;
2421 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2427 uint64_t mbox : 2;
2460 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2466 uint64_t mbox : 2;
2504 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2510 uint64_t mbox : 2;
2553 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2559 uint64_t mbox : 2;
2604 uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */
2610 uint64_t mbox : 2;
2655 uint64_t mbox : 2; /**< Two mailbox/PCIe/sRIO interrupt enables */
2661 uint64_t mbox : 2;
2705 uint64_t mbox : 2; /**< Two mailbox/PCIe interrupt enables */
2711 uint64_t mbox : 2;
2771 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt
2778 uint64_t mbox : 2;
2821 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2827 uint64_t mbox : 2;
2869 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2875 uint64_t mbox : 2;
2910 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
2916 uint64_t mbox : 2;
2956 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt
2963 uint64_t mbox : 2;
3012 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe/sRIO interrupt
3019 uint64_t mbox : 2;
3066 uint64_t mbox : 2; /**< Write 1s to clear mailbox/PCIe interrupt
3073 uint64_t mbox : 2;
3133 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt
3140 uint64_t mbox : 2;
3183 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
3189 uint64_t mbox : 2;
3231 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
3237 uint64_t mbox : 2;
3272 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
3278 uint64_t mbox : 2;
3318 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt
3325 uint64_t mbox : 2;
3374 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe/sRIO interrupt
3381 uint64_t mbox : 2;
3428 uint64_t mbox : 2; /**< Write 1s to set mailbox/PCIe interrupt
3435 uint64_t mbox : 2;
4843 uint64_t mbox : 2; /**< Two mailbox interrupt enables */
4849 uint64_t mbox : 2;
4889 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
4895 uint64_t mbox : 2;
4935 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
4941 uint64_t mbox : 2;
4984 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
4990 uint64_t mbox : 2;
5026 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5032 uint64_t mbox : 2;
5069 uint64_t mbox : 2; /**< Two mailbox interrupt enables */
5075 uint64_t mbox : 2;
5120 uint64_t mbox : 2; /**< Two mailbox interrupt enables */
5126 uint64_t mbox : 2;
5170 uint64_t mbox : 2; /**< Two mailbox interrupt enables */
5176 uint64_t mbox : 2;
5236 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
5242 uint64_t mbox : 2;
5285 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5291 uint64_t mbox : 2;
5333 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5339 uint64_t mbox : 2;
5374 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5380 uint64_t mbox : 2;
5420 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
5426 uint64_t mbox : 2;
5475 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
5481 uint64_t mbox : 2;
5528 uint64_t mbox : 2; /**< Write 1s to clear mailbox interrupt enables */
5534 uint64_t mbox : 2;
5594 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
5600 uint64_t mbox : 2;
5643 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5649 uint64_t mbox : 2;
5691 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5697 uint64_t mbox : 2;
5732 uint64_t mbox : 2; /**< Two mailbox/PCI interrupts */
5738 uint64_t mbox : 2;
5778 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
5784 uint64_t mbox : 2;
5833 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
5839 uint64_t mbox : 2;
5886 uint64_t mbox : 2; /**< Write 1s to set mailbox interrupt enables */
5892 uint64_t mbox : 2;
7292 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
7310 uint64_t mbox : 2;
7358 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
7369 uint64_t mbox : 2;
7414 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
7425 uint64_t mbox : 2;
7468 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
7479 uint64_t mbox : 2;
7533 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-7
7544 uint64_t mbox : 2;
7597 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-23
7608 uint64_t mbox : 2;
7700 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
7718 uint64_t mbox : 2;
7814 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
7826 uint64_t mbox : 2;
7916 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
7934 uint64_t mbox : 2;
8024 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5
8041 uint64_t mbox : 2;
8086 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
8097 uint64_t mbox : 2;
8150 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-3
8159 uint64_t mbox : 2;
8209 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-11
8218 uint64_t mbox : 2;
8261 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-31
8272 uint64_t mbox : 2;
8355 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5
8372 uint64_t mbox : 2;
8467 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5
8477 uint64_t mbox : 2;
8566 uint64_t mbox : 2; /**< Two mailbox interrupts for entries 0-5
8583 uint64_t mbox : 2;
8682 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */
8696 uint64_t mbox : 2;
8773 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */
8781 uint64_t mbox : 2;
8875 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */
8883 uint64_t mbox : 2;
8973 uint64_t mbox : 2; /**< A read-only copy of CIU_PCI_INTA[INT] */
8987 uint64_t mbox : 2;