contrib/octeon-sdk/cvmx-asxx-defs.h

56 static inline uint64_t CVMX_ASXX_GMII_RX_CLK_SET(unsigned long block_id)
59 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
60 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
61 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
62 		cvmx_warn("CVMX_ASXX_GMII_RX_CLK_SET(%lu) is invalid on this chip\n", block_id);
66 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
69 static inline uint64_t CVMX_ASXX_GMII_RX_DAT_SET(unsigned long block_id)
72 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
73 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
74 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
75 		cvmx_warn("CVMX_ASXX_GMII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
79 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
82 static inline uint64_t CVMX_ASXX_INT_EN(unsigned long block_id)
85 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
86 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
87 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
88 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
89 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
90 		cvmx_warn("CVMX_ASXX_INT_EN(%lu) is invalid on this chip\n", block_id);
91 	return CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull;
94 #define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
97 static inline uint64_t CVMX_ASXX_INT_REG(unsigned long block_id)
100 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
101 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
102 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
103 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
104 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
105 		cvmx_warn("CVMX_ASXX_INT_REG(%lu) is invalid on this chip\n", block_id);
106 	return CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull;
109 #define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
112 static inline uint64_t CVMX_ASXX_MII_RX_DAT_SET(unsigned long block_id)
115 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
116 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0)))))
117 		cvmx_warn("CVMX_ASXX_MII_RX_DAT_SET(%lu) is invalid on this chip\n", block_id);
121 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
124 static inline uint64_t CVMX_ASXX_PRT_LOOP(unsigned long block_id)
127 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
128 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
129 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
130 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
131 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
132 		cvmx_warn("CVMX_ASXX_PRT_LOOP(%lu) is invalid on this chip\n", block_id);
133 	return CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull;
136 #define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
139 static inline uint64_t CVMX_ASXX_RLD_BYPASS(unsigned long block_id)
142 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
143 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
144 		cvmx_warn("CVMX_ASXX_RLD_BYPASS(%lu) is invalid on this chip\n", block_id);
145 	return CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull;
148 #define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
151 static inline uint64_t CVMX_ASXX_RLD_BYPASS_SETTING(unsigned long block_id)
154 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
155 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
156 		cvmx_warn("CVMX_ASXX_RLD_BYPASS_SETTING(%lu) is invalid on this chip\n", block_id);
157 	return CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull;
160 #define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
163 static inline uint64_t CVMX_ASXX_RLD_COMP(unsigned long block_id)
166 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
167 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
168 		cvmx_warn("CVMX_ASXX_RLD_COMP(%lu) is invalid on this chip\n", block_id);
169 	return CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull;
172 #define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
175 static inline uint64_t CVMX_ASXX_RLD_DATA_DRV(unsigned long block_id)
178 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
179 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
180 		cvmx_warn("CVMX_ASXX_RLD_DATA_DRV(%lu) is invalid on this chip\n", block_id);
181 	return CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull;
184 #define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
187 static inline uint64_t CVMX_ASXX_RLD_FCRAM_MODE(unsigned long block_id)
190 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
191 		cvmx_warn("CVMX_ASXX_RLD_FCRAM_MODE(%lu) is invalid on this chip\n", block_id);
192 	return CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull;
195 #define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
198 static inline uint64_t CVMX_ASXX_RLD_NCTL_STRONG(unsigned long block_id)
201 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
202 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
203 		cvmx_warn("CVMX_ASXX_RLD_NCTL_STRONG(%lu) is invalid on this chip\n", block_id);
204 	return CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull;
207 #define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
210 static inline uint64_t CVMX_ASXX_RLD_NCTL_WEAK(unsigned long block_id)
213 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
214 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
215 		cvmx_warn("CVMX_ASXX_RLD_NCTL_WEAK(%lu) is invalid on this chip\n", block_id);
216 	return CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull;
219 #define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
222 static inline uint64_t CVMX_ASXX_RLD_PCTL_STRONG(unsigned long block_id)
225 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
226 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
227 		cvmx_warn("CVMX_ASXX_RLD_PCTL_STRONG(%lu) is invalid on this chip\n", block_id);
228 	return CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull;
231 #define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
234 static inline uint64_t CVMX_ASXX_RLD_PCTL_WEAK(unsigned long block_id)
237 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
238 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
239 		cvmx_warn("CVMX_ASXX_RLD_PCTL_WEAK(%lu) is invalid on this chip\n", block_id);
240 	return CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull;
243 #define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
246 static inline uint64_t CVMX_ASXX_RLD_SETTING(unsigned long block_id)
249 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
250 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
251 		cvmx_warn("CVMX_ASXX_RLD_SETTING(%lu) is invalid on this chip\n", block_id);
252 	return CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull;
255 #define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
258 static inline uint64_t CVMX_ASXX_RX_CLK_SETX(unsigned long offset, unsigned long block_id)
261 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
262 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
263 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
264 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
265 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
266 		cvmx_warn("CVMX_ASXX_RX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
267 	return CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
270 #define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
273 static inline uint64_t CVMX_ASXX_RX_PRT_EN(unsigned long block_id)
276 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
277 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
278 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
279 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
280 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
281 		cvmx_warn("CVMX_ASXX_RX_PRT_EN(%lu) is invalid on this chip\n", block_id);
282 	return CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull;
285 #define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
288 static inline uint64_t CVMX_ASXX_RX_WOL(unsigned long block_id)
291 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
292 		cvmx_warn("CVMX_ASXX_RX_WOL(%lu) is invalid on this chip\n", block_id);
293 	return CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull;
296 #define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
299 static inline uint64_t CVMX_ASXX_RX_WOL_MSK(unsigned long block_id)
302 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
303 		cvmx_warn("CVMX_ASXX_RX_WOL_MSK(%lu) is invalid on this chip\n", block_id);
304 	return CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull;
307 #define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
310 static inline uint64_t CVMX_ASXX_RX_WOL_POWOK(unsigned long block_id)
313 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
314 		cvmx_warn("CVMX_ASXX_RX_WOL_POWOK(%lu) is invalid on this chip\n", block_id);
315 	return CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull;
318 #define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
321 static inline uint64_t CVMX_ASXX_RX_WOL_SIG(unsigned long block_id)
324 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1)))))
325 		cvmx_warn("CVMX_ASXX_RX_WOL_SIG(%lu) is invalid on this chip\n", block_id);
326 	return CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull;
329 #define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
332 static inline uint64_t CVMX_ASXX_TX_CLK_SETX(unsigned long offset, unsigned long block_id)
335 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
336 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
337 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
338 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
339 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
340 		cvmx_warn("CVMX_ASXX_TX_CLK_SETX(%lu,%lu) is invalid on this chip\n", offset, block_id);
341 	return CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
344 #define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
347 static inline uint64_t CVMX_ASXX_TX_COMP_BYP(unsigned long block_id)
350 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
351 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
352 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
353 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
354 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
355 		cvmx_warn("CVMX_ASXX_TX_COMP_BYP(%lu) is invalid on this chip\n", block_id);
356 	return CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull;
359 #define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
362 static inline uint64_t CVMX_ASXX_TX_HI_WATERX(unsigned long offset, unsigned long block_id)
365 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset <= 2)) && ((block_id == 0)))) ||
366 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset <= 2)) && ((block_id == 0)))) ||
367 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset <= 3)) && ((block_id <= 1)))) ||
368 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset <= 2)) && ((block_id == 0)))) ||
369 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset <= 3)) && ((block_id <= 1))))))
370 		cvmx_warn("CVMX_ASXX_TX_HI_WATERX(%lu,%lu) is invalid on this chip\n", offset, block_id);
371 	return CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8;
374 #define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
377 static inline uint64_t CVMX_ASXX_TX_PRT_EN(unsigned long block_id)
380 	      (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) ||
381 	      (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) ||
382 	      (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((block_id <= 1))) ||
383 	      (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) ||
384 	      (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((block_id <= 1)))))
385 		cvmx_warn("CVMX_ASXX_TX_PRT_EN(%lu) is invalid on this chip\n", block_id);
386 	return CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull;
389 #define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)