Lines Matching refs:dst
92 #define MAC_DMA_CR__RXE_LP__SET(dst) \
93 (dst) = ((dst) &\
95 #define MAC_DMA_CR__RXE_LP__CLR(dst) \
96 (dst) = ((dst) &\
104 #define MAC_DMA_CR__RXE_HP__SET(dst) \
105 (dst) = ((dst) &\
107 #define MAC_DMA_CR__RXE_HP__CLR(dst) \
108 (dst) = ((dst) &\
117 #define MAC_DMA_CR__RXD__MODIFY(dst, src) \
118 (dst) = ((dst) &\
124 #define MAC_DMA_CR__RXD__SET(dst) \
125 (dst) = ((dst) &\
127 #define MAC_DMA_CR__RXD__CLR(dst) \
128 (dst) = ((dst) &\
136 #define MAC_DMA_CR__SWI__SET(dst) \
137 (dst) = ((dst) &\
139 #define MAC_DMA_CR__SWI__CLR(dst) \
140 (dst) = ((dst) &\
166 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MODIFY(dst, src) \
167 (dst) = ((dst) &\
173 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__SET(dst) \
174 (dst) = ((dst) &\
176 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__CLR(dst) \
177 (dst) = ((dst) &\
190 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MODIFY(dst, src) \
191 (dst) = ((dst) &\
197 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__SET(dst) \
198 (dst) = ((dst) &\
200 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__CLR(dst) \
201 (dst) = ((dst) &\
214 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__MODIFY(dst, src) \
215 (dst) = ((dst) &\
221 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__SET(dst) \
222 (dst) = ((dst) &\
224 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__CLR(dst) \
225 (dst) = ((dst) &\
238 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__MODIFY(dst, src) \
239 (dst) = ((dst) &\
245 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__SET(dst) \
246 (dst) = ((dst) &\
248 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__CLR(dst) \
249 (dst) = ((dst) &\
262 #define MAC_DMA_CFG__BE_MODE_MMR__MODIFY(dst, src) \
263 (dst) = ((dst) &\
269 #define MAC_DMA_CFG__BE_MODE_MMR__SET(dst) \
270 (dst) = ((dst) &\
272 #define MAC_DMA_CFG__BE_MODE_MMR__CLR(dst) \
273 (dst) = ((dst) &\
282 #define MAC_DMA_CFG__ADHOC__MODIFY(dst, src) \
283 (dst) = ((dst) &\
289 #define MAC_DMA_CFG__ADHOC__SET(dst) \
290 (dst) = ((dst) &\
292 #define MAC_DMA_CFG__ADHOC__CLR(dst) \
293 (dst) = ((dst) &\
301 #define MAC_DMA_CFG__PHY_OK__SET(dst) \
302 (dst) = ((dst) &\
304 #define MAC_DMA_CFG__PHY_OK__CLR(dst) \
305 (dst) = ((dst) &\
315 #define MAC_DMA_CFG__EEPROM_BUSY__SET(dst) \
316 (dst) = ((dst) &\
318 #define MAC_DMA_CFG__EEPROM_BUSY__CLR(dst) \
319 (dst) = ((dst) &\
332 #define MAC_DMA_CFG__CLKGATE_DIS__MODIFY(dst, src) \
333 (dst) = ((dst) &\
339 #define MAC_DMA_CFG__CLKGATE_DIS__SET(dst) \
340 (dst) = ((dst) &\
342 #define MAC_DMA_CFG__CLKGATE_DIS__CLR(dst) \
343 (dst) = ((dst) &\
356 #define MAC_DMA_CFG__HALT_REQ__MODIFY(dst, src) \
357 (dst) = ((dst) &\
363 #define MAC_DMA_CFG__HALT_REQ__SET(dst) \
364 (dst) = ((dst) &\
366 #define MAC_DMA_CFG__HALT_REQ__CLR(dst) \
367 (dst) = ((dst) &\
377 #define MAC_DMA_CFG__HALT_ACK__SET(dst) \
378 (dst) = ((dst) &\
380 #define MAC_DMA_CFG__HALT_ACK__CLR(dst) \
381 (dst) = ((dst) &\
394 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MODIFY(dst, src) \
395 (dst) = ((dst) &\
412 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MODIFY(dst, src) \
413 (dst) = ((dst) &\
419 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__SET(dst) \
420 (dst) = ((dst) &\
422 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__CLR(dst) \
423 (dst) = ((dst) &\
449 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MODIFY(dst, src) \
450 (dst) = ((dst) &\
467 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MODIFY(dst, src) \
468 (dst) = ((dst) &\
496 #define MAC_DMA_TXDPPTR_THRESH__DATA__MODIFY(dst, src) \
497 (dst) = ((dst) &\
523 #define MAC_DMA_MIRT__RATE_THRESH__MODIFY(dst, src) \
524 (dst) = ((dst) &\
550 #define MAC_DMA_GLOBAL_IER__ENABLE__MODIFY(dst, src) \
551 (dst) = ((dst) &\
557 #define MAC_DMA_GLOBAL_IER__ENABLE__SET(dst) \
558 (dst) = ((dst) &\
560 #define MAC_DMA_GLOBAL_IER__ENABLE__CLR(dst) \
561 (dst) = ((dst) &\
587 #define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
588 (dst) = ((dst) &\
605 #define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
606 (dst) = ((dst) &\
636 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MODIFY(dst, src) \
637 (dst) = ((dst) &\
654 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MODIFY(dst, src) \
655 (dst) = ((dst) &\
681 #define MAC_DMA_TXCFG__DMA_SIZE__MODIFY(dst, src) \
682 (dst) = ((dst) &\
699 #define MAC_DMA_TXCFG__TRIGLVL__MODIFY(dst, src) \
700 (dst) = ((dst) &\
717 #define MAC_DMA_TXCFG__JUMBO_EN__MODIFY(dst, src) \
718 (dst) = ((dst) &\
724 #define MAC_DMA_TXCFG__JUMBO_EN__SET(dst) \
725 (dst) = ((dst) &\
727 #define MAC_DMA_TXCFG__JUMBO_EN__CLR(dst) \
728 (dst) = ((dst) &\
741 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MODIFY(dst, src) \
742 (dst) = ((dst) &\
748 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__SET(dst) \
749 (dst) = ((dst) &\
751 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__CLR(dst) \
752 (dst) = ((dst) &\
765 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MODIFY(dst, src) \
766 (dst) = ((dst) &\
772 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__SET(dst) \
773 (dst) = ((dst) &\
775 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__CLR(dst) \
776 (dst) = ((dst) &\
789 #define MAC_DMA_TXCFG__RTCI_DIS__MODIFY(dst, src) \
790 (dst) = ((dst) &\
796 #define MAC_DMA_TXCFG__RTCI_DIS__SET(dst) \
797 (dst) = ((dst) &\
799 #define MAC_DMA_TXCFG__RTCI_DIS__CLR(dst) \
800 (dst) = ((dst) &\
813 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MODIFY(dst, src) \
814 (dst) = ((dst) &\
820 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__SET(dst) \
821 (dst) = ((dst) &\
823 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__CLR(dst) \
824 (dst) = ((dst) &\
837 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MODIFY(dst, src) \
838 (dst) = ((dst) &\
844 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__SET(dst) \
845 (dst) = ((dst) &\
847 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__CLR(dst) \
848 (dst) = ((dst) &\
870 #define MAC_DMA_RXCFG__DMA_SIZE__MODIFY(dst, src) \
871 (dst) = ((dst) &\
888 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MODIFY(dst, src) \
889 (dst) = ((dst) &\
906 #define MAC_DMA_RXCFG__JUMBO_EN__MODIFY(dst, src) \
907 (dst) = ((dst) &\
913 #define MAC_DMA_RXCFG__JUMBO_EN__SET(dst) \
914 (dst) = ((dst) &\
916 #define MAC_DMA_RXCFG__JUMBO_EN__CLR(dst) \
917 (dst) = ((dst) &\
930 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MODIFY(dst, src) \
931 (dst) = ((dst) &\
937 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__SET(dst) \
938 (dst) = ((dst) &\
940 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__CLR(dst) \
941 (dst) = ((dst) &\
954 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MODIFY(dst, src) \
955 (dst) = ((dst) &\
961 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__SET(dst) \
962 (dst) = ((dst) &\
964 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__CLR(dst) \
965 (dst) = ((dst) &\
1004 #define MAC_DMA_MIBC__WARNING__SET(dst) \
1005 (dst) = ((dst) &\
1007 #define MAC_DMA_MIBC__WARNING__CLR(dst) \
1008 (dst) = ((dst) &\
1019 #define MAC_DMA_MIBC__FREEZE__MODIFY(dst, src) \
1020 (dst) = ((dst) &\
1026 #define MAC_DMA_MIBC__FREEZE__SET(dst) \
1027 (dst) = ((dst) &\
1029 #define MAC_DMA_MIBC__FREEZE__CLR(dst) \
1030 (dst) = ((dst) &\
1039 #define MAC_DMA_MIBC__CLEAR__MODIFY(dst, src) \
1040 (dst) = ((dst) &\
1046 #define MAC_DMA_MIBC__CLEAR__SET(dst) \
1047 (dst) = ((dst) &\
1049 #define MAC_DMA_MIBC__CLEAR__CLR(dst) \
1050 (dst) = ((dst) &\
1058 #define MAC_DMA_MIBC__STROBE__SET(dst) \
1059 (dst) = ((dst) &\
1061 #define MAC_DMA_MIBC__STROBE__CLR(dst) \
1062 (dst) = ((dst) &\
1084 #define MAC_DMA_TOPS__TIMEOUT__MODIFY(dst, src) \
1085 (dst) = ((dst) &\
1111 #define MAC_DMA_RXNPTO__TIMEOUT__MODIFY(dst, src) \
1112 (dst) = ((dst) &\
1138 #define MAC_DMA_TXNPTO__TIMEOUT__MODIFY(dst, src) \
1139 (dst) = ((dst) &\
1156 #define MAC_DMA_TXNPTO__MASK__MODIFY(dst, src) \
1157 (dst) = ((dst) &\
1183 #define MAC_DMA_RPGTO__TIMEOUT__MODIFY(dst, src) \
1184 (dst) = ((dst) &\
1214 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__MODIFY(dst, src) \
1215 (dst) = ((dst) &\
1221 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__SET(dst) \
1222 (dst) = ((dst) &\
1224 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__CLR(dst) \
1225 (dst) = ((dst) &\
1238 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MODIFY(dst, src) \
1239 (dst) = ((dst) &\
1256 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MODIFY(dst, src) \
1257 (dst) = ((dst) &\
1274 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MODIFY(dst, src) \
1275 (dst) = ((dst) &\
1292 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MODIFY(dst, src) \
1293 (dst) = ((dst) &\
1319 #define MAC_DMA_INTER__REQ__MODIFY(dst, src) \
1320 (dst) = ((dst) &\
1324 #define MAC_DMA_INTER__REQ__SET(dst) \
1325 (dst) = ((dst) &\
1327 #define MAC_DMA_INTER__REQ__CLR(dst) \
1328 (dst) = ((dst) &\
1341 #define MAC_DMA_INTER__MSI_RX_SRC__MODIFY(dst, src) \
1342 (dst) = ((dst) &\
1359 #define MAC_DMA_INTER__MSI_TX_SRC__MODIFY(dst, src) \
1360 (dst) = ((dst) &\
1386 #define MAC_DMA_DATABUF__LEN__MODIFY(dst, src) \
1387 (dst) = ((dst) &\
1413 #define MAC_DMA_GTT__COUNT__MODIFY(dst, src) \
1414 (dst) = ((dst) &\
1425 #define MAC_DMA_GTT__LIMIT__MODIFY(dst, src) \
1426 (dst) = ((dst) &\
1452 #define MAC_DMA_GTTM__USEC_STROBE__MODIFY(dst, src) \
1453 (dst) = ((dst) &\
1459 #define MAC_DMA_GTTM__USEC_STROBE__SET(dst) \
1460 (dst) = ((dst) &\
1462 #define MAC_DMA_GTTM__USEC_STROBE__CLR(dst) \
1463 (dst) = ((dst) &\
1476 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MODIFY(dst, src) \
1477 (dst) = ((dst) &\
1483 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__SET(dst) \
1484 (dst) = ((dst) &\
1486 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__CLR(dst) \
1487 (dst) = ((dst) &\
1500 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MODIFY(dst, src) \
1501 (dst) = ((dst) &\
1507 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__SET(dst) \
1508 (dst) = ((dst) &\
1510 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__CLR(dst) \
1511 (dst) = ((dst) &\
1524 #define MAC_DMA_GTTM__CST_USEC_STROBE__MODIFY(dst, src) \
1525 (dst) = ((dst) &\
1531 #define MAC_DMA_GTTM__CST_USEC_STROBE__SET(dst) \
1532 (dst) = ((dst) &\
1534 #define MAC_DMA_GTTM__CST_USEC_STROBE__CLR(dst) \
1535 (dst) = ((dst) &\
1548 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MODIFY(dst, src) \
1549 (dst) = ((dst) &\
1555 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__SET(dst) \
1556 (dst) = ((dst) &\
1558 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__CLR(dst) \
1559 (dst) = ((dst) &\
1572 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MODIFY(dst, src) \
1573 (dst) = ((dst) &\
1579 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__SET(dst) \
1580 (dst) = ((dst) &\
1582 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__CLR(dst) \
1583 (dst) = ((dst) &\
1605 #define MAC_DMA_CST__COUNT__MODIFY(dst, src) \
1606 (dst) = ((dst) &\
1617 #define MAC_DMA_CST__LIMIT__MODIFY(dst, src) \
1618 (dst) = ((dst) &\
1674 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MODIFY(dst, src) \
1675 (dst) = ((dst) &\
1705 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MODIFY(dst, src) \
1706 (dst) = ((dst) &\
1732 #define MAC_DMA_ISR_P__DATA__MODIFY(dst, src) \
1733 (dst) = ((dst) &\
1757 #define MAC_DMA_ISR_S0__DATA__MODIFY(dst, src) \
1758 (dst) = ((dst) &\
1784 #define MAC_DMA_ISR_S1__DATA__MODIFY(dst, src) \
1785 (dst) = ((dst) &\
1811 #define MAC_DMA_ISR_S2__DATA__MODIFY(dst, src) \
1812 (dst) = ((dst) &\
1838 #define MAC_DMA_ISR_S3__DATA__MODIFY(dst, src) \
1839 (dst) = ((dst) &\
1865 #define MAC_DMA_ISR_S4__DATA__MODIFY(dst, src) \
1866 (dst) = ((dst) &\
1892 #define MAC_DMA_ISR_S5__DATA__MODIFY(dst, src) \
1893 (dst) = ((dst) &\
1919 #define MAC_DMA_IMR_P__MASK__MODIFY(dst, src) \
1920 (dst) = ((dst) &\
1944 #define MAC_DMA_IMR_S0__MASK__MODIFY(dst, src) \
1945 (dst) = ((dst) &\
1971 #define MAC_DMA_IMR_S1__DATA__MODIFY(dst, src) \
1972 (dst) = ((dst) &\
1998 #define MAC_DMA_IMR_S2__MASK__MODIFY(dst, src) \
1999 (dst) = ((dst) &\
2025 #define MAC_DMA_IMR_S3__MASK__MODIFY(dst, src) \
2026 (dst) = ((dst) &\
2052 #define MAC_DMA_IMR_S4__MASK__MODIFY(dst, src) \
2053 (dst) = ((dst) &\
2079 #define MAC_DMA_IMR_S5__MASK__MODIFY(dst, src) \
2080 (dst) = ((dst) &\
2416 #define MAC_QCU_TXDP__DATA__MODIFY(dst, src) \
2417 (dst) = ((dst) &\
2445 #define MAC_QCU_STATUS_RING_START__ADDR__MODIFY(dst, src) \
2446 (dst) = ((dst) &\
2474 #define MAC_QCU_STATUS_RING_END__ADDR__MODIFY(dst, src) \
2475 (dst) = ((dst) &\
2539 #define MAC_QCU_TXD__DATA__MODIFY(dst, src) \
2540 (dst) = ((dst) &\
2564 #define MAC_QCU_CBR__INTERVAL__MODIFY(dst, src) \
2565 (dst) = ((dst) &\
2582 #define MAC_QCU_CBR__OVF_THRESH__MODIFY(dst, src) \
2583 (dst) = ((dst) &\
2609 #define MAC_QCU_RDYTIME__DURATION__MODIFY(dst, src) \
2610 (dst) = ((dst) &\
2625 #define MAC_QCU_RDYTIME__EN__MODIFY(dst, src) \
2626 (dst) = ((dst) &\
2632 #define MAC_QCU_RDYTIME__EN__SET(dst) \
2633 (dst) = ((dst) &\
2635 #define MAC_QCU_RDYTIME__EN__CLR(dst) \
2636 (dst) = ((dst) &\
2660 #define MAC_QCU_ONESHOT_ARM_SC__SET__MODIFY(dst, src) \
2661 (dst) = ((dst) &\
2689 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MODIFY(dst, src) \
2690 (dst) = ((dst) &\
2716 #define MAC_QCU_MISC__FSP__MODIFY(dst, src) \
2717 (dst) = ((dst) &\
2732 #define MAC_QCU_MISC__ONESHOT_EN__MODIFY(dst, src) \
2733 (dst) = ((dst) &\
2739 #define MAC_QCU_MISC__ONESHOT_EN__SET(dst) \
2740 (dst) = ((dst) &\
2742 #define MAC_QCU_MISC__ONESHOT_EN__CLR(dst) \
2743 (dst) = ((dst) &\
2756 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MODIFY(dst, src) \
2757 (dst) = ((dst) &\
2763 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__SET(dst) \
2764 (dst) = ((dst) &\
2766 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__CLR(dst) \
2767 (dst) = ((dst) &\
2780 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MODIFY(dst, src) \
2781 (dst) = ((dst) &\
2787 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__SET(dst) \
2788 (dst) = ((dst) &\
2790 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__CLR(dst) \
2791 (dst) = ((dst) &\
2802 #define MAC_QCU_MISC__IS_BCN__MODIFY(dst, src) \
2803 (dst) = ((dst) &\
2809 #define MAC_QCU_MISC__IS_BCN__SET(dst) \
2810 (dst) = ((dst) &\
2812 #define MAC_QCU_MISC__IS_BCN__CLR(dst) \
2813 (dst) = ((dst) &\
2826 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MODIFY(dst, src) \
2827 (dst) = ((dst) &\
2833 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__SET(dst) \
2834 (dst) = ((dst) &\
2836 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__CLR(dst) \
2837 (dst) = ((dst) &\
2850 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MODIFY(dst, src) \
2851 (dst) = ((dst) &\
2857 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__SET(dst) \
2858 (dst) = ((dst) &\
2860 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__CLR(dst) \
2861 (dst) = ((dst) &\
2874 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MODIFY(dst, src) \
2875 (dst) = ((dst) &\
2881 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__SET(dst) \
2882 (dst) = ((dst) &\
2884 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__CLR(dst) \
2885 (dst) = ((dst) &\
2898 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__MODIFY(dst, src) \
2899 (dst) = ((dst) &\
2905 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__SET(dst) \
2906 (dst) = ((dst) &\
2908 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__CLR(dst) \
2909 (dst) = ((dst) &\
2959 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MODIFY(dst, src) \
2960 (dst) = ((dst) &\
2987 #define MAC_QCU_DESC_CRC_CHK__EN__MODIFY(dst, src) \
2988 (dst) = ((dst) &\
2994 #define MAC_QCU_DESC_CRC_CHK__EN__SET(dst) \
2995 (dst) = ((dst) &\
2997 #define MAC_QCU_DESC_CRC_CHK__EN__CLR(dst) \
2998 (dst) = ((dst) &\
3020 #define MAC_DCU_QCUMASK__DATA__MODIFY(dst, src) \
3021 (dst) = ((dst) &\
3051 #define MAC_DCU_GBL_IFS_SIFS__DURATION__MODIFY(dst, src) \
3052 (dst) = ((dst) &\
3082 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MODIFY(dst, src) \
3083 (dst) = ((dst) &\
3129 #define MAC_DCU_LCL_IFS__CW_MIN__MODIFY(dst, src) \
3130 (dst) = ((dst) &\
3147 #define MAC_DCU_LCL_IFS__CW_MAX__MODIFY(dst, src) \
3148 (dst) = ((dst) &\
3165 #define MAC_DCU_LCL_IFS__AIFS__MODIFY(dst, src) \
3166 (dst) = ((dst) &\
3183 #define MAC_DCU_LCL_IFS__LONG_AIFS__MODIFY(dst, src) \
3184 (dst) = ((dst) &\
3190 #define MAC_DCU_LCL_IFS__LONG_AIFS__SET(dst) \
3191 (dst) = ((dst) &\
3193 #define MAC_DCU_LCL_IFS__LONG_AIFS__CLR(dst) \
3194 (dst) = ((dst) &\
3220 #define MAC_DCU_GBL_IFS_SLOT__DURATION__MODIFY(dst, src) \
3221 (dst) = ((dst) &\
3251 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MODIFY(dst, src) \
3252 (dst) = ((dst) &\
3298 #define MAC_DCU_RETRY_LIMIT__FRFL__MODIFY(dst, src) \
3299 (dst) = ((dst) &\
3316 #define MAC_DCU_RETRY_LIMIT__SRFL__MODIFY(dst, src) \
3317 (dst) = ((dst) &\
3334 #define MAC_DCU_RETRY_LIMIT__SDFL__MODIFY(dst, src) \
3335 (dst) = ((dst) &\
3365 #define MAC_DCU_GBL_IFS_EIFS__DURATION__MODIFY(dst, src) \
3366 (dst) = ((dst) &\
3396 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MODIFY(dst, src) \
3397 (dst) = ((dst) &\
3447 #define MAC_DCU_CHANNEL_TIME__DURATION__MODIFY(dst, src) \
3448 (dst) = ((dst) &\
3465 #define MAC_DCU_CHANNEL_TIME__ENABLE__MODIFY(dst, src) \
3466 (dst) = ((dst) &\
3472 #define MAC_DCU_CHANNEL_TIME__ENABLE__SET(dst) \
3473 (dst) = ((dst) &\
3475 #define MAC_DCU_CHANNEL_TIME__ENABLE__CLR(dst) \
3476 (dst) = ((dst) &\
3502 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MODIFY(dst, src) \
3503 (dst) = ((dst) &\
3520 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MODIFY(dst, src) \
3521 (dst) = ((dst) &\
3527 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__SET(dst) \
3528 (dst) = ((dst) &\
3530 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__CLR(dst) \
3531 (dst) = ((dst) &\
3544 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MODIFY(dst, src) \
3545 (dst) = ((dst) &\
3562 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MODIFY(dst, src) \
3563 (dst) = ((dst) &\
3580 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MODIFY(dst, src) \
3581 (dst) = ((dst) &\
3587 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__SET(dst) \
3588 (dst) = ((dst) &\
3590 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__CLR(dst) \
3591 (dst) = ((dst) &\
3604 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MODIFY(dst, src) \
3605 (dst) = ((dst) &\
3611 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__SET(dst) \
3612 (dst) = ((dst) &\
3614 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__CLR(dst) \
3615 (dst) = ((dst) &\
3628 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MODIFY(dst, src) \
3629 (dst) = ((dst) &\
3635 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__SET(dst) \
3636 (dst) = ((dst) &\
3638 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__CLR(dst) \
3639 (dst) = ((dst) &\
3652 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MODIFY(dst, src) \
3653 (dst) = ((dst) &\
3670 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MODIFY(dst, src) \
3671 (dst) = ((dst) &\
3677 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__SET(dst) \
3678 (dst) = ((dst) &\
3680 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__CLR(dst) \
3681 (dst) = ((dst) &\
3694 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MODIFY(dst, src) \
3695 (dst) = ((dst) &\
3701 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__SET(dst) \
3702 (dst) = ((dst) &\
3704 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__CLR(dst) \
3705 (dst) = ((dst) &\
3731 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MODIFY(dst, src) \
3732 (dst) = ((dst) &\
3778 #define MAC_DCU_MISC__BKOFF_THRESH__MODIFY(dst, src) \
3779 (dst) = ((dst) &\
3796 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MODIFY(dst, src) \
3797 (dst) = ((dst) &\
3803 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__SET(dst) \
3804 (dst) = ((dst) &\
3806 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__CLR(dst) \
3807 (dst) = ((dst) &\
3820 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MODIFY(dst, src) \
3821 (dst) = ((dst) &\
3827 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__SET(dst) \
3828 (dst) = ((dst) &\
3830 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__CLR(dst) \
3831 (dst) = ((dst) &\
3844 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MODIFY(dst, src) \
3845 (dst) = ((dst) &\
3851 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__SET(dst) \
3852 (dst) = ((dst) &\
3854 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__CLR(dst) \
3855 (dst) = ((dst) &\
3868 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MODIFY(dst, src) \
3869 (dst) = ((dst) &\
3875 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__SET(dst) \
3876 (dst) = ((dst) &\
3878 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__CLR(dst) \
3879 (dst) = ((dst) &\
3892 #define MAC_DCU_MISC__HCF_POLL_EN__MODIFY(dst, src) \
3893 (dst) = ((dst) &\
3899 #define MAC_DCU_MISC__HCF_POLL_EN__SET(dst) \
3900 (dst) = ((dst) &\
3902 #define MAC_DCU_MISC__HCF_POLL_EN__CLR(dst) \
3903 (dst) = ((dst) &\
3916 #define MAC_DCU_MISC__BKOFF_PF__MODIFY(dst, src) \
3917 (dst) = ((dst) &\
3923 #define MAC_DCU_MISC__BKOFF_PF__SET(dst) \
3924 (dst) = ((dst) &\
3926 #define MAC_DCU_MISC__BKOFF_PF__CLR(dst) \
3927 (dst) = ((dst) &\
3940 #define MAC_DCU_MISC__VIRT_COLL_POLICY__MODIFY(dst, src) \
3941 (dst) = ((dst) &\
3958 #define MAC_DCU_MISC__IS_BCN__MODIFY(dst, src) \
3959 (dst) = ((dst) &\
3965 #define MAC_DCU_MISC__IS_BCN__SET(dst) \
3966 (dst) = ((dst) &\
3968 #define MAC_DCU_MISC__IS_BCN__CLR(dst) \
3969 (dst) = ((dst) &\
3982 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MODIFY(dst, src) \
3983 (dst) = ((dst) &\
3989 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__SET(dst) \
3990 (dst) = ((dst) &\
3992 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__CLR(dst) \
3993 (dst) = ((dst) &\
4006 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__MODIFY(dst, src) \
4007 (dst) = ((dst) &\
4013 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__SET(dst) \
4014 (dst) = ((dst) &\
4016 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__CLR(dst) \
4017 (dst) = ((dst) &\
4030 #define MAC_DCU_MISC__LOCKOUT_IGNORE__MODIFY(dst, src) \
4031 (dst) = ((dst) &\
4037 #define MAC_DCU_MISC__LOCKOUT_IGNORE__SET(dst) \
4038 (dst) = ((dst) &\
4040 #define MAC_DCU_MISC__LOCKOUT_IGNORE__CLR(dst) \
4041 (dst) = ((dst) &\
4054 #define MAC_DCU_MISC__SEQNUM_FREEZE__MODIFY(dst, src) \
4055 (dst) = ((dst) &\
4061 #define MAC_DCU_MISC__SEQNUM_FREEZE__SET(dst) \
4062 (dst) = ((dst) &\
4064 #define MAC_DCU_MISC__SEQNUM_FREEZE__CLR(dst) \
4065 (dst) = ((dst) &\
4078 #define MAC_DCU_MISC__POST_BKOFF_SKIP__MODIFY(dst, src) \
4079 (dst) = ((dst) &\
4085 #define MAC_DCU_MISC__POST_BKOFF_SKIP__SET(dst) \
4086 (dst) = ((dst) &\
4088 #define MAC_DCU_MISC__POST_BKOFF_SKIP__CLR(dst) \
4089 (dst) = ((dst) &\
4102 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MODIFY(dst, src) \
4103 (dst) = ((dst) &\
4109 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__SET(dst) \
4110 (dst) = ((dst) &\
4112 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__CLR(dst) \
4113 (dst) = ((dst) &\
4126 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MODIFY(dst, src) \
4127 (dst) = ((dst) &\
4133 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__SET(dst) \
4134 (dst) = ((dst) &\
4136 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__CLR(dst) \
4137 (dst) = ((dst) &\
4150 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MODIFY(dst, src) \
4151 (dst) = ((dst) &\
4157 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__SET(dst) \
4158 (dst) = ((dst) &\
4160 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__CLR(dst) \
4161 (dst) = ((dst) &\
4223 #define MAC_DCU_SEQ__NUM__MODIFY(dst, src) \
4224 (dst) = ((dst) &\
4388 #define MAC_DCU_PAUSE__REQUEST__MODIFY(dst, src) \
4389 (dst) = ((dst) &\
4403 #define MAC_DCU_PAUSE__STATUS__SET(dst) \
4404 (dst) = ((dst) &\
4406 #define MAC_DCU_PAUSE__STATUS__CLR(dst) \
4407 (dst) = ((dst) &\
4449 #define MAC_DCU_WOW_KACFG__TX_EN__MODIFY(dst, src) \
4450 (dst) = ((dst) &\
4456 #define MAC_DCU_WOW_KACFG__TX_EN__SET(dst) \
4457 (dst) = ((dst) &\
4459 #define MAC_DCU_WOW_KACFG__TX_EN__CLR(dst) \
4460 (dst) = ((dst) &\
4473 #define MAC_DCU_WOW_KACFG__TIM_EN__MODIFY(dst, src) \
4474 (dst) = ((dst) &\
4480 #define MAC_DCU_WOW_KACFG__TIM_EN__SET(dst) \
4481 (dst) = ((dst) &\
4483 #define MAC_DCU_WOW_KACFG__TIM_EN__CLR(dst) \
4484 (dst) = ((dst) &\
4497 #define MAC_DCU_WOW_KACFG__BCN_CNT__MODIFY(dst, src) \
4498 (dst) = ((dst) &\
4515 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MODIFY(dst, src) \
4516 (dst) = ((dst) &\
4562 #define MAC_DCU_TXSLOT__MASK__MODIFY(dst, src) \
4563 (dst) = ((dst) &\
4711 #define MAC_DCU_TXFILTER_CLEAR__DATA__MODIFY(dst, src) \
4712 (dst) = ((dst) &\
4758 #define MAC_DCU_TXFILTER_SET__DATA__MODIFY(dst, src) \
4759 (dst) = ((dst) &\
5069 #define HOST_INTF_RESET_CONTROL__AHB_RESET__MODIFY(dst, src) \
5070 (dst) = ((dst) &\
5076 #define HOST_INTF_RESET_CONTROL__AHB_RESET__SET(dst) \
5077 (dst) = ((dst) &\
5079 #define HOST_INTF_RESET_CONTROL__AHB_RESET__CLR(dst) \
5080 (dst) = ((dst) &\
5093 #define HOST_INTF_RESET_CONTROL__APB_RESET__MODIFY(dst, src) \
5094 (dst) = ((dst) &\
5100 #define HOST_INTF_RESET_CONTROL__APB_RESET__SET(dst) \
5101 (dst) = ((dst) &\
5103 #define HOST_INTF_RESET_CONTROL__APB_RESET__CLR(dst) \
5104 (dst) = ((dst) &\
5117 #define HOST_INTF_RESET_CONTROL__LOCAL_RESET__MODIFY(dst, src) \
5118 (dst) = ((dst) &\
5124 #define HOST_INTF_RESET_CONTROL__LOCAL_RESET__SET(dst) \
5125 (dst) = ((dst) &\
5127 #define HOST_INTF_RESET_CONTROL__LOCAL_RESET__CLR(dst) \
5128 (dst) = ((dst) &\
5154 #define HOST_INTF_WORK_AROUND__TS1_WA_EN__MODIFY(dst, src) \
5155 (dst) = ((dst) &\
5161 #define HOST_INTF_WORK_AROUND__TS1_WA_EN__SET(dst) \
5162 (dst) = ((dst) &\
5164 #define HOST_INTF_WORK_AROUND__TS1_WA_EN__CLR(dst) \
5165 (dst) = ((dst) &\
5178 #define HOST_INTF_WORK_AROUND__TS2_WA_EN__MODIFY(dst, src) \
5179 (dst) = ((dst) &\
5185 #define HOST_INTF_WORK_AROUND__TS2_WA_EN__SET(dst) \
5186 (dst) = ((dst) &\
5188 #define HOST_INTF_WORK_AROUND__TS2_WA_EN__CLR(dst) \
5189 (dst) = ((dst) &\
5202 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__MODIFY(dst, src) \
5203 (dst) = ((dst) &\
5209 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__SET(dst) \
5210 (dst) = ((dst) &\
5212 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__CLR(dst) \
5213 (dst) = ((dst) &\
5226 #define HOST_INTF_WORK_AROUND__GDATA_WA_EN__MODIFY(dst, src) \
5227 (dst) = ((dst) &\
5233 #define HOST_INTF_WORK_AROUND__GDATA_WA_EN__SET(dst) \
5234 (dst) = ((dst) &\
5236 #define HOST_INTF_WORK_AROUND__GDATA_WA_EN__CLR(dst) \
5237 (dst) = ((dst) &\
5250 #define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__MODIFY(dst, src) \
5251 (dst) = ((dst) &\
5257 #define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__SET(dst) \
5258 (dst) = ((dst) &\
5260 #define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__CLR(dst) \
5261 (dst) = ((dst) &\
5274 #define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__MODIFY(dst, src) \
5275 (dst) = ((dst) &\
5281 #define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__SET(dst) \
5282 (dst) = ((dst) &\
5284 #define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__CLR(dst) \
5285 (dst) = ((dst) &\
5298 #define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__MODIFY(dst, src) \
5299 (dst) = ((dst) &\
5305 #define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__SET(dst) \
5306 (dst) = ((dst) &\
5308 #define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__CLR(dst) \
5309 (dst) = ((dst) &\
5322 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__MODIFY(dst, src) \
5323 (dst) = ((dst) &\
5329 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__SET(dst) \
5330 (dst) = ((dst) &\
5332 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__CLR(dst) \
5333 (dst) = ((dst) &\
5346 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__MODIFY(dst, src) \
5347 (dst) = ((dst) &\
5353 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__SET(dst) \
5354 (dst) = ((dst) &\
5356 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__CLR(dst) \
5357 (dst) = ((dst) &\
5370 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__MODIFY(dst, src) \
5371 (dst) = ((dst) &\
5377 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__SET(dst) \
5378 (dst) = ((dst) &\
5380 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__CLR(dst) \
5381 (dst) = ((dst) &\
5394 #define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__MODIFY(dst, src) \
5395 (dst) = ((dst) &\
5401 #define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__SET(dst) \
5402 (dst) = ((dst) &\
5404 #define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__CLR(dst) \
5405 (dst) = ((dst) &\
5418 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__MODIFY(dst, src) \
5419 (dst) = ((dst) &\
5425 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__SET(dst) \
5426 (dst) = ((dst) &\
5428 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__CLR(dst) \
5429 (dst) = ((dst) &\
5442 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__MODIFY(dst, src) \
5443 (dst) = ((dst) &\
5449 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__SET(dst) \
5450 (dst) = ((dst) &\
5452 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__CLR(dst) \
5453 (dst) = ((dst) &\
5466 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__MODIFY(dst, src) \
5467 (dst) = ((dst) &\
5473 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__SET(dst) \
5474 (dst) = ((dst) &\
5476 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__CLR(dst) \
5477 (dst) = ((dst) &\
5490 #define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__MODIFY(dst, src) \
5491 (dst) = ((dst) &\
5497 #define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__SET(dst) \
5498 (dst) = ((dst) &\
5500 #define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__CLR(dst) \
5501 (dst) = ((dst) &\
5514 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__MODIFY(dst, src) \
5515 (dst) = ((dst) &\
5542 #define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__SET(dst) \
5543 (dst) = ((dst) &\
5545 #define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__CLR(dst) \
5546 (dst) = ((dst) &\
5572 #define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__SET(dst) \
5573 (dst) = ((dst) &\
5575 #define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__CLR(dst) \
5576 (dst) = ((dst) &\
5586 #define HOST_INTF_PM_STATE__PCIE_PM_STATUS__SET(dst) \
5587 (dst) = ((dst) &\
5589 #define HOST_INTF_PM_STATE__PCIE_PM_STATUS__CLR(dst) \
5590 (dst) = ((dst) &\
5600 #define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__SET(dst) \
5601 (dst) = ((dst) &\
5603 #define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__CLR(dst) \
5604 (dst) = ((dst) &\
5622 #define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__SET(dst) \
5623 (dst) = ((dst) &\
5625 #define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__CLR(dst) \
5626 (dst) = ((dst) &\
5636 #define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__SET(dst) \
5637 (dst) = ((dst) &\
5639 #define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__CLR(dst) \
5640 (dst) = ((dst) &\
5650 #define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__SET(dst) \
5651 (dst) = ((dst) &\
5653 #define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__CLR(dst) \
5654 (dst) = ((dst) &\
5719 #define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__MODIFY(dst, src) \
5720 (dst) = ((dst) &\
5726 #define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__SET(dst) \
5727 (dst) = ((dst) &\
5729 #define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__CLR(dst) \
5730 (dst) = ((dst) &\
5743 #define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__MODIFY(dst, src) \
5744 (dst) = ((dst) &\
5761 #define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__MODIFY(dst, src) \
5762 (dst) = ((dst) &\
5768 #define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__SET(dst) \
5769 (dst) = ((dst) &\
5771 #define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__CLR(dst) \
5772 (dst) = ((dst) &\
5785 #define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__MODIFY(dst, src) \
5786 (dst) = ((dst) &\
5792 #define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__SET(dst) \
5793 (dst) = ((dst) &\
5795 #define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__CLR(dst) \
5796 (dst) = ((dst) &\
5809 #define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__MODIFY(dst, src) \
5810 (dst) = ((dst) &\
5816 #define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__SET(dst) \
5817 (dst) = ((dst) &\
5819 #define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__CLR(dst) \
5820 (dst) = ((dst) &\
5833 #define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__MODIFY(dst, src) \
5834 (dst) = ((dst) &\
5840 #define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__SET(dst) \
5841 (dst) = ((dst) &\
5843 #define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__CLR(dst) \
5844 (dst) = ((dst) &\
5857 #define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__MODIFY(dst, src) \
5858 (dst) = ((dst) &\
5864 #define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__SET(dst) \
5865 (dst) = ((dst) &\
5867 #define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__CLR(dst) \
5868 (dst) = ((dst) &\
5881 #define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__MODIFY(dst, src) \
5882 (dst) = ((dst) &\
5899 #define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__MODIFY(dst, src) \
5900 (dst) = ((dst) &\
5906 #define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__SET(dst) \
5907 (dst) = ((dst) &\
5909 #define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__CLR(dst) \
5910 (dst) = ((dst) &\
5923 #define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__MODIFY(dst, src) \
5924 (dst) = ((dst) &\
5930 #define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__SET(dst) \
5931 (dst) = ((dst) &\
5933 #define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__CLR(dst) \
5934 (dst) = ((dst) &\
5947 #define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__MODIFY(dst, src) \
5948 (dst) = ((dst) &\
5954 #define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__SET(dst) \
5955 (dst) = ((dst) &\
5957 #define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__CLR(dst) \
5958 (dst) = ((dst) &\
5984 #define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__MODIFY(dst, src) \
5985 (dst) = ((dst) &\
6002 #define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__MODIFY(dst, src) \
6003 (dst) = ((dst) &\
6033 #define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__MODIFY(dst, src) \
6034 (dst) = ((dst) &\
6040 #define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__SET(dst) \
6041 (dst) = ((dst) &\
6043 #define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__CLR(dst) \
6044 (dst) = ((dst) &\
6057 #define HOST_INTF_EEPROM_CTRL__FORCE_RESET__MODIFY(dst, src) \
6058 (dst) = ((dst) &\
6064 #define HOST_INTF_EEPROM_CTRL__FORCE_RESET__SET(dst) \
6065 (dst) = ((dst) &\
6067 #define HOST_INTF_EEPROM_CTRL__FORCE_RESET__CLR(dst) \
6068 (dst) = ((dst) &\
6081 #define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__MODIFY(dst, src) \
6082 (dst) = ((dst) &\
6096 #define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__SET(dst) \
6097 (dst) = ((dst) &\
6099 #define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__CLR(dst) \
6100 (dst) = ((dst) &\
6110 #define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__SET(dst) \
6111 (dst) = ((dst) &\
6113 #define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__CLR(dst) \
6114 (dst) = ((dst) &\
6166 #define HOST_INTF_INTR_SYNC_CAUSE__DATA__MODIFY(dst, src) \
6167 (dst) = ((dst) &\
6197 #define HOST_INTF_INTR_SYNC_ENABLE__DATA__MODIFY(dst, src) \
6198 (dst) = ((dst) &\
6228 #define HOST_INTF_INTR_ASYNC_MASK__DATA__MODIFY(dst, src) \
6229 (dst) = ((dst) &\
6259 #define HOST_INTF_INTR_SYNC_MASK__DATA__MODIFY(dst, src) \
6260 (dst) = ((dst) &\
6310 #define HOST_INTF_INTR_ASYNC_ENABLE__DATA__MODIFY(dst, src) \
6311 (dst) = ((dst) &\
6339 #define HOST_INTF_PCIE_PHY_RW__DATA__MODIFY(dst, src) \
6340 (dst) = ((dst) &\
6368 #define HOST_INTF_PCIE_PHY_LOAD__DATA__MODIFY(dst, src) \
6369 (dst) = ((dst) &\
6395 #define HOST_INTF_GPIO_OUT__OUT__MODIFY(dst, src) \
6396 (dst) = ((dst) &\
6440 #define HOST_INTF_GPIO_OE__DATA__MODIFY(dst, src) \
6441 (dst) = ((dst) &\
6467 #define HOST_INTF_GPIO_OE1__DATA__MODIFY(dst, src) \
6468 (dst) = ((dst) &\
6498 #define HOST_INTF_GPIO_INTR_POLAR__DATA__MODIFY(dst, src) \
6499 (dst) = ((dst) &\
6529 #define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__MODIFY(dst, src) \
6530 (dst) = ((dst) &\
6536 #define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__SET(dst) \
6537 (dst) = ((dst) &\
6539 #define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__CLR(dst) \
6540 (dst) = ((dst) &\
6553 #define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__MODIFY(dst, src) \
6554 (dst) = ((dst) &\
6560 #define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__SET(dst) \
6561 (dst) = ((dst) &\
6563 #define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__CLR(dst) \
6564 (dst) = ((dst) &\
6577 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__MODIFY(dst, src) \
6578 (dst) = ((dst) &\
6584 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__SET(dst) \
6585 (dst) = ((dst) &\
6587 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__CLR(dst) \
6588 (dst) = ((dst) &\
6601 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__MODIFY(dst, src) \
6602 (dst) = ((dst) &\
6608 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__SET(dst) \
6609 (dst) = ((dst) &\
6611 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__CLR(dst) \
6612 (dst) = ((dst) &\
6625 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__MODIFY(dst, src) \
6626 (dst) = ((dst) &\
6632 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__SET(dst) \
6633 (dst) = ((dst) &\
6635 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__CLR(dst) \
6636 (dst) = ((dst) &\
6649 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__MODIFY(dst, src) \
6650 (dst) = ((dst) &\
6656 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__SET(dst) \
6657 (dst) = ((dst) &\
6659 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__CLR(dst) \
6660 (dst) = ((dst) &\
6673 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__MODIFY(dst, src) \
6674 (dst) = ((dst) &\
6680 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__SET(dst) \
6681 (dst) = ((dst) &\
6683 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__CLR(dst) \
6684 (dst) = ((dst) &\
6697 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__MODIFY(dst, src) \
6698 (dst) = ((dst) &\
6704 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__SET(dst) \
6705 (dst) = ((dst) &\
6707 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__CLR(dst) \
6708 (dst) = ((dst) &\
6721 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__MODIFY(dst, src) \
6722 (dst) = ((dst) &\
6728 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__SET(dst) \
6729 (dst) = ((dst) &\
6731 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__CLR(dst) \
6732 (dst) = ((dst) &\
6745 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__MODIFY(dst, src) \
6746 (dst) = ((dst) &\
6752 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__SET(dst) \
6753 (dst) = ((dst) &\
6755 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__CLR(dst) \
6756 (dst) = ((dst) &\
6769 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__MODIFY(dst, src) \
6770 (dst) = ((dst) &\
6776 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__SET(dst) \
6777 (dst) = ((dst) &\
6779 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__CLR(dst) \
6780 (dst) = ((dst) &\
6793 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__MODIFY(dst, src) \
6794 (dst) = ((dst) &\
6800 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__SET(dst) \
6801 (dst) = ((dst) &\
6803 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__CLR(dst) \
6804 (dst) = ((dst) &\
6817 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__MODIFY(dst, src) \
6818 (dst) = ((dst) &\
6824 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__SET(dst) \
6825 (dst) = ((dst) &\
6827 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__CLR(dst) \
6828 (dst) = ((dst) &\
6841 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__MODIFY(dst, src) \
6842 (dst) = ((dst) &\
6848 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__SET(dst) \
6849 (dst) = ((dst) &\
6851 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__CLR(dst) \
6852 (dst) = ((dst) &\
6865 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__MODIFY(dst, src) \
6866 (dst) = ((dst) &\
6872 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__SET(dst) \
6873 (dst) = ((dst) &\
6875 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__CLR(dst) \
6876 (dst) = ((dst) &\
6889 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__MODIFY(dst, src) \
6890 (dst) = ((dst) &\
6896 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__SET(dst) \
6897 (dst) = ((dst) &\
6899 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__CLR(dst) \
6900 (dst) = ((dst) &\
6913 #define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__MODIFY(dst, src) \
6914 (dst) = ((dst) &\
6920 #define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__SET(dst) \
6921 (dst) = ((dst) &\
6923 #define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__CLR(dst) \
6924 (dst) = ((dst) &\
6937 #define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__MODIFY(dst, src) \
6938 (dst) = ((dst) &\
6944 #define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__SET(dst) \
6945 (dst) = ((dst) &\
6947 #define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__CLR(dst) \
6948 (dst) = ((dst) &\
6961 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__MODIFY(dst, src) \
6962 (dst) = ((dst) &\
6968 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__SET(dst) \
6969 (dst) = ((dst) &\
6971 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__CLR(dst) \
6972 (dst) = ((dst) &\
6985 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__MODIFY(dst, src) \
6986 (dst) = ((dst) &\
6992 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__SET(dst) \
6993 (dst) = ((dst) &\
6995 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__CLR(dst) \
6996 (dst) = ((dst) &\
7009 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__MODIFY(dst, src) \
7010 (dst) = ((dst) &\
7016 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__SET(dst) \
7017 (dst) = ((dst) &\
7019 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__CLR(dst) \
7020 (dst) = ((dst) &\
7033 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__MODIFY(dst, src) \
7034 (dst) = ((dst) &\
7040 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__SET(dst) \
7041 (dst) = ((dst) &\
7043 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__CLR(dst) \
7044 (dst) = ((dst) &\
7070 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__MODIFY(dst, src) \
7071 (dst) = ((dst) &\
7088 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__MODIFY(dst, src) \
7089 (dst) = ((dst) &\
7106 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__MODIFY(dst, src) \
7107 (dst) = ((dst) &\
7124 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__MODIFY(dst, src) \
7125 (dst) = ((dst) &\
7142 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__MODIFY(dst, src) \
7143 (dst) = ((dst) &\
7160 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__MODIFY(dst, src) \
7161 (dst) = ((dst) &\
7191 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__MODIFY(dst, src) \
7192 (dst) = ((dst) &\
7209 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__MODIFY(dst, src) \
7210 (dst) = ((dst) &\
7227 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__MODIFY(dst, src) \
7228 (dst) = ((dst) &\
7245 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__MODIFY(dst, src) \
7246 (dst) = ((dst) &\
7263 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__MODIFY(dst, src) \
7264 (dst) = ((dst) &\
7294 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__MODIFY(dst, src) \
7295 (dst) = ((dst) &\
7312 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__MODIFY(dst, src) \
7313 (dst) = ((dst) &\
7330 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__MODIFY(dst, src) \
7331 (dst) = ((dst) &\
7348 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__MODIFY(dst, src) \
7349 (dst) = ((dst) &\
7366 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__MODIFY(dst, src) \
7367 (dst) = ((dst) &\
7384 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__MODIFY(dst, src) \
7385 (dst) = ((dst) &\
7415 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__MODIFY(dst, src) \
7416 (dst) = ((dst) &\
7433 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__MODIFY(dst, src) \
7434 (dst) = ((dst) &\
7451 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__MODIFY(dst, src) \
7452 (dst) = ((dst) &\
7469 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__MODIFY(dst, src) \
7470 (dst) = ((dst) &\
7487 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__MODIFY(dst, src) \
7488 (dst) = ((dst) &\
7505 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__MODIFY(dst, src) \
7506 (dst) = ((dst) &\
7536 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__MODIFY(dst, src) \
7537 (dst) = ((dst) &\
7554 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__MODIFY(dst, src) \
7555 (dst) = ((dst) &\
7572 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__MODIFY(dst, src) \
7573 (dst) = ((dst) &\
7590 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__MODIFY(dst, src) \
7591 (dst) = ((dst) &\
7608 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__MODIFY(dst, src) \
7609 (dst) = ((dst) &\
7636 #define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__SET(dst) \
7637 (dst) = ((dst) &\
7639 #define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__CLR(dst) \
7640 (dst) = ((dst) &\
7650 #define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__SET(dst) \
7651 (dst) = ((dst) &\
7653 #define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__CLR(dst) \
7654 (dst) = ((dst) &\
7664 #define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__SET(dst) \
7665 (dst) = ((dst) &\
7667 #define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__CLR(dst) \
7668 (dst) = ((dst) &\
7678 #define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__SET(dst) \
7679 (dst) = ((dst) &\
7681 #define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__CLR(dst) \
7682 (dst) = ((dst) &\
7692 #define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__SET(dst) \
7693 (dst) = ((dst) &\
7695 #define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__CLR(dst) \
7696 (dst) = ((dst) &\
7706 #define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__SET(dst) \
7707 (dst) = ((dst) &\
7709 #define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__CLR(dst) \
7710 (dst) = ((dst) &\
7720 #define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__SET(dst) \
7721 (dst) = ((dst) &\
7723 #define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__CLR(dst) \
7724 (dst) = ((dst) &\
7734 #define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__SET(dst) \
7735 (dst) = ((dst) &\
7737 #define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__CLR(dst) \
7738 (dst) = ((dst) &\
7763 #define HOST_INTF_SPARE__SUPER_CONDOR_L1__MODIFY(dst, src) \
7764 (dst) = ((dst) &\
7794 #define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__MODIFY(dst, src) \
7795 (dst) = ((dst) &\
7801 #define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__SET(dst) \
7802 (dst) = ((dst) &\
7804 #define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__CLR(dst) \
7805 (dst) = ((dst) &\
7818 #define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__MODIFY(dst, src) \
7819 (dst) = ((dst) &\
7825 #define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__SET(dst) \
7826 (dst) = ((dst) &\
7828 #define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__CLR(dst) \
7829 (dst) = ((dst) &\
7842 #define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__MODIFY(dst, src) \
7843 (dst) = ((dst) &\
7849 #define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__SET(dst) \
7850 (dst) = ((dst) &\
7852 #define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__CLR(dst) \
7853 (dst) = ((dst) &\
7866 #define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__MODIFY(dst, src) \
7867 (dst) = ((dst) &\
7873 #define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__SET(dst) \
7874 (dst) = ((dst) &\
7876 #define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__CLR(dst) \
7877 (dst) = ((dst) &\
7899 #define HOST_INTF_CLKRUN__FORCE__MODIFY(dst, src) \
7900 (dst) = ((dst) &\
7906 #define HOST_INTF_CLKRUN__FORCE__SET(dst) \
7907 (dst) = ((dst) &\
7909 #define HOST_INTF_CLKRUN__FORCE__CLR(dst) \
7910 (dst) = ((dst) &\
7923 #define HOST_INTF_CLKRUN__CNT__MODIFY(dst, src) \
7924 (dst) = ((dst) &\
7957 #define HOST_INTF_EEPROM_STS__BUSY__SET(dst) \
7958 (dst) = ((dst) &\
7960 #define HOST_INTF_EEPROM_STS__BUSY__CLR(dst) \
7961 (dst) = ((dst) &\
7971 #define HOST_INTF_EEPROM_STS__BUSY_ACCESS__SET(dst) \
7972 (dst) = ((dst) &\
7974 #define HOST_INTF_EEPROM_STS__BUSY_ACCESS__CLR(dst) \
7975 (dst) = ((dst) &\
7985 #define HOST_INTF_EEPROM_STS__MASK_ACCESS__SET(dst) \
7986 (dst) = ((dst) &\
7988 #define HOST_INTF_EEPROM_STS__MASK_ACCESS__CLR(dst) \
7989 (dst) = ((dst) &\
8012 #define HOST_INTF_OBS_CTRL__OBS_SEL__MODIFY(dst, src) \
8013 (dst) = ((dst) &\
8030 #define HOST_INTF_OBS_CTRL__ANT_SEL__MODIFY(dst, src) \
8031 (dst) = ((dst) &\
8048 #define HOST_INTF_OBS_CTRL__OBS_MODE__MODIFY(dst, src) \
8049 (dst) = ((dst) &\
8075 #define HOST_INTF_RFSILENT__FORCE__MODIFY(dst, src) \
8076 (dst) = ((dst) &\
8082 #define HOST_INTF_RFSILENT__FORCE__SET(dst) \
8083 (dst) = ((dst) &\
8085 #define HOST_INTF_RFSILENT__FORCE__CLR(dst) \
8086 (dst) = ((dst) &\
8099 #define HOST_INTF_RFSILENT__INVERT__MODIFY(dst, src) \
8100 (dst) = ((dst) &\
8106 #define HOST_INTF_RFSILENT__INVERT__SET(dst) \
8107 (dst) = ((dst) &\
8109 #define HOST_INTF_RFSILENT__INVERT__CLR(dst) \
8110 (dst) = ((dst) &\
8123 #define HOST_INTF_RFSILENT__RTC_RESET_INVERT__MODIFY(dst, src) \
8124 (dst) = ((dst) &\
8130 #define HOST_INTF_RFSILENT__RTC_RESET_INVERT__SET(dst) \
8131 (dst) = ((dst) &\
8133 #define HOST_INTF_RFSILENT__RTC_RESET_INVERT__CLR(dst) \
8134 (dst) = ((dst) &\
8156 #define HOST_INTF_GPIO_PDPU__INT__MODIFY(dst, src) \
8157 (dst) = ((dst) &\
8183 #define HOST_INTF_GPIO_PDPU1__INT__MODIFY(dst, src) \
8184 (dst) = ((dst) &\
8210 #define HOST_INTF_GPIO_DS__INT__MODIFY(dst, src) \
8211 (dst) = ((dst) &\
8237 #define HOST_INTF_GPIO_DS1__INT__MODIFY(dst, src) \
8238 (dst) = ((dst) &\
8266 #define HOST_INTF_MISC__AT_SPEED_EN__MODIFY(dst, src) \
8267 (dst) = ((dst) &\
8273 #define HOST_INTF_MISC__AT_SPEED_EN__SET(dst) \
8274 (dst) = ((dst) &\
8276 #define HOST_INTF_MISC__AT_SPEED_EN__CLR(dst) \
8277 (dst) = ((dst) &\
8290 #define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__MODIFY(dst, src) \
8291 (dst) = ((dst) &\
8297 #define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__SET(dst) \
8298 (dst) = ((dst) &\
8300 #define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__CLR(dst) \
8301 (dst) = ((dst) &\
8314 #define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__MODIFY(dst, src) \
8315 (dst) = ((dst) &\
8321 #define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__SET(dst) \
8322 (dst) = ((dst) &\
8324 #define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__CLR(dst) \
8325 (dst) = ((dst) &\
8347 #define HOST_INTF_PCIE_MSI__INT_EN__MODIFY(dst, src) \
8348 (dst) = ((dst) &\
8354 #define HOST_INTF_PCIE_MSI__INT_EN__SET(dst) \
8355 (dst) = ((dst) &\
8357 #define HOST_INTF_PCIE_MSI__INT_EN__CLR(dst) \
8358 (dst) = ((dst) &\
8371 #define HOST_INTF_PCIE_MSI__MULTI_MSI__MODIFY(dst, src) \
8372 (dst) = ((dst) &\
8389 #define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__MODIFY(dst, src) \
8390 (dst) = ((dst) &\
8407 #define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__MODIFY(dst, src) \
8408 (dst) = ((dst) &\
8414 #define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__SET(dst) \
8415 (dst) = ((dst) &\
8417 #define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__CLR(dst) \
8418 (dst) = ((dst) &\
8452 #define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__MODIFY(dst, src) \
8453 (dst) = ((dst) &\
8483 #define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__MODIFY(dst, src) \
8484 (dst) = ((dst) &\
8514 #define HOST_INTF_MAC_TXAPSYNC__ENABLE__MODIFY(dst, src) \
8515 (dst) = ((dst) &\
8521 #define HOST_INTF_MAC_TXAPSYNC__ENABLE__SET(dst) \
8522 (dst) = ((dst) &\
8524 #define HOST_INTF_MAC_TXAPSYNC__ENABLE__CLR(dst) \
8525 (dst) = ((dst) &\
8551 #define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__MODIFY(dst, src) \
8552 (dst) = ((dst) &\
8582 #define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__MODIFY(dst, src) \
8583 (dst) = ((dst) &\
8613 #define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__MODIFY(dst, src) \
8614 (dst) = ((dst) &\
8644 #define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__MODIFY(dst, src) \
8645 (dst) = ((dst) &\
8675 #define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__MODIFY(dst, src) \
8676 (dst) = ((dst) &\
8726 #define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__MODIFY(dst, src) \
8727 (dst) = ((dst) &\
8771 #define PCIE_CO_ERR_CTR0__RCVD_ERR__MODIFY(dst, src) \
8772 (dst) = ((dst) &\
8789 #define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__MODIFY(dst, src) \
8790 (dst) = ((dst) &\
8807 #define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__MODIFY(dst, src) \
8808 (dst) = ((dst) &\
8836 #define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__MODIFY(dst, src) \
8837 (dst) = ((dst) &\
8854 #define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__MODIFY(dst, src) \
8855 (dst) = ((dst) &\
8885 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__MODIFY(dst, src) \
8886 (dst) = ((dst) &\
8892 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__SET(dst) \
8893 (dst) = ((dst) &\
8895 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__CLR(dst) \
8896 (dst) = ((dst) &\
8909 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \
8910 (dst) = ((dst) &\
8916 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__SET(dst) \
8917 (dst) = ((dst) &\
8919 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__CLR(dst) \
8920 (dst) = ((dst) &\
8933 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__MODIFY(dst, src) \
8934 (dst) = ((dst) &\
8940 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__SET(dst) \
8941 (dst) = ((dst) &\
8943 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__CLR(dst) \
8944 (dst) = ((dst) &\
8957 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \
8958 (dst) = ((dst) &\
8964 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__SET(dst) \
8965 (dst) = ((dst) &\
8967 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__CLR(dst) \
8968 (dst) = ((dst) &\
8981 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__MODIFY(dst, src) \
8982 (dst) = ((dst) &\
8988 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__SET(dst) \
8989 (dst) = ((dst) &\
8991 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__CLR(dst) \
8992 (dst) = ((dst) &\
9005 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \
9006 (dst) = ((dst) &\
9012 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__SET(dst) \
9013 (dst) = ((dst) &\
9015 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__CLR(dst) \
9016 (dst) = ((dst) &\
9029 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__MODIFY(dst, src) \
9030 (dst) = ((dst) &\
9036 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__SET(dst) \
9037 (dst) = ((dst) &\
9039 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__CLR(dst) \
9040 (dst) = ((dst) &\
9053 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \
9054 (dst) = ((dst) &\
9060 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__SET(dst) \
9061 (dst) = ((dst) &\
9063 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__CLR(dst) \
9064 (dst) = ((dst) &\
9077 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__MODIFY(dst, src) \
9078 (dst) = ((dst) &\
9084 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__SET(dst) \
9085 (dst) = ((dst) &\
9087 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__CLR(dst) \
9088 (dst) = ((dst) &\
9101 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \
9102 (dst) = ((dst) &\
9108 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__SET(dst) \
9109 (dst) = ((dst) &\
9111 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__CLR(dst) \
9112 (dst) = ((dst) &\
9190 #define FPGA_REG1__SPARE_REG1_BIT0__MODIFY(dst, src) \
9191 (dst) = ((dst) &\
9197 #define FPGA_REG1__SPARE_REG1_BIT0__SET(dst) \
9198 (dst) = ((dst) &\
9200 #define FPGA_REG1__SPARE_REG1_BIT0__CLR(dst) \
9201 (dst) = ((dst) &\
9214 #define FPGA_REG1__MASK_RX_RF__MODIFY(dst, src) \
9215 (dst) = ((dst) &\
9221 #define FPGA_REG1__MASK_RX_RF__SET(dst) \
9222 (dst) = ((dst) &\
9224 #define FPGA_REG1__MASK_RX_RF__CLR(dst) \
9225 (dst) = ((dst) &\
9235 #define FPGA_REG1__DCM_RELEASE__SET(dst) \
9236 (dst) = ((dst) &\
9238 #define FPGA_REG1__DCM_RELEASE__CLR(dst) \
9239 (dst) = ((dst) &\
9248 #define FPGA_REG1__SPARE0__MODIFY(dst, src) \
9249 (dst) = ((dst) &\
9255 #define FPGA_REG1__SPARE0__SET(dst) \
9256 (dst) = ((dst) &\
9258 #define FPGA_REG1__SPARE0__CLR(dst) \
9259 (dst) = ((dst) &\
9272 #define FPGA_REG1__EMULATION_CLOCK_RATIO__MODIFY(dst, src) \
9273 (dst) = ((dst) &\
9290 #define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__MODIFY(dst, src) \
9291 (dst) = ((dst) &\
9308 #define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__MODIFY(dst, src) \
9309 (dst) = ((dst) &\
9315 #define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__SET(dst) \
9316 (dst) = ((dst) &\
9318 #define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__CLR(dst) \
9319 (dst) = ((dst) &\
9328 #define FPGA_REG1__SPARE1__MODIFY(dst, src) \
9329 (dst) = ((dst) &\
9357 #define FPGA_REG2__RXPIPEIFERRINJEN__MODIFY(dst, src) \
9358 (dst) = ((dst) &\
9364 #define FPGA_REG2__RXPIPEIFERRINJEN__SET(dst) \
9365 (dst) = ((dst) &\
9367 #define FPGA_REG2__RXPIPEIFERRINJEN__CLR(dst) \
9368 (dst) = ((dst) &\
9381 #define FPGA_REG2__TXPIPEIFERRINJEN__MODIFY(dst, src) \
9382 (dst) = ((dst) &\
9388 #define FPGA_REG2__TXPIPEIFERRINJEN__SET(dst) \
9389 (dst) = ((dst) &\
9391 #define FPGA_REG2__TXPIPEIFERRINJEN__CLR(dst) \
9392 (dst) = ((dst) &\
9405 #define FPGA_REG2__RXPIPEIFINJERRINDATAK__MODIFY(dst, src) \
9406 (dst) = ((dst) &\
9412 #define FPGA_REG2__RXPIPEIFINJERRINDATAK__SET(dst) \
9413 (dst) = ((dst) &\
9415 #define FPGA_REG2__RXPIPEIFINJERRINDATAK__CLR(dst) \
9416 (dst) = ((dst) &\
9429 #define FPGA_REG2__TXPIPEIFINJERRINDATAK__MODIFY(dst, src) \
9430 (dst) = ((dst) &\
9436 #define FPGA_REG2__TXPIPEIFINJERRINDATAK__SET(dst) \
9437 (dst) = ((dst) &\
9439 #define FPGA_REG2__TXPIPEIFINJERRINDATAK__CLR(dst) \
9440 (dst) = ((dst) &\
9453 #define FPGA_REG2__DUMMY_ERROR_INJECTION__MODIFY(dst, src) \
9454 (dst) = ((dst) &\
9498 #define FPGA_REG4__RADIO_0_TCK__MODIFY(dst, src) \
9499 (dst) = ((dst) &\
9505 #define FPGA_REG4__RADIO_0_TCK__SET(dst) \
9506 (dst) = ((dst) &\
9508 #define FPGA_REG4__RADIO_0_TCK__CLR(dst) \
9509 (dst) = ((dst) &\
9522 #define FPGA_REG4__RADIO_0_TDI__MODIFY(dst, src) \
9523 (dst) = ((dst) &\
9529 #define FPGA_REG4__RADIO_0_TDI__SET(dst) \
9530 (dst) = ((dst) &\
9532 #define FPGA_REG4__RADIO_0_TDI__CLR(dst) \
9533 (dst) = ((dst) &\
9546 #define FPGA_REG4__RADIO_0_TMS__MODIFY(dst, src) \
9547 (dst) = ((dst) &\
9553 #define FPGA_REG4__RADIO_0_TMS__SET(dst) \
9554 (dst) = ((dst) &\
9556 #define FPGA_REG4__RADIO_0_TMS__CLR(dst) \
9557 (dst) = ((dst) &\
9567 #define FPGA_REG4__RADIO_0_TDO__SET(dst) \
9568 (dst) = ((dst) &\
9570 #define FPGA_REG4__RADIO_0_TDO__CLR(dst) \
9571 (dst) = ((dst) &\
9584 #define FPGA_REG4__RADIO_1_TCK__MODIFY(dst, src) \
9585 (dst) = ((dst) &\
9591 #define FPGA_REG4__RADIO_1_TCK__SET(dst) \
9592 (dst) = ((dst) &\
9594 #define FPGA_REG4__RADIO_1_TCK__CLR(dst) \
9595 (dst) = ((dst) &\
9608 #define FPGA_REG4__RADIO_1_TDI__MODIFY(dst, src) \
9609 (dst) = ((dst) &\
9615 #define FPGA_REG4__RADIO_1_TDI__SET(dst) \
9616 (dst) = ((dst) &\
9618 #define FPGA_REG4__RADIO_1_TDI__CLR(dst) \
9619 (dst) = ((dst) &\
9632 #define FPGA_REG4__RADIO_1_TMS__MODIFY(dst, src) \
9633 (dst) = ((dst) &\
9639 #define FPGA_REG4__RADIO_1_TMS__SET(dst) \
9640 (dst) = ((dst) &\
9642 #define FPGA_REG4__RADIO_1_TMS__CLR(dst) \
9643 (dst) = ((dst) &\
9653 #define FPGA_REG4__RADIO_1_TDO__SET(dst) \
9654 (dst) = ((dst) &\
9656 #define FPGA_REG4__RADIO_1_TDO__CLR(dst) \
9657 (dst) = ((dst) &\
9670 #define FPGA_REG4__RADIO_2_TCK__MODIFY(dst, src) \
9671 (dst) = ((dst) &\
9677 #define FPGA_REG4__RADIO_2_TCK__SET(dst) \
9678 (dst) = ((dst) &\
9680 #define FPGA_REG4__RADIO_2_TCK__CLR(dst) \
9681 (dst) = ((dst) &\
9694 #define FPGA_REG4__RADIO_2_TDI__MODIFY(dst, src) \
9695 (dst) = ((dst) &\
9701 #define FPGA_REG4__RADIO_2_TDI__SET(dst) \
9702 (dst) = ((dst) &\
9704 #define FPGA_REG4__RADIO_2_TDI__CLR(dst) \
9705 (dst) = ((dst) &\
9718 #define FPGA_REG4__RADIO_2_TMS__MODIFY(dst, src) \
9719 (dst) = ((dst) &\
9725 #define FPGA_REG4__RADIO_2_TMS__SET(dst) \
9726 (dst) = ((dst) &\
9728 #define FPGA_REG4__RADIO_2_TMS__CLR(dst) \
9729 (dst) = ((dst) &\
9739 #define FPGA_REG4__RADIO_2_TDO__SET(dst) \
9740 (dst) = ((dst) &\
9742 #define FPGA_REG4__RADIO_2_TDO__CLR(dst) \
9743 (dst) = ((dst) &\
9756 #define FPGA_REG4__RADIO_3_TCK__MODIFY(dst, src) \
9757 (dst) = ((dst) &\
9763 #define FPGA_REG4__RADIO_3_TCK__SET(dst) \
9764 (dst) = ((dst) &\
9766 #define FPGA_REG4__RADIO_3_TCK__CLR(dst) \
9767 (dst) = ((dst) &\
9780 #define FPGA_REG4__RADIO_3_TDI__MODIFY(dst, src) \
9781 (dst) = ((dst) &\
9787 #define FPGA_REG4__RADIO_3_TDI__SET(dst) \
9788 (dst) = ((dst) &\
9790 #define FPGA_REG4__RADIO_3_TDI__CLR(dst) \
9791 (dst) = ((dst) &\
9804 #define FPGA_REG4__RADIO_3_TMS__MODIFY(dst, src) \
9805 (dst) = ((dst) &\
9811 #define FPGA_REG4__RADIO_3_TMS__SET(dst) \
9812 (dst) = ((dst) &\
9814 #define FPGA_REG4__RADIO_3_TMS__CLR(dst) \
9815 (dst) = ((dst) &\
9825 #define FPGA_REG4__RADIO_3_TDO__SET(dst) \
9826 (dst) = ((dst) &\
9828 #define FPGA_REG4__RADIO_3_TDO__CLR(dst) \
9829 (dst) = ((dst) &\
9851 #define FPGA_REG5__DRP_DEN__MODIFY(dst, src) \
9852 (dst) = ((dst) &\
9856 #define FPGA_REG5__DRP_DEN__SET(dst) \
9857 (dst) = ((dst) &\
9859 #define FPGA_REG5__DRP_DEN__CLR(dst) \
9860 (dst) = ((dst) &\
9869 #define FPGA_REG5__DRP_DWE__MODIFY(dst, src) \
9870 (dst) = ((dst) &\
9876 #define FPGA_REG5__DRP_DWE__SET(dst) \
9877 (dst) = ((dst) &\
9879 #define FPGA_REG5__DRP_DWE__CLR(dst) \
9880 (dst) = ((dst) &\
9891 #define FPGA_REG5__DRP_RESET__MODIFY(dst, src) \
9892 (dst) = ((dst) &\
9898 #define FPGA_REG5__DRP_RESET__SET(dst) \
9899 (dst) = ((dst) &\
9901 #define FPGA_REG5__DRP_RESET__CLR(dst) \
9902 (dst) = ((dst) &\
9915 #define FPGA_REG5__DRP_ADDRESS__MODIFY(dst, src) \
9916 (dst) = ((dst) &\
9933 #define FPGA_REG5__DRP_RESERVED__MODIFY(dst, src) \
9934 (dst) = ((dst) &\
9947 #define FPGA_REG5__DRP_DIN__MODIFY(dst, src) \
9948 (dst) = ((dst) &\
9973 #define FPGA_REG6__DRP_DRDY__SET(dst) \
9974 (dst) = ((dst) &\
9976 #define FPGA_REG6__DRP_DRDY__CLR(dst) \
9977 (dst) = ((dst) &\
10006 #define FPGA_REG7__RXPIPEIFERRINJMSK__MODIFY(dst, src) \
10007 (dst) = ((dst) &\
10035 #define FPGA_REG8__TXPIPEIFERRINJMSK__MODIFY(dst, src) \
10036 (dst) = ((dst) &\
10064 #define FPGA_REG9__RXPIPEIFDATAERRMSK__MODIFY(dst, src) \
10065 (dst) = ((dst) &\
10082 #define FPGA_REG9__TXPIPEIFDATAERRMSK__MODIFY(dst, src) \
10083 (dst) = ((dst) &\
10109 #define FPGA_REG10__RXPIPEIFSPDMSK__MODIFY(dst, src) \
10110 (dst) = ((dst) &\
10127 #define FPGA_REG10__TXPIPEIFSPDMSK__MODIFY(dst, src) \
10128 (dst) = ((dst) &\
11517 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__MODIFY(dst, src) \
11518 (dst) = ((dst) &\
11548 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__MODIFY(dst, src) \
11549 (dst) = ((dst) &\
11579 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__MODIFY(dst, src) \
11580 (dst) = ((dst) &\
11610 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__MODIFY(dst, src) \
11611 (dst) = ((dst) &\
11642 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__MODIFY(dst, src) \
11643 (dst) = ((dst) &\
11673 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__MODIFY(dst, src) \
11674 (dst) = ((dst) &\
11704 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__MODIFY(dst, src) \
11705 (dst) = ((dst) &\
11735 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__MODIFY(dst, src) \
11736 (dst) = ((dst) &\
11766 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__MODIFY(dst, src) \
11767 (dst) = ((dst) &\
11918 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__MODIFY(dst, src) \
11919 (dst) = ((dst) &\
11949 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__MODIFY(dst, src) \
11950 (dst) = ((dst) &\
12468 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__MODIFY(dst, src) \
12469 (dst) = ((dst) &\
12499 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__MODIFY(dst, src) \
12500 (dst) = ((dst) &\
12530 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__MODIFY(dst, src) \
12531 (dst) = ((dst) &\
12561 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__MODIFY(dst, src) \
12562 (dst) = ((dst) &\
12592 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__MODIFY(dst, src) \
12593 (dst) = ((dst) &\
12623 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__MODIFY(dst, src) \
12624 (dst) = ((dst) &\
12654 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__MODIFY(dst, src) \
12655 (dst) = ((dst) &\
12685 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__MODIFY(dst, src) \
12686 (dst) = ((dst) &\
12716 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__MODIFY(dst, src) \
12717 (dst) = ((dst) &\
12747 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__MODIFY(dst, src) \
12748 (dst) = ((dst) &\
12778 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__MODIFY(dst, src) \
12779 (dst) = ((dst) &\
12809 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__MODIFY(dst, src) \
12810 (dst) = ((dst) &\
12840 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__MODIFY(dst, src) \
12841 (dst) = ((dst) &\
12871 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__MODIFY(dst, src) \
12872 (dst) = ((dst) &\
12902 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__MODIFY(dst, src) \
12903 (dst) = ((dst) &\
12933 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__MODIFY(dst, src) \
12934 (dst) = ((dst) &\
12964 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__MODIFY(dst, src) \
12965 (dst) = ((dst) &\
12995 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__MODIFY(dst, src) \
12996 (dst) = ((dst) &\
13026 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__MODIFY(dst, src) \
13027 (dst) = ((dst) &\
13057 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__MODIFY(dst, src) \
13058 (dst) = ((dst) &\
13088 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__MODIFY(dst, src) \
13089 (dst) = ((dst) &\
13119 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__MODIFY(dst, src) \
13120 (dst) = ((dst) &\
13150 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__MODIFY(dst, src) \
13151 (dst) = ((dst) &\
13181 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__MODIFY(dst, src) \
13182 (dst) = ((dst) &\
13212 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__MODIFY(dst, src) \
13213 (dst) = ((dst) &\
13243 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__MODIFY(dst, src) \
13244 (dst) = ((dst) &\
13274 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__MODIFY(dst, src) \
13275 (dst) = ((dst) &\
13312 #define RESET_CONTROL__MAC_WARM_RST__MODIFY(dst, src) \
13313 (dst) = ((dst) &\
13319 #define RESET_CONTROL__MAC_WARM_RST__SET(dst) \
13320 (dst) = ((dst) &\
13322 #define RESET_CONTROL__MAC_WARM_RST__CLR(dst) \
13323 (dst) = ((dst) &\
13336 #define RESET_CONTROL__MAC_COLD_RST__MODIFY(dst, src) \
13337 (dst) = ((dst) &\
13343 #define RESET_CONTROL__MAC_COLD_RST__SET(dst) \
13344 (dst) = ((dst) &\
13346 #define RESET_CONTROL__MAC_COLD_RST__CLR(dst) \
13347 (dst) = ((dst) &\
13360 #define RESET_CONTROL__WARM_RST__MODIFY(dst, src) \
13361 (dst) = ((dst) &\
13367 #define RESET_CONTROL__WARM_RST__SET(dst) \
13368 (dst) = ((dst) &\
13370 #define RESET_CONTROL__WARM_RST__CLR(dst) \
13371 (dst) = ((dst) &\
13384 #define RESET_CONTROL__COLD_RST__MODIFY(dst, src) \
13385 (dst) = ((dst) &\
13391 #define RESET_CONTROL__COLD_RST__SET(dst) \
13392 (dst) = ((dst) &\
13394 #define RESET_CONTROL__COLD_RST__CLR(dst) \
13395 (dst) = ((dst) &\
13417 #define XTAL_CONTROL__TCXO__MODIFY(dst, src) \
13418 (dst) = ((dst) &\
13422 #define XTAL_CONTROL__TCXO__SET(dst) \
13423 (dst) = ((dst) &\
13425 #define XTAL_CONTROL__TCXO__CLR(dst) \
13426 (dst) = ((dst) &\
13448 #define REG_CONTROL0__SWREG_BITS__MODIFY(dst, src) \
13449 (dst) = ((dst) &\
13477 #define REG_CONTROL1__SWREG_PROGRAM__MODIFY(dst, src) \
13478 (dst) = ((dst) &\
13484 #define REG_CONTROL1__SWREG_PROGRAM__SET(dst) \
13485 (dst) = ((dst) &\
13487 #define REG_CONTROL1__SWREG_PROGRAM__CLR(dst) \
13488 (dst) = ((dst) &\
13501 #define REG_CONTROL1__OTPREG_LVL__MODIFY(dst, src) \
13502 (dst) = ((dst) &\
13528 #define QUADRATURE__DAC__MODIFY(dst, src) \
13529 (dst) = ((dst) &\
13540 #define QUADRATURE__ADC__MODIFY(dst, src) \
13541 (dst) = ((dst) &\
13567 #define PLL_CONTROL__DIV__MODIFY(dst, src) \
13568 (dst) = ((dst) &\
13581 #define PLL_CONTROL__REFDIV__MODIFY(dst, src) \
13582 (dst) = ((dst) &\
13599 #define PLL_CONTROL__CLK_SEL__MODIFY(dst, src) \
13600 (dst) = ((dst) &\
13615 #define PLL_CONTROL__BYPASS__MODIFY(dst, src) \
13616 (dst) = ((dst) &\
13622 #define PLL_CONTROL__BYPASS__SET(dst) \
13623 (dst) = ((dst) &\
13625 #define PLL_CONTROL__BYPASS__CLR(dst) \
13626 (dst) = ((dst) &\
13636 #define PLL_CONTROL__UPDATING__SET(dst) \
13637 (dst) = ((dst) &\
13639 #define PLL_CONTROL__UPDATING__CLR(dst) \
13640 (dst) = ((dst) &\
13649 #define PLL_CONTROL__NOPWD__MODIFY(dst, src) \
13650 (dst) = ((dst) &\
13656 #define PLL_CONTROL__NOPWD__SET(dst) \
13657 (dst) = ((dst) &\
13659 #define PLL_CONTROL__NOPWD__CLR(dst) \
13660 (dst) = ((dst) &\
13673 #define PLL_CONTROL__MAC_OVERRIDE__MODIFY(dst, src) \
13674 (dst) = ((dst) &\
13680 #define PLL_CONTROL__MAC_OVERRIDE__SET(dst) \
13681 (dst) = ((dst) &\
13683 #define PLL_CONTROL__MAC_OVERRIDE__CLR(dst) \
13684 (dst) = ((dst) &\
13706 #define PLL_SETTLE__TIME__MODIFY(dst, src) \
13707 (dst) = ((dst) &\
13731 #define XTAL_SETTLE__TIME__MODIFY(dst, src) \
13732 (dst) = ((dst) &\
13756 #define CLOCK_OUT__SELECT__MODIFY(dst, src) \
13757 (dst) = ((dst) &\
13768 #define CLOCK_OUT__DELAY__MODIFY(dst, src) \
13769 (dst) = ((dst) &\
13795 #define BIAS_OVERRIDE__ON__MODIFY(dst, src) \
13796 (dst) = ((dst) &\
13800 #define BIAS_OVERRIDE__ON__SET(dst) \
13801 (dst) = ((dst) &\
13803 #define BIAS_OVERRIDE__ON__CLR(dst) \
13804 (dst) = ((dst) &\
13844 #define SYSTEM_SLEEP__DISABLE__MODIFY(dst, src) \
13845 (dst) = ((dst) &\
13851 #define SYSTEM_SLEEP__DISABLE__SET(dst) \
13852 (dst) = ((dst) &\
13854 #define SYSTEM_SLEEP__DISABLE__CLR(dst) \
13855 (dst) = ((dst) &\
13864 #define SYSTEM_SLEEP__LIGHT__MODIFY(dst, src) \
13865 (dst) = ((dst) &\
13871 #define SYSTEM_SLEEP__LIGHT__SET(dst) \
13872 (dst) = ((dst) &\
13874 #define SYSTEM_SLEEP__LIGHT__CLR(dst) \
13875 (dst) = ((dst) &\
13883 #define SYSTEM_SLEEP__MAC_IF__SET(dst) \
13884 (dst) = ((dst) &\
13886 #define SYSTEM_SLEEP__MAC_IF__CLR(dst) \
13887 (dst) = ((dst) &\
13909 #define MAC_SLEEP_CONTROL__ENABLE__MODIFY(dst, src) \
13910 (dst) = ((dst) &\
13936 #define KEEP_AWAKE__COUNT__MODIFY(dst, src) \
13937 (dst) = ((dst) &\
13965 #define DERIVED_RTC_CLK__PERIOD__MODIFY(dst, src) \
13966 (dst) = ((dst) &\
13980 #define DERIVED_RTC_CLK__EXTERNAL_DETECT__SET(dst) \
13981 (dst) = ((dst) &\
13983 #define DERIVED_RTC_CLK__EXTERNAL_DETECT__CLR(dst) \
13984 (dst) = ((dst) &\
14006 #define RTC_SYNC_RESET__RESET_L__MODIFY(dst, src) \
14007 (dst) = ((dst) &\
14013 #define RTC_SYNC_RESET__RESET_L__SET(dst) \
14014 (dst) = ((dst) &\
14016 #define RTC_SYNC_RESET__RESET_L__CLR(dst) \
14017 (dst) = ((dst) &\
14040 #define RTC_SYNC_STATUS__SHUTDOWN_STATE__SET(dst) \
14041 (dst) = ((dst) &\
14043 #define RTC_SYNC_STATUS__SHUTDOWN_STATE__CLR(dst) \
14044 (dst) = ((dst) &\
14054 #define RTC_SYNC_STATUS__ON_STATE__SET(dst) \
14055 (dst) = ((dst) &\
14057 #define RTC_SYNC_STATUS__ON_STATE__CLR(dst) \
14058 (dst) = ((dst) &\
14068 #define RTC_SYNC_STATUS__SLEEP_STATE__SET(dst) \
14069 (dst) = ((dst) &\
14071 #define RTC_SYNC_STATUS__SLEEP_STATE__CLR(dst) \
14072 (dst) = ((dst) &\
14082 #define RTC_SYNC_STATUS__WAKEUP_STATE__SET(dst) \
14083 (dst) = ((dst) &\
14085 #define RTC_SYNC_STATUS__WAKEUP_STATE__CLR(dst) \
14086 (dst) = ((dst) &\
14096 #define RTC_SYNC_STATUS__WRESET__SET(dst) \
14097 (dst) = ((dst) &\
14099 #define RTC_SYNC_STATUS__WRESET__CLR(dst) \
14100 (dst) = ((dst) &\
14110 #define RTC_SYNC_STATUS__PLL_CHANGING__SET(dst) \
14111 (dst) = ((dst) &\
14113 #define RTC_SYNC_STATUS__PLL_CHANGING__CLR(dst) \
14114 (dst) = ((dst) &\
14135 #define RTC_SYNC_DERIVED__BYPASS__MODIFY(dst, src) \
14136 (dst) = ((dst) &\
14142 #define RTC_SYNC_DERIVED__BYPASS__SET(dst) \
14143 (dst) = ((dst) &\
14145 #define RTC_SYNC_DERIVED__BYPASS__CLR(dst) \
14146 (dst) = ((dst) &\
14159 #define RTC_SYNC_DERIVED__FORCE__MODIFY(dst, src) \
14160 (dst) = ((dst) &\
14166 #define RTC_SYNC_DERIVED__FORCE__SET(dst) \
14167 (dst) = ((dst) &\
14169 #define RTC_SYNC_DERIVED__FORCE__CLR(dst) \
14170 (dst) = ((dst) &\
14180 #define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__MODIFY(dst, src) \
14181 (dst) = ((dst) &\
14187 #define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__SET(dst) \
14188 (dst) = ((dst) &\
14190 #define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__CLR(dst) \
14191 (dst) = ((dst) &\
14201 #define RTC_SYNC_DERIVED__FORCE_LPO_PWD__MODIFY(dst, src) \
14202 (dst) = ((dst) &\
14208 #define RTC_SYNC_DERIVED__FORCE_LPO_PWD__SET(dst) \
14209 (dst) = ((dst) &\
14211 #define RTC_SYNC_DERIVED__FORCE_LPO_PWD__CLR(dst) \
14212 (dst) = ((dst) &\
14233 #define RTC_SYNC_FORCE_WAKE__ENABLE__SET(dst) \
14234 (dst) = ((dst) &\
14236 #define RTC_SYNC_FORCE_WAKE__ENABLE__CLR(dst) \
14237 (dst) = ((dst) &\
14250 #define RTC_SYNC_FORCE_WAKE__INTR__MODIFY(dst, src) \
14251 (dst) = ((dst) &\
14257 #define RTC_SYNC_FORCE_WAKE__INTR__SET(dst) \
14258 (dst) = ((dst) &\
14260 #define RTC_SYNC_FORCE_WAKE__INTR__CLR(dst) \
14261 (dst) = ((dst) &\
14287 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MODIFY(dst, src) \
14288 (dst) = ((dst) &\
14294 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__SET(dst) \
14295 (dst) = ((dst) &\
14297 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__CLR(dst) \
14298 (dst) = ((dst) &\
14311 #define RTC_SYNC_INTR_CAUSE__ON_STATE__MODIFY(dst, src) \
14312 (dst) = ((dst) &\
14318 #define RTC_SYNC_INTR_CAUSE__ON_STATE__SET(dst) \
14319 (dst) = ((dst) &\
14321 #define RTC_SYNC_INTR_CAUSE__ON_STATE__CLR(dst) \
14322 (dst) = ((dst) &\
14335 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MODIFY(dst, src) \
14336 (dst) = ((dst) &\
14342 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__SET(dst) \
14343 (dst) = ((dst) &\
14345 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__CLR(dst) \
14346 (dst) = ((dst) &\
14359 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MODIFY(dst, src) \
14360 (dst) = ((dst) &\
14366 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__SET(dst) \
14367 (dst) = ((dst) &\
14369 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__CLR(dst) \
14370 (dst) = ((dst) &\
14383 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MODIFY(dst, src) \
14384 (dst) = ((dst) &\
14390 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__SET(dst) \
14391 (dst) = ((dst) &\
14393 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__CLR(dst) \
14394 (dst) = ((dst) &\
14407 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MODIFY(dst, src) \
14408 (dst) = ((dst) &\
14414 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__SET(dst) \
14415 (dst) = ((dst) &\
14417 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__CLR(dst) \
14418 (dst) = ((dst) &\
14444 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MODIFY(dst, src) \
14445 (dst) = ((dst) &\
14451 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__SET(dst) \
14452 (dst) = ((dst) &\
14454 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__CLR(dst) \
14455 (dst) = ((dst) &\
14468 #define RTC_SYNC_INTR_ENABLE__ON_STATE__MODIFY(dst, src) \
14469 (dst) = ((dst) &\
14475 #define RTC_SYNC_INTR_ENABLE__ON_STATE__SET(dst) \
14476 (dst) = ((dst) &\
14478 #define RTC_SYNC_INTR_ENABLE__ON_STATE__CLR(dst) \
14479 (dst) = ((dst) &\
14492 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MODIFY(dst, src) \
14493 (dst) = ((dst) &\
14499 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__SET(dst) \
14500 (dst) = ((dst) &\
14502 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__CLR(dst) \
14503 (dst) = ((dst) &\
14516 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MODIFY(dst, src) \
14517 (dst) = ((dst) &\
14523 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__SET(dst) \
14524 (dst) = ((dst) &\
14526 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__CLR(dst) \
14527 (dst) = ((dst) &\
14540 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MODIFY(dst, src) \
14541 (dst) = ((dst) &\
14547 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__SET(dst) \
14548 (dst) = ((dst) &\
14550 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__CLR(dst) \
14551 (dst) = ((dst) &\
14564 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MODIFY(dst, src) \
14565 (dst) = ((dst) &\
14571 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__SET(dst) \
14572 (dst) = ((dst) &\
14574 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__CLR(dst) \
14575 (dst) = ((dst) &\
14601 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MODIFY(dst, src) \
14602 (dst) = ((dst) &\
14608 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__SET(dst) \
14609 (dst) = ((dst) &\
14611 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__CLR(dst) \
14612 (dst) = ((dst) &\
14625 #define RTC_SYNC_INTR_MASK__ON_STATE__MODIFY(dst, src) \
14626 (dst) = ((dst) &\
14632 #define RTC_SYNC_INTR_MASK__ON_STATE__SET(dst) \
14633 (dst) = ((dst) &\
14635 #define RTC_SYNC_INTR_MASK__ON_STATE__CLR(dst) \
14636 (dst) = ((dst) &\
14649 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__MODIFY(dst, src) \
14650 (dst) = ((dst) &\
14656 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__SET(dst) \
14657 (dst) = ((dst) &\
14659 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__CLR(dst) \
14660 (dst) = ((dst) &\
14673 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MODIFY(dst, src) \
14674 (dst) = ((dst) &\
14680 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__SET(dst) \
14681 (dst) = ((dst) &\
14683 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__CLR(dst) \
14684 (dst) = ((dst) &\
14697 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MODIFY(dst, src) \
14698 (dst) = ((dst) &\
14704 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__SET(dst) \
14705 (dst) = ((dst) &\
14707 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__CLR(dst) \
14708 (dst) = ((dst) &\
14721 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__MODIFY(dst, src) \
14722 (dst) = ((dst) &\
14728 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__SET(dst) \
14729 (dst) = ((dst) &\
14731 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__CLR(dst) \
14732 (dst) = ((dst) &\
14756 #define RADIO130NM_RXTXBB1_CH1__PDHIQ__MODIFY(dst, src) \
14757 (dst) = ((dst) &\
14763 #define RADIO130NM_RXTXBB1_CH1__PDHIQ__SET(dst) \
14764 (dst) = ((dst) &\
14766 #define RADIO130NM_RXTXBB1_CH1__PDHIQ__CLR(dst) \
14767 (dst) = ((dst) &\
14780 #define RADIO130NM_RXTXBB1_CH1__PDLOQ__MODIFY(dst, src) \
14781 (dst) = ((dst) &\
14787 #define RADIO130NM_RXTXBB1_CH1__PDLOQ__SET(dst) \
14788 (dst) = ((dst) &\
14790 #define RADIO130NM_RXTXBB1_CH1__PDLOQ__CLR(dst) \
14791 (dst) = ((dst) &\
14804 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__MODIFY(dst, src) \
14805 (dst) = ((dst) &\
14811 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__SET(dst) \
14812 (dst) = ((dst) &\
14814 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__CLR(dst) \
14815 (dst) = ((dst) &\
14828 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__MODIFY(dst, src) \
14829 (dst) = ((dst) &\
14835 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__SET(dst) \
14836 (dst) = ((dst) &\
14838 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__CLR(dst) \
14839 (dst) = ((dst) &\
14852 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__MODIFY(dst, src) \
14853 (dst) = ((dst) &\
14859 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__SET(dst) \
14860 (dst) = ((dst) &\
14862 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__CLR(dst) \
14863 (dst) = ((dst) &\
14876 #define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__MODIFY(dst, src) \
14877 (dst) = ((dst) &\
14883 #define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__SET(dst) \
14884 (dst) = ((dst) &\
14886 #define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__CLR(dst) \
14887 (dst) = ((dst) &\
14900 #define RADIO130NM_RXTXBB1_CH1__PDI2V__MODIFY(dst, src) \
14901 (dst) = ((dst) &\
14907 #define RADIO130NM_RXTXBB1_CH1__PDI2V__SET(dst) \
14908 (dst) = ((dst) &\
14910 #define RADIO130NM_RXTXBB1_CH1__PDI2V__CLR(dst) \
14911 (dst) = ((dst) &\
14924 #define RADIO130NM_RXTXBB1_CH1__PDV2I__MODIFY(dst, src) \
14925 (dst) = ((dst) &\
14931 #define RADIO130NM_RXTXBB1_CH1__PDV2I__SET(dst) \
14932 (dst) = ((dst) &\
14934 #define RADIO130NM_RXTXBB1_CH1__PDV2I__CLR(dst) \
14935 (dst) = ((dst) &\
14948 #define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__MODIFY(dst, src) \
14949 (dst) = ((dst) &\
14955 #define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__SET(dst) \
14956 (dst) = ((dst) &\
14958 #define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__CLR(dst) \
14959 (dst) = ((dst) &\
14972 #define RADIO130NM_RXTXBB1_CH1__SEL_ATB__MODIFY(dst, src) \
14973 (dst) = ((dst) &\
14990 #define RADIO130NM_RXTXBB1_CH1__FNOTCH__MODIFY(dst, src) \
14991 (dst) = ((dst) &\
15008 #define RADIO130NM_RXTXBB1_CH1__SPARE__MODIFY(dst, src) \
15009 (dst) = ((dst) &\
15039 #define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__MODIFY(dst, src) \
15040 (dst) = ((dst) &\
15046 #define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__SET(dst) \
15047 (dst) = ((dst) &\
15049 #define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__CLR(dst) \
15050 (dst) = ((dst) &\
15063 #define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__MODIFY(dst, src) \
15064 (dst) = ((dst) &\
15070 #define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__SET(dst) \
15071 (dst) = ((dst) &\
15073 #define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__CLR(dst) \
15074 (dst) = ((dst) &\
15087 #define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__MODIFY(dst, src) \
15088 (dst) = ((dst) &\
15094 #define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__SET(dst) \
15095 (dst) = ((dst) &\
15097 #define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__CLR(dst) \
15098 (dst) = ((dst) &\
15111 #define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__MODIFY(dst, src) \
15112 (dst) = ((dst) &\
15118 #define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__SET(dst) \
15119 (dst) = ((dst) &\
15121 #define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__CLR(dst) \
15122 (dst) = ((dst) &\
15135 #define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__MODIFY(dst, src) \
15136 (dst) = ((dst) &\
15142 #define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__SET(dst) \
15143 (dst) = ((dst) &\
15145 #define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__CLR(dst) \
15146 (dst) = ((dst) &\
15159 #define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__MODIFY(dst, src) \
15160 (dst) = ((dst) &\
15166 #define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__SET(dst) \
15167 (dst) = ((dst) &\
15169 #define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__CLR(dst) \
15170 (dst) = ((dst) &\
15183 #define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__MODIFY(dst, src) \
15184 (dst) = ((dst) &\
15190 #define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__SET(dst) \
15191 (dst) = ((dst) &\
15193 #define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__CLR(dst) \
15194 (dst) = ((dst) &\
15207 #define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__MODIFY(dst, src) \
15208 (dst) = ((dst) &\
15214 #define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__SET(dst) \
15215 (dst) = ((dst) &\
15217 #define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__CLR(dst) \
15218 (dst) = ((dst) &\
15231 #define RADIO130NM_RXTXBB2_CH1__FILTERFC__MODIFY(dst, src) \
15232 (dst) = ((dst) &\
15249 #define RADIO130NM_RXTXBB2_CH1__CMSEL__MODIFY(dst, src) \
15250 (dst) = ((dst) &\
15267 #define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__MODIFY(dst, src) \
15268 (dst) = ((dst) &\
15274 #define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__SET(dst) \
15275 (dst) = ((dst) &\
15277 #define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__CLR(dst) \
15278 (dst) = ((dst) &\
15291 #define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__MODIFY(dst, src) \
15292 (dst) = ((dst) &\
15298 #define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__SET(dst) \
15299 (dst) = ((dst) &\
15301 #define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__CLR(dst) \
15302 (dst) = ((dst) &\
15315 #define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__MODIFY(dst, src) \
15316 (dst) = ((dst) &\
15322 #define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__SET(dst) \
15323 (dst) = ((dst) &\
15325 #define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__CLR(dst) \
15326 (dst) = ((dst) &\
15339 #define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__MODIFY(dst, src) \
15340 (dst) = ((dst) &\
15346 #define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__SET(dst) \
15347 (dst) = ((dst) &\
15349 #define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__CLR(dst) \
15350 (dst) = ((dst) &\
15363 #define RADIO130NM_RXTXBB2_CH1__SELBUFFER__MODIFY(dst, src) \
15364 (dst) = ((dst) &\
15370 #define RADIO130NM_RXTXBB2_CH1__SELBUFFER__SET(dst) \
15371 (dst) = ((dst) &\
15373 #define RADIO130NM_RXTXBB2_CH1__SELBUFFER__CLR(dst) \
15374 (dst) = ((dst) &\
15387 #define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__MODIFY(dst, src) \
15388 (dst) = ((dst) &\
15394 #define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__SET(dst) \
15395 (dst) = ((dst) &\
15397 #define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__CLR(dst) \
15398 (dst) = ((dst) &\
15411 #define RADIO130NM_RXTXBB2_CH1__SPARE__MODIFY(dst, src) \
15412 (dst) = ((dst) &\
15429 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__MODIFY(dst, src) \
15430 (dst) = ((dst) &\
15447 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__MODIFY(dst, src) \
15448 (dst) = ((dst) &\
15465 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__MODIFY(dst, src) \
15466 (dst) = ((dst) &\
15496 #define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__MODIFY(dst, src) \
15497 (dst) = ((dst) &\
15514 #define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__MODIFY(dst, src) \
15515 (dst) = ((dst) &\
15532 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__MODIFY(dst, src) \
15533 (dst) = ((dst) &\
15550 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__MODIFY(dst, src) \
15551 (dst) = ((dst) &\
15568 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__MODIFY(dst, src) \
15569 (dst) = ((dst) &\
15586 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__MODIFY(dst, src) \
15587 (dst) = ((dst) &\
15604 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__MODIFY(dst, src) \
15605 (dst) = ((dst) &\
15622 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__MODIFY(dst, src) \
15623 (dst) = ((dst) &\
15640 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__MODIFY(dst, src) \
15641 (dst) = ((dst) &\
15658 #define RADIO130NM_RXTXBB3_CH1__SPARE__MODIFY(dst, src) \
15659 (dst) = ((dst) &\
15689 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__MODIFY(dst, src) \
15690 (dst) = ((dst) &\
15707 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__MODIFY(dst, src) \
15708 (dst) = ((dst) &\
15725 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__MODIFY(dst, src) \
15726 (dst) = ((dst) &\
15743 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__MODIFY(dst, src) \
15744 (dst) = ((dst) &\
15761 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__MODIFY(dst, src) \
15762 (dst) = ((dst) &\
15779 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__MODIFY(dst, src) \
15780 (dst) = ((dst) &\
15797 #define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__MODIFY(dst, src) \
15798 (dst) = ((dst) &\
15804 #define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__SET(dst) \
15805 (dst) = ((dst) &\
15807 #define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__CLR(dst) \
15808 (dst) = ((dst) &\
15821 #define RADIO130NM_RXTXBB4_CH1__SPARE__MODIFY(dst, src) \
15822 (dst) = ((dst) &\
15828 #define RADIO130NM_RXTXBB4_CH1__SPARE__SET(dst) \
15829 (dst) = ((dst) &\
15831 #define RADIO130NM_RXTXBB4_CH1__SPARE__CLR(dst) \
15832 (dst) = ((dst) &\
15856 #define RADIO130NM_RF2G1_CH1__SPARES__MODIFY(dst, src) \
15857 (dst) = ((dst) &\
15874 #define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__MODIFY(dst, src) \
15875 (dst) = ((dst) &\
15881 #define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__SET(dst) \
15882 (dst) = ((dst) &\
15884 #define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__CLR(dst) \
15885 (dst) = ((dst) &\
15898 #define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__MODIFY(dst, src) \
15899 (dst) = ((dst) &\
15905 #define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__SET(dst) \
15906 (dst) = ((dst) &\
15908 #define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__CLR(dst) \
15909 (dst) = ((dst) &\
15922 #define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__MODIFY(dst, src) \
15923 (dst) = ((dst) &\
15940 #define RADIO130NM_RF2G1_CH1__PACA_SEL__MODIFY(dst, src) \
15941 (dst) = ((dst) &\
15958 #define RADIO130NM_RF2G1_CH1__LOCONTROL__MODIFY(dst, src) \
15959 (dst) = ((dst) &\
15965 #define RADIO130NM_RF2G1_CH1__LOCONTROL__SET(dst) \
15966 (dst) = ((dst) &\
15968 #define RADIO130NM_RF2G1_CH1__LOCONTROL__CLR(dst) \
15969 (dst) = ((dst) &\
15982 #define RADIO130NM_RF2G1_CH1__TXATB_SEL__MODIFY(dst, src) \
15983 (dst) = ((dst) &\
16000 #define RADIO130NM_RF2G1_CH1__RXATB_SEL__MODIFY(dst, src) \
16001 (dst) = ((dst) &\
16018 #define RADIO130NM_RF2G1_CH1__LOATB_SEL__MODIFY(dst, src) \
16019 (dst) = ((dst) &\
16036 #define RADIO130NM_RF2G1_CH1__OB__MODIFY(dst, src) \
16037 (dst) = ((dst) &\
16054 #define RADIO130NM_RF2G1_CH1__DB__MODIFY(dst, src) \
16055 (dst) = ((dst) &\
16072 #define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__MODIFY(dst, src) \
16073 (dst) = ((dst) &\
16103 #define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__MODIFY(dst, src) \
16104 (dst) = ((dst) &\
16121 #define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__MODIFY(dst, src) \
16122 (dst) = ((dst) &\
16139 #define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__MODIFY(dst, src) \
16140 (dst) = ((dst) &\
16157 #define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__MODIFY(dst, src) \
16158 (dst) = ((dst) &\
16175 #define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__MODIFY(dst, src) \
16176 (dst) = ((dst) &\
16193 #define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__MODIFY(dst, src) \
16194 (dst) = ((dst) &\
16211 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__MODIFY(dst, src) \
16212 (dst) = ((dst) &\
16218 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__SET(dst) \
16219 (dst) = ((dst) &\
16221 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__CLR(dst) \
16222 (dst) = ((dst) &\
16235 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__MODIFY(dst, src) \
16236 (dst) = ((dst) &\
16253 #define RADIO130NM_RF2G2_CH1__PDTXMIX__MODIFY(dst, src) \
16254 (dst) = ((dst) &\
16260 #define RADIO130NM_RF2G2_CH1__PDTXMIX__SET(dst) \
16261 (dst) = ((dst) &\
16263 #define RADIO130NM_RF2G2_CH1__PDTXMIX__CLR(dst) \
16264 (dst) = ((dst) &\
16277 #define RADIO130NM_RF2G2_CH1__PDTXLO__MODIFY(dst, src) \
16278 (dst) = ((dst) &\
16284 #define RADIO130NM_RF2G2_CH1__PDTXLO__SET(dst) \
16285 (dst) = ((dst) &\
16287 #define RADIO130NM_RF2G2_CH1__PDTXLO__CLR(dst) \
16288 (dst) = ((dst) &\
16301 #define RADIO130NM_RF2G2_CH1__PDRXLO__MODIFY(dst, src) \
16302 (dst) = ((dst) &\
16308 #define RADIO130NM_RF2G2_CH1__PDRXLO__SET(dst) \
16309 (dst) = ((dst) &\
16311 #define RADIO130NM_RF2G2_CH1__PDRXLO__CLR(dst) \
16312 (dst) = ((dst) &\
16325 #define RADIO130NM_RF2G2_CH1__PDVGM__MODIFY(dst, src) \
16326 (dst) = ((dst) &\
16332 #define RADIO130NM_RF2G2_CH1__PDVGM__SET(dst) \
16333 (dst) = ((dst) &\
16335 #define RADIO130NM_RF2G2_CH1__PDVGM__CLR(dst) \
16336 (dst) = ((dst) &\
16349 #define RADIO130NM_RF2G2_CH1__PDREGLO__MODIFY(dst, src) \
16350 (dst) = ((dst) &\
16356 #define RADIO130NM_RF2G2_CH1__PDREGLO__SET(dst) \
16357 (dst) = ((dst) &\
16359 #define RADIO130NM_RF2G2_CH1__PDREGLO__CLR(dst) \
16360 (dst) = ((dst) &\
16373 #define RADIO130NM_RF2G2_CH1__PDREGLNA__MODIFY(dst, src) \
16374 (dst) = ((dst) &\
16380 #define RADIO130NM_RF2G2_CH1__PDREGLNA__SET(dst) \
16381 (dst) = ((dst) &\
16383 #define RADIO130NM_RF2G2_CH1__PDREGLNA__CLR(dst) \
16384 (dst) = ((dst) &\
16397 #define RADIO130NM_RF2G2_CH1__PDPAOUT__MODIFY(dst, src) \
16398 (dst) = ((dst) &\
16404 #define RADIO130NM_RF2G2_CH1__PDPAOUT__SET(dst) \
16405 (dst) = ((dst) &\
16407 #define RADIO130NM_RF2G2_CH1__PDPAOUT__CLR(dst) \
16408 (dst) = ((dst) &\
16421 #define RADIO130NM_RF2G2_CH1__PDPADRV__MODIFY(dst, src) \
16422 (dst) = ((dst) &\
16428 #define RADIO130NM_RF2G2_CH1__PDPADRV__SET(dst) \
16429 (dst) = ((dst) &\
16431 #define RADIO130NM_RF2G2_CH1__PDPADRV__CLR(dst) \
16432 (dst) = ((dst) &\
16445 #define RADIO130NM_RF2G2_CH1__PDDIV__MODIFY(dst, src) \
16446 (dst) = ((dst) &\
16452 #define RADIO130NM_RF2G2_CH1__PDDIV__SET(dst) \
16453 (dst) = ((dst) &\
16455 #define RADIO130NM_RF2G2_CH1__PDDIV__CLR(dst) \
16456 (dst) = ((dst) &\
16469 #define RADIO130NM_RF2G2_CH1__PDLNA__MODIFY(dst, src) \
16470 (dst) = ((dst) &\
16476 #define RADIO130NM_RF2G2_CH1__PDLNA__SET(dst) \
16477 (dst) = ((dst) &\
16479 #define RADIO130NM_RF2G2_CH1__PDLNA__CLR(dst) \
16480 (dst) = ((dst) &\
16504 #define RADIO130NM_RF5G1_CH1__SPARE__MODIFY(dst, src) \
16505 (dst) = ((dst) &\
16522 #define RADIO130NM_RF5G1_CH1__PDREGLO5__MODIFY(dst, src) \
16523 (dst) = ((dst) &\
16529 #define RADIO130NM_RF5G1_CH1__PDREGLO5__SET(dst) \
16530 (dst) = ((dst) &\
16532 #define RADIO130NM_RF5G1_CH1__PDREGLO5__CLR(dst) \
16533 (dst) = ((dst) &\
16546 #define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__MODIFY(dst, src) \
16547 (dst) = ((dst) &\
16553 #define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__SET(dst) \
16554 (dst) = ((dst) &\
16556 #define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__CLR(dst) \
16557 (dst) = ((dst) &\
16570 #define RADIO130NM_RF5G1_CH1__LO5CONTROL__MODIFY(dst, src) \
16571 (dst) = ((dst) &\
16577 #define RADIO130NM_RF5G1_CH1__LO5CONTROL__SET(dst) \
16578 (dst) = ((dst) &\
16580 #define RADIO130NM_RF5G1_CH1__LO5CONTROL__CLR(dst) \
16581 (dst) = ((dst) &\
16594 #define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__MODIFY(dst, src) \
16595 (dst) = ((dst) &\
16612 #define RADIO130NM_RF5G1_CH1__OB5__MODIFY(dst, src) \
16613 (dst) = ((dst) &\
16630 #define RADIO130NM_RF5G1_CH1__DB5__MODIFY(dst, src) \
16631 (dst) = ((dst) &\
16648 #define RADIO130NM_RF5G1_CH1__PWDTXPKD__MODIFY(dst, src) \
16649 (dst) = ((dst) &\
16666 #define RADIO130NM_RF5G1_CH1__PACASCBIAS__MODIFY(dst, src) \
16667 (dst) = ((dst) &\
16684 #define RADIO130NM_RF5G1_CH1__PDPAOUT5__MODIFY(dst, src) \
16685 (dst) = ((dst) &\
16691 #define RADIO130NM_RF5G1_CH1__PDPAOUT5__SET(dst) \
16692 (dst) = ((dst) &\
16694 #define RADIO130NM_RF5G1_CH1__PDPAOUT5__CLR(dst) \
16695 (dst) = ((dst) &\
16708 #define RADIO130NM_RF5G1_CH1__PDPADRV5__MODIFY(dst, src) \
16709 (dst) = ((dst) &\
16715 #define RADIO130NM_RF5G1_CH1__PDPADRV5__SET(dst) \
16716 (dst) = ((dst) &\
16718 #define RADIO130NM_RF5G1_CH1__PDPADRV5__CLR(dst) \
16719 (dst) = ((dst) &\
16732 #define RADIO130NM_RF5G1_CH1__PDTXBUF5__MODIFY(dst, src) \
16733 (dst) = ((dst) &\
16739 #define RADIO130NM_RF5G1_CH1__PDTXBUF5__SET(dst) \
16740 (dst) = ((dst) &\
16742 #define RADIO130NM_RF5G1_CH1__PDTXBUF5__CLR(dst) \
16743 (dst) = ((dst) &\
16756 #define RADIO130NM_RF5G1_CH1__PDTXMIX5__MODIFY(dst, src) \
16757 (dst) = ((dst) &\
16763 #define RADIO130NM_RF5G1_CH1__PDTXMIX5__SET(dst) \
16764 (dst) = ((dst) &\
16766 #define RADIO130NM_RF5G1_CH1__PDTXMIX5__CLR(dst) \
16767 (dst) = ((dst) &\
16780 #define RADIO130NM_RF5G1_CH1__PDTXLO5__MODIFY(dst, src) \
16781 (dst) = ((dst) &\
16787 #define RADIO130NM_RF5G1_CH1__PDTXLO5__SET(dst) \
16788 (dst) = ((dst) &\
16790 #define RADIO130NM_RF5G1_CH1__PDTXLO5__CLR(dst) \
16791 (dst) = ((dst) &\
16815 #define RADIO130NM_RF5G2_CH1__SPARE__MODIFY(dst, src) \
16816 (dst) = ((dst) &\
16833 #define RADIO130NM_RF5G2_CH1__PDBIR2__MODIFY(dst, src) \
16834 (dst) = ((dst) &\
16851 #define RADIO130NM_RF5G2_CH1__PDBIR1__MODIFY(dst, src) \
16852 (dst) = ((dst) &\
16869 #define RADIO130NM_RF5G2_CH1__PDBIRTXPA__MODIFY(dst, src) \
16870 (dst) = ((dst) &\
16887 #define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__MODIFY(dst, src) \
16888 (dst) = ((dst) &\
16905 #define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__MODIFY(dst, src) \
16906 (dst) = ((dst) &\
16923 #define RADIO130NM_RF5G2_CH1__PDRFVGA5__MODIFY(dst, src) \
16924 (dst) = ((dst) &\
16930 #define RADIO130NM_RF5G2_CH1__PDRFVGA5__SET(dst) \
16931 (dst) = ((dst) &\
16933 #define RADIO130NM_RF5G2_CH1__PDRFVGA5__CLR(dst) \
16934 (dst) = ((dst) &\
16947 #define RADIO130NM_RF5G2_CH1__PDCSLNA5__MODIFY(dst, src) \
16948 (dst) = ((dst) &\
16954 #define RADIO130NM_RF5G2_CH1__PDCSLNA5__SET(dst) \
16955 (dst) = ((dst) &\
16957 #define RADIO130NM_RF5G2_CH1__PDCSLNA5__CLR(dst) \
16958 (dst) = ((dst) &\
16971 #define RADIO130NM_RF5G2_CH1__PDVGM5__MODIFY(dst, src) \
16972 (dst) = ((dst) &\
16978 #define RADIO130NM_RF5G2_CH1__PDVGM5__SET(dst) \
16979 (dst) = ((dst) &\
16981 #define RADIO130NM_RF5G2_CH1__PDVGM5__CLR(dst) \
16982 (dst) = ((dst) &\
16995 #define RADIO130NM_RF5G2_CH1__PDRXLO5__MODIFY(dst, src) \
16996 (dst) = ((dst) &\
17002 #define RADIO130NM_RF5G2_CH1__PDRXLO5__SET(dst) \
17003 (dst) = ((dst) &\
17005 #define RADIO130NM_RF5G2_CH1__PDRXLO5__CLR(dst) \
17006 (dst) = ((dst) &\
17019 #define RADIO130NM_RF5G2_CH1__PDREGFE5__MODIFY(dst, src) \
17020 (dst) = ((dst) &\
17026 #define RADIO130NM_RF5G2_CH1__PDREGFE5__SET(dst) \
17027 (dst) = ((dst) &\
17029 #define RADIO130NM_RF5G2_CH1__PDREGFE5__CLR(dst) \
17030 (dst) = ((dst) &\
17043 #define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__MODIFY(dst, src) \
17044 (dst) = ((dst) &\
17050 #define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__SET(dst) \
17051 (dst) = ((dst) &\
17053 #define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__CLR(dst) \
17054 (dst) = ((dst) &\
17078 #define RADIO130NM_RF5G3_CH1__SPARE__MODIFY(dst, src) \
17079 (dst) = ((dst) &\
17096 #define RADIO130NM_RF5G3_CH1__PDBIBCVGM__MODIFY(dst, src) \
17097 (dst) = ((dst) &\
17114 #define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__MODIFY(dst, src) \
17115 (dst) = ((dst) &\
17132 #define RADIO130NM_RF5G3_CH1__PDBIBCLNA__MODIFY(dst, src) \
17133 (dst) = ((dst) &\
17150 #define RADIO130NM_RF5G3_CH1__PDBIC3__MODIFY(dst, src) \
17151 (dst) = ((dst) &\
17168 #define RADIO130NM_RF5G3_CH1__PDBIC2__MODIFY(dst, src) \
17169 (dst) = ((dst) &\
17186 #define RADIO130NM_RF5G3_CH1__PDBIC1__MODIFY(dst, src) \
17187 (dst) = ((dst) &\
17204 #define RADIO130NM_RF5G3_CH1__PDBICTXMIX__MODIFY(dst, src) \
17205 (dst) = ((dst) &\
17222 #define RADIO130NM_RF5G3_CH1__PDBICTXPA__MODIFY(dst, src) \
17223 (dst) = ((dst) &\
17240 #define RADIO130NM_RF5G3_CH1__PDBICTXBUF__MODIFY(dst, src) \
17241 (dst) = ((dst) &\
17269 #define RADIO130NM_RXTXBB1_CH0__PDHIQ__MODIFY(dst, src) \
17270 (dst) = ((dst) &\
17276 #define RADIO130NM_RXTXBB1_CH0__PDHIQ__SET(dst) \
17277 (dst) = ((dst) &\
17279 #define RADIO130NM_RXTXBB1_CH0__PDHIQ__CLR(dst) \
17280 (dst) = ((dst) &\
17293 #define RADIO130NM_RXTXBB1_CH0__PDLOQ__MODIFY(dst, src) \
17294 (dst) = ((dst) &\
17300 #define RADIO130NM_RXTXBB1_CH0__PDLOQ__SET(dst) \
17301 (dst) = ((dst) &\
17303 #define RADIO130NM_RXTXBB1_CH0__PDLOQ__CLR(dst) \
17304 (dst) = ((dst) &\
17317 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__MODIFY(dst, src) \
17318 (dst) = ((dst) &\
17324 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__SET(dst) \
17325 (dst) = ((dst) &\
17327 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__CLR(dst) \
17328 (dst) = ((dst) &\
17341 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__MODIFY(dst, src) \
17342 (dst) = ((dst) &\
17348 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__SET(dst) \
17349 (dst) = ((dst) &\
17351 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__CLR(dst) \
17352 (dst) = ((dst) &\
17365 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__MODIFY(dst, src) \
17366 (dst) = ((dst) &\
17372 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__SET(dst) \
17373 (dst) = ((dst) &\
17375 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__CLR(dst) \
17376 (dst) = ((dst) &\
17389 #define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__MODIFY(dst, src) \
17390 (dst) = ((dst) &\
17396 #define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__SET(dst) \
17397 (dst) = ((dst) &\
17399 #define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__CLR(dst) \
17400 (dst) = ((dst) &\
17413 #define RADIO130NM_RXTXBB1_CH0__PDI2V__MODIFY(dst, src) \
17414 (dst) = ((dst) &\
17420 #define RADIO130NM_RXTXBB1_CH0__PDI2V__SET(dst) \
17421 (dst) = ((dst) &\
17423 #define RADIO130NM_RXTXBB1_CH0__PDI2V__CLR(dst) \
17424 (dst) = ((dst) &\
17437 #define RADIO130NM_RXTXBB1_CH0__PDV2I__MODIFY(dst, src) \
17438 (dst) = ((dst) &\
17444 #define RADIO130NM_RXTXBB1_CH0__PDV2I__SET(dst) \
17445 (dst) = ((dst) &\
17447 #define RADIO130NM_RXTXBB1_CH0__PDV2I__CLR(dst) \
17448 (dst) = ((dst) &\
17461 #define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__MODIFY(dst, src) \
17462 (dst) = ((dst) &\
17468 #define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__SET(dst) \
17469 (dst) = ((dst) &\
17471 #define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__CLR(dst) \
17472 (dst) = ((dst) &\
17485 #define RADIO130NM_RXTXBB1_CH0__SEL_ATB__MODIFY(dst, src) \
17486 (dst) = ((dst) &\
17503 #define RADIO130NM_RXTXBB1_CH0__FNOTCH__MODIFY(dst, src) \
17504 (dst) = ((dst) &\
17521 #define RADIO130NM_RXTXBB1_CH0__SPARE__MODIFY(dst, src) \
17522 (dst) = ((dst) &\
17552 #define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__MODIFY(dst, src) \
17553 (dst) = ((dst) &\
17559 #define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__SET(dst) \
17560 (dst) = ((dst) &\
17562 #define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__CLR(dst) \
17563 (dst) = ((dst) &\
17576 #define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__MODIFY(dst, src) \
17577 (dst) = ((dst) &\
17583 #define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__SET(dst) \
17584 (dst) = ((dst) &\
17586 #define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__CLR(dst) \
17587 (dst) = ((dst) &\
17600 #define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__MODIFY(dst, src) \
17601 (dst) = ((dst) &\
17607 #define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__SET(dst) \
17608 (dst) = ((dst) &\
17610 #define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__CLR(dst) \
17611 (dst) = ((dst) &\
17624 #define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__MODIFY(dst, src) \
17625 (dst) = ((dst) &\
17631 #define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__SET(dst) \
17632 (dst) = ((dst) &\
17634 #define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__CLR(dst) \
17635 (dst) = ((dst) &\
17648 #define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__MODIFY(dst, src) \
17649 (dst) = ((dst) &\
17655 #define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__SET(dst) \
17656 (dst) = ((dst) &\
17658 #define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__CLR(dst) \
17659 (dst) = ((dst) &\
17672 #define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__MODIFY(dst, src) \
17673 (dst) = ((dst) &\
17679 #define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__SET(dst) \
17680 (dst) = ((dst) &\
17682 #define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__CLR(dst) \
17683 (dst) = ((dst) &\
17696 #define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__MODIFY(dst, src) \
17697 (dst) = ((dst) &\
17703 #define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__SET(dst) \
17704 (dst) = ((dst) &\
17706 #define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__CLR(dst) \
17707 (dst) = ((dst) &\
17720 #define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__MODIFY(dst, src) \
17721 (dst) = ((dst) &\
17727 #define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__SET(dst) \
17728 (dst) = ((dst) &\
17730 #define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__CLR(dst) \
17731 (dst) = ((dst) &\
17744 #define RADIO130NM_RXTXBB2_CH0__FILTERFC__MODIFY(dst, src) \
17745 (dst) = ((dst) &\
17762 #define RADIO130NM_RXTXBB2_CH0__CMSEL__MODIFY(dst, src) \
17763 (dst) = ((dst) &\
17780 #define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__MODIFY(dst, src) \
17781 (dst) = ((dst) &\
17787 #define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__SET(dst) \
17788 (dst) = ((dst) &\
17790 #define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__CLR(dst) \
17791 (dst) = ((dst) &\
17804 #define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__MODIFY(dst, src) \
17805 (dst) = ((dst) &\
17811 #define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__SET(dst) \
17812 (dst) = ((dst) &\
17814 #define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__CLR(dst) \
17815 (dst) = ((dst) &\
17828 #define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__MODIFY(dst, src) \
17829 (dst) = ((dst) &\
17835 #define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__SET(dst) \
17836 (dst) = ((dst) &\
17838 #define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__CLR(dst) \
17839 (dst) = ((dst) &\
17852 #define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__MODIFY(dst, src) \
17853 (dst) = ((dst) &\
17859 #define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__SET(dst) \
17860 (dst) = ((dst) &\
17862 #define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__CLR(dst) \
17863 (dst) = ((dst) &\
17876 #define RADIO130NM_RXTXBB2_CH0__SELBUFFER__MODIFY(dst, src) \
17877 (dst) = ((dst) &\
17883 #define RADIO130NM_RXTXBB2_CH0__SELBUFFER__SET(dst) \
17884 (dst) = ((dst) &\
17886 #define RADIO130NM_RXTXBB2_CH0__SELBUFFER__CLR(dst) \
17887 (dst) = ((dst) &\
17900 #define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__MODIFY(dst, src) \
17901 (dst) = ((dst) &\
17907 #define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__SET(dst) \
17908 (dst) = ((dst) &\
17910 #define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__CLR(dst) \
17911 (dst) = ((dst) &\
17924 #define RADIO130NM_RXTXBB2_CH0__SPARE__MODIFY(dst, src) \
17925 (dst) = ((dst) &\
17942 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__MODIFY(dst, src) \
17943 (dst) = ((dst) &\
17960 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__MODIFY(dst, src) \
17961 (dst) = ((dst) &\
17978 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__MODIFY(dst, src) \
17979 (dst) = ((dst) &\
18009 #define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__MODIFY(dst, src) \
18010 (dst) = ((dst) &\
18027 #define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__MODIFY(dst, src) \
18028 (dst) = ((dst) &\
18045 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__MODIFY(dst, src) \
18046 (dst) = ((dst) &\
18063 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__MODIFY(dst, src) \
18064 (dst) = ((dst) &\
18081 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__MODIFY(dst, src) \
18082 (dst) = ((dst) &\
18099 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__MODIFY(dst, src) \
18100 (dst) = ((dst) &\
18117 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__MODIFY(dst, src) \
18118 (dst) = ((dst) &\
18135 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__MODIFY(dst, src) \
18136 (dst) = ((dst) &\
18153 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__MODIFY(dst, src) \
18154 (dst) = ((dst) &\
18171 #define RADIO130NM_RXTXBB3_CH0__SPARE__MODIFY(dst, src) \
18172 (dst) = ((dst) &\
18202 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__MODIFY(dst, src) \
18203 (dst) = ((dst) &\
18220 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__MODIFY(dst, src) \
18221 (dst) = ((dst) &\
18238 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__MODIFY(dst, src) \
18239 (dst) = ((dst) &\
18256 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__MODIFY(dst, src) \
18257 (dst) = ((dst) &\
18274 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__MODIFY(dst, src) \
18275 (dst) = ((dst) &\
18292 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__MODIFY(dst, src) \
18293 (dst) = ((dst) &\
18310 #define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__MODIFY(dst, src) \
18311 (dst) = ((dst) &\
18317 #define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__SET(dst) \
18318 (dst) = ((dst) &\
18320 #define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__CLR(dst) \
18321 (dst) = ((dst) &\
18334 #define RADIO130NM_RXTXBB4_CH0__SPARE__MODIFY(dst, src) \
18335 (dst) = ((dst) &\
18341 #define RADIO130NM_RXTXBB4_CH0__SPARE__SET(dst) \
18342 (dst) = ((dst) &\
18344 #define RADIO130NM_RXTXBB4_CH0__SPARE__CLR(dst) \
18345 (dst) = ((dst) &\
18369 #define RADIO130NM_RF5G1_CH0__SPARE__MODIFY(dst, src) \
18370 (dst) = ((dst) &\
18387 #define RADIO130NM_RF5G1_CH0__PDREGLO5__MODIFY(dst, src) \
18388 (dst) = ((dst) &\
18394 #define RADIO130NM_RF5G1_CH0__PDREGLO5__SET(dst) \
18395 (dst) = ((dst) &\
18397 #define RADIO130NM_RF5G1_CH0__PDREGLO5__CLR(dst) \
18398 (dst) = ((dst) &\
18411 #define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__MODIFY(dst, src) \
18412 (dst) = ((dst) &\
18418 #define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__SET(dst) \
18419 (dst) = ((dst) &\
18421 #define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__CLR(dst) \
18422 (dst) = ((dst) &\
18435 #define RADIO130NM_RF5G1_CH0__LO5CONTROL__MODIFY(dst, src) \
18436 (dst) = ((dst) &\
18442 #define RADIO130NM_RF5G1_CH0__LO5CONTROL__SET(dst) \
18443 (dst) = ((dst) &\
18445 #define RADIO130NM_RF5G1_CH0__LO5CONTROL__CLR(dst) \
18446 (dst) = ((dst) &\
18459 #define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__MODIFY(dst, src) \
18460 (dst) = ((dst) &\
18477 #define RADIO130NM_RF5G1_CH0__OB5__MODIFY(dst, src) \
18478 (dst) = ((dst) &\
18495 #define RADIO130NM_RF5G1_CH0__DB5__MODIFY(dst, src) \
18496 (dst) = ((dst) &\
18513 #define RADIO130NM_RF5G1_CH0__PWDTXPKD__MODIFY(dst, src) \
18514 (dst) = ((dst) &\
18531 #define RADIO130NM_RF5G1_CH0__PACASCBIAS__MODIFY(dst, src) \
18532 (dst) = ((dst) &\
18549 #define RADIO130NM_RF5G1_CH0__PDPAOUT5__MODIFY(dst, src) \
18550 (dst) = ((dst) &\
18556 #define RADIO130NM_RF5G1_CH0__PDPAOUT5__SET(dst) \
18557 (dst) = ((dst) &\
18559 #define RADIO130NM_RF5G1_CH0__PDPAOUT5__CLR(dst) \
18560 (dst) = ((dst) &\
18573 #define RADIO130NM_RF5G1_CH0__PDPADRV5__MODIFY(dst, src) \
18574 (dst) = ((dst) &\
18580 #define RADIO130NM_RF5G1_CH0__PDPADRV5__SET(dst) \
18581 (dst) = ((dst) &\
18583 #define RADIO130NM_RF5G1_CH0__PDPADRV5__CLR(dst) \
18584 (dst) = ((dst) &\
18597 #define RADIO130NM_RF5G1_CH0__PDTXBUF5__MODIFY(dst, src) \
18598 (dst) = ((dst) &\
18604 #define RADIO130NM_RF5G1_CH0__PDTXBUF5__SET(dst) \
18605 (dst) = ((dst) &\
18607 #define RADIO130NM_RF5G1_CH0__PDTXBUF5__CLR(dst) \
18608 (dst) = ((dst) &\
18621 #define RADIO130NM_RF5G1_CH0__PDTXMIX5__MODIFY(dst, src) \
18622 (dst) = ((dst) &\
18628 #define RADIO130NM_RF5G1_CH0__PDTXMIX5__SET(dst) \
18629 (dst) = ((dst) &\
18631 #define RADIO130NM_RF5G1_CH0__PDTXMIX5__CLR(dst) \
18632 (dst) = ((dst) &\
18645 #define RADIO130NM_RF5G1_CH0__PDTXLO5__MODIFY(dst, src) \
18646 (dst) = ((dst) &\
18652 #define RADIO130NM_RF5G1_CH0__PDTXLO5__SET(dst) \
18653 (dst) = ((dst) &\
18655 #define RADIO130NM_RF5G1_CH0__PDTXLO5__CLR(dst) \
18656 (dst) = ((dst) &\
18680 #define RADIO130NM_RF5G2_CH0__SPARE__MODIFY(dst, src) \
18681 (dst) = ((dst) &\
18698 #define RADIO130NM_RF5G2_CH0__PDBIR2__MODIFY(dst, src) \
18699 (dst) = ((dst) &\
18716 #define RADIO130NM_RF5G2_CH0__PDBIR1__MODIFY(dst, src) \
18717 (dst) = ((dst) &\
18734 #define RADIO130NM_RF5G2_CH0__PDBIRTXPA__MODIFY(dst, src) \
18735 (dst) = ((dst) &\
18752 #define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__MODIFY(dst, src) \
18753 (dst) = ((dst) &\
18770 #define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__MODIFY(dst, src) \
18771 (dst) = ((dst) &\
18788 #define RADIO130NM_RF5G2_CH0__PDRFVGA5__MODIFY(dst, src) \
18789 (dst) = ((dst) &\
18795 #define RADIO130NM_RF5G2_CH0__PDRFVGA5__SET(dst) \
18796 (dst) = ((dst) &\
18798 #define RADIO130NM_RF5G2_CH0__PDRFVGA5__CLR(dst) \
18799 (dst) = ((dst) &\
18812 #define RADIO130NM_RF5G2_CH0__PDCSLNA5__MODIFY(dst, src) \
18813 (dst) = ((dst) &\
18819 #define RADIO130NM_RF5G2_CH0__PDCSLNA5__SET(dst) \
18820 (dst) = ((dst) &\
18822 #define RADIO130NM_RF5G2_CH0__PDCSLNA5__CLR(dst) \
18823 (dst) = ((dst) &\
18836 #define RADIO130NM_RF5G2_CH0__PDVGM5__MODIFY(dst, src) \
18837 (dst) = ((dst) &\
18843 #define RADIO130NM_RF5G2_CH0__PDVGM5__SET(dst) \
18844 (dst) = ((dst) &\
18846 #define RADIO130NM_RF5G2_CH0__PDVGM5__CLR(dst) \
18847 (dst) = ((dst) &\
18860 #define RADIO130NM_RF5G2_CH0__PDRXLO5__MODIFY(dst, src) \
18861 (dst) = ((dst) &\
18867 #define RADIO130NM_RF5G2_CH0__PDRXLO5__SET(dst) \
18868 (dst) = ((dst) &\
18870 #define RADIO130NM_RF5G2_CH0__PDRXLO5__CLR(dst) \
18871 (dst) = ((dst) &\
18884 #define RADIO130NM_RF5G2_CH0__PDREGFE5__MODIFY(dst, src) \
18885 (dst) = ((dst) &\
18891 #define RADIO130NM_RF5G2_CH0__PDREGFE5__SET(dst) \
18892 (dst) = ((dst) &\
18894 #define RADIO130NM_RF5G2_CH0__PDREGFE5__CLR(dst) \
18895 (dst) = ((dst) &\
18908 #define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__MODIFY(dst, src) \
18909 (dst) = ((dst) &\
18915 #define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__SET(dst) \
18916 (dst) = ((dst) &\
18918 #define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__CLR(dst) \
18919 (dst) = ((dst) &\
18943 #define RADIO130NM_RF5G3_CH0__SPARE__MODIFY(dst, src) \
18944 (dst) = ((dst) &\
18961 #define RADIO130NM_RF5G3_CH0__PDBIBCVGM__MODIFY(dst, src) \
18962 (dst) = ((dst) &\
18979 #define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__MODIFY(dst, src) \
18980 (dst) = ((dst) &\
18997 #define RADIO130NM_RF5G3_CH0__PDBIBCLNA__MODIFY(dst, src) \
18998 (dst) = ((dst) &\
19015 #define RADIO130NM_RF5G3_CH0__PDBIC3__MODIFY(dst, src) \
19016 (dst) = ((dst) &\
19033 #define RADIO130NM_RF5G3_CH0__PDBIC2__MODIFY(dst, src) \
19034 (dst) = ((dst) &\
19051 #define RADIO130NM_RF5G3_CH0__PDBIC1__MODIFY(dst, src) \
19052 (dst) = ((dst) &\
19069 #define RADIO130NM_RF5G3_CH0__PDBICTXMIX__MODIFY(dst, src) \
19070 (dst) = ((dst) &\
19087 #define RADIO130NM_RF5G3_CH0__PDBICTXPA__MODIFY(dst, src) \
19088 (dst) = ((dst) &\
19105 #define RADIO130NM_RF5G3_CH0__PDBICTXBUF__MODIFY(dst, src) \
19106 (dst) = ((dst) &\
19134 #define RADIO130NM_RF2G1_CH0__SPARES__MODIFY(dst, src) \
19135 (dst) = ((dst) &\
19152 #define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__MODIFY(dst, src) \
19153 (dst) = ((dst) &\
19159 #define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__SET(dst) \
19160 (dst) = ((dst) &\
19162 #define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__CLR(dst) \
19163 (dst) = ((dst) &\
19176 #define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__MODIFY(dst, src) \
19177 (dst) = ((dst) &\
19183 #define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__SET(dst) \
19184 (dst) = ((dst) &\
19186 #define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__CLR(dst) \
19187 (dst) = ((dst) &\
19200 #define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__MODIFY(dst, src) \
19201 (dst) = ((dst) &\
19218 #define RADIO130NM_RF2G1_CH0__PACA_SEL__MODIFY(dst, src) \
19219 (dst) = ((dst) &\
19236 #define RADIO130NM_RF2G1_CH0__LOCONTROL__MODIFY(dst, src) \
19237 (dst) = ((dst) &\
19243 #define RADIO130NM_RF2G1_CH0__LOCONTROL__SET(dst) \
19244 (dst) = ((dst) &\
19246 #define RADIO130NM_RF2G1_CH0__LOCONTROL__CLR(dst) \
19247 (dst) = ((dst) &\
19260 #define RADIO130NM_RF2G1_CH0__TXATB_SEL__MODIFY(dst, src) \
19261 (dst) = ((dst) &\
19278 #define RADIO130NM_RF2G1_CH0__RXATB_SEL__MODIFY(dst, src) \
19279 (dst) = ((dst) &\
19296 #define RADIO130NM_RF2G1_CH0__LOATB_SEL__MODIFY(dst, src) \
19297 (dst) = ((dst) &\
19314 #define RADIO130NM_RF2G1_CH0__OB__MODIFY(dst, src) \
19315 (dst) = ((dst) &\
19332 #define RADIO130NM_RF2G1_CH0__DB__MODIFY(dst, src) \
19333 (dst) = ((dst) &\
19350 #define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__MODIFY(dst, src) \
19351 (dst) = ((dst) &\
19381 #define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__MODIFY(dst, src) \
19382 (dst) = ((dst) &\
19399 #define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__MODIFY(dst, src) \
19400 (dst) = ((dst) &\
19417 #define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__MODIFY(dst, src) \
19418 (dst) = ((dst) &\
19435 #define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__MODIFY(dst, src) \
19436 (dst) = ((dst) &\
19453 #define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__MODIFY(dst, src) \
19454 (dst) = ((dst) &\
19471 #define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__MODIFY(dst, src) \
19472 (dst) = ((dst) &\
19489 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__MODIFY(dst, src) \
19490 (dst) = ((dst) &\
19496 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__SET(dst) \
19497 (dst) = ((dst) &\
19499 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__CLR(dst) \
19500 (dst) = ((dst) &\
19513 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__MODIFY(dst, src) \
19514 (dst) = ((dst) &\
19531 #define RADIO130NM_RF2G2_CH0__PDTXMIX__MODIFY(dst, src) \
19532 (dst) = ((dst) &\
19538 #define RADIO130NM_RF2G2_CH0__PDTXMIX__SET(dst) \
19539 (dst) = ((dst) &\
19541 #define RADIO130NM_RF2G2_CH0__PDTXMIX__CLR(dst) \
19542 (dst) = ((dst) &\
19555 #define RADIO130NM_RF2G2_CH0__PDTXLO__MODIFY(dst, src) \
19556 (dst) = ((dst) &\
19562 #define RADIO130NM_RF2G2_CH0__PDTXLO__SET(dst) \
19563 (dst) = ((dst) &\
19565 #define RADIO130NM_RF2G2_CH0__PDTXLO__CLR(dst) \
19566 (dst) = ((dst) &\
19579 #define RADIO130NM_RF2G2_CH0__PDRXLO__MODIFY(dst, src) \
19580 (dst) = ((dst) &\
19586 #define RADIO130NM_RF2G2_CH0__PDRXLO__SET(dst) \
19587 (dst) = ((dst) &\
19589 #define RADIO130NM_RF2G2_CH0__PDRXLO__CLR(dst) \
19590 (dst) = ((dst) &\
19603 #define RADIO130NM_RF2G2_CH0__PDVGM__MODIFY(dst, src) \
19604 (dst) = ((dst) &\
19610 #define RADIO130NM_RF2G2_CH0__PDVGM__SET(dst) \
19611 (dst) = ((dst) &\
19613 #define RADIO130NM_RF2G2_CH0__PDVGM__CLR(dst) \
19614 (dst) = ((dst) &\
19627 #define RADIO130NM_RF2G2_CH0__PDREGLO__MODIFY(dst, src) \
19628 (dst) = ((dst) &\
19634 #define RADIO130NM_RF2G2_CH0__PDREGLO__SET(dst) \
19635 (dst) = ((dst) &\
19637 #define RADIO130NM_RF2G2_CH0__PDREGLO__CLR(dst) \
19638 (dst) = ((dst) &\
19651 #define RADIO130NM_RF2G2_CH0__PDREGLNA__MODIFY(dst, src) \
19652 (dst) = ((dst) &\
19658 #define RADIO130NM_RF2G2_CH0__PDREGLNA__SET(dst) \
19659 (dst) = ((dst) &\
19661 #define RADIO130NM_RF2G2_CH0__PDREGLNA__CLR(dst) \
19662 (dst) = ((dst) &\
19675 #define RADIO130NM_RF2G2_CH0__PDPAOUT__MODIFY(dst, src) \
19676 (dst) = ((dst) &\
19682 #define RADIO130NM_RF2G2_CH0__PDPAOUT__SET(dst) \
19683 (dst) = ((dst) &\
19685 #define RADIO130NM_RF2G2_CH0__PDPAOUT__CLR(dst) \
19686 (dst) = ((dst) &\
19699 #define RADIO130NM_RF2G2_CH0__PDPADRV__MODIFY(dst, src) \
19700 (dst) = ((dst) &\
19706 #define RADIO130NM_RF2G2_CH0__PDPADRV__SET(dst) \
19707 (dst) = ((dst) &\
19709 #define RADIO130NM_RF2G2_CH0__PDPADRV__CLR(dst) \
19710 (dst) = ((dst) &\
19723 #define RADIO130NM_RF2G2_CH0__PDDIV__MODIFY(dst, src) \
19724 (dst) = ((dst) &\
19730 #define RADIO130NM_RF2G2_CH0__PDDIV__SET(dst) \
19731 (dst) = ((dst) &\
19733 #define RADIO130NM_RF2G2_CH0__PDDIV__CLR(dst) \
19734 (dst) = ((dst) &\
19747 #define RADIO130NM_RF2G2_CH0__PDLNA__MODIFY(dst, src) \
19748 (dst) = ((dst) &\
19754 #define RADIO130NM_RF2G2_CH0__PDLNA__SET(dst) \
19755 (dst) = ((dst) &\
19757 #define RADIO130NM_RF2G2_CH0__PDLNA__CLR(dst) \
19758 (dst) = ((dst) &\
19784 #define RADIO130NM_SYNTH1__SEL_VCMONABUS__MODIFY(dst, src) \
19785 (dst) = ((dst) &\
19802 #define RADIO130NM_SYNTH1__CON_IVCOBUF__MODIFY(dst, src) \
19803 (dst) = ((dst) &\
19809 #define RADIO130NM_SYNTH1__CON_IVCOBUF__SET(dst) \
19810 (dst) = ((dst) &\
19812 #define RADIO130NM_SYNTH1__CON_IVCOBUF__CLR(dst) \
19813 (dst) = ((dst) &\
19826 #define RADIO130NM_SYNTH1__CON_IVCOREG__MODIFY(dst, src) \
19827 (dst) = ((dst) &\
19833 #define RADIO130NM_SYNTH1__CON_IVCOREG__SET(dst) \
19834 (dst) = ((dst) &\
19836 #define RADIO130NM_SYNTH1__CON_IVCOREG__CLR(dst) \
19837 (dst) = ((dst) &\
19850 #define RADIO130NM_SYNTH1__CON_VDDVCOREG__MODIFY(dst, src) \
19851 (dst) = ((dst) &\
19857 #define RADIO130NM_SYNTH1__CON_VDDVCOREG__SET(dst) \
19858 (dst) = ((dst) &\
19860 #define RADIO130NM_SYNTH1__CON_VDDVCOREG__CLR(dst) \
19861 (dst) = ((dst) &\
19874 #define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__MODIFY(dst, src) \
19875 (dst) = ((dst) &\
19881 #define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__SET(dst) \
19882 (dst) = ((dst) &\
19884 #define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__CLR(dst) \
19885 (dst) = ((dst) &\
19898 #define RADIO130NM_SYNTH1__MONITOR_VC2LOW__MODIFY(dst, src) \
19899 (dst) = ((dst) &\
19905 #define RADIO130NM_SYNTH1__MONITOR_VC2LOW__SET(dst) \
19906 (dst) = ((dst) &\
19908 #define RADIO130NM_SYNTH1__MONITOR_VC2LOW__CLR(dst) \
19909 (dst) = ((dst) &\
19922 #define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__MODIFY(dst, src) \
19923 (dst) = ((dst) &\
19929 #define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__SET(dst) \
19930 (dst) = ((dst) &\
19932 #define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__CLR(dst) \
19933 (dst) = ((dst) &\
19946 #define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__MODIFY(dst, src) \
19947 (dst) = ((dst) &\
19953 #define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__SET(dst) \
19954 (dst) = ((dst) &\
19956 #define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__CLR(dst) \
19957 (dst) = ((dst) &\
19970 #define RADIO130NM_SYNTH1__MONITOR_REF__MODIFY(dst, src) \
19971 (dst) = ((dst) &\
19977 #define RADIO130NM_SYNTH1__MONITOR_REF__SET(dst) \
19978 (dst) = ((dst) &\
19980 #define RADIO130NM_SYNTH1__MONITOR_REF__CLR(dst) \
19981 (dst) = ((dst) &\
19994 #define RADIO130NM_SYNTH1__MONITOR_FB__MODIFY(dst, src) \
19995 (dst) = ((dst) &\
20001 #define RADIO130NM_SYNTH1__MONITOR_FB__SET(dst) \
20002 (dst) = ((dst) &\
20004 #define RADIO130NM_SYNTH1__MONITOR_FB__CLR(dst) \
20005 (dst) = ((dst) &\
20018 #define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__MODIFY(dst, src) \
20019 (dst) = ((dst) &\
20025 #define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__SET(dst) \
20026 (dst) = ((dst) &\
20028 #define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__CLR(dst) \
20029 (dst) = ((dst) &\
20042 #define RADIO130NM_SYNTH1__PWUP_LODIV_PD__MODIFY(dst, src) \
20043 (dst) = ((dst) &\
20049 #define RADIO130NM_SYNTH1__PWUP_LODIV_PD__SET(dst) \
20050 (dst) = ((dst) &\
20052 #define RADIO130NM_SYNTH1__PWUP_LODIV_PD__CLR(dst) \
20053 (dst) = ((dst) &\
20066 #define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__MODIFY(dst, src) \
20067 (dst) = ((dst) &\
20073 #define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__SET(dst) \
20074 (dst) = ((dst) &\
20076 #define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__CLR(dst) \
20077 (dst) = ((dst) &\
20090 #define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__MODIFY(dst, src) \
20091 (dst) = ((dst) &\
20097 #define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__SET(dst) \
20098 (dst) = ((dst) &\
20100 #define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__CLR(dst) \
20101 (dst) = ((dst) &\
20114 #define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__MODIFY(dst, src) \
20115 (dst) = ((dst) &\
20121 #define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__SET(dst) \
20122 (dst) = ((dst) &\
20124 #define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__CLR(dst) \
20125 (dst) = ((dst) &\
20138 #define RADIO130NM_SYNTH1__VCOBUFBIAS__MODIFY(dst, src) \
20139 (dst) = ((dst) &\
20156 #define RADIO130NM_SYNTH1__VCOREGLEVEL__MODIFY(dst, src) \
20157 (dst) = ((dst) &\
20174 #define RADIO130NM_SYNTH1__VCOREGBYPASS__MODIFY(dst, src) \
20175 (dst) = ((dst) &\
20181 #define RADIO130NM_SYNTH1__VCOREGBYPASS__SET(dst) \
20182 (dst) = ((dst) &\
20184 #define RADIO130NM_SYNTH1__VCOREGBYPASS__CLR(dst) \
20185 (dst) = ((dst) &\
20198 #define RADIO130NM_SYNTH1__PWUP_LOREF__MODIFY(dst, src) \
20199 (dst) = ((dst) &\
20205 #define RADIO130NM_SYNTH1__PWUP_LOREF__SET(dst) \
20206 (dst) = ((dst) &\
20208 #define RADIO130NM_SYNTH1__PWUP_LOREF__CLR(dst) \
20209 (dst) = ((dst) &\
20222 #define RADIO130NM_SYNTH1__PWD_LOMIX__MODIFY(dst, src) \
20223 (dst) = ((dst) &\
20229 #define RADIO130NM_SYNTH1__PWD_LOMIX__SET(dst) \
20230 (dst) = ((dst) &\
20232 #define RADIO130NM_SYNTH1__PWD_LOMIX__CLR(dst) \
20233 (dst) = ((dst) &\
20246 #define RADIO130NM_SYNTH1__PWD_LODIV__MODIFY(dst, src) \
20247 (dst) = ((dst) &\
20253 #define RADIO130NM_SYNTH1__PWD_LODIV__SET(dst) \
20254 (dst) = ((dst) &\
20256 #define RADIO130NM_SYNTH1__PWD_LODIV__CLR(dst) \
20257 (dst) = ((dst) &\
20270 #define RADIO130NM_SYNTH1__PWD_LOBUF5G__MODIFY(dst, src) \
20271 (dst) = ((dst) &\
20277 #define RADIO130NM_SYNTH1__PWD_LOBUF5G__SET(dst) \
20278 (dst) = ((dst) &\
20280 #define RADIO130NM_SYNTH1__PWD_LOBUF5G__CLR(dst) \
20281 (dst) = ((dst) &\
20294 #define RADIO130NM_SYNTH1__PWD_LOBUF2G__MODIFY(dst, src) \
20295 (dst) = ((dst) &\
20301 #define RADIO130NM_SYNTH1__PWD_LOBUF2G__SET(dst) \
20302 (dst) = ((dst) &\
20304 #define RADIO130NM_SYNTH1__PWD_LOBUF2G__CLR(dst) \
20305 (dst) = ((dst) &\
20318 #define RADIO130NM_SYNTH1__PWD_PRESC__MODIFY(dst, src) \
20319 (dst) = ((dst) &\
20325 #define RADIO130NM_SYNTH1__PWD_PRESC__SET(dst) \
20326 (dst) = ((dst) &\
20328 #define RADIO130NM_SYNTH1__PWD_PRESC__CLR(dst) \
20329 (dst) = ((dst) &\
20342 #define RADIO130NM_SYNTH1__PWD_VCO__MODIFY(dst, src) \
20343 (dst) = ((dst) &\
20349 #define RADIO130NM_SYNTH1__PWD_VCO__SET(dst) \
20350 (dst) = ((dst) &\
20352 #define RADIO130NM_SYNTH1__PWD_VCO__CLR(dst) \
20353 (dst) = ((dst) &\
20366 #define RADIO130NM_SYNTH1__PWD_VCMON__MODIFY(dst, src) \
20367 (dst) = ((dst) &\
20373 #define RADIO130NM_SYNTH1__PWD_VCMON__SET(dst) \
20374 (dst) = ((dst) &\
20376 #define RADIO130NM_SYNTH1__PWD_VCMON__CLR(dst) \
20377 (dst) = ((dst) &\
20390 #define RADIO130NM_SYNTH1__PWD_CP__MODIFY(dst, src) \
20391 (dst) = ((dst) &\
20397 #define RADIO130NM_SYNTH1__PWD_CP__SET(dst) \
20398 (dst) = ((dst) &\
20400 #define RADIO130NM_SYNTH1__PWD_CP__CLR(dst) \
20401 (dst) = ((dst) &\
20414 #define RADIO130NM_SYNTH1__PWD_BIAS__MODIFY(dst, src) \
20415 (dst) = ((dst) &\
20421 #define RADIO130NM_SYNTH1__PWD_BIAS__SET(dst) \
20422 (dst) = ((dst) &\
20424 #define RADIO130NM_SYNTH1__PWD_BIAS__CLR(dst) \
20425 (dst) = ((dst) &\
20449 #define RADIO130NM_SYNTH2__CAPRANGE3__MODIFY(dst, src) \
20450 (dst) = ((dst) &\
20467 #define RADIO130NM_SYNTH2__CAPRANGE2__MODIFY(dst, src) \
20468 (dst) = ((dst) &\
20485 #define RADIO130NM_SYNTH2__CAPRANGE1__MODIFY(dst, src) \
20486 (dst) = ((dst) &\
20503 #define RADIO130NM_SYNTH2__LOOPLEAKCUR__MODIFY(dst, src) \
20504 (dst) = ((dst) &\
20521 #define RADIO130NM_SYNTH2__CPLOWLK__MODIFY(dst, src) \
20522 (dst) = ((dst) &\
20528 #define RADIO130NM_SYNTH2__CPLOWLK__SET(dst) \
20529 (dst) = ((dst) &\
20531 #define RADIO130NM_SYNTH2__CPLOWLK__CLR(dst) \
20532 (dst) = ((dst) &\
20545 #define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__MODIFY(dst, src) \
20546 (dst) = ((dst) &\
20552 #define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__SET(dst) \
20553 (dst) = ((dst) &\
20555 #define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__CLR(dst) \
20556 (dst) = ((dst) &\
20569 #define RADIO130NM_SYNTH2__CPBIAS__MODIFY(dst, src) \
20570 (dst) = ((dst) &\
20587 #define RADIO130NM_SYNTH2__VC_LOW_REF__MODIFY(dst, src) \
20588 (dst) = ((dst) &\
20605 #define RADIO130NM_SYNTH2__VC_MID_REF__MODIFY(dst, src) \
20606 (dst) = ((dst) &\
20623 #define RADIO130NM_SYNTH2__VC_HI_REF__MODIFY(dst, src) \
20624 (dst) = ((dst) &\
20641 #define RADIO130NM_SYNTH2__VC_CAL_REF__MODIFY(dst, src) \
20642 (dst) = ((dst) &\
20672 #define RADIO130NM_SYNTH3__WAIT_VC_CHECK__MODIFY(dst, src) \
20673 (dst) = ((dst) &\
20690 #define RADIO130NM_SYNTH3__WAIT_CAL_LIN__MODIFY(dst, src) \
20691 (dst) = ((dst) &\
20708 #define RADIO130NM_SYNTH3__WAIT_CAL_BIN__MODIFY(dst, src) \
20709 (dst) = ((dst) &\
20726 #define RADIO130NM_SYNTH3__WAIT_PWRUP__MODIFY(dst, src) \
20727 (dst) = ((dst) &\
20744 #define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__MODIFY(dst, src) \
20745 (dst) = ((dst) &\
20762 #define RADIO130NM_SYNTH3__SEL_CLK_DIV2__MODIFY(dst, src) \
20763 (dst) = ((dst) &\
20769 #define RADIO130NM_SYNTH3__SEL_CLK_DIV2__SET(dst) \
20770 (dst) = ((dst) &\
20772 #define RADIO130NM_SYNTH3__SEL_CLK_DIV2__CLR(dst) \
20773 (dst) = ((dst) &\
20786 #define RADIO130NM_SYNTH3__DIS_CLK_XTAL__MODIFY(dst, src) \
20787 (dst) = ((dst) &\
20793 #define RADIO130NM_SYNTH3__DIS_CLK_XTAL__SET(dst) \
20794 (dst) = ((dst) &\
20796 #define RADIO130NM_SYNTH3__DIS_CLK_XTAL__CLR(dst) \
20797 (dst) = ((dst) &\
20823 #define RADIO130NM_SYNTH4__FORCE_SHIFTREG__MODIFY(dst, src) \
20824 (dst) = ((dst) &\
20830 #define RADIO130NM_SYNTH4__FORCE_SHIFTREG__SET(dst) \
20831 (dst) = ((dst) &\
20833 #define RADIO130NM_SYNTH4__FORCE_SHIFTREG__CLR(dst) \
20834 (dst) = ((dst) &\
20847 #define RADIO130NM_SYNTH4__LONGSHIFTSEL__MODIFY(dst, src) \
20848 (dst) = ((dst) &\
20854 #define RADIO130NM_SYNTH4__LONGSHIFTSEL__SET(dst) \
20855 (dst) = ((dst) &\
20857 #define RADIO130NM_SYNTH4__LONGSHIFTSEL__CLR(dst) \
20858 (dst) = ((dst) &\
20871 #define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__MODIFY(dst, src) \
20872 (dst) = ((dst) &\
20889 #define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__MODIFY(dst, src) \
20890 (dst) = ((dst) &\
20896 #define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__SET(dst) \
20897 (dst) = ((dst) &\
20899 #define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__CLR(dst) \
20900 (dst) = ((dst) &\
20913 #define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__MODIFY(dst, src) \
20914 (dst) = ((dst) &\
20920 #define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__SET(dst) \
20921 (dst) = ((dst) &\
20923 #define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__CLR(dst) \
20924 (dst) = ((dst) &\
20937 #define RADIO130NM_SYNTH4__SDM_DITHER__MODIFY(dst, src) \
20938 (dst) = ((dst) &\
20955 #define RADIO130NM_SYNTH4__SDM_MODE__MODIFY(dst, src) \
20956 (dst) = ((dst) &\
20962 #define RADIO130NM_SYNTH4__SDM_MODE__SET(dst) \
20963 (dst) = ((dst) &\
20965 #define RADIO130NM_SYNTH4__SDM_MODE__CLR(dst) \
20966 (dst) = ((dst) &\
20979 #define RADIO130NM_SYNTH4__SDM_DISABLE__MODIFY(dst, src) \
20980 (dst) = ((dst) &\
20986 #define RADIO130NM_SYNTH4__SDM_DISABLE__SET(dst) \
20987 (dst) = ((dst) &\
20989 #define RADIO130NM_SYNTH4__SDM_DISABLE__CLR(dst) \
20990 (dst) = ((dst) &\
21003 #define RADIO130NM_SYNTH4__RESET_PRESC__MODIFY(dst, src) \
21004 (dst) = ((dst) &\
21010 #define RADIO130NM_SYNTH4__RESET_PRESC__SET(dst) \
21011 (dst) = ((dst) &\
21013 #define RADIO130NM_SYNTH4__RESET_PRESC__CLR(dst) \
21014 (dst) = ((dst) &\
21027 #define RADIO130NM_SYNTH4__PRESCSEL__MODIFY(dst, src) \
21028 (dst) = ((dst) &\
21045 #define RADIO130NM_SYNTH4__PFD_DISABLE__MODIFY(dst, src) \
21046 (dst) = ((dst) &\
21052 #define RADIO130NM_SYNTH4__PFD_DISABLE__SET(dst) \
21053 (dst) = ((dst) &\
21055 #define RADIO130NM_SYNTH4__PFD_DISABLE__CLR(dst) \
21056 (dst) = ((dst) &\
21069 #define RADIO130NM_SYNTH4__PFDDELAY_FRACN__MODIFY(dst, src) \
21070 (dst) = ((dst) &\
21076 #define RADIO130NM_SYNTH4__PFDDELAY_FRACN__SET(dst) \
21077 (dst) = ((dst) &\
21079 #define RADIO130NM_SYNTH4__PFDDELAY_FRACN__CLR(dst) \
21080 (dst) = ((dst) &\
21093 #define RADIO130NM_SYNTH4__FORCE_LO_ON__MODIFY(dst, src) \
21094 (dst) = ((dst) &\
21100 #define RADIO130NM_SYNTH4__FORCE_LO_ON__SET(dst) \
21101 (dst) = ((dst) &\
21103 #define RADIO130NM_SYNTH4__FORCE_LO_ON__CLR(dst) \
21104 (dst) = ((dst) &\
21117 #define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__MODIFY(dst, src) \
21118 (dst) = ((dst) &\
21124 #define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__SET(dst) \
21125 (dst) = ((dst) &\
21127 #define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__CLR(dst) \
21128 (dst) = ((dst) &\
21141 #define RADIO130NM_SYNTH4__VCOCAPPULLUP__MODIFY(dst, src) \
21142 (dst) = ((dst) &\
21148 #define RADIO130NM_SYNTH4__VCOCAPPULLUP__SET(dst) \
21149 (dst) = ((dst) &\
21151 #define RADIO130NM_SYNTH4__VCOCAPPULLUP__CLR(dst) \
21152 (dst) = ((dst) &\
21165 #define RADIO130NM_SYNTH4__VCOCAP_OVR__MODIFY(dst, src) \
21166 (dst) = ((dst) &\
21183 #define RADIO130NM_SYNTH4__FORCE_VCOCAP__MODIFY(dst, src) \
21184 (dst) = ((dst) &\
21190 #define RADIO130NM_SYNTH4__FORCE_VCOCAP__SET(dst) \
21191 (dst) = ((dst) &\
21193 #define RADIO130NM_SYNTH4__FORCE_VCOCAP__CLR(dst) \
21194 (dst) = ((dst) &\
21207 #define RADIO130NM_SYNTH4__FORCE_PINVC__MODIFY(dst, src) \
21208 (dst) = ((dst) &\
21214 #define RADIO130NM_SYNTH4__FORCE_PINVC__SET(dst) \
21215 (dst) = ((dst) &\
21217 #define RADIO130NM_SYNTH4__FORCE_PINVC__CLR(dst) \
21218 (dst) = ((dst) &\
21231 #define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__MODIFY(dst, src) \
21232 (dst) = ((dst) &\
21238 #define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__SET(dst) \
21239 (dst) = ((dst) &\
21241 #define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__CLR(dst) \
21242 (dst) = ((dst) &\
21255 #define RADIO130NM_SYNTH4__ALWAYS_SHORTR__MODIFY(dst, src) \
21256 (dst) = ((dst) &\
21262 #define RADIO130NM_SYNTH4__ALWAYS_SHORTR__SET(dst) \
21263 (dst) = ((dst) &\
21265 #define RADIO130NM_SYNTH4__ALWAYS_SHORTR__CLR(dst) \
21266 (dst) = ((dst) &\
21279 #define RADIO130NM_SYNTH4__DIS_LOSTVC__MODIFY(dst, src) \
21280 (dst) = ((dst) &\
21286 #define RADIO130NM_SYNTH4__DIS_LOSTVC__SET(dst) \
21287 (dst) = ((dst) &\
21289 #define RADIO130NM_SYNTH4__DIS_LOSTVC__CLR(dst) \
21290 (dst) = ((dst) &\
21303 #define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__MODIFY(dst, src) \
21304 (dst) = ((dst) &\
21310 #define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__SET(dst) \
21311 (dst) = ((dst) &\
21313 #define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__CLR(dst) \
21314 (dst) = ((dst) &\
21338 #define RADIO130NM_SYNTH5__ICPKCOMP__MODIFY(dst, src) \
21339 (dst) = ((dst) &\
21356 #define RADIO130NM_SYNTH5__ICLOBUF5G__MODIFY(dst, src) \
21357 (dst) = ((dst) &\
21374 #define RADIO130NM_SYNTH5__ICLOBUF2G__MODIFY(dst, src) \
21375 (dst) = ((dst) &\
21392 #define RADIO130NM_SYNTH5__ICVCO__MODIFY(dst, src) \
21393 (dst) = ((dst) &\
21410 #define RADIO130NM_SYNTH5__ICVCOREG__MODIFY(dst, src) \
21411 (dst) = ((dst) &\
21428 #define RADIO130NM_SYNTH5__ICLOMIX__MODIFY(dst, src) \
21429 (dst) = ((dst) &\
21446 #define RADIO130NM_SYNTH5__ICLODIV__MODIFY(dst, src) \
21447 (dst) = ((dst) &\
21464 #define RADIO130NM_SYNTH5__ICPRESC__MODIFY(dst, src) \
21465 (dst) = ((dst) &\
21482 #define RADIO130NM_SYNTH5__IRLOPKDET__MODIFY(dst, src) \
21483 (dst) = ((dst) &\
21500 #define RADIO130NM_SYNTH5__IRVCMON__MODIFY(dst, src) \
21501 (dst) = ((dst) &\
21518 #define RADIO130NM_SYNTH5__IRCP__MODIFY(dst, src) \
21519 (dst) = ((dst) &\
21562 #define RADIO130NM_SYNTH6__VC2LOW__SET(dst) \
21563 (dst) = ((dst) &\
21565 #define RADIO130NM_SYNTH6__VC2LOW__CLR(dst) \
21566 (dst) = ((dst) &\
21576 #define RADIO130NM_SYNTH6__VC2HIGH__SET(dst) \
21577 (dst) = ((dst) &\
21579 #define RADIO130NM_SYNTH6__VC2HIGH__CLR(dst) \
21580 (dst) = ((dst) &\
21590 #define RADIO130NM_SYNTH6__RESET_SDM_B__SET(dst) \
21591 (dst) = ((dst) &\
21593 #define RADIO130NM_SYNTH6__RESET_SDM_B__CLR(dst) \
21594 (dst) = ((dst) &\
21604 #define RADIO130NM_SYNTH6__RESET_PSCOUNTERS__SET(dst) \
21605 (dst) = ((dst) &\
21607 #define RADIO130NM_SYNTH6__RESET_PSCOUNTERS__CLR(dst) \
21608 (dst) = ((dst) &\
21618 #define RADIO130NM_SYNTH6__RESET_PFD__SET(dst) \
21619 (dst) = ((dst) &\
21621 #define RADIO130NM_SYNTH6__RESET_PFD__CLR(dst) \
21622 (dst) = ((dst) &\
21632 #define RADIO130NM_SYNTH6__RESET_RFD__SET(dst) \
21633 (dst) = ((dst) &\
21635 #define RADIO130NM_SYNTH6__RESET_RFD__CLR(dst) \
21636 (dst) = ((dst) &\
21646 #define RADIO130NM_SYNTH6__SHORT_R__SET(dst) \
21647 (dst) = ((dst) &\
21649 #define RADIO130NM_SYNTH6__SHORT_R__CLR(dst) \
21650 (dst) = ((dst) &\
21668 #define RADIO130NM_SYNTH6__PIN_VC__SET(dst) \
21669 (dst) = ((dst) &\
21671 #define RADIO130NM_SYNTH6__PIN_VC__CLR(dst) \
21672 (dst) = ((dst) &\
21682 #define RADIO130NM_SYNTH6__SYNTH_LOCK_VC_OK__SET(dst) \
21683 (dst) = ((dst) &\
21685 #define RADIO130NM_SYNTH6__SYNTH_LOCK_VC_OK__CLR(dst) \
21686 (dst) = ((dst) &\
21696 #define RADIO130NM_SYNTH6__CAP_SEARCH__SET(dst) \
21697 (dst) = ((dst) &\
21699 #define RADIO130NM_SYNTH6__CAP_SEARCH__CLR(dst) \
21700 (dst) = ((dst) &\
21718 #define RADIO130NM_SYNTH6__SYNTH_ON__SET(dst) \
21719 (dst) = ((dst) &\
21721 #define RADIO130NM_SYNTH6__SYNTH_ON__CLR(dst) \
21722 (dst) = ((dst) &\
21747 #define RADIO130NM_SYNTH7__OVRCHANDECODER__MODIFY(dst, src) \
21748 (dst) = ((dst) &\
21754 #define RADIO130NM_SYNTH7__OVRCHANDECODER__SET(dst) \
21755 (dst) = ((dst) &\
21757 #define RADIO130NM_SYNTH7__OVRCHANDECODER__CLR(dst) \
21758 (dst) = ((dst) &\
21771 #define RADIO130NM_SYNTH7__FORCE_FRACLSB__MODIFY(dst, src) \
21772 (dst) = ((dst) &\
21778 #define RADIO130NM_SYNTH7__FORCE_FRACLSB__SET(dst) \
21779 (dst) = ((dst) &\
21781 #define RADIO130NM_SYNTH7__FORCE_FRACLSB__CLR(dst) \
21782 (dst) = ((dst) &\
21795 #define RADIO130NM_SYNTH7__CHANFRAC__MODIFY(dst, src) \
21796 (dst) = ((dst) &\
21813 #define RADIO130NM_SYNTH7__CHANSEL__MODIFY(dst, src) \
21814 (dst) = ((dst) &\
21831 #define RADIO130NM_SYNTH7__AMODEREFSEL__MODIFY(dst, src) \
21832 (dst) = ((dst) &\
21849 #define RADIO130NM_SYNTH7__FRACMODE__MODIFY(dst, src) \
21850 (dst) = ((dst) &\
21856 #define RADIO130NM_SYNTH7__FRACMODE__SET(dst) \
21857 (dst) = ((dst) &\
21859 #define RADIO130NM_SYNTH7__FRACMODE__CLR(dst) \
21860 (dst) = ((dst) &\
21873 #define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__MODIFY(dst, src) \
21874 (dst) = ((dst) &\
21880 #define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__SET(dst) \
21881 (dst) = ((dst) &\
21883 #define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__CLR(dst) \
21884 (dst) = ((dst) &\
21910 #define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__MODIFY(dst, src) \
21911 (dst) = ((dst) &\
21917 #define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__SET(dst) \
21918 (dst) = ((dst) &\
21920 #define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__CLR(dst) \
21921 (dst) = ((dst) &\
21934 #define RADIO130NM_SYNTH8__LOOP_ICPB__MODIFY(dst, src) \
21935 (dst) = ((dst) &\
21952 #define RADIO130NM_SYNTH8__LOOP_CSB__MODIFY(dst, src) \
21953 (dst) = ((dst) &\
21970 #define RADIO130NM_SYNTH8__LOOP_RSB__MODIFY(dst, src) \
21971 (dst) = ((dst) &\
21988 #define RADIO130NM_SYNTH8__LOOP_CPB__MODIFY(dst, src) \
21989 (dst) = ((dst) &\
22006 #define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__MODIFY(dst, src) \
22007 (dst) = ((dst) &\
22024 #define RADIO130NM_SYNTH8__REFDIVB__MODIFY(dst, src) \
22025 (dst) = ((dst) &\
22055 #define RADIO130NM_SYNTH9__PFDDELAY_INTN__MODIFY(dst, src) \
22056 (dst) = ((dst) &\
22062 #define RADIO130NM_SYNTH9__PFDDELAY_INTN__SET(dst) \
22063 (dst) = ((dst) &\
22065 #define RADIO130NM_SYNTH9__PFDDELAY_INTN__CLR(dst) \
22066 (dst) = ((dst) &\
22079 #define RADIO130NM_SYNTH9__SLOPE_ICPA0__MODIFY(dst, src) \
22080 (dst) = ((dst) &\
22097 #define RADIO130NM_SYNTH9__LOOP_ICPA0__MODIFY(dst, src) \
22098 (dst) = ((dst) &\
22115 #define RADIO130NM_SYNTH9__LOOP_CSA0__MODIFY(dst, src) \
22116 (dst) = ((dst) &\
22133 #define RADIO130NM_SYNTH9__LOOP_RSA0__MODIFY(dst, src) \
22134 (dst) = ((dst) &\
22151 #define RADIO130NM_SYNTH9__LOOP_CPA0__MODIFY(dst, src) \
22152 (dst) = ((dst) &\
22169 #define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__MODIFY(dst, src) \
22170 (dst) = ((dst) &\
22187 #define RADIO130NM_SYNTH9__REFDIVA__MODIFY(dst, src) \
22188 (dst) = ((dst) &\
22214 #define RADIO130NM_SYNTH10__SPARE__MODIFY(dst, src) \
22215 (dst) = ((dst) &\
22232 #define RADIO130NM_SYNTH10__SLOPE_ICPA1__MODIFY(dst, src) \
22233 (dst) = ((dst) &\
22250 #define RADIO130NM_SYNTH10__LOOP_ICPA1__MODIFY(dst, src) \
22251 (dst) = ((dst) &\
22268 #define RADIO130NM_SYNTH10__LOOP_CSA1__MODIFY(dst, src) \
22269 (dst) = ((dst) &\
22286 #define RADIO130NM_SYNTH10__LOOP_RSA1__MODIFY(dst, src) \
22287 (dst) = ((dst) &\
22304 #define RADIO130NM_SYNTH10__LOOP_CPA1__MODIFY(dst, src) \
22305 (dst) = ((dst) &\
22331 #define RADIO130NM_SYNTH11__SPARE__MODIFY(dst, src) \
22332 (dst) = ((dst) &\
22349 #define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__MODIFY(dst, src) \
22350 (dst) = ((dst) &\
22356 #define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__SET(dst) \
22357 (dst) = ((dst) &\
22359 #define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__CLR(dst) \
22360 (dst) = ((dst) &\
22373 #define RADIO130NM_SYNTH11__LOREFSEL__MODIFY(dst, src) \
22374 (dst) = ((dst) &\
22391 #define RADIO130NM_SYNTH11__LO2GSEL__MODIFY(dst, src) \
22392 (dst) = ((dst) &\
22409 #define RADIO130NM_SYNTH11__CPSTEERING_MODE__MODIFY(dst, src) \
22410 (dst) = ((dst) &\
22416 #define RADIO130NM_SYNTH11__CPSTEERING_MODE__SET(dst) \
22417 (dst) = ((dst) &\
22419 #define RADIO130NM_SYNTH11__CPSTEERING_MODE__CLR(dst) \
22420 (dst) = ((dst) &\
22433 #define RADIO130NM_SYNTH11__SLOPE_ICPA2__MODIFY(dst, src) \
22434 (dst) = ((dst) &\
22451 #define RADIO130NM_SYNTH11__LOOP_ICPA2__MODIFY(dst, src) \
22452 (dst) = ((dst) &\
22469 #define RADIO130NM_SYNTH11__LOOP_CSA2__MODIFY(dst, src) \
22470 (dst) = ((dst) &\
22487 #define RADIO130NM_SYNTH11__LOOP_RSA2__MODIFY(dst, src) \
22488 (dst) = ((dst) &\
22505 #define RADIO130NM_SYNTH11__LOOP_CPA2__MODIFY(dst, src) \
22506 (dst) = ((dst) &\
22536 #define RADIO130NM_BIAS1__PWD_IRPCIE50__MODIFY(dst, src) \
22537 (dst) = ((dst) &\
22543 #define RADIO130NM_BIAS1__PWD_IRPCIE50__SET(dst) \
22544 (dst) = ((dst) &\
22546 #define RADIO130NM_BIAS1__PWD_IRPCIE50__CLR(dst) \
22547 (dst) = ((dst) &\
22560 #define RADIO130NM_BIAS1__PWD_ICPCIE50__MODIFY(dst, src) \
22561 (dst) = ((dst) &\
22567 #define RADIO130NM_BIAS1__PWD_ICPCIE50__SET(dst) \
22568 (dst) = ((dst) &\
22570 #define RADIO130NM_BIAS1__PWD_ICPCIE50__CLR(dst) \
22571 (dst) = ((dst) &\
22584 #define RADIO130NM_BIAS1__PWD_IRPLL25__MODIFY(dst, src) \
22585 (dst) = ((dst) &\
22591 #define RADIO130NM_BIAS1__PWD_IRPLL25__SET(dst) \
22592 (dst) = ((dst) &\
22594 #define RADIO130NM_BIAS1__PWD_IRPLL25__CLR(dst) \
22595 (dst) = ((dst) &\
22608 #define RADIO130NM_BIAS1__PWD_ICPLL25__MODIFY(dst, src) \
22609 (dst) = ((dst) &\
22615 #define RADIO130NM_BIAS1__PWD_ICPLL25__SET(dst) \
22616 (dst) = ((dst) &\
22618 #define RADIO130NM_BIAS1__PWD_ICPLL25__CLR(dst) \
22619 (dst) = ((dst) &\
22632 #define RADIO130NM_BIAS1__PWD_IRRXLDO25__MODIFY(dst, src) \
22633 (dst) = ((dst) &\
22650 #define RADIO130NM_BIAS1__PWD_ICRXLDO25__MODIFY(dst, src) \
22651 (dst) = ((dst) &\
22668 #define RADIO130NM_BIAS1__PWD_IRXPALDO25__MODIFY(dst, src) \
22669 (dst) = ((dst) &\
22686 #define RADIO130NM_BIAS1__PWD_ICXPALDO25__MODIFY(dst, src) \
22687 (dst) = ((dst) &\
22704 #define RADIO130NM_BIAS1__PWD_IRXTAL25__MODIFY(dst, src) \
22705 (dst) = ((dst) &\
22722 #define RADIO130NM_BIAS1__PWD_ICXTAL25__MODIFY(dst, src) \
22723 (dst) = ((dst) &\
22740 #define RADIO130NM_BIAS1__BIAS1_SPARE__MODIFY(dst, src) \
22741 (dst) = ((dst) &\
22758 #define RADIO130NM_BIAS1__SEL_BIAS__MODIFY(dst, src) \
22759 (dst) = ((dst) &\
22776 #define RADIO130NM_BIAS1__PADON__MODIFY(dst, src) \
22777 (dst) = ((dst) &\
22783 #define RADIO130NM_BIAS1__PADON__SET(dst) \
22784 (dst) = ((dst) &\
22786 #define RADIO130NM_BIAS1__PADON__CLR(dst) \
22787 (dst) = ((dst) &\
22811 #define RADIO130NM_BIAS2__PWD_ICDAC50__MODIFY(dst, src) \
22812 (dst) = ((dst) &\
22829 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__MODIFY(dst, src) \
22830 (dst) = ((dst) &\
22836 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__SET(dst) \
22837 (dst) = ((dst) &\
22839 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__CLR(dst) \
22840 (dst) = ((dst) &\
22853 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__MODIFY(dst, src) \
22854 (dst) = ((dst) &\
22860 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__SET(dst) \
22861 (dst) = ((dst) &\
22863 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__CLR(dst) \
22864 (dst) = ((dst) &\
22877 #define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__MODIFY(dst, src) \
22878 (dst) = ((dst) &\
22895 #define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__MODIFY(dst, src) \
22896 (dst) = ((dst) &\
22913 #define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__MODIFY(dst, src) \
22914 (dst) = ((dst) &\
22931 #define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__MODIFY(dst, src) \
22932 (dst) = ((dst) &\
22949 #define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__MODIFY(dst, src) \
22950 (dst) = ((dst) &\
22967 #define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__MODIFY(dst, src) \
22968 (dst) = ((dst) &\
22985 #define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__MODIFY(dst, src) \
22986 (dst) = ((dst) &\
22992 #define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__SET(dst) \
22993 (dst) = ((dst) &\
22995 #define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__CLR(dst) \
22996 (dst) = ((dst) &\
23009 #define RADIO130NM_BIAS2__PWD_IRBB50__MODIFY(dst, src) \
23010 (dst) = ((dst) &\
23016 #define RADIO130NM_BIAS2__PWD_IRBB50__SET(dst) \
23017 (dst) = ((dst) &\
23019 #define RADIO130NM_BIAS2__PWD_IRBB50__CLR(dst) \
23020 (dst) = ((dst) &\
23033 #define RADIO130NM_BIAS2__PWD_ICBB50__MODIFY(dst, src) \
23034 (dst) = ((dst) &\
23040 #define RADIO130NM_BIAS2__PWD_ICBB50__SET(dst) \
23041 (dst) = ((dst) &\
23043 #define RADIO130NM_BIAS2__PWD_ICBB50__CLR(dst) \
23044 (dst) = ((dst) &\
23057 #define RADIO130NM_BIAS2__PWD_IRRF2G50__MODIFY(dst, src) \
23058 (dst) = ((dst) &\
23064 #define RADIO130NM_BIAS2__PWD_IRRF2G50__SET(dst) \
23065 (dst) = ((dst) &\
23067 #define RADIO130NM_BIAS2__PWD_IRRF2G50__CLR(dst) \
23068 (dst) = ((dst) &\
23081 #define RADIO130NM_BIAS2__PWD_IRRF5G50__MODIFY(dst, src) \
23082 (dst) = ((dst) &\
23088 #define RADIO130NM_BIAS2__PWD_IRRF5G50__SET(dst) \
23089 (dst) = ((dst) &\
23091 #define RADIO130NM_BIAS2__PWD_IRRF5G50__CLR(dst) \
23092 (dst) = ((dst) &\
23105 #define RADIO130NM_BIAS2__PWD_ICRF2G50__MODIFY(dst, src) \
23106 (dst) = ((dst) &\
23112 #define RADIO130NM_BIAS2__PWD_ICRF2G50__SET(dst) \
23113 (dst) = ((dst) &\
23115 #define RADIO130NM_BIAS2__PWD_ICRF2G50__CLR(dst) \
23116 (dst) = ((dst) &\
23129 #define RADIO130NM_BIAS2__PWD_ICRF5G50__MODIFY(dst, src) \
23130 (dst) = ((dst) &\
23136 #define RADIO130NM_BIAS2__PWD_ICRF5G50__SET(dst) \
23137 (dst) = ((dst) &\
23139 #define RADIO130NM_BIAS2__PWD_ICRF5G50__CLR(dst) \
23140 (dst) = ((dst) &\
23153 #define RADIO130NM_BIAS2__PWD_IRSYNTH50__MODIFY(dst, src) \
23154 (dst) = ((dst) &\
23160 #define RADIO130NM_BIAS2__PWD_IRSYNTH50__SET(dst) \
23161 (dst) = ((dst) &\
23163 #define RADIO130NM_BIAS2__PWD_IRSYNTH50__CLR(dst) \
23164 (dst) = ((dst) &\
23177 #define RADIO130NM_BIAS2__PWD_ICSYNTH50__MODIFY(dst, src) \
23178 (dst) = ((dst) &\
23184 #define RADIO130NM_BIAS2__PWD_ICSYNTH50__SET(dst) \
23185 (dst) = ((dst) &\
23187 #define RADIO130NM_BIAS2__PWD_ICSYNTH50__CLR(dst) \
23188 (dst) = ((dst) &\
23212 #define RADIO130NM_BIAS3__BIAS3_SPARE__MODIFY(dst, src) \
23213 (dst) = ((dst) &\
23219 #define RADIO130NM_BIAS3__BIAS3_SPARE__SET(dst) \
23220 (dst) = ((dst) &\
23222 #define RADIO130NM_BIAS3__BIAS3_SPARE__CLR(dst) \
23223 (dst) = ((dst) &\
23236 #define RADIO130NM_BIAS3__PWD_ICLOLDO25__MODIFY(dst, src) \
23237 (dst) = ((dst) &\
23254 #define RADIO130NM_BIAS3__PWD_IR25SPARE4__MODIFY(dst, src) \
23255 (dst) = ((dst) &\
23272 #define RADIO130NM_BIAS3__PWD_IR25SPARE3__MODIFY(dst, src) \
23273 (dst) = ((dst) &\
23290 #define RADIO130NM_BIAS3__PWD_IR25SPARE2__MODIFY(dst, src) \
23291 (dst) = ((dst) &\
23308 #define RADIO130NM_BIAS3__PWD_IR25SPARE1__MODIFY(dst, src) \
23309 (dst) = ((dst) &\
23326 #define RADIO130NM_BIAS3__PWD_IC25SPARE4__MODIFY(dst, src) \
23327 (dst) = ((dst) &\
23344 #define RADIO130NM_BIAS3__PWD_IC25SPARE3__MODIFY(dst, src) \
23345 (dst) = ((dst) &\
23362 #define RADIO130NM_BIAS3__PWD_IC25SPARE2__MODIFY(dst, src) \
23363 (dst) = ((dst) &\
23380 #define RADIO130NM_BIAS3__PWD_IC25SPARE1__MODIFY(dst, src) \
23381 (dst) = ((dst) &\
23398 #define RADIO130NM_BIAS3__PWD_IRTSENS25__MODIFY(dst, src) \
23399 (dst) = ((dst) &\
23405 #define RADIO130NM_BIAS3__PWD_IRTSENS25__SET(dst) \
23406 (dst) = ((dst) &\
23408 #define RADIO130NM_BIAS3__PWD_IRTSENS25__CLR(dst) \
23409 (dst) = ((dst) &\
23422 #define RADIO130NM_BIAS3__PWD_ICTSENS25__MODIFY(dst, src) \
23423 (dst) = ((dst) &\
23429 #define RADIO130NM_BIAS3__PWD_ICTSENS25__SET(dst) \
23430 (dst) = ((dst) &\
23432 #define RADIO130NM_BIAS3__PWD_ICTSENS25__CLR(dst) \
23433 (dst) = ((dst) &\
23446 #define RADIO130NM_BIAS3__PWD_IRTXPC25__MODIFY(dst, src) \
23447 (dst) = ((dst) &\
23453 #define RADIO130NM_BIAS3__PWD_IRTXPC25__SET(dst) \
23454 (dst) = ((dst) &\
23456 #define RADIO130NM_BIAS3__PWD_IRTXPC25__CLR(dst) \
23457 (dst) = ((dst) &\
23470 #define RADIO130NM_BIAS3__PWD_ICTXPC25__MODIFY(dst, src) \
23471 (dst) = ((dst) &\
23477 #define RADIO130NM_BIAS3__PWD_ICTXPC25__SET(dst) \
23478 (dst) = ((dst) &\
23480 #define RADIO130NM_BIAS3__PWD_ICTXPC25__CLR(dst) \
23481 (dst) = ((dst) &\
23505 #define RADIO130NM_BIAS4__BIAS4_SPARE__MODIFY(dst, src) \
23506 (dst) = ((dst) &\
23523 #define RADIO130NM_BIAS4__PWD_IRLOLDO25__MODIFY(dst, src) \
23524 (dst) = ((dst) &\
23541 #define RADIO130NM_BIAS4__PWD_ICXLNA5G50__MODIFY(dst, src) \
23542 (dst) = ((dst) &\
23559 #define RADIO130NM_BIAS4__PWD_ICXLNA2G50__MODIFY(dst, src) \
23560 (dst) = ((dst) &\
23577 #define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__MODIFY(dst, src) \
23578 (dst) = ((dst) &\
23604 #define RADIO130NM_GAIN0__SPARE__MODIFY(dst, src) \
23605 (dst) = ((dst) &\
23611 #define RADIO130NM_GAIN0__SPARE__SET(dst) \
23612 (dst) = ((dst) &\
23614 #define RADIO130NM_GAIN0__SPARE__CLR(dst) \
23615 (dst) = ((dst) &\
23628 #define RADIO130NM_GAIN0__RX6DBHIQGAIN__MODIFY(dst, src) \
23629 (dst) = ((dst) &\
23646 #define RADIO130NM_GAIN0__RX1DBLOQGAIN__MODIFY(dst, src) \
23647 (dst) = ((dst) &\
23664 #define RADIO130NM_GAIN0__RX6DBLOQGAIN__MODIFY(dst, src) \
23665 (dst) = ((dst) &\
23682 #define RADIO130NM_GAIN0__RFGMGN__MODIFY(dst, src) \
23683 (dst) = ((dst) &\
23700 #define RADIO130NM_GAIN0__RFVGA5GAIN__MODIFY(dst, src) \
23701 (dst) = ((dst) &\
23718 #define RADIO130NM_GAIN0__LNAGAIN__MODIFY(dst, src) \
23719 (dst) = ((dst) &\
23736 #define RADIO130NM_GAIN0__LNAON__MODIFY(dst, src) \
23737 (dst) = ((dst) &\
23743 #define RADIO130NM_GAIN0__LNAON__SET(dst) \
23744 (dst) = ((dst) &\
23746 #define RADIO130NM_GAIN0__LNAON__CLR(dst) \
23747 (dst) = ((dst) &\
23760 #define RADIO130NM_GAIN0__PAOUT2GN__MODIFY(dst, src) \
23761 (dst) = ((dst) &\
23778 #define RADIO130NM_GAIN0__PADRVGN__MODIFY(dst, src) \
23779 (dst) = ((dst) &\
23796 #define RADIO130NM_GAIN0__PABUF5GN__MODIFY(dst, src) \
23797 (dst) = ((dst) &\
23803 #define RADIO130NM_GAIN0__PABUF5GN__SET(dst) \
23804 (dst) = ((dst) &\
23806 #define RADIO130NM_GAIN0__PABUF5GN__CLR(dst) \
23807 (dst) = ((dst) &\
23820 #define RADIO130NM_GAIN0__TXV2IGAIN__MODIFY(dst, src) \
23821 (dst) = ((dst) &\
23838 #define RADIO130NM_GAIN0__TX1DBLOQGAIN__MODIFY(dst, src) \
23839 (dst) = ((dst) &\
23856 #define RADIO130NM_GAIN0__TX6DBLOQGAIN__MODIFY(dst, src) \
23857 (dst) = ((dst) &\
23883 #define RADIO130NM_GAIN1__SPARE__MODIFY(dst, src) \
23884 (dst) = ((dst) &\
23890 #define RADIO130NM_GAIN1__SPARE__SET(dst) \
23891 (dst) = ((dst) &\
23893 #define RADIO130NM_GAIN1__SPARE__CLR(dst) \
23894 (dst) = ((dst) &\
23907 #define RADIO130NM_GAIN1__RX6DBHIQGAIN__MODIFY(dst, src) \
23908 (dst) = ((dst) &\
23925 #define RADIO130NM_GAIN1__RX1DBLOQGAIN__MODIFY(dst, src) \
23926 (dst) = ((dst) &\
23943 #define RADIO130NM_GAIN1__RX6DBLOQGAIN__MODIFY(dst, src) \
23944 (dst) = ((dst) &\
23961 #define RADIO130NM_GAIN1__RFGMGN__MODIFY(dst, src) \
23962 (dst) = ((dst) &\
23979 #define RADIO130NM_GAIN1__RFVGA5GAIN__MODIFY(dst, src) \
23980 (dst) = ((dst) &\
23997 #define RADIO130NM_GAIN1__LNAGAIN__MODIFY(dst, src) \
23998 (dst) = ((dst) &\
24015 #define RADIO130NM_GAIN1__LNAON__MODIFY(dst, src) \
24016 (dst) = ((dst) &\
24022 #define RADIO130NM_GAIN1__LNAON__SET(dst) \
24023 (dst) = ((dst) &\
24025 #define RADIO130NM_GAIN1__LNAON__CLR(dst) \
24026 (dst) = ((dst) &\
24039 #define RADIO130NM_GAIN1__PAOUT2GN__MODIFY(dst, src) \
24040 (dst) = ((dst) &\
24057 #define RADIO130NM_GAIN1__PADRVGN__MODIFY(dst, src) \
24058 (dst) = ((dst) &\
24075 #define RADIO130NM_GAIN1__PABUF5GN__MODIFY(dst, src) \
24076 (dst) = ((dst) &\
24082 #define RADIO130NM_GAIN1__PABUF5GN__SET(dst) \
24083 (dst) = ((dst) &\
24085 #define RADIO130NM_GAIN1__PABUF5GN__CLR(dst) \
24086 (dst) = ((dst) &\
24099 #define RADIO130NM_GAIN1__TXV2IGAIN__MODIFY(dst, src) \
24100 (dst) = ((dst) &\
24117 #define RADIO130NM_GAIN1__TX1DBLOQGAIN__MODIFY(dst, src) \
24118 (dst) = ((dst) &\
24135 #define RADIO130NM_GAIN1__TX6DBLOQGAIN__MODIFY(dst, src) \
24136 (dst) = ((dst) &\
24164 #define RADIO130NM_TOP0__FORCEMSBLOW__MODIFY(dst, src) \
24165 (dst) = ((dst) &\
24171 #define RADIO130NM_TOP0__FORCEMSBLOW__SET(dst) \
24172 (dst) = ((dst) &\
24174 #define RADIO130NM_TOP0__FORCEMSBLOW__CLR(dst) \
24175 (dst) = ((dst) &\
24188 #define RADIO130NM_TOP0__PWDBIAS__MODIFY(dst, src) \
24189 (dst) = ((dst) &\
24195 #define RADIO130NM_TOP0__PWDBIAS__SET(dst) \
24196 (dst) = ((dst) &\
24198 #define RADIO130NM_TOP0__PWDBIAS__CLR(dst) \
24199 (dst) = ((dst) &\
24212 #define RADIO130NM_TOP0__SYNTHON_FORCE__MODIFY(dst, src) \
24213 (dst) = ((dst) &\
24219 #define RADIO130NM_TOP0__SYNTHON_FORCE__SET(dst) \
24220 (dst) = ((dst) &\
24222 #define RADIO130NM_TOP0__SYNTHON_FORCE__CLR(dst) \
24223 (dst) = ((dst) &\
24236 #define RADIO130NM_TOP0__SCLKEN_FORCE__MODIFY(dst, src) \
24237 (dst) = ((dst) &\
24243 #define RADIO130NM_TOP0__SCLKEN_FORCE__SET(dst) \
24244 (dst) = ((dst) &\
24246 #define RADIO130NM_TOP0__SCLKEN_FORCE__CLR(dst) \
24247 (dst) = ((dst) &\
24260 #define RADIO130NM_TOP0__OSCON__MODIFY(dst, src) \
24261 (dst) = ((dst) &\
24267 #define RADIO130NM_TOP0__OSCON__SET(dst) \
24268 (dst) = ((dst) &\
24270 #define RADIO130NM_TOP0__OSCON__CLR(dst) \
24271 (dst) = ((dst) &\
24284 #define RADIO130NM_TOP0__PWDCLKIN__MODIFY(dst, src) \
24285 (dst) = ((dst) &\
24291 #define RADIO130NM_TOP0__PWDCLKIN__SET(dst) \
24292 (dst) = ((dst) &\
24294 #define RADIO130NM_TOP0__PWDCLKIN__CLR(dst) \
24295 (dst) = ((dst) &\
24308 #define RADIO130NM_TOP0__LOCALXTAL__MODIFY(dst, src) \
24309 (dst) = ((dst) &\
24315 #define RADIO130NM_TOP0__LOCALXTAL__SET(dst) \
24316 (dst) = ((dst) &\
24318 #define RADIO130NM_TOP0__LOCALXTAL__CLR(dst) \
24319 (dst) = ((dst) &\
24332 #define RADIO130NM_TOP0__XPAON__MODIFY(dst, src) \
24333 (dst) = ((dst) &\
24339 #define RADIO130NM_TOP0__XPAON__SET(dst) \
24340 (dst) = ((dst) &\
24342 #define RADIO130NM_TOP0__XPAON__CLR(dst) \
24343 (dst) = ((dst) &\
24356 #define RADIO130NM_TOP0__XLNAON__MODIFY(dst, src) \
24357 (dst) = ((dst) &\
24374 #define RADIO130NM_TOP0__PAON__MODIFY(dst, src) \
24375 (dst) = ((dst) &\
24392 #define RADIO130NM_TOP0__TXON__MODIFY(dst, src) \
24393 (dst) = ((dst) &\
24410 #define RADIO130NM_TOP0__RXON__MODIFY(dst, src) \
24411 (dst) = ((dst) &\
24428 #define RADIO130NM_TOP0__SYNTHON__MODIFY(dst, src) \
24429 (dst) = ((dst) &\
24435 #define RADIO130NM_TOP0__SYNTHON__SET(dst) \
24436 (dst) = ((dst) &\
24438 #define RADIO130NM_TOP0__SYNTHON__CLR(dst) \
24439 (dst) = ((dst) &\
24452 #define RADIO130NM_TOP0__TURBOMODE__MODIFY(dst, src) \
24453 (dst) = ((dst) &\
24459 #define RADIO130NM_TOP0__TURBOMODE__SET(dst) \
24460 (dst) = ((dst) &\
24462 #define RADIO130NM_TOP0__TURBOMODE__CLR(dst) \
24463 (dst) = ((dst) &\
24476 #define RADIO130NM_TOP0__BMODERXTX__MODIFY(dst, src) \
24477 (dst) = ((dst) &\
24494 #define RADIO130NM_TOP0__BMODE__MODIFY(dst, src) \
24495 (dst) = ((dst) &\
24501 #define RADIO130NM_TOP0__BMODE__SET(dst) \
24502 (dst) = ((dst) &\
24504 #define RADIO130NM_TOP0__BMODE__CLR(dst) \
24505 (dst) = ((dst) &\
24518 #define RADIO130NM_TOP0__CALTX__MODIFY(dst, src) \
24519 (dst) = ((dst) &\
24536 #define RADIO130NM_TOP0__CAL_RESIDUE__MODIFY(dst, src) \
24537 (dst) = ((dst) &\
24554 #define RADIO130NM_TOP0__CALDC__MODIFY(dst, src) \
24555 (dst) = ((dst) &\
24572 #define RADIO130NM_TOP0__CALFC__MODIFY(dst, src) \
24573 (dst) = ((dst) &\
24590 #define RADIO130NM_TOP0__LOCALMODE__MODIFY(dst, src) \
24591 (dst) = ((dst) &\
24597 #define RADIO130NM_TOP0__LOCALMODE__SET(dst) \
24598 (dst) = ((dst) &\
24600 #define RADIO130NM_TOP0__LOCALMODE__CLR(dst) \
24601 (dst) = ((dst) &\
24614 #define RADIO130NM_TOP0__LOCALRXGAIN__MODIFY(dst, src) \
24615 (dst) = ((dst) &\
24621 #define RADIO130NM_TOP0__LOCALRXGAIN__SET(dst) \
24622 (dst) = ((dst) &\
24624 #define RADIO130NM_TOP0__LOCALRXGAIN__CLR(dst) \
24625 (dst) = ((dst) &\
24638 #define RADIO130NM_TOP0__LOCALTXGAIN__MODIFY(dst, src) \
24639 (dst) = ((dst) &\
24645 #define RADIO130NM_TOP0__LOCALTXGAIN__SET(dst) \
24646 (dst) = ((dst) &\
24648 #define RADIO130NM_TOP0__LOCALTXGAIN__CLR(dst) \
24649 (dst) = ((dst) &\
24671 #define RADIO130NM_TOP1__PLL_SVREG__MODIFY(dst, src) \
24672 (dst) = ((dst) &\
24678 #define RADIO130NM_TOP1__PLL_SVREG__SET(dst) \
24679 (dst) = ((dst) &\
24681 #define RADIO130NM_TOP1__PLL_SVREG__CLR(dst) \
24682 (dst) = ((dst) &\
24695 #define RADIO130NM_TOP1__PLL_SCLAMP__MODIFY(dst, src) \
24696 (dst) = ((dst) &\
24713 #define RADIO130NM_TOP1__PLL_ICP__MODIFY(dst, src) \
24714 (dst) = ((dst) &\
24731 #define RADIO130NM_TOP1__PLL_FILTER__MODIFY(dst, src) \
24732 (dst) = ((dst) &\
24749 #define RADIO130NM_TOP1__PLL_ATB__MODIFY(dst, src) \
24750 (dst) = ((dst) &\
24767 #define RADIO130NM_TOP1__INV_CLK160_ADC__MODIFY(dst, src) \
24768 (dst) = ((dst) &\
24774 #define RADIO130NM_TOP1__INV_CLK160_ADC__SET(dst) \
24775 (dst) = ((dst) &\
24777 #define RADIO130NM_TOP1__INV_CLK160_ADC__CLR(dst) \
24778 (dst) = ((dst) &\
24791 #define RADIO130NM_TOP1__DACLPMODE__MODIFY(dst, src) \
24792 (dst) = ((dst) &\
24798 #define RADIO130NM_TOP1__DACLPMODE__SET(dst) \
24799 (dst) = ((dst) &\
24801 #define RADIO130NM_TOP1__DACLPMODE__CLR(dst) \
24802 (dst) = ((dst) &\
24815 #define RADIO130NM_TOP1__PWDDAC__MODIFY(dst, src) \
24816 (dst) = ((dst) &\
24833 #define RADIO130NM_TOP1__PWDADC__MODIFY(dst, src) \
24834 (dst) = ((dst) &\
24851 #define RADIO130NM_TOP1__PWDPLL__MODIFY(dst, src) \
24852 (dst) = ((dst) &\
24858 #define RADIO130NM_TOP1__PWDPLL__SET(dst) \
24859 (dst) = ((dst) &\
24861 #define RADIO130NM_TOP1__PWDPLL__CLR(dst) \
24862 (dst) = ((dst) &\
24875 #define RADIO130NM_TOP1__LOCALADDAC__MODIFY(dst, src) \
24876 (dst) = ((dst) &\
24882 #define RADIO130NM_TOP1__LOCALADDAC__SET(dst) \
24883 (dst) = ((dst) &\
24885 #define RADIO130NM_TOP1__LOCALADDAC__CLR(dst) \
24886 (dst) = ((dst) &\
24899 #define RADIO130NM_TOP1__INT2GND__MODIFY(dst, src) \
24900 (dst) = ((dst) &\
24906 #define RADIO130NM_TOP1__INT2GND__SET(dst) \
24907 (dst) = ((dst) &\
24909 #define RADIO130NM_TOP1__INT2GND__CLR(dst) \
24910 (dst) = ((dst) &\
24923 #define RADIO130NM_TOP1__PAD2GND__MODIFY(dst, src) \
24924 (dst) = ((dst) &\
24930 #define RADIO130NM_TOP1__PAD2GND__SET(dst) \
24931 (dst) = ((dst) &\
24933 #define RADIO130NM_TOP1__PAD2GND__CLR(dst) \
24934 (dst) = ((dst) &\
24947 #define RADIO130NM_TOP1__INTH2PAD__MODIFY(dst, src) \
24948 (dst) = ((dst) &\
24954 #define RADIO130NM_TOP1__INTH2PAD__SET(dst) \
24955 (dst) = ((dst) &\
24957 #define RADIO130NM_TOP1__INTH2PAD__CLR(dst) \
24958 (dst) = ((dst) &\
24971 #define RADIO130NM_TOP1__INT2PAD__MODIFY(dst, src) \
24972 (dst) = ((dst) &\
24978 #define RADIO130NM_TOP1__INT2PAD__SET(dst) \
24979 (dst) = ((dst) &\
24981 #define RADIO130NM_TOP1__INT2PAD__CLR(dst) \
24982 (dst) = ((dst) &\
25014 #define RADIO130NM_TOP2__BYPASSVREGLO__MODIFY(dst, src) \
25015 (dst) = ((dst) &\
25021 #define RADIO130NM_TOP2__BYPASSVREGLO__SET(dst) \
25022 (dst) = ((dst) &\
25024 #define RADIO130NM_TOP2__BYPASSVREGLO__CLR(dst) \
25025 (dst) = ((dst) &\
25038 #define RADIO130NM_TOP2__DATAOUTSEL__MODIFY(dst, src) \
25039 (dst) = ((dst) &\
25056 #define RADIO130NM_TOP2__TXPC_CLKDELAY__MODIFY(dst, src) \
25057 (dst) = ((dst) &\
25063 #define RADIO130NM_TOP2__TXPC_CLKDELAY__SET(dst) \
25064 (dst) = ((dst) &\
25066 #define RADIO130NM_TOP2__TXPC_CLKDELAY__CLR(dst) \
25067 (dst) = ((dst) &\
25080 #define RADIO130NM_TOP2__TXPC_XPDBS__MODIFY(dst, src) \
25081 (dst) = ((dst) &\
25098 #define RADIO130NM_TOP2__TXPC_TESTPWD__MODIFY(dst, src) \
25099 (dst) = ((dst) &\
25105 #define RADIO130NM_TOP2__TXPC_TESTPWD__SET(dst) \
25106 (dst) = ((dst) &\
25108 #define RADIO130NM_TOP2__TXPC_TESTPWD__CLR(dst) \
25109 (dst) = ((dst) &\
25122 #define RADIO130NM_TOP2__TXPC_TESTGAIN__MODIFY(dst, src) \
25123 (dst) = ((dst) &\
25140 #define RADIO130NM_TOP2__TXPC_TESTDAC__MODIFY(dst, src) \
25141 (dst) = ((dst) &\
25158 #define RADIO130NM_TOP2__TXPC_TEST__MODIFY(dst, src) \
25159 (dst) = ((dst) &\
25165 #define RADIO130NM_TOP2__TXPC_TEST__SET(dst) \
25166 (dst) = ((dst) &\
25168 #define RADIO130NM_TOP2__TXPC_TEST__CLR(dst) \
25169 (dst) = ((dst) &\
25182 #define RADIO130NM_TOP2__TXPC_NEGOUT__MODIFY(dst, src) \
25183 (dst) = ((dst) &\
25189 #define RADIO130NM_TOP2__TXPC_NEGOUT__SET(dst) \
25190 (dst) = ((dst) &\
25192 #define RADIO130NM_TOP2__TXPC_NEGOUT__CLR(dst) \
25193 (dst) = ((dst) &\
25206 #define RADIO130NM_TOP2__XTALDIV__MODIFY(dst, src) \
25207 (dst) = ((dst) &\
25224 #define RADIO130NM_TOP2__LOCALBIAS2X__MODIFY(dst, src) \
25225 (dst) = ((dst) &\
25231 #define RADIO130NM_TOP2__LOCALBIAS2X__SET(dst) \
25232 (dst) = ((dst) &\
25234 #define RADIO130NM_TOP2__LOCALBIAS2X__CLR(dst) \
25235 (dst) = ((dst) &\
25248 #define RADIO130NM_TOP2__LOCALBIAS__MODIFY(dst, src) \
25249 (dst) = ((dst) &\
25255 #define RADIO130NM_TOP2__LOCALBIAS__SET(dst) \
25256 (dst) = ((dst) &\
25258 #define RADIO130NM_TOP2__LOCALBIAS__CLR(dst) \
25259 (dst) = ((dst) &\
25272 #define RADIO130NM_TOP2__PWDCLKIND__MODIFY(dst, src) \
25273 (dst) = ((dst) &\
25279 #define RADIO130NM_TOP2__PWDCLKIND__SET(dst) \
25280 (dst) = ((dst) &\
25282 #define RADIO130NM_TOP2__PWDCLKIND__CLR(dst) \
25283 (dst) = ((dst) &\
25296 #define RADIO130NM_TOP2__PWDXINPAD__MODIFY(dst, src) \
25297 (dst) = ((dst) &\
25303 #define RADIO130NM_TOP2__PWDXINPAD__SET(dst) \
25304 (dst) = ((dst) &\
25306 #define RADIO130NM_TOP2__PWDXINPAD__CLR(dst) \
25307 (dst) = ((dst) &\
25320 #define RADIO130NM_TOP2__NOTCXODET__MODIFY(dst, src) \
25321 (dst) = ((dst) &\
25327 #define RADIO130NM_TOP2__NOTCXODET__SET(dst) \
25328 (dst) = ((dst) &\
25330 #define RADIO130NM_TOP2__NOTCXODET__CLR(dst) \
25331 (dst) = ((dst) &\
25344 #define RADIO130NM_TOP2__XLNABUFIN__MODIFY(dst, src) \
25345 (dst) = ((dst) &\
25351 #define RADIO130NM_TOP2__XLNABUFIN__SET(dst) \
25352 (dst) = ((dst) &\
25354 #define RADIO130NM_TOP2__XLNABUFIN__CLR(dst) \
25355 (dst) = ((dst) &\
25368 #define RADIO130NM_TOP2__XLNAISEL__MODIFY(dst, src) \
25369 (dst) = ((dst) &\
25386 #define RADIO130NM_TOP2__XLNABUFMODE__MODIFY(dst, src) \
25387 (dst) = ((dst) &\
25393 #define RADIO130NM_TOP2__XLNABUFMODE__SET(dst) \
25394 (dst) = ((dst) &\
25396 #define RADIO130NM_TOP2__XLNABUFMODE__CLR(dst) \
25397 (dst) = ((dst) &\
25410 #define RADIO130NM_TOP2__FORCE_XLDO_ON__MODIFY(dst, src) \
25411 (dst) = ((dst) &\
25417 #define RADIO130NM_TOP2__FORCE_XLDO_ON__SET(dst) \
25418 (dst) = ((dst) &\
25420 #define RADIO130NM_TOP2__FORCE_XLDO_ON__CLR(dst) \
25421 (dst) = ((dst) &\
25434 #define RADIO130NM_TOP2__XPABIAS_LVL__MODIFY(dst, src) \
25435 (dst) = ((dst) &\
25465 #define RADIO130NM_TOP3__VREGLO_ATBSEL__MODIFY(dst, src) \
25466 (dst) = ((dst) &\
25483 #define RADIO130NM_TOP3__PLLFBDIVB__MODIFY(dst, src) \
25484 (dst) = ((dst) &\
25501 #define RADIO130NM_TOP3__PLLFBDIVA__MODIFY(dst, src) \
25502 (dst) = ((dst) &\
25519 #define RADIO130NM_TOP3__PLLREFDIVB__MODIFY(dst, src) \
25520 (dst) = ((dst) &\
25537 #define RADIO130NM_TOP3__PLLREFDIVA__MODIFY(dst, src) \
25538 (dst) = ((dst) &\
25555 #define RADIO130NM_TOP3__LOCALPLLDIV__MODIFY(dst, src) \
25556 (dst) = ((dst) &\
25562 #define RADIO130NM_TOP3__LOCALPLLDIV__SET(dst) \
25563 (dst) = ((dst) &\
25565 #define RADIO130NM_TOP3__LOCALPLLDIV__CLR(dst) \
25566 (dst) = ((dst) &\
25592 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__MODIFY(dst, src) \
25593 (dst) = ((dst) &\
25599 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__SET(dst) \
25600 (dst) = ((dst) &\
25602 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__CLR(dst) \
25603 (dst) = ((dst) &\
25616 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__MODIFY(dst, src) \
25617 (dst) = ((dst) &\
25623 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__SET(dst) \
25624 (dst) = ((dst) &\
25626 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__CLR(dst) \
25627 (dst) = ((dst) &\
25650 #define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__SET(dst) \
25651 (dst) = ((dst) &\
25653 #define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__CLR(dst) \
25654 (dst) = ((dst) &\
25679 #define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__MODIFY(dst, src) \
25680 (dst) = ((dst) &\
25686 #define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__SET(dst) \
25687 (dst) = ((dst) &\
25689 #define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__CLR(dst) \
25690 (dst) = ((dst) &\
25716 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__MODIFY(dst, src) \
25717 (dst) = ((dst) &\
25723 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__SET(dst) \
25724 (dst) = ((dst) &\
25726 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__CLR(dst) \
25727 (dst) = ((dst) &\
25740 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__MODIFY(dst, src) \
25741 (dst) = ((dst) &\
25747 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__SET(dst) \
25748 (dst) = ((dst) &\
25750 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__CLR(dst) \
25751 (dst) = ((dst) &\
25764 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__MODIFY(dst, src) \
25765 (dst) = ((dst) &\
25771 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__SET(dst) \
25772 (dst) = ((dst) &\
25774 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__CLR(dst) \
25775 (dst) = ((dst) &\
25801 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MODIFY(dst, src) \
25802 (dst) = ((dst) &\
25832 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MODIFY(dst, src) \
25833 (dst) = ((dst) &\
25850 #define MAC_PCU_STA_ADDR_U16__STA_AP__MODIFY(dst, src) \
25851 (dst) = ((dst) &\
25857 #define MAC_PCU_STA_ADDR_U16__STA_AP__SET(dst) \
25858 (dst) = ((dst) &\
25860 #define MAC_PCU_STA_ADDR_U16__STA_AP__CLR(dst) \
25861 (dst) = ((dst) &\
25874 #define MAC_PCU_STA_ADDR_U16__ADHOC__MODIFY(dst, src) \
25875 (dst) = ((dst) &\
25881 #define MAC_PCU_STA_ADDR_U16__ADHOC__SET(dst) \
25882 (dst) = ((dst) &\
25884 #define MAC_PCU_STA_ADDR_U16__ADHOC__CLR(dst) \
25885 (dst) = ((dst) &\
25898 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__MODIFY(dst, src) \
25899 (dst) = ((dst) &\
25905 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__SET(dst) \
25906 (dst) = ((dst) &\
25908 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__CLR(dst) \
25909 (dst) = ((dst) &\
25922 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MODIFY(dst, src) \
25923 (dst) = ((dst) &\
25929 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__SET(dst) \
25930 (dst) = ((dst) &\
25932 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__CLR(dst) \
25933 (dst) = ((dst) &\
25946 #define MAC_PCU_STA_ADDR_U16__PCF__MODIFY(dst, src) \
25947 (dst) = ((dst) &\
25953 #define MAC_PCU_STA_ADDR_U16__PCF__SET(dst) \
25954 (dst) = ((dst) &\
25956 #define MAC_PCU_STA_ADDR_U16__PCF__CLR(dst) \
25957 (dst) = ((dst) &\
25970 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MODIFY(dst, src) \
25971 (dst) = ((dst) &\
25977 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__SET(dst) \
25978 (dst) = ((dst) &\
25980 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__CLR(dst) \
25981 (dst) = ((dst) &\
25994 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MODIFY(dst, src) \
25995 (dst) = ((dst) &\
26001 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__SET(dst) \
26002 (dst) = ((dst) &\
26004 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__CLR(dst) \
26005 (dst) = ((dst) &\
26018 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MODIFY(dst, src) \
26019 (dst) = ((dst) &\
26025 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__SET(dst) \
26026 (dst) = ((dst) &\
26028 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__CLR(dst) \
26029 (dst) = ((dst) &\
26042 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MODIFY(dst, src) \
26043 (dst) = ((dst) &\
26049 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__SET(dst) \
26050 (dst) = ((dst) &\
26052 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__CLR(dst) \
26053 (dst) = ((dst) &\
26066 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MODIFY(dst, src) \
26067 (dst) = ((dst) &\
26073 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__SET(dst) \
26074 (dst) = ((dst) &\
26076 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__CLR(dst) \
26077 (dst) = ((dst) &\
26090 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MODIFY(dst, src) \
26091 (dst) = ((dst) &\
26097 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__SET(dst) \
26098 (dst) = ((dst) &\
26100 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__CLR(dst) \
26101 (dst) = ((dst) &\
26114 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MODIFY(dst, src) \
26115 (dst) = ((dst) &\
26121 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__SET(dst) \
26122 (dst) = ((dst) &\
26124 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__CLR(dst) \
26125 (dst) = ((dst) &\
26138 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MODIFY(dst, src) \
26139 (dst) = ((dst) &\
26145 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__SET(dst) \
26146 (dst) = ((dst) &\
26148 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__CLR(dst) \
26149 (dst) = ((dst) &\
26162 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MODIFY(dst, src) \
26163 (dst) = ((dst) &\
26169 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__SET(dst) \
26170 (dst) = ((dst) &\
26172 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__CLR(dst) \
26173 (dst) = ((dst) &\
26186 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MODIFY(dst, src) \
26187 (dst) = ((dst) &\
26193 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__SET(dst) \
26194 (dst) = ((dst) &\
26196 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__CLR(dst) \
26197 (dst) = ((dst) &\
26210 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MODIFY(dst, src) \
26211 (dst) = ((dst) &\
26217 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__SET(dst) \
26218 (dst) = ((dst) &\
26220 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__CLR(dst) \
26221 (dst) = ((dst) &\
26243 #define MAC_PCU_BSSID_L32__ADDR__MODIFY(dst, src) \
26244 (dst) = ((dst) &\
26270 #define MAC_PCU_BSSID_U16__ADDR__MODIFY(dst, src) \
26271 (dst) = ((dst) &\
26288 #define MAC_PCU_BSSID_U16__AID__MODIFY(dst, src) \
26289 (dst) = ((dst) &\
26339 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MODIFY(dst, src) \
26340 (dst) = ((dst) &\
26357 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MODIFY(dst, src) \
26358 (dst) = ((dst) &\
26388 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MODIFY(dst, src) \
26389 (dst) = ((dst) &\
26406 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MODIFY(dst, src) \
26407 (dst) = ((dst) &\
26424 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MODIFY(dst, src) \
26425 (dst) = ((dst) &\
26442 #define MAC_PCU_BCN_RSSI_CTL__RESET__MODIFY(dst, src) \
26443 (dst) = ((dst) &\
26449 #define MAC_PCU_BCN_RSSI_CTL__RESET__SET(dst) \
26450 (dst) = ((dst) &\
26452 #define MAC_PCU_BCN_RSSI_CTL__RESET__CLR(dst) \
26453 (dst) = ((dst) &\
26475 #define MAC_PCU_USEC_LATENCY__USEC__MODIFY(dst, src) \
26476 (dst) = ((dst) &\
26493 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__MODIFY(dst, src) \
26494 (dst) = ((dst) &\
26511 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__MODIFY(dst, src) \
26512 (dst) = ((dst) &\
26542 #define MAC_PCU_RESET_TSF__ONE_SHOT__MODIFY(dst, src) \
26543 (dst) = ((dst) &\
26549 #define MAC_PCU_RESET_TSF__ONE_SHOT__SET(dst) \
26550 (dst) = ((dst) &\
26552 #define MAC_PCU_RESET_TSF__ONE_SHOT__CLR(dst) \
26553 (dst) = ((dst) &\
26566 #define MAC_PCU_RESET_TSF__ONE_SHOT2__MODIFY(dst, src) \
26567 (dst) = ((dst) &\
26573 #define MAC_PCU_RESET_TSF__ONE_SHOT2__SET(dst) \
26574 (dst) = ((dst) &\
26576 #define MAC_PCU_RESET_TSF__ONE_SHOT2__CLR(dst) \
26577 (dst) = ((dst) &\
26599 #define MAC_PCU_MAX_CFP_DUR__VALUE__MODIFY(dst, src) \
26600 (dst) = ((dst) &\
26617 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MODIFY(dst, src) \
26618 (dst) = ((dst) &\
26635 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MODIFY(dst, src) \
26636 (dst) = ((dst) &\
26662 #define MAC_PCU_RX_FILTER__UNICAST__MODIFY(dst, src) \
26663 (dst) = ((dst) &\
26669 #define MAC_PCU_RX_FILTER__UNICAST__SET(dst) \
26670 (dst) = ((dst) &\
26672 #define MAC_PCU_RX_FILTER__UNICAST__CLR(dst) \
26673 (dst) = ((dst) &\
26686 #define MAC_PCU_RX_FILTER__MULTICAST__MODIFY(dst, src) \
26687 (dst) = ((dst) &\
26693 #define MAC_PCU_RX_FILTER__MULTICAST__SET(dst) \
26694 (dst) = ((dst) &\
26696 #define MAC_PCU_RX_FILTER__MULTICAST__CLR(dst) \
26697 (dst) = ((dst) &\
26710 #define MAC_PCU_RX_FILTER__BROADCAST__MODIFY(dst, src) \
26711 (dst) = ((dst) &\
26717 #define MAC_PCU_RX_FILTER__BROADCAST__SET(dst) \
26718 (dst) = ((dst) &\
26720 #define MAC_PCU_RX_FILTER__BROADCAST__CLR(dst) \
26721 (dst) = ((dst) &\
26734 #define MAC_PCU_RX_FILTER__CONTROL__MODIFY(dst, src) \
26735 (dst) = ((dst) &\
26741 #define MAC_PCU_RX_FILTER__CONTROL__SET(dst) \
26742 (dst) = ((dst) &\
26744 #define MAC_PCU_RX_FILTER__CONTROL__CLR(dst) \
26745 (dst) = ((dst) &\
26758 #define MAC_PCU_RX_FILTER__BEACON__MODIFY(dst, src) \
26759 (dst) = ((dst) &\
26765 #define MAC_PCU_RX_FILTER__BEACON__SET(dst) \
26766 (dst) = ((dst) &\
26768 #define MAC_PCU_RX_FILTER__BEACON__CLR(dst) \
26769 (dst) = ((dst) &\
26782 #define MAC_PCU_RX_FILTER__PROMISCUOUS__MODIFY(dst, src) \
26783 (dst) = ((dst) &\
26789 #define MAC_PCU_RX_FILTER__PROMISCUOUS__SET(dst) \
26790 (dst) = ((dst) &\
26792 #define MAC_PCU_RX_FILTER__PROMISCUOUS__CLR(dst) \
26793 (dst) = ((dst) &\
26806 #define MAC_PCU_RX_FILTER__XR_POLL__MODIFY(dst, src) \
26807 (dst) = ((dst) &\
26813 #define MAC_PCU_RX_FILTER__XR_POLL__SET(dst) \
26814 (dst) = ((dst) &\
26816 #define MAC_PCU_RX_FILTER__XR_POLL__CLR(dst) \
26817 (dst) = ((dst) &\
26830 #define MAC_PCU_RX_FILTER__PROBE_REQ__MODIFY(dst, src) \
26831 (dst) = ((dst) &\
26837 #define MAC_PCU_RX_FILTER__PROBE_REQ__SET(dst) \
26838 (dst) = ((dst) &\
26840 #define MAC_PCU_RX_FILTER__PROBE_REQ__CLR(dst) \
26841 (dst) = ((dst) &\
26854 #define MAC_PCU_RX_FILTER__SYNC_FRAME__MODIFY(dst, src) \
26855 (dst) = ((dst) &\
26861 #define MAC_PCU_RX_FILTER__SYNC_FRAME__SET(dst) \
26862 (dst) = ((dst) &\
26864 #define MAC_PCU_RX_FILTER__SYNC_FRAME__CLR(dst) \
26865 (dst) = ((dst) &\
26878 #define MAC_PCU_RX_FILTER__MY_BEACON__MODIFY(dst, src) \
26879 (dst) = ((dst) &\
26885 #define MAC_PCU_RX_FILTER__MY_BEACON__SET(dst) \
26886 (dst) = ((dst) &\
26888 #define MAC_PCU_RX_FILTER__MY_BEACON__CLR(dst) \
26889 (dst) = ((dst) &\
26902 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MODIFY(dst, src) \
26903 (dst) = ((dst) &\
26909 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__SET(dst) \
26910 (dst) = ((dst) &\
26912 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__CLR(dst) \
26913 (dst) = ((dst) &\
26926 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__MODIFY(dst, src) \
26927 (dst) = ((dst) &\
26933 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__SET(dst) \
26934 (dst) = ((dst) &\
26936 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__CLR(dst) \
26937 (dst) = ((dst) &\
26950 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MODIFY(dst, src) \
26951 (dst) = ((dst) &\
26957 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__SET(dst) \
26958 (dst) = ((dst) &\
26960 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__CLR(dst) \
26961 (dst) = ((dst) &\
26974 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__MODIFY(dst, src) \
26975 (dst) = ((dst) &\
26981 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__SET(dst) \
26982 (dst) = ((dst) &\
26984 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__CLR(dst) \
26985 (dst) = ((dst) &\
26998 #define MAC_PCU_RX_FILTER__PS_POLL__MODIFY(dst, src) \
26999 (dst) = ((dst) &\
27005 #define MAC_PCU_RX_FILTER__PS_POLL__SET(dst) \
27006 (dst) = ((dst) &\
27008 #define MAC_PCU_RX_FILTER__PS_POLL__CLR(dst) \
27009 (dst) = ((dst) &\
27022 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MODIFY(dst, src) \
27023 (dst) = ((dst) &\
27029 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__SET(dst) \
27030 (dst) = ((dst) &\
27032 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__CLR(dst) \
27033 (dst) = ((dst) &\
27046 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MODIFY(dst, src) \
27047 (dst) = ((dst) &\
27053 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__SET(dst) \
27054 (dst) = ((dst) &\
27056 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__CLR(dst) \
27057 (dst) = ((dst) &\
27070 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MODIFY(dst, src) \
27071 (dst) = ((dst) &\
27077 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__SET(dst) \
27078 (dst) = ((dst) &\
27080 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__CLR(dst) \
27081 (dst) = ((dst) &\
27094 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MODIFY(dst, src) \
27095 (dst) = ((dst) &\
27101 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__SET(dst) \
27102 (dst) = ((dst) &\
27104 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__CLR(dst) \
27105 (dst) = ((dst) &\
27131 #define MAC_PCU_MCAST_FILTER_L32__VALUE__MODIFY(dst, src) \
27132 (dst) = ((dst) &\
27162 #define MAC_PCU_MCAST_FILTER_U32__VALUE__MODIFY(dst, src) \
27163 (dst) = ((dst) &\
27193 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MODIFY(dst, src) \
27194 (dst) = ((dst) &\
27200 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__SET(dst) \
27201 (dst) = ((dst) &\
27203 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__CLR(dst) \
27204 (dst) = ((dst) &\
27217 #define MAC_PCU_DIAG_SW__NO_ACK__MODIFY(dst, src) \
27218 (dst) = ((dst) &\
27224 #define MAC_PCU_DIAG_SW__NO_ACK__SET(dst) \
27225 (dst) = ((dst) &\
27227 #define MAC_PCU_DIAG_SW__NO_ACK__CLR(dst) \
27228 (dst) = ((dst) &\
27241 #define MAC_PCU_DIAG_SW__NO_CTS__MODIFY(dst, src) \
27242 (dst) = ((dst) &\
27248 #define MAC_PCU_DIAG_SW__NO_CTS__SET(dst) \
27249 (dst) = ((dst) &\
27251 #define MAC_PCU_DIAG_SW__NO_CTS__CLR(dst) \
27252 (dst) = ((dst) &\
27265 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__MODIFY(dst, src) \
27266 (dst) = ((dst) &\
27272 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__SET(dst) \
27273 (dst) = ((dst) &\
27275 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__CLR(dst) \
27276 (dst) = ((dst) &\
27289 #define MAC_PCU_DIAG_SW__NO_DECRYPT__MODIFY(dst, src) \
27290 (dst) = ((dst) &\
27296 #define MAC_PCU_DIAG_SW__NO_DECRYPT__SET(dst) \
27297 (dst) = ((dst) &\
27299 #define MAC_PCU_DIAG_SW__NO_DECRYPT__CLR(dst) \
27300 (dst) = ((dst) &\
27313 #define MAC_PCU_DIAG_SW__HALT_RX__MODIFY(dst, src) \
27314 (dst) = ((dst) &\
27320 #define MAC_PCU_DIAG_SW__HALT_RX__SET(dst) \
27321 (dst) = ((dst) &\
27323 #define MAC_PCU_DIAG_SW__HALT_RX__CLR(dst) \
27324 (dst) = ((dst) &\
27337 #define MAC_PCU_DIAG_SW__LOOP_BACK__MODIFY(dst, src) \
27338 (dst) = ((dst) &\
27344 #define MAC_PCU_DIAG_SW__LOOP_BACK__SET(dst) \
27345 (dst) = ((dst) &\
27347 #define MAC_PCU_DIAG_SW__LOOP_BACK__CLR(dst) \
27348 (dst) = ((dst) &\
27361 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__MODIFY(dst, src) \
27362 (dst) = ((dst) &\
27368 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__SET(dst) \
27369 (dst) = ((dst) &\
27371 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__CLR(dst) \
27372 (dst) = ((dst) &\
27385 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MODIFY(dst, src) \
27386 (dst) = ((dst) &\
27392 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__SET(dst) \
27393 (dst) = ((dst) &\
27395 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__CLR(dst) \
27396 (dst) = ((dst) &\
27409 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MODIFY(dst, src) \
27410 (dst) = ((dst) &\
27416 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__SET(dst) \
27417 (dst) = ((dst) &\
27419 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__CLR(dst) \
27420 (dst) = ((dst) &\
27433 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MODIFY(dst, src) \
27434 (dst) = ((dst) &\
27451 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MODIFY(dst, src) \
27452 (dst) = ((dst) &\
27458 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__SET(dst) \
27459 (dst) = ((dst) &\
27461 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__CLR(dst) \
27462 (dst) = ((dst) &\
27475 #define MAC_PCU_DIAG_SW__IGNORE_NAV__MODIFY(dst, src) \
27476 (dst) = ((dst) &\
27482 #define MAC_PCU_DIAG_SW__IGNORE_NAV__SET(dst) \
27483 (dst) = ((dst) &\
27485 #define MAC_PCU_DIAG_SW__IGNORE_NAV__CLR(dst) \
27486 (dst) = ((dst) &\
27499 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MODIFY(dst, src) \
27500 (dst) = ((dst) &\
27506 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__SET(dst) \
27507 (dst) = ((dst) &\
27509 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__CLR(dst) \
27510 (dst) = ((dst) &\
27523 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MODIFY(dst, src) \
27524 (dst) = ((dst) &\
27530 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__SET(dst) \
27531 (dst) = ((dst) &\
27533 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__CLR(dst) \
27534 (dst) = ((dst) &\
27547 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MODIFY(dst, src) \
27548 (dst) = ((dst) &\
27554 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__SET(dst) \
27555 (dst) = ((dst) &\
27557 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__CLR(dst) \
27558 (dst) = ((dst) &\
27571 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MODIFY(dst, src) \
27572 (dst) = ((dst) &\
27578 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__SET(dst) \
27579 (dst) = ((dst) &\
27581 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__CLR(dst) \
27582 (dst) = ((dst) &\
27595 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MODIFY(dst, src) \
27596 (dst) = ((dst) &\
27602 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__SET(dst) \
27603 (dst) = ((dst) &\
27605 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__CLR(dst) \
27606 (dst) = ((dst) &\
27619 #define MAC_PCU_DIAG_SW__OBS_SEL_2__MODIFY(dst, src) \
27620 (dst) = ((dst) &\
27626 #define MAC_PCU_DIAG_SW__OBS_SEL_2__SET(dst) \
27627 (dst) = ((dst) &\
27629 #define MAC_PCU_DIAG_SW__OBS_SEL_2__CLR(dst) \
27630 (dst) = ((dst) &\
27643 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MODIFY(dst, src) \
27644 (dst) = ((dst) &\
27650 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__SET(dst) \
27651 (dst) = ((dst) &\
27653 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__CLR(dst) \
27654 (dst) = ((dst) &\
27667 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MODIFY(dst, src) \
27668 (dst) = ((dst) &\
27674 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__SET(dst) \
27675 (dst) = ((dst) &\
27677 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__CLR(dst) \
27678 (dst) = ((dst) &\
27691 #define MAC_PCU_DIAG_SW__DEBUG_MODE__MODIFY(dst, src) \
27692 (dst) = ((dst) &\
27718 #define MAC_PCU_TSF_L32__VALUE__MODIFY(dst, src) \
27719 (dst) = ((dst) &\
27745 #define MAC_PCU_TSF_U32__VALUE__MODIFY(dst, src) \
27746 (dst) = ((dst) &\
27772 #define MAC_PCU_TST_ADDAC__CONT_TX__MODIFY(dst, src) \
27773 (dst) = ((dst) &\
27779 #define MAC_PCU_TST_ADDAC__CONT_TX__SET(dst) \
27780 (dst) = ((dst) &\
27782 #define MAC_PCU_TST_ADDAC__CONT_TX__CLR(dst) \
27783 (dst) = ((dst) &\
27796 #define MAC_PCU_TST_ADDAC__TESTMODE__MODIFY(dst, src) \
27797 (dst) = ((dst) &\
27803 #define MAC_PCU_TST_ADDAC__TESTMODE__SET(dst) \
27804 (dst) = ((dst) &\
27806 #define MAC_PCU_TST_ADDAC__TESTMODE__CLR(dst) \
27807 (dst) = ((dst) &\
27820 #define MAC_PCU_TST_ADDAC__LOOP__MODIFY(dst, src) \
27821 (dst) = ((dst) &\
27827 #define MAC_PCU_TST_ADDAC__LOOP__SET(dst) \
27828 (dst) = ((dst) &\
27830 #define MAC_PCU_TST_ADDAC__LOOP__CLR(dst) \
27831 (dst) = ((dst) &\
27844 #define MAC_PCU_TST_ADDAC__LOOP_LEN__MODIFY(dst, src) \
27845 (dst) = ((dst) &\
27862 #define MAC_PCU_TST_ADDAC__UPPER_8B__MODIFY(dst, src) \
27863 (dst) = ((dst) &\
27869 #define MAC_PCU_TST_ADDAC__UPPER_8B__SET(dst) \
27870 (dst) = ((dst) &\
27872 #define MAC_PCU_TST_ADDAC__UPPER_8B__CLR(dst) \
27873 (dst) = ((dst) &\
27886 #define MAC_PCU_TST_ADDAC__TRIG_SEL__MODIFY(dst, src) \
27887 (dst) = ((dst) &\
27893 #define MAC_PCU_TST_ADDAC__TRIG_SEL__SET(dst) \
27894 (dst) = ((dst) &\
27896 #define MAC_PCU_TST_ADDAC__TRIG_SEL__CLR(dst) \
27897 (dst) = ((dst) &\
27910 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MODIFY(dst, src) \
27911 (dst) = ((dst) &\
27917 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__SET(dst) \
27918 (dst) = ((dst) &\
27920 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__CLR(dst) \
27921 (dst) = ((dst) &\
27931 #define MAC_PCU_TST_ADDAC__CONT_TEST__SET(dst) \
27932 (dst) = ((dst) &\
27934 #define MAC_PCU_TST_ADDAC__CONT_TEST__CLR(dst) \
27935 (dst) = ((dst) &\
27948 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MODIFY(dst, src) \
27949 (dst) = ((dst) &\
27955 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__SET(dst) \
27956 (dst) = ((dst) &\
27958 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__CLR(dst) \
27959 (dst) = ((dst) &\
27972 #define MAC_PCU_TST_ADDAC__TEST_ARM__MODIFY(dst, src) \
27973 (dst) = ((dst) &\
27979 #define MAC_PCU_TST_ADDAC__TEST_ARM__SET(dst) \
27980 (dst) = ((dst) &\
27982 #define MAC_PCU_TST_ADDAC__TEST_ARM__CLR(dst) \
27983 (dst) = ((dst) &\
28005 #define MAC_PCU_DEF_ANTENNA__VALUE__MODIFY(dst, src) \
28006 (dst) = ((dst) &\
28023 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MODIFY(dst, src) \
28024 (dst) = ((dst) &\
28030 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__SET(dst) \
28031 (dst) = ((dst) &\
28033 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__CLR(dst) \
28034 (dst) = ((dst) &\
28047 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MODIFY(dst, src) \
28048 (dst) = ((dst) &\
28054 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__SET(dst) \
28055 (dst) = ((dst) &\
28057 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__CLR(dst) \
28058 (dst) = ((dst) &\
28071 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MODIFY(dst, src) \
28072 (dst) = ((dst) &\
28078 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__SET(dst) \
28079 (dst) = ((dst) &\
28081 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__CLR(dst) \
28082 (dst) = ((dst) &\
28095 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MODIFY(dst, src) \
28096 (dst) = ((dst) &\
28102 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__SET(dst) \
28103 (dst) = ((dst) &\
28105 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__CLR(dst) \
28106 (dst) = ((dst) &\
28119 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MODIFY(dst, src) \
28120 (dst) = ((dst) &\
28126 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__SET(dst) \
28127 (dst) = ((dst) &\
28129 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__CLR(dst) \
28130 (dst) = ((dst) &\
28143 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MODIFY(dst, src) \
28144 (dst) = ((dst) &\
28150 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__SET(dst) \
28151 (dst) = ((dst) &\
28153 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__CLR(dst) \
28154 (dst) = ((dst) &\
28178 #define MAC_PCU_AES_MUTE_MASK_0__FC__MODIFY(dst, src) \
28179 (dst) = ((dst) &\
28196 #define MAC_PCU_AES_MUTE_MASK_0__QOS__MODIFY(dst, src) \
28197 (dst) = ((dst) &\
28225 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__MODIFY(dst, src) \
28226 (dst) = ((dst) &\
28243 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MODIFY(dst, src) \
28244 (dst) = ((dst) &\
28274 #define MAC_PCU_GATED_CLKS__GATED_TX__MODIFY(dst, src) \
28275 (dst) = ((dst) &\
28281 #define MAC_PCU_GATED_CLKS__GATED_TX__SET(dst) \
28282 (dst) = ((dst) &\
28284 #define MAC_PCU_GATED_CLKS__GATED_TX__CLR(dst) \
28285 (dst) = ((dst) &\
28298 #define MAC_PCU_GATED_CLKS__GATED_RX__MODIFY(dst, src) \
28299 (dst) = ((dst) &\
28305 #define MAC_PCU_GATED_CLKS__GATED_RX__SET(dst) \
28306 (dst) = ((dst) &\
28308 #define MAC_PCU_GATED_CLKS__GATED_RX__CLR(dst) \
28309 (dst) = ((dst) &\
28322 #define MAC_PCU_GATED_CLKS__GATED_REG__MODIFY(dst, src) \
28323 (dst) = ((dst) &\
28329 #define MAC_PCU_GATED_CLKS__GATED_REG__SET(dst) \
28330 (dst) = ((dst) &\
28332 #define MAC_PCU_GATED_CLKS__GATED_REG__CLR(dst) \
28333 (dst) = ((dst) &\
28370 #define MAC_PCU_OBS_BUS_2__WCF0_FULL__SET(dst) \
28371 (dst) = ((dst) &\
28373 #define MAC_PCU_OBS_BUS_2__WCF0_FULL__CLR(dst) \
28374 (dst) = ((dst) &\
28384 #define MAC_PCU_OBS_BUS_2__WCF1_FULL__SET(dst) \
28385 (dst) = ((dst) &\
28387 #define MAC_PCU_OBS_BUS_2__WCF1_FULL__CLR(dst) \
28388 (dst) = ((dst) &\
28406 #define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__SET(dst) \
28407 (dst) = ((dst) &\
28409 #define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__CLR(dst) \
28410 (dst) = ((dst) &\
28432 #define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__SET(dst) \
28433 (dst) = ((dst) &\
28435 #define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__CLR(dst) \
28436 (dst) = ((dst) &\
28446 #define MAC_PCU_OBS_BUS_1__PCU_RX_END__SET(dst) \
28447 (dst) = ((dst) &\
28449 #define MAC_PCU_OBS_BUS_1__PCU_RX_END__CLR(dst) \
28450 (dst) = ((dst) &\
28460 #define MAC_PCU_OBS_BUS_1__RX_WEP__SET(dst) \
28461 (dst) = ((dst) &\
28463 #define MAC_PCU_OBS_BUS_1__RX_WEP__CLR(dst) \
28464 (dst) = ((dst) &\
28474 #define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__SET(dst) \
28475 (dst) = ((dst) &\
28477 #define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__CLR(dst) \
28478 (dst) = ((dst) &\
28488 #define MAC_PCU_OBS_BUS_1__FILTER_PASS__SET(dst) \
28489 (dst) = ((dst) &\
28491 #define MAC_PCU_OBS_BUS_1__FILTER_PASS__CLR(dst) \
28492 (dst) = ((dst) &\
28502 #define MAC_PCU_OBS_BUS_1__TX_HCF__SET(dst) \
28503 (dst) = ((dst) &\
28505 #define MAC_PCU_OBS_BUS_1__TX_HCF__CLR(dst) \
28506 (dst) = ((dst) &\
28516 #define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__SET(dst) \
28517 (dst) = ((dst) &\
28519 #define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__CLR(dst) \
28520 (dst) = ((dst) &\
28530 #define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__SET(dst) \
28531 (dst) = ((dst) &\
28533 #define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__CLR(dst) \
28534 (dst) = ((dst) &\
28544 #define MAC_PCU_OBS_BUS_1__TX_HOLD__SET(dst) \
28545 (dst) = ((dst) &\
28547 #define MAC_PCU_OBS_BUS_1__TX_HOLD__CLR(dst) \
28548 (dst) = ((dst) &\
28558 #define MAC_PCU_OBS_BUS_1__TX_FRAME__SET(dst) \
28559 (dst) = ((dst) &\
28561 #define MAC_PCU_OBS_BUS_1__TX_FRAME__CLR(dst) \
28562 (dst) = ((dst) &\
28572 #define MAC_PCU_OBS_BUS_1__RX_FRAME__SET(dst) \
28573 (dst) = ((dst) &\
28575 #define MAC_PCU_OBS_BUS_1__RX_FRAME__CLR(dst) \
28576 (dst) = ((dst) &\
28586 #define MAC_PCU_OBS_BUS_1__RX_CLEAR__SET(dst) \
28587 (dst) = ((dst) &\
28589 #define MAC_PCU_OBS_BUS_1__RX_CLEAR__CLR(dst) \
28590 (dst) = ((dst) &\
28639 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MODIFY(dst, src) \
28640 (dst) = ((dst) &\
28646 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__SET(dst) \
28647 (dst) = ((dst) &\
28649 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__CLR(dst) \
28650 (dst) = ((dst) &\
28663 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MODIFY(dst, src) \
28664 (dst) = ((dst) &\
28670 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__SET(dst) \
28671 (dst) = ((dst) &\
28673 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__CLR(dst) \
28674 (dst) = ((dst) &\
28687 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MODIFY(dst, src) \
28688 (dst) = ((dst) &\
28694 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__SET(dst) \
28695 (dst) = ((dst) &\
28697 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__CLR(dst) \
28698 (dst) = ((dst) &\
28711 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MODIFY(dst, src) \
28712 (dst) = ((dst) &\
28729 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MODIFY(dst, src) \
28730 (dst) = ((dst) &\
28760 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MODIFY(dst, src) \
28761 (dst) = ((dst) &\
28792 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MODIFY(dst, src) \
28793 (dst) = ((dst) &\
28840 #define MAC_PCU_NAV__VALUE__MODIFY(dst, src) \
28841 (dst) = ((dst) &\
28961 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MODIFY(dst, src) \
28962 (dst) = ((dst) &\
28988 #define MAC_PCU_BASIC_SET__MCS__MODIFY(dst, src) \
28989 (dst) = ((dst) &\
29015 #define MAC_PCU_MGMT_SEQ__MIN__MODIFY(dst, src) \
29016 (dst) = ((dst) &\
29033 #define MAC_PCU_MGMT_SEQ__MAX__MODIFY(dst, src) \
29034 (dst) = ((dst) &\
29064 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MODIFY(dst, src) \
29065 (dst) = ((dst) &\
29082 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MODIFY(dst, src) \
29083 (dst) = ((dst) &\
29100 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MODIFY(dst, src) \
29101 (dst) = ((dst) &\
29118 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \
29119 (dst) = ((dst) &\
29136 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MODIFY(dst, src) \
29137 (dst) = ((dst) &\
29167 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \
29168 (dst) = ((dst) &\
29194 #define MAC_PCU_TX_ANT_1__VALUE__MODIFY(dst, src) \
29195 (dst) = ((dst) &\
29221 #define MAC_PCU_TX_ANT_2__VALUE__MODIFY(dst, src) \
29222 (dst) = ((dst) &\
29248 #define MAC_PCU_TX_ANT_3__VALUE__MODIFY(dst, src) \
29249 (dst) = ((dst) &\
29275 #define MAC_PCU_TX_ANT_4__VALUE__MODIFY(dst, src) \
29276 (dst) = ((dst) &\
29302 #define MAC_PCU_XRMODE__POLL_TYPE__MODIFY(dst, src) \
29303 (dst) = ((dst) &\
29320 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__MODIFY(dst, src) \
29321 (dst) = ((dst) &\
29327 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__SET(dst) \
29328 (dst) = ((dst) &\
29330 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__CLR(dst) \
29331 (dst) = ((dst) &\
29344 #define MAC_PCU_XRMODE__FRAME_HOLD__MODIFY(dst, src) \
29345 (dst) = ((dst) &\
29371 #define MAC_PCU_XRDEL__SLOT_DELAY__MODIFY(dst, src) \
29372 (dst) = ((dst) &\
29389 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MODIFY(dst, src) \
29390 (dst) = ((dst) &\
29418 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__MODIFY(dst, src) \
29419 (dst) = ((dst) &\
29436 #define MAC_PCU_XRTO__POLL_TIMEOUT__MODIFY(dst, src) \
29437 (dst) = ((dst) &\
29463 #define MAC_PCU_XRCRP__SEND_CHIRP__MODIFY(dst, src) \
29464 (dst) = ((dst) &\
29470 #define MAC_PCU_XRCRP__SEND_CHIRP__SET(dst) \
29471 (dst) = ((dst) &\
29473 #define MAC_PCU_XRCRP__SEND_CHIRP__CLR(dst) \
29474 (dst) = ((dst) &\
29487 #define MAC_PCU_XRCRP__CHIRP_GAP__MODIFY(dst, src) \
29488 (dst) = ((dst) &\
29516 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MODIFY(dst, src) \
29517 (dst) = ((dst) &\
29523 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__SET(dst) \
29524 (dst) = ((dst) &\
29526 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__CLR(dst) \
29527 (dst) = ((dst) &\
29540 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MODIFY(dst, src) \
29541 (dst) = ((dst) &\
29547 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__SET(dst) \
29548 (dst) = ((dst) &\
29550 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__CLR(dst) \
29551 (dst) = ((dst) &\
29564 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MODIFY(dst, src) \
29565 (dst) = ((dst) &\
29571 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__SET(dst) \
29572 (dst) = ((dst) &\
29574 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__CLR(dst) \
29575 (dst) = ((dst) &\
29588 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MODIFY(dst, src) \
29589 (dst) = ((dst) &\
29595 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__SET(dst) \
29596 (dst) = ((dst) &\
29598 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__CLR(dst) \
29599 (dst) = ((dst) &\
29612 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__MODIFY(dst, src) \
29613 (dst) = ((dst) &\
29619 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__SET(dst) \
29620 (dst) = ((dst) &\
29622 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__CLR(dst) \
29623 (dst) = ((dst) &\
29636 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__MODIFY(dst, src) \
29637 (dst) = ((dst) &\
29643 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__SET(dst) \
29644 (dst) = ((dst) &\
29646 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__CLR(dst) \
29647 (dst) = ((dst) &\
29660 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MODIFY(dst, src) \
29661 (dst) = ((dst) &\
29678 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MODIFY(dst, src) \
29679 (dst) = ((dst) &\
29709 #define MAC_PCU_SLP1__ASSUME_DTIM__MODIFY(dst, src) \
29710 (dst) = ((dst) &\
29716 #define MAC_PCU_SLP1__ASSUME_DTIM__SET(dst) \
29717 (dst) = ((dst) &\
29719 #define MAC_PCU_SLP1__ASSUME_DTIM__CLR(dst) \
29720 (dst) = ((dst) &\
29733 #define MAC_PCU_SLP1__CAB_TIMEOUT__MODIFY(dst, src) \
29734 (dst) = ((dst) &\
29764 #define MAC_PCU_SLP2__BEACON_TIMEOUT__MODIFY(dst, src) \
29765 (dst) = ((dst) &\
29795 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MODIFY(dst, src) \
29796 (dst) = ((dst) &\
29813 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__MODIFY(dst, src) \
29814 (dst) = ((dst) &\
29831 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MODIFY(dst, src) \
29832 (dst) = ((dst) &\
29838 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__SET(dst) \
29839 (dst) = ((dst) &\
29841 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__CLR(dst) \
29842 (dst) = ((dst) &\
29866 #define MAC_PCU_ADDR1_MASK_L32__VALUE__MODIFY(dst, src) \
29867 (dst) = ((dst) &\
29895 #define MAC_PCU_ADDR1_MASK_U16__VALUE__MODIFY(dst, src) \
29896 (dst) = ((dst) &\
29922 #define MAC_PCU_TPC__ACK_PWR__MODIFY(dst, src) \
29923 (dst) = ((dst) &\
29938 #define MAC_PCU_TPC__CTS_PWR__MODIFY(dst, src) \
29939 (dst) = ((dst) &\
29956 #define MAC_PCU_TPC__CHIRP_PWR__MODIFY(dst, src) \
29957 (dst) = ((dst) &\
29974 #define MAC_PCU_TPC__RPT_PWR__MODIFY(dst, src) \
29975 (dst) = ((dst) &\
30003 #define MAC_PCU_TX_FRAME_CNT__VALUE__MODIFY(dst, src) \
30004 (dst) = ((dst) &\
30032 #define MAC_PCU_RX_FRAME_CNT__VALUE__MODIFY(dst, src) \
30033 (dst) = ((dst) &\
30061 #define MAC_PCU_RX_CLEAR_CNT__VALUE__MODIFY(dst, src) \
30062 (dst) = ((dst) &\
30088 #define MAC_PCU_CYCLE_CNT__VALUE__MODIFY(dst, src) \
30089 (dst) = ((dst) &\
30119 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MODIFY(dst, src) \
30120 (dst) = ((dst) &\
30126 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__SET(dst) \
30127 (dst) = ((dst) &\
30129 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__CLR(dst) \
30130 (dst) = ((dst) &\
30156 #define MAC_PCU_QUIET_TIME_2__DURATION__MODIFY(dst, src) \
30157 (dst) = ((dst) &\
30187 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MODIFY(dst, src) \
30188 (dst) = ((dst) &\
30205 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MODIFY(dst, src) \
30206 (dst) = ((dst) &\
30223 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MODIFY(dst, src) \
30224 (dst) = ((dst) &\
30252 #define MAC_PCU_PHY_ERROR_MASK__VALUE__MODIFY(dst, src) \
30253 (dst) = ((dst) &\
30279 #define MAC_PCU_XRLAT__VALUE__MODIFY(dst, src) \
30280 (dst) = ((dst) &\
30310 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MODIFY(dst, src) \
30311 (dst) = ((dst) &\
30328 #define MAC_PCU_RXBUF__REG_RD_ENABLE__MODIFY(dst, src) \
30329 (dst) = ((dst) &\
30335 #define MAC_PCU_RXBUF__REG_RD_ENABLE__SET(dst) \
30336 (dst) = ((dst) &\
30338 #define MAC_PCU_RXBUF__REG_RD_ENABLE__CLR(dst) \
30339 (dst) = ((dst) &\
30365 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MODIFY(dst, src) \
30366 (dst) = ((dst) &\
30383 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MODIFY(dst, src) \
30384 (dst) = ((dst) &\
30401 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MODIFY(dst, src) \
30402 (dst) = ((dst) &\
30419 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MODIFY(dst, src) \
30420 (dst) = ((dst) &\
30437 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MODIFY(dst, src) \
30438 (dst) = ((dst) &\
30455 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MODIFY(dst, src) \
30456 (dst) = ((dst) &\
30473 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MODIFY(dst, src) \
30474 (dst) = ((dst) &\
30491 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MODIFY(dst, src) \
30492 (dst) = ((dst) &\
30509 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MODIFY(dst, src) \
30510 (dst) = ((dst) &\
30516 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__SET(dst) \
30517 (dst) = ((dst) &\
30519 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__CLR(dst) \
30520 (dst) = ((dst) &\
30546 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MODIFY(dst, src) \
30547 (dst) = ((dst) &\
30564 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MODIFY(dst, src) \
30565 (dst) = ((dst) &\
30582 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MODIFY(dst, src) \
30583 (dst) = ((dst) &\
30600 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MODIFY(dst, src) \
30601 (dst) = ((dst) &\
30618 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MODIFY(dst, src) \
30619 (dst) = ((dst) &\
30636 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MODIFY(dst, src) \
30637 (dst) = ((dst) &\
30654 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MODIFY(dst, src) \
30655 (dst) = ((dst) &\
30672 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MODIFY(dst, src) \
30673 (dst) = ((dst) &\
30703 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MODIFY(dst, src) \
30704 (dst) = ((dst) &\
30710 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__SET(dst) \
30711 (dst) = ((dst) &\
30713 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__CLR(dst) \
30714 (dst) = ((dst) &\
30727 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MODIFY(dst, src) \
30728 (dst) = ((dst) &\
30734 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__SET(dst) \
30735 (dst) = ((dst) &\
30737 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__CLR(dst) \
30738 (dst) = ((dst) &\
30751 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MODIFY(dst, src) \
30752 (dst) = ((dst) &\
30758 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__SET(dst) \
30759 (dst) = ((dst) &\
30761 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__CLR(dst) \
30762 (dst) = ((dst) &\
30775 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__MODIFY(dst, src) \
30776 (dst) = ((dst) &\
30782 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__SET(dst) \
30783 (dst) = ((dst) &\
30785 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__CLR(dst) \
30786 (dst) = ((dst) &\
30799 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MODIFY(dst, src) \
30800 (dst) = ((dst) &\
30806 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__SET(dst) \
30807 (dst) = ((dst) &\
30809 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__CLR(dst) \
30810 (dst) = ((dst) &\
30823 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MODIFY(dst, src) \
30824 (dst) = ((dst) &\
30830 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__SET(dst) \
30831 (dst) = ((dst) &\
30833 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__CLR(dst) \
30834 (dst) = ((dst) &\
30847 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MODIFY(dst, src) \
30848 (dst) = ((dst) &\
30854 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__SET(dst) \
30855 (dst) = ((dst) &\
30857 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__CLR(dst) \
30858 (dst) = ((dst) &\
30871 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MODIFY(dst, src) \
30872 (dst) = ((dst) &\
30878 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__SET(dst) \
30879 (dst) = ((dst) &\
30881 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__CLR(dst) \
30882 (dst) = ((dst) &\
30895 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MODIFY(dst, src) \
30896 (dst) = ((dst) &\
30902 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__SET(dst) \
30903 (dst) = ((dst) &\
30905 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__CLR(dst) \
30906 (dst) = ((dst) &\
30919 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MODIFY(dst, src) \
30920 (dst) = ((dst) &\
30926 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__SET(dst) \
30927 (dst) = ((dst) &\
30929 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__CLR(dst) \
30930 (dst) = ((dst) &\
30943 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MODIFY(dst, src) \
30944 (dst) = ((dst) &\
30950 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__SET(dst) \
30951 (dst) = ((dst) &\
30953 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__CLR(dst) \
30954 (dst) = ((dst) &\
30967 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MODIFY(dst, src) \
30968 (dst) = ((dst) &\
30974 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__SET(dst) \
30975 (dst) = ((dst) &\
30977 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__CLR(dst) \
30978 (dst) = ((dst) &\
30991 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MODIFY(dst, src) \
30992 (dst) = ((dst) &\
30998 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__SET(dst) \
30999 (dst) = ((dst) &\
31001 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__CLR(dst) \
31002 (dst) = ((dst) &\
31015 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MODIFY(dst, src) \
31016 (dst) = ((dst) &\
31022 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__SET(dst) \
31023 (dst) = ((dst) &\
31025 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__CLR(dst) \
31026 (dst) = ((dst) &\
31039 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__MODIFY(dst, src) \
31040 (dst) = ((dst) &\
31046 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__SET(dst) \
31047 (dst) = ((dst) &\
31049 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__CLR(dst) \
31050 (dst) = ((dst) &\
31063 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MODIFY(dst, src) \
31064 (dst) = ((dst) &\
31070 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__SET(dst) \
31071 (dst) = ((dst) &\
31073 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__CLR(dst) \
31074 (dst) = ((dst) &\
31087 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MODIFY(dst, src) \
31088 (dst) = ((dst) &\
31094 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__SET(dst) \
31095 (dst) = ((dst) &\
31097 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__CLR(dst) \
31098 (dst) = ((dst) &\
31111 #define MAC_PCU_MISC_MODE__CLEAR_VMF__MODIFY(dst, src) \
31112 (dst) = ((dst) &\
31118 #define MAC_PCU_MISC_MODE__CLEAR_VMF__SET(dst) \
31119 (dst) = ((dst) &\
31121 #define MAC_PCU_MISC_MODE__CLEAR_VMF__CLR(dst) \
31122 (dst) = ((dst) &\
31135 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MODIFY(dst, src) \
31136 (dst) = ((dst) &\
31142 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__SET(dst) \
31143 (dst) = ((dst) &\
31145 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__CLR(dst) \
31146 (dst) = ((dst) &\
31159 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MODIFY(dst, src) \
31160 (dst) = ((dst) &\
31166 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__SET(dst) \
31167 (dst) = ((dst) &\
31169 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__CLR(dst) \
31170 (dst) = ((dst) &\
31183 #define MAC_PCU_MISC_MODE__SEL_EVM__MODIFY(dst, src) \
31184 (dst) = ((dst) &\
31190 #define MAC_PCU_MISC_MODE__SEL_EVM__SET(dst) \
31191 (dst) = ((dst) &\
31193 #define MAC_PCU_MISC_MODE__SEL_EVM__CLR(dst) \
31194 (dst) = ((dst) &\
31207 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MODIFY(dst, src) \
31208 (dst) = ((dst) &\
31214 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__SET(dst) \
31215 (dst) = ((dst) &\
31217 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__CLR(dst) \
31218 (dst) = ((dst) &\
31231 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MODIFY(dst, src) \
31232 (dst) = ((dst) &\
31238 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__SET(dst) \
31239 (dst) = ((dst) &\
31241 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__CLR(dst) \
31242 (dst) = ((dst) &\
31255 #define MAC_PCU_MISC_MODE__DEBUG_MODE__MODIFY(dst, src) \
31256 (dst) = ((dst) &\
31286 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__MODIFY(dst, src) \
31287 (dst) = ((dst) &\
31315 #define MAC_PCU_FILTER_CCK_CNT__VALUE__MODIFY(dst, src) \
31316 (dst) = ((dst) &\
31344 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__MODIFY(dst, src) \
31345 (dst) = ((dst) &\
31375 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MODIFY(dst, src) \
31376 (dst) = ((dst) &\
31404 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__MODIFY(dst, src) \
31405 (dst) = ((dst) &\
31435 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MODIFY(dst, src) \
31436 (dst) = ((dst) &\
31464 #define MAC_PCU_TSF_THRESHOLD__VALUE__MODIFY(dst, src) \
31465 (dst) = ((dst) &\
31495 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MODIFY(dst, src) \
31496 (dst) = ((dst) &\
31524 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__MODIFY(dst, src) \
31525 (dst) = ((dst) &\
31555 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MODIFY(dst, src) \
31556 (dst) = ((dst) &\
31586 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MODIFY(dst, src) \
31587 (dst) = ((dst) &\
31604 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MODIFY(dst, src) \
31605 (dst) = ((dst) &\
31611 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__SET(dst) \
31612 (dst) = ((dst) &\
31614 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__CLR(dst) \
31615 (dst) = ((dst) &\
31628 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MODIFY(dst, src) \
31629 (dst) = ((dst) &\
31635 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__SET(dst) \
31636 (dst) = ((dst) &\
31638 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__CLR(dst) \
31639 (dst) = ((dst) &\
31652 #define MAC_PCU_BLUETOOTH_MODE__MODE__MODIFY(dst, src) \
31653 (dst) = ((dst) &\
31670 #define MAC_PCU_BLUETOOTH_MODE__QUIET__MODIFY(dst, src) \
31671 (dst) = ((dst) &\
31677 #define MAC_PCU_BLUETOOTH_MODE__QUIET__SET(dst) \
31678 (dst) = ((dst) &\
31680 #define MAC_PCU_BLUETOOTH_MODE__QUIET__CLR(dst) \
31681 (dst) = ((dst) &\
31694 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MODIFY(dst, src) \
31695 (dst) = ((dst) &\
31712 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MODIFY(dst, src) \
31713 (dst) = ((dst) &\
31719 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__SET(dst) \
31720 (dst) = ((dst) &\
31722 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__CLR(dst) \
31723 (dst) = ((dst) &\
31736 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MODIFY(dst, src) \
31737 (dst) = ((dst) &\
31754 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MODIFY(dst, src) \
31755 (dst) = ((dst) &\
31785 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MODIFY(dst, src) \
31786 (dst) = ((dst) &\
31812 #define MAC_PCU_HCF_TIMEOUT__VALUE__MODIFY(dst, src) \
31813 (dst) = ((dst) &\
31843 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MODIFY(dst, src) \
31844 (dst) = ((dst) &\
31869 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MODIFY(dst, src) \
31870 (dst) = ((dst) &\
31876 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__SET(dst) \
31877 (dst) = ((dst) &\
31879 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__CLR(dst) \
31880 (dst) = ((dst) &\
31893 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MODIFY(dst, src) \
31894 (dst) = ((dst) &\
31900 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__SET(dst) \
31901 (dst) = ((dst) &\
31903 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__CLR(dst) \
31904 (dst) = ((dst) &\
31917 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MODIFY(dst, src) \
31918 (dst) = ((dst) &\
31924 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__SET(dst) \
31925 (dst) = ((dst) &\
31927 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__CLR(dst) \
31928 (dst) = ((dst) &\
31941 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MODIFY(dst, src) \
31942 (dst) = ((dst) &\
31948 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__SET(dst) \
31949 (dst) = ((dst) &\
31951 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__CLR(dst) \
31952 (dst) = ((dst) &\
31965 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MODIFY(dst, src) \
31966 (dst) = ((dst) &\
31972 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__SET(dst) \
31973 (dst) = ((dst) &\
31975 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__CLR(dst) \
31976 (dst) = ((dst) &\
31989 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MODIFY(dst, src) \
31990 (dst) = ((dst) &\
32007 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MODIFY(dst, src) \
32008 (dst) = ((dst) &\
32014 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__SET(dst) \
32015 (dst) = ((dst) &\
32017 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__CLR(dst) \
32018 (dst) = ((dst) &\
32031 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MODIFY(dst, src) \
32032 (dst) = ((dst) &\
32038 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__SET(dst) \
32039 (dst) = ((dst) &\
32041 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__CLR(dst) \
32042 (dst) = ((dst) &\
32055 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MODIFY(dst, src) \
32056 (dst) = ((dst) &\
32073 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MODIFY(dst, src) \
32074 (dst) = ((dst) &\
32091 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MODIFY(dst, src) \
32092 (dst) = ((dst) &\
32098 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__SET(dst) \
32099 (dst) = ((dst) &\
32101 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__CLR(dst) \
32102 (dst) = ((dst) &\
32115 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MODIFY(dst, src) \
32116 (dst) = ((dst) &\
32122 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__SET(dst) \
32123 (dst) = ((dst) &\
32125 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__CLR(dst) \
32126 (dst) = ((dst) &\
32150 #define MAC_PCU_GENERIC_TIMERS2__DATA__MODIFY(dst, src) \
32151 (dst) = ((dst) &\
32181 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MODIFY(dst, src) \
32182 (dst) = ((dst) &\
32220 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MODIFY(dst, src) \
32221 (dst) = ((dst) &\
32287 #define MAC_PCU_TXSIFS__SIFS_TIME__MODIFY(dst, src) \
32288 (dst) = ((dst) &\
32305 #define MAC_PCU_TXSIFS__TX_LATENCY__MODIFY(dst, src) \
32306 (dst) = ((dst) &\
32323 #define MAC_PCU_TXSIFS__ACK_SHIFT__MODIFY(dst, src) \
32324 (dst) = ((dst) &\
32354 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MODIFY(dst, src) \
32355 (dst) = ((dst) &\
32372 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MODIFY(dst, src) \
32373 (dst) = ((dst) &\
32390 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MODIFY(dst, src) \
32391 (dst) = ((dst) &\
32408 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MODIFY(dst, src) \
32409 (dst) = ((dst) &\
32415 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__SET(dst) \
32416 (dst) = ((dst) &\
32418 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__CLR(dst) \
32419 (dst) = ((dst) &\
32441 #define MAC_PCU_TXOP_X__VALUE__MODIFY(dst, src) \
32442 (dst) = ((dst) &\
32468 #define MAC_PCU_TXOP_0_3__VALUE_0__MODIFY(dst, src) \
32469 (dst) = ((dst) &\
32486 #define MAC_PCU_TXOP_0_3__VALUE_1__MODIFY(dst, src) \
32487 (dst) = ((dst) &\
32504 #define MAC_PCU_TXOP_0_3__VALUE_2__MODIFY(dst, src) \
32505 (dst) = ((dst) &\
32522 #define MAC_PCU_TXOP_0_3__VALUE_3__MODIFY(dst, src) \
32523 (dst) = ((dst) &\
32549 #define MAC_PCU_TXOP_4_7__VALUE_4__MODIFY(dst, src) \
32550 (dst) = ((dst) &\
32567 #define MAC_PCU_TXOP_4_7__VALUE_5__MODIFY(dst, src) \
32568 (dst) = ((dst) &\
32585 #define MAC_PCU_TXOP_4_7__VALUE_6__MODIFY(dst, src) \
32586 (dst) = ((dst) &\
32603 #define MAC_PCU_TXOP_4_7__VALUE_7__MODIFY(dst, src) \
32604 (dst) = ((dst) &\
32630 #define MAC_PCU_TXOP_8_11__VALUE_8__MODIFY(dst, src) \
32631 (dst) = ((dst) &\
32648 #define MAC_PCU_TXOP_8_11__VALUE_9__MODIFY(dst, src) \
32649 (dst) = ((dst) &\
32666 #define MAC_PCU_TXOP_8_11__VALUE_10__MODIFY(dst, src) \
32667 (dst) = ((dst) &\
32684 #define MAC_PCU_TXOP_8_11__VALUE_11__MODIFY(dst, src) \
32685 (dst) = ((dst) &\
32713 #define MAC_PCU_TXOP_12_15__VALUE_12__MODIFY(dst, src) \
32714 (dst) = ((dst) &\
32731 #define MAC_PCU_TXOP_12_15__VALUE_13__MODIFY(dst, src) \
32732 (dst) = ((dst) &\
32749 #define MAC_PCU_TXOP_12_15__VALUE_14__MODIFY(dst, src) \
32750 (dst) = ((dst) &\
32767 #define MAC_PCU_TXOP_12_15__VALUE_15__MODIFY(dst, src) \
32768 (dst) = ((dst) &\
32796 #define MAC_PCU_GENERIC_TIMERS__DATA__MODIFY(dst, src) \
32797 (dst) = ((dst) &\
32827 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MODIFY(dst, src) \
32828 (dst) = ((dst) &\
32853 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MODIFY(dst, src) \
32854 (dst) = ((dst) &\
32884 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MODIFY(dst, src) \
32885 (dst) = ((dst) &\
32902 #define MAC_PCU_SLP32_MODE__ENABLE__MODIFY(dst, src) \
32903 (dst) = ((dst) &\
32909 #define MAC_PCU_SLP32_MODE__ENABLE__SET(dst) \
32910 (dst) = ((dst) &\
32912 #define MAC_PCU_SLP32_MODE__ENABLE__CLR(dst) \
32913 (dst) = ((dst) &\
32923 #define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__SET(dst) \
32924 (dst) = ((dst) &\
32926 #define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__CLR(dst) \
32927 (dst) = ((dst) &\
32940 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MODIFY(dst, src) \
32941 (dst) = ((dst) &\
32947 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__SET(dst) \
32948 (dst) = ((dst) &\
32950 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__CLR(dst) \
32951 (dst) = ((dst) &\
32964 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MODIFY(dst, src) \
32965 (dst) = ((dst) &\
32971 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__SET(dst) \
32972 (dst) = ((dst) &\
32974 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__CLR(dst) \
32975 (dst) = ((dst) &\
32985 #define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__SET(dst) \
32986 (dst) = ((dst) &\
32988 #define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__CLR(dst) \
32989 (dst) = ((dst) &\
33013 #define MAC_PCU_SLP32_WAKE__XTL_TIME__MODIFY(dst, src) \
33014 (dst) = ((dst) &\
33040 #define MAC_PCU_SLP32_INC__TSF_INC__MODIFY(dst, src) \
33041 (dst) = ((dst) &\
33069 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__MODIFY(dst, src) \
33070 (dst) = ((dst) &\
33098 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__MODIFY(dst, src) \
33099 (dst) = ((dst) &\
33125 #define MAC_PCU_SLP_MIB3__CLR_CNT__MODIFY(dst, src) \
33126 (dst) = ((dst) &\
33132 #define MAC_PCU_SLP_MIB3__CLR_CNT__SET(dst) \
33133 (dst) = ((dst) &\
33135 #define MAC_PCU_SLP_MIB3__CLR_CNT__CLR(dst) \
33136 (dst) = ((dst) &\
33146 #define MAC_PCU_SLP_MIB3__PENDING__SET(dst) \
33147 (dst) = ((dst) &\
33149 #define MAC_PCU_SLP_MIB3__PENDING__CLR(dst) \
33150 (dst) = ((dst) &\
33174 #define MAC_PCU_WOW1__PATTERN_ENABLE__MODIFY(dst, src) \
33175 (dst) = ((dst) &\
33200 #define MAC_PCU_WOW1__MAGIC_ENABLE__MODIFY(dst, src) \
33201 (dst) = ((dst) &\
33207 #define MAC_PCU_WOW1__MAGIC_ENABLE__SET(dst) \
33208 (dst) = ((dst) &\
33210 #define MAC_PCU_WOW1__MAGIC_ENABLE__CLR(dst) \
33211 (dst) = ((dst) &\
33221 #define MAC_PCU_WOW1__MAGIC_DETECT__SET(dst) \
33222 (dst) = ((dst) &\
33224 #define MAC_PCU_WOW1__MAGIC_DETECT__CLR(dst) \
33225 (dst) = ((dst) &\
33238 #define MAC_PCU_WOW1__INTR_ENABLE__MODIFY(dst, src) \
33239 (dst) = ((dst) &\
33245 #define MAC_PCU_WOW1__INTR_ENABLE__SET(dst) \
33246 (dst) = ((dst) &\
33248 #define MAC_PCU_WOW1__INTR_ENABLE__CLR(dst) \
33249 (dst) = ((dst) &\
33259 #define MAC_PCU_WOW1__INTR_DETECT__SET(dst) \
33260 (dst) = ((dst) &\
33262 #define MAC_PCU_WOW1__INTR_DETECT__CLR(dst) \
33263 (dst) = ((dst) &\
33273 #define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__SET(dst) \
33274 (dst) = ((dst) &\
33276 #define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__CLR(dst) \
33277 (dst) = ((dst) &\
33287 #define MAC_PCU_WOW1__BEACON_FAIL__SET(dst) \
33288 (dst) = ((dst) &\
33290 #define MAC_PCU_WOW1__BEACON_FAIL__CLR(dst) \
33291 (dst) = ((dst) &\
33304 #define MAC_PCU_WOW1__CW_BITS__MODIFY(dst, src) \
33305 (dst) = ((dst) &\
33331 #define MAC_PCU_WOW2__AIFS__MODIFY(dst, src) \
33332 (dst) = ((dst) &\
33343 #define MAC_PCU_WOW2__SLOT__MODIFY(dst, src) \
33344 (dst) = ((dst) &\
33361 #define MAC_PCU_WOW2__TRY_CNT__MODIFY(dst, src) \
33362 (dst) = ((dst) &\
33390 #define MAC_PCU_LOGIC_ANALYZER__HOLD__MODIFY(dst, src) \
33391 (dst) = ((dst) &\
33397 #define MAC_PCU_LOGIC_ANALYZER__HOLD__SET(dst) \
33398 (dst) = ((dst) &\
33400 #define MAC_PCU_LOGIC_ANALYZER__HOLD__CLR(dst) \
33401 (dst) = ((dst) &\
33414 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__MODIFY(dst, src) \
33415 (dst) = ((dst) &\
33421 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__SET(dst) \
33422 (dst) = ((dst) &\
33424 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__CLR(dst) \
33425 (dst) = ((dst) &\
33435 #define MAC_PCU_LOGIC_ANALYZER__STATE__SET(dst) \
33436 (dst) = ((dst) &\
33438 #define MAC_PCU_LOGIC_ANALYZER__STATE__CLR(dst) \
33439 (dst) = ((dst) &\
33452 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__MODIFY(dst, src) \
33453 (dst) = ((dst) &\
33459 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__SET(dst) \
33460 (dst) = ((dst) &\
33462 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__CLR(dst) \
33463 (dst) = ((dst) &\
33476 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MODIFY(dst, src) \
33477 (dst) = ((dst) &\
33502 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MODIFY(dst, src) \
33503 (dst) = ((dst) &\
33533 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MODIFY(dst, src) \
33534 (dst) = ((dst) &\
33564 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MODIFY(dst, src) \
33565 (dst) = ((dst) &\
33595 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MODIFY(dst, src) \
33596 (dst) = ((dst) &\
33602 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__SET(dst) \
33603 (dst) = ((dst) &\
33605 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__CLR(dst) \
33606 (dst) = ((dst) &\
33630 #define MAC_PCU_WOW3_BEACON__TIMEOUT__MODIFY(dst, src) \
33631 (dst) = ((dst) &\
33661 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MODIFY(dst, src) \
33662 (dst) = ((dst) &\
33690 #define MAC_PCU_WOW_KA__AUTO_DISABLE__MODIFY(dst, src) \
33691 (dst) = ((dst) &\
33697 #define MAC_PCU_WOW_KA__AUTO_DISABLE__SET(dst) \
33698 (dst) = ((dst) &\
33700 #define MAC_PCU_WOW_KA__AUTO_DISABLE__CLR(dst) \
33701 (dst) = ((dst) &\
33714 #define MAC_PCU_WOW_KA__FAIL_DISABLE__MODIFY(dst, src) \
33715 (dst) = ((dst) &\
33721 #define MAC_PCU_WOW_KA__FAIL_DISABLE__SET(dst) \
33722 (dst) = ((dst) &\
33724 #define MAC_PCU_WOW_KA__FAIL_DISABLE__CLR(dst) \
33725 (dst) = ((dst) &\
33738 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MODIFY(dst, src) \
33739 (dst) = ((dst) &\
33745 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__SET(dst) \
33746 (dst) = ((dst) &\
33748 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__CLR(dst) \
33749 (dst) = ((dst) &\
33771 #define PCU_1US__SCALER__MODIFY(dst, src) \
33772 (dst) = ((dst) &\
33796 #define PCU_KA__DEL__MODIFY(dst, src) \
33797 (dst) = ((dst) &\
33821 #define WOW_EXACT__LENGTH__MODIFY(dst, src) \
33822 (dst) = ((dst) &\
33833 #define WOW_EXACT__OFFSET__MODIFY(dst, src) \
33834 (dst) = ((dst) &\
33860 #define PCU_WOW4__OFFSET0__MODIFY(dst, src) \
33861 (dst) = ((dst) &\
33872 #define PCU_WOW4__OFFSET1__MODIFY(dst, src) \
33873 (dst) = ((dst) &\
33886 #define PCU_WOW4__OFFSET2__MODIFY(dst, src) \
33887 (dst) = ((dst) &\
33900 #define PCU_WOW4__OFFSET3__MODIFY(dst, src) \
33901 (dst) = ((dst) &\
33927 #define PCU_WOW5__OFFSET4__MODIFY(dst, src) \
33928 (dst) = ((dst) &\
33939 #define PCU_WOW5__OFFSET5__MODIFY(dst, src) \
33940 (dst) = ((dst) &\
33953 #define PCU_WOW5__OFFSET6__MODIFY(dst, src) \
33954 (dst) = ((dst) &\
33967 #define PCU_WOW5__OFFSET7__MODIFY(dst, src) \
33968 (dst) = ((dst) &\
33998 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MODIFY(dst, src) \
33999 (dst) = ((dst) &\
34016 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MODIFY(dst, src) \
34017 (dst) = ((dst) &\
34034 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MODIFY(dst, src) \
34035 (dst) = ((dst) &\
34065 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MODIFY(dst, src) \
34066 (dst) = ((dst) &\
34072 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__SET(dst) \
34073 (dst) = ((dst) &\
34075 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__CLR(dst) \
34076 (dst) = ((dst) &\
34089 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MODIFY(dst, src) \
34090 (dst) = ((dst) &\
34096 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__SET(dst) \
34097 (dst) = ((dst) &\
34099 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__CLR(dst) \
34100 (dst) = ((dst) &\
34113 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MODIFY(dst, src) \
34114 (dst) = ((dst) &\
34120 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__SET(dst) \
34121 (dst) = ((dst) &\
34123 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__CLR(dst) \
34124 (dst) = ((dst) &\
34137 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MODIFY(dst, src) \
34138 (dst) = ((dst) &\
34144 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__SET(dst) \
34145 (dst) = ((dst) &\
34147 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__CLR(dst) \
34148 (dst) = ((dst) &\
34161 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__MODIFY(dst, src) \
34162 (dst) = ((dst) &\
34168 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__SET(dst) \
34169 (dst) = ((dst) &\
34171 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__CLR(dst) \
34172 (dst) = ((dst) &\
34185 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MODIFY(dst, src) \
34186 (dst) = ((dst) &\
34192 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__SET(dst) \
34193 (dst) = ((dst) &\
34195 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__CLR(dst) \
34196 (dst) = ((dst) &\
34209 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MODIFY(dst, src) \
34210 (dst) = ((dst) &\
34216 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__SET(dst) \
34217 (dst) = ((dst) &\
34219 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__CLR(dst) \
34220 (dst) = ((dst) &\
34233 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MODIFY(dst, src) \
34234 (dst) = ((dst) &\
34240 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__SET(dst) \
34241 (dst) = ((dst) &\
34243 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__CLR(dst) \
34244 (dst) = ((dst) &\
34257 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MODIFY(dst, src) \
34258 (dst) = ((dst) &\
34264 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__SET(dst) \
34265 (dst) = ((dst) &\
34267 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__CLR(dst) \
34268 (dst) = ((dst) &\
34281 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MODIFY(dst, src) \
34282 (dst) = ((dst) &\
34288 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__SET(dst) \
34289 (dst) = ((dst) &\
34291 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__CLR(dst) \
34292 (dst) = ((dst) &\
34318 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MODIFY(dst, src) \
34319 (dst) = ((dst) &\
34349 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MODIFY(dst, src) \
34350 (dst) = ((dst) &\
34356 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__SET(dst) \
34357 (dst) = ((dst) &\
34359 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__CLR(dst) \
34360 (dst) = ((dst) &\
34373 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MODIFY(dst, src) \
34374 (dst) = ((dst) &\
34380 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__SET(dst) \
34381 (dst) = ((dst) &\
34383 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__CLR(dst) \
34384 (dst) = ((dst) &\
34397 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MODIFY(dst, src) \
34398 (dst) = ((dst) &\
34404 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__SET(dst) \
34405 (dst) = ((dst) &\
34407 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__CLR(dst) \
34408 (dst) = ((dst) &\
34421 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MODIFY(dst, src) \
34422 (dst) = ((dst) &\
34428 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__SET(dst) \
34429 (dst) = ((dst) &\
34431 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__CLR(dst) \
34432 (dst) = ((dst) &\
34445 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__MODIFY(dst, src) \
34446 (dst) = ((dst) &\
34474 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__MODIFY(dst, src) \
34475 (dst) = ((dst) &\
34492 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MODIFY(dst, src) \
34493 (dst) = ((dst) &\
34499 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__SET(dst) \
34500 (dst) = ((dst) &\
34502 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__CLR(dst) \
34503 (dst) = ((dst) &\
34516 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MODIFY(dst, src) \
34517 (dst) = ((dst) &\
34523 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__SET(dst) \
34524 (dst) = ((dst) &\
34526 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__CLR(dst) \
34527 (dst) = ((dst) &\
34540 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MODIFY(dst, src) \
34541 (dst) = ((dst) &\
34547 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__SET(dst) \
34548 (dst) = ((dst) &\
34550 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__CLR(dst) \
34551 (dst) = ((dst) &\
34564 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MODIFY(dst, src) \
34565 (dst) = ((dst) &\
34571 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__SET(dst) \
34572 (dst) = ((dst) &\
34574 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__CLR(dst) \
34575 (dst) = ((dst) &\
34601 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MODIFY(dst, src) \
34602 (dst) = ((dst) &\
34632 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MODIFY(dst, src) \
34633 (dst) = ((dst) &\
34663 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MODIFY(dst, src) \
34664 (dst) = ((dst) &\
34681 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MODIFY(dst, src) \
34682 (dst) = ((dst) &\
34699 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MODIFY(dst, src) \
34700 (dst) = ((dst) &\
34706 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__SET(dst) \
34707 (dst) = ((dst) &\
34709 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__CLR(dst) \
34710 (dst) = ((dst) &\
34723 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MODIFY(dst, src) \
34724 (dst) = ((dst) &\
34730 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__SET(dst) \
34731 (dst) = ((dst) &\
34733 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__CLR(dst) \
34734 (dst) = ((dst) &\
34747 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MODIFY(dst, src) \
34748 (dst) = ((dst) &\
34754 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__SET(dst) \
34755 (dst) = ((dst) &\
34757 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__CLR(dst) \
34758 (dst) = ((dst) &\
34771 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MODIFY(dst, src) \
34772 (dst) = ((dst) &\
34778 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__SET(dst) \
34779 (dst) = ((dst) &\
34781 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__CLR(dst) \
34782 (dst) = ((dst) &\
34795 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MODIFY(dst, src) \
34796 (dst) = ((dst) &\
34802 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__SET(dst) \
34803 (dst) = ((dst) &\
34805 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__CLR(dst) \
34806 (dst) = ((dst) &\
34832 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MODIFY(dst, src) \
34833 (dst) = ((dst) &\
34850 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MODIFY(dst, src) \
34851 (dst) = ((dst) &\
34881 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MODIFY(dst, src) \
34882 (dst) = ((dst) &\
34899 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MODIFY(dst, src) \
34900 (dst) = ((dst) &\
34926 #define MAC_PCU_TX_TIMER__TX_TIMER__MODIFY(dst, src) \
34927 (dst) = ((dst) &\
34944 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MODIFY(dst, src) \
34945 (dst) = ((dst) &\
34951 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__SET(dst) \
34952 (dst) = ((dst) &\
34954 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__CLR(dst) \
34955 (dst) = ((dst) &\
34968 #define MAC_PCU_TX_TIMER__RIFS_TIMER__MODIFY(dst, src) \
34969 (dst) = ((dst) &\
34986 #define MAC_PCU_TX_TIMER__QUIET_TIMER__MODIFY(dst, src) \
34987 (dst) = ((dst) &\
35004 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MODIFY(dst, src) \
35005 (dst) = ((dst) &\
35011 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__SET(dst) \
35012 (dst) = ((dst) &\
35014 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__CLR(dst) \
35015 (dst) = ((dst) &\
35041 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MODIFY(dst, src) \
35042 (dst) = ((dst) &\
35059 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MODIFY(dst, src) \
35060 (dst) = ((dst) &\
35066 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__SET(dst) \
35067 (dst) = ((dst) &\
35069 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__CLR(dst) \
35070 (dst) = ((dst) &\
35096 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MODIFY(dst, src) \
35097 (dst) = ((dst) &\
35103 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__SET(dst) \
35104 (dst) = ((dst) &\
35106 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__CLR(dst) \
35107 (dst) = ((dst) &\
35120 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MODIFY(dst, src) \
35121 (dst) = ((dst) &\
35127 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__SET(dst) \
35128 (dst) = ((dst) &\
35130 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__CLR(dst) \
35131 (dst) = ((dst) &\
35144 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MODIFY(dst, src) \
35145 (dst) = ((dst) &\
35151 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__SET(dst) \
35152 (dst) = ((dst) &\
35154 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__CLR(dst) \
35155 (dst) = ((dst) &\
35168 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MODIFY(dst, src) \
35169 (dst) = ((dst) &\
35175 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__SET(dst) \
35176 (dst) = ((dst) &\
35178 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__CLR(dst) \
35179 (dst) = ((dst) &\
35192 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MODIFY(dst, src) \
35193 (dst) = ((dst) &\
35199 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__SET(dst) \
35200 (dst) = ((dst) &\
35202 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__CLR(dst) \
35203 (dst) = ((dst) &\
35216 #define MAC_PCU_MISC_MODE2__RESERVED_0__MODIFY(dst, src) \
35217 (dst) = ((dst) &\
35223 #define MAC_PCU_MISC_MODE2__RESERVED_0__SET(dst) \
35224 (dst) = ((dst) &\
35226 #define MAC_PCU_MISC_MODE2__RESERVED_0__CLR(dst) \
35227 (dst) = ((dst) &\
35240 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MODIFY(dst, src) \
35241 (dst) = ((dst) &\
35247 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__SET(dst) \
35248 (dst) = ((dst) &\
35250 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__CLR(dst) \
35251 (dst) = ((dst) &\
35264 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__MODIFY(dst, src) \
35265 (dst) = ((dst) &\
35271 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__SET(dst) \
35272 (dst) = ((dst) &\
35274 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__CLR(dst) \
35275 (dst) = ((dst) &\
35288 #define MAC_PCU_MISC_MODE2__MGMT_QOS__MODIFY(dst, src) \
35289 (dst) = ((dst) &\
35306 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MODIFY(dst, src) \
35307 (dst) = ((dst) &\
35313 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__SET(dst) \
35314 (dst) = ((dst) &\
35316 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__CLR(dst) \
35317 (dst) = ((dst) &\
35330 #define MAC_PCU_MISC_MODE2__AGG_WEP__MODIFY(dst, src) \
35331 (dst) = ((dst) &\
35337 #define MAC_PCU_MISC_MODE2__AGG_WEP__SET(dst) \
35338 (dst) = ((dst) &\
35340 #define MAC_PCU_MISC_MODE2__AGG_WEP__CLR(dst) \
35341 (dst) = ((dst) &\
35354 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MODIFY(dst, src) \
35355 (dst) = ((dst) &\
35361 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__SET(dst) \
35362 (dst) = ((dst) &\
35364 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__CLR(dst) \
35365 (dst) = ((dst) &\
35378 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MODIFY(dst, src) \
35379 (dst) = ((dst) &\
35385 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__SET(dst) \
35386 (dst) = ((dst) &\
35388 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__CLR(dst) \
35389 (dst) = ((dst) &\
35402 #define MAC_PCU_MISC_MODE2__BUG_28676__MODIFY(dst, src) \
35403 (dst) = ((dst) &\
35409 #define MAC_PCU_MISC_MODE2__BUG_28676__SET(dst) \
35410 (dst) = ((dst) &\
35412 #define MAC_PCU_MISC_MODE2__BUG_28676__CLR(dst) \
35413 (dst) = ((dst) &\
35426 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MODIFY(dst, src) \
35427 (dst) = ((dst) &\
35433 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__SET(dst) \
35434 (dst) = ((dst) &\
35436 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__CLR(dst) \
35437 (dst) = ((dst) &\
35450 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MODIFY(dst, src) \
35451 (dst) = ((dst) &\
35457 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__SET(dst) \
35458 (dst) = ((dst) &\
35460 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__CLR(dst) \
35461 (dst) = ((dst) &\
35474 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MODIFY(dst, src) \
35475 (dst) = ((dst) &\
35481 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__SET(dst) \
35482 (dst) = ((dst) &\
35484 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__CLR(dst) \
35485 (dst) = ((dst) &\
35498 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MODIFY(dst, src) \
35499 (dst) = ((dst) &\
35505 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__SET(dst) \
35506 (dst) = ((dst) &\
35508 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__CLR(dst) \
35509 (dst) = ((dst) &\
35522 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MODIFY(dst, src) \
35523 (dst) = ((dst) &\
35529 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__SET(dst) \
35530 (dst) = ((dst) &\
35532 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__CLR(dst) \
35533 (dst) = ((dst) &\
35546 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MODIFY(dst, src) \
35547 (dst) = ((dst) &\
35553 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__SET(dst) \
35554 (dst) = ((dst) &\
35556 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__CLR(dst) \
35557 (dst) = ((dst) &\
35570 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MODIFY(dst, src) \
35571 (dst) = ((dst) &\
35577 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__SET(dst) \
35578 (dst) = ((dst) &\
35580 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__CLR(dst) \
35581 (dst) = ((dst) &\
35594 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MODIFY(dst, src) \
35595 (dst) = ((dst) &\
35601 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__SET(dst) \
35602 (dst) = ((dst) &\
35604 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__CLR(dst) \
35605 (dst) = ((dst) &\
35618 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MODIFY(dst, src) \
35619 (dst) = ((dst) &\
35625 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__SET(dst) \
35626 (dst) = ((dst) &\
35628 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__CLR(dst) \
35629 (dst) = ((dst) &\
35642 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MODIFY(dst, src) \
35643 (dst) = ((dst) &\
35649 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__SET(dst) \
35650 (dst) = ((dst) &\
35652 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__CLR(dst) \
35653 (dst) = ((dst) &\
35666 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MODIFY(dst, src) \
35667 (dst) = ((dst) &\
35673 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__SET(dst) \
35674 (dst) = ((dst) &\
35676 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__CLR(dst) \
35677 (dst) = ((dst) &\
35703 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MODIFY(dst, src) \
35704 (dst) = ((dst) &\
35750 #define ASYNC_FIFO_REG1__DBG__MODIFY(dst, src) \
35751 (dst) = ((dst) &\
35777 #define ASYNC_FIFO_REG2__DBG__MODIFY(dst, src) \
35778 (dst) = ((dst) &\
35804 #define ASYNC_FIFO_REG3__DBG__MODIFY(dst, src) \
35805 (dst) = ((dst) &\
35822 #define ASYNC_FIFO_REG3__DATAPATH_SEL__MODIFY(dst, src) \
35823 (dst) = ((dst) &\
35829 #define ASYNC_FIFO_REG3__DATAPATH_SEL__SET(dst) \
35830 (dst) = ((dst) &\
35832 #define ASYNC_FIFO_REG3__DATAPATH_SEL__CLR(dst) \
35833 (dst) = ((dst) &\
35846 #define ASYNC_FIFO_REG3__SFT_RST_N__MODIFY(dst, src) \
35847 (dst) = ((dst) &\
35853 #define ASYNC_FIFO_REG3__SFT_RST_N__SET(dst) \
35854 (dst) = ((dst) &\
35856 #define ASYNC_FIFO_REG3__SFT_RST_N__CLR(dst) \
35857 (dst) = ((dst) &\
35881 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__MODIFY(dst, src) \
35882 (dst) = ((dst) &\
35912 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__MODIFY(dst, src) \
35913 (dst) = ((dst) &\
35930 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__MODIFY(dst, src) \
35931 (dst) = ((dst) &\
35948 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__MODIFY(dst, src) \
35949 (dst) = ((dst) &\
35966 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__MODIFY(dst, src) \
35967 (dst) = ((dst) &\
35997 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__MODIFY(dst, src) \
35998 (dst) = ((dst) &\
36015 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__MODIFY(dst, src) \
36016 (dst) = ((dst) &\
36033 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__MODIFY(dst, src) \
36034 (dst) = ((dst) &\
36051 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__MODIFY(dst, src) \
36052 (dst) = ((dst) &\
36082 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MODIFY(dst, src) \
36083 (dst) = ((dst) &\
36111 #define MAC_PCU_WOW4__PATTERN_ENABLE__MODIFY(dst, src) \
36112 (dst) = ((dst) &\
36146 #define WOW2_EXACT__LENGTH__MODIFY(dst, src) \
36147 (dst) = ((dst) &\
36158 #define WOW2_EXACT__OFFSET__MODIFY(dst, src) \
36159 (dst) = ((dst) &\
36185 #define PCU_WOW6__OFFSET8__MODIFY(dst, src) \
36186 (dst) = ((dst) &\
36197 #define PCU_WOW6__OFFSET9__MODIFY(dst, src) \
36198 (dst) = ((dst) &\
36211 #define PCU_WOW6__OFFSET10__MODIFY(dst, src) \
36212 (dst) = ((dst) &\
36225 #define PCU_WOW6__OFFSET11__MODIFY(dst, src) \
36226 (dst) = ((dst) &\
36252 #define PCU_WOW7__OFFSET12__MODIFY(dst, src) \
36253 (dst) = ((dst) &\
36264 #define PCU_WOW7__OFFSET13__MODIFY(dst, src) \
36265 (dst) = ((dst) &\
36278 #define PCU_WOW7__OFFSET14__MODIFY(dst, src) \
36279 (dst) = ((dst) &\
36292 #define PCU_WOW7__OFFSET15__MODIFY(dst, src) \
36293 (dst) = ((dst) &\
36323 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__MODIFY(dst, src) \
36324 (dst) = ((dst) &\
36341 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__MODIFY(dst, src) \
36342 (dst) = ((dst) &\
36359 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__MODIFY(dst, src) \
36360 (dst) = ((dst) &\
36377 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__MODIFY(dst, src) \
36378 (dst) = ((dst) &\
36408 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__MODIFY(dst, src) \
36409 (dst) = ((dst) &\
36426 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__MODIFY(dst, src) \
36427 (dst) = ((dst) &\
36444 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__MODIFY(dst, src) \
36445 (dst) = ((dst) &\
36462 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__MODIFY(dst, src) \
36463 (dst) = ((dst) &\
36493 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MODIFY(dst, src) \
36494 (dst) = ((dst) &\
36500 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__SET(dst) \
36501 (dst) = ((dst) &\
36503 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__CLR(dst) \
36504 (dst) = ((dst) &\
36530 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MODIFY(dst, src) \
36531 (dst) = ((dst) &\
36557 #define MAC_PCU_TSF2_L32__VALUE__MODIFY(dst, src) \
36558 (dst) = ((dst) &\
36584 #define MAC_PCU_TSF2_U32__VALUE__MODIFY(dst, src) \
36585 (dst) = ((dst) &\
36611 #define MAC_PCU_BSSID2_L32__ADDR__MODIFY(dst, src) \
36612 (dst) = ((dst) &\
36638 #define MAC_PCU_BSSID2_U16__ADDR__MODIFY(dst, src) \
36639 (dst) = ((dst) &\
36656 #define MAC_PCU_BSSID2_U16__ENABLE__MODIFY(dst, src) \
36657 (dst) = ((dst) &\
36663 #define MAC_PCU_BSSID2_U16__ENABLE__SET(dst) \
36664 (dst) = ((dst) &\
36666 #define MAC_PCU_BSSID2_U16__ENABLE__CLR(dst) \
36667 (dst) = ((dst) &\
36693 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MODIFY(dst, src) \
36694 (dst) = ((dst) &\
36700 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__SET(dst) \
36701 (dst) = ((dst) &\
36703 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__CLR(dst) \
36704 (dst) = ((dst) &\
36717 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MODIFY(dst, src) \
36718 (dst) = ((dst) &\
36724 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__SET(dst) \
36725 (dst) = ((dst) &\
36727 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__CLR(dst) \
36728 (dst) = ((dst) &\
36741 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MODIFY(dst, src) \
36742 (dst) = ((dst) &\
36748 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__SET(dst) \
36749 (dst) = ((dst) &\
36751 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__CLR(dst) \
36752 (dst) = ((dst) &\
36765 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MODIFY(dst, src) \
36766 (dst) = ((dst) &\
36772 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__SET(dst) \
36773 (dst) = ((dst) &\
36775 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__CLR(dst) \
36776 (dst) = ((dst) &\
36789 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MODIFY(dst, src) \
36790 (dst) = ((dst) &\
36796 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__SET(dst) \
36797 (dst) = ((dst) &\
36799 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__CLR(dst) \
36800 (dst) = ((dst) &\
36813 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MODIFY(dst, src) \
36814 (dst) = ((dst) &\
36820 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__SET(dst) \
36821 (dst) = ((dst) &\
36823 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__CLR(dst) \
36824 (dst) = ((dst) &\
36837 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MODIFY(dst, src) \
36838 (dst) = ((dst) &\
36844 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__SET(dst) \
36845 (dst) = ((dst) &\
36847 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__CLR(dst) \
36848 (dst) = ((dst) &\
36861 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MODIFY(dst, src) \
36862 (dst) = ((dst) &\
36868 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__SET(dst) \
36869 (dst) = ((dst) &\
36871 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__CLR(dst) \
36872 (dst) = ((dst) &\
36885 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MODIFY(dst, src) \
36886 (dst) = ((dst) &\
36892 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__SET(dst) \
36893 (dst) = ((dst) &\
36895 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__CLR(dst) \
36896 (dst) = ((dst) &\
36909 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MODIFY(dst, src) \
36910 (dst) = ((dst) &\
36916 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__SET(dst) \
36917 (dst) = ((dst) &\
36919 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__CLR(dst) \
36920 (dst) = ((dst) &\
36933 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MODIFY(dst, src) \
36934 (dst) = ((dst) &\
36940 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__SET(dst) \
36941 (dst) = ((dst) &\
36943 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__CLR(dst) \
36944 (dst) = ((dst) &\
36966 #define MAC_PCU_TID_TO_AC__DATA__MODIFY(dst, src) \
36967 (dst) = ((dst) &\
36993 #define MAC_PCU_HP_QUEUE__ENABLE__MODIFY(dst, src) \
36994 (dst) = ((dst) &\
37000 #define MAC_PCU_HP_QUEUE__ENABLE__SET(dst) \
37001 (dst) = ((dst) &\
37003 #define MAC_PCU_HP_QUEUE__ENABLE__CLR(dst) \
37004 (dst) = ((dst) &\
37017 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__MODIFY(dst, src) \
37018 (dst) = ((dst) &\
37024 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__SET(dst) \
37025 (dst) = ((dst) &\
37027 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__CLR(dst) \
37028 (dst) = ((dst) &\
37041 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__MODIFY(dst, src) \
37042 (dst) = ((dst) &\
37048 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__SET(dst) \
37049 (dst) = ((dst) &\
37051 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__CLR(dst) \
37052 (dst) = ((dst) &\
37065 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__MODIFY(dst, src) \
37066 (dst) = ((dst) &\
37072 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__SET(dst) \
37073 (dst) = ((dst) &\
37075 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__CLR(dst) \
37076 (dst) = ((dst) &\
37089 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__MODIFY(dst, src) \
37090 (dst) = ((dst) &\
37096 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__SET(dst) \
37097 (dst) = ((dst) &\
37099 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__CLR(dst) \
37100 (dst) = ((dst) &\
37113 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MODIFY(dst, src) \
37114 (dst) = ((dst) &\
37120 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__SET(dst) \
37121 (dst) = ((dst) &\
37123 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__CLR(dst) \
37124 (dst) = ((dst) &\
37137 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MODIFY(dst, src) \
37138 (dst) = ((dst) &\
37144 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__SET(dst) \
37145 (dst) = ((dst) &\
37147 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__CLR(dst) \
37148 (dst) = ((dst) &\
37161 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MODIFY(dst, src) \
37162 (dst) = ((dst) &\
37168 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__SET(dst) \
37169 (dst) = ((dst) &\
37171 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__CLR(dst) \
37172 (dst) = ((dst) &\
37185 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MODIFY(dst, src) \
37186 (dst) = ((dst) &\
37203 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MODIFY(dst, src) \
37204 (dst) = ((dst) &\
37221 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MODIFY(dst, src) \
37222 (dst) = ((dst) &\
37239 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MODIFY(dst, src) \
37240 (dst) = ((dst) &\
37257 #define MAC_PCU_HP_QUEUE__UAPSD_EN__MODIFY(dst, src) \
37258 (dst) = ((dst) &\
37264 #define MAC_PCU_HP_QUEUE__UAPSD_EN__SET(dst) \
37265 (dst) = ((dst) &\
37267 #define MAC_PCU_HP_QUEUE__UAPSD_EN__CLR(dst) \
37268 (dst) = ((dst) &\
37294 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MODIFY(dst, src) \
37295 (dst) = ((dst) &\
37325 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MODIFY(dst, src) \
37326 (dst) = ((dst) &\
37356 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MODIFY(dst, src) \
37357 (dst) = ((dst) &\
37387 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MODIFY(dst, src) \
37388 (dst) = ((dst) &\
37418 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MODIFY(dst, src) \
37419 (dst) = ((dst) &\
37449 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MODIFY(dst, src) \
37450 (dst) = ((dst) &\
37480 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MODIFY(dst, src) \
37481 (dst) = ((dst) &\
37511 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MODIFY(dst, src) \
37512 (dst) = ((dst) &\
37518 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__SET(dst) \
37519 (dst) = ((dst) &\
37521 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__CLR(dst) \
37522 (dst) = ((dst) &\
37535 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MODIFY(dst, src) \
37536 (dst) = ((dst) &\
37542 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__SET(dst) \
37543 (dst) = ((dst) &\
37545 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__CLR(dst) \
37546 (dst) = ((dst) &\
37559 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MODIFY(dst, src) \
37560 (dst) = ((dst) &\
37566 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__SET(dst) \
37567 (dst) = ((dst) &\
37569 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__CLR(dst) \
37570 (dst) = ((dst) &\
37583 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MODIFY(dst, src) \
37584 (dst) = ((dst) &\
37590 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__SET(dst) \
37591 (dst) = ((dst) &\
37593 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__CLR(dst) \
37594 (dst) = ((dst) &\
37607 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MODIFY(dst, src) \
37608 (dst) = ((dst) &\
37614 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__SET(dst) \
37615 (dst) = ((dst) &\
37617 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__CLR(dst) \
37618 (dst) = ((dst) &\
37631 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MODIFY(dst, src) \
37632 (dst) = ((dst) &\
37638 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__SET(dst) \
37639 (dst) = ((dst) &\
37641 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__CLR(dst) \
37642 (dst) = ((dst) &\
37655 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MODIFY(dst, src) \
37656 (dst) = ((dst) &\
37662 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__SET(dst) \
37663 (dst) = ((dst) &\
37665 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__CLR(dst) \
37666 (dst) = ((dst) &\
37679 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MODIFY(dst, src) \
37680 (dst) = ((dst) &\
37686 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__SET(dst) \
37687 (dst) = ((dst) &\
37689 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__CLR(dst) \
37690 (dst) = ((dst) &\
37703 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MODIFY(dst, src) \
37704 (dst) = ((dst) &\
37721 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MODIFY(dst, src) \
37722 (dst) = ((dst) &\
37739 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MODIFY(dst, src) \
37740 (dst) = ((dst) &\
37770 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MODIFY(dst, src) \
37771 (dst) = ((dst) &\
37777 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__SET(dst) \
37778 (dst) = ((dst) &\
37780 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__CLR(dst) \
37781 (dst) = ((dst) &\
37794 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MODIFY(dst, src) \
37795 (dst) = ((dst) &\
37801 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__SET(dst) \
37802 (dst) = ((dst) &\
37804 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__CLR(dst) \
37805 (dst) = ((dst) &\
37818 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MODIFY(dst, src) \
37819 (dst) = ((dst) &\
37825 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__SET(dst) \
37826 (dst) = ((dst) &\
37828 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__CLR(dst) \
37829 (dst) = ((dst) &\
37842 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MODIFY(dst, src) \
37843 (dst) = ((dst) &\
37860 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MODIFY(dst, src) \
37861 (dst) = ((dst) &\
37891 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MODIFY(dst, src) \
37892 (dst) = ((dst) &\
37898 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__SET(dst) \
37899 (dst) = ((dst) &\
37901 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__CLR(dst) \
37902 (dst) = ((dst) &\
37915 #define MAC_PCU_MISC_MODE3__AES_3STREAM__MODIFY(dst, src) \
37916 (dst) = ((dst) &\
37922 #define MAC_PCU_MISC_MODE3__AES_3STREAM__SET(dst) \
37923 (dst) = ((dst) &\
37925 #define MAC_PCU_MISC_MODE3__AES_3STREAM__CLR(dst) \
37926 (dst) = ((dst) &\
37939 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MODIFY(dst, src) \
37940 (dst) = ((dst) &\
37946 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__SET(dst) \
37947 (dst) = ((dst) &\
37949 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__CLR(dst) \
37950 (dst) = ((dst) &\
37963 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MODIFY(dst, src) \
37964 (dst) = ((dst) &\
37970 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__SET(dst) \
37971 (dst) = ((dst) &\
37973 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__CLR(dst) \
37974 (dst) = ((dst) &\
37987 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MODIFY(dst, src) \
37988 (dst) = ((dst) &\
37994 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__SET(dst) \
37995 (dst) = ((dst) &\
37997 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__CLR(dst) \
37998 (dst) = ((dst) &\
38011 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MODIFY(dst, src) \
38012 (dst) = ((dst) &\
38018 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__SET(dst) \
38019 (dst) = ((dst) &\
38021 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__CLR(dst) \
38022 (dst) = ((dst) &\
38035 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MODIFY(dst, src) \
38036 (dst) = ((dst) &\
38042 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__SET(dst) \
38043 (dst) = ((dst) &\
38045 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__CLR(dst) \
38046 (dst) = ((dst) &\
38059 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MODIFY(dst, src) \
38060 (dst) = ((dst) &\
38066 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__SET(dst) \
38067 (dst) = ((dst) &\
38069 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__CLR(dst) \
38070 (dst) = ((dst) &\
38083 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MODIFY(dst, src) \
38084 (dst) = ((dst) &\
38101 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MODIFY(dst, src) \
38102 (dst) = ((dst) &\
38108 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__SET(dst) \
38109 (dst) = ((dst) &\
38111 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__CLR(dst) \
38112 (dst) = ((dst) &\
38125 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MODIFY(dst, src) \
38126 (dst) = ((dst) &\
38132 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__SET(dst) \
38133 (dst) = ((dst) &\
38135 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__CLR(dst) \
38136 (dst) = ((dst) &\
38149 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MODIFY(dst, src) \
38150 (dst) = ((dst) &\
38156 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__SET(dst) \
38157 (dst) = ((dst) &\
38159 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__CLR(dst) \
38160 (dst) = ((dst) &\
38182 #define MAC_PCU_TXBUF_BA__DATA__MODIFY(dst, src) \
38183 (dst) = ((dst) &\
38209 #define MAC_PCU_KEY_CACHE__DATA__MODIFY(dst, src) \
38210 (dst) = ((dst) &\
38236 #define MAC_PCU_BUF__DATA__MODIFY(dst, src) \
38237 (dst) = ((dst) &\
38261 #define TIMING_CONTROLS_1__STE_THR__MODIFY(dst, src) \
38262 (dst) = ((dst) &\
38279 #define TIMING_CONTROLS_1__STE_TO_LONG1__MODIFY(dst, src) \
38280 (dst) = ((dst) &\
38297 #define TIMING_CONTROLS_1__TIMING_BACKOFF__MODIFY(dst, src) \
38298 (dst) = ((dst) &\
38315 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MODIFY(dst, src) \
38316 (dst) = ((dst) &\
38322 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__SET(dst) \
38323 (dst) = ((dst) &\
38325 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__CLR(dst) \
38326 (dst) = ((dst) &\
38339 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MODIFY(dst, src) \
38340 (dst) = ((dst) &\
38357 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MODIFY(dst, src) \
38358 (dst) = ((dst) &\
38375 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MODIFY(dst, src) \
38376 (dst) = ((dst) &\
38382 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__SET(dst) \
38383 (dst) = ((dst) &\
38385 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__CLR(dst) \
38386 (dst) = ((dst) &\
38399 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__MODIFY(dst, src) \
38400 (dst) = ((dst) &\
38406 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__SET(dst) \
38407 (dst) = ((dst) &\
38409 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__CLR(dst) \
38410 (dst) = ((dst) &\
38423 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MODIFY(dst, src) \
38424 (dst) = ((dst) &\
38430 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__SET(dst) \
38431 (dst) = ((dst) &\
38433 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__CLR(dst) \
38434 (dst) = ((dst) &\
38447 #define TIMING_CONTROLS_1__FALSE_ALARM__MODIFY(dst, src) \
38448 (dst) = ((dst) &\
38465 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MODIFY(dst, src) \
38466 (dst) = ((dst) &\
38472 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__SET(dst) \
38473 (dst) = ((dst) &\
38475 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__CLR(dst) \
38476 (dst) = ((dst) &\
38489 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MODIFY(dst, src) \
38490 (dst) = ((dst) &\
38496 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__SET(dst) \
38497 (dst) = ((dst) &\
38499 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__CLR(dst) \
38500 (dst) = ((dst) &\
38513 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MODIFY(dst, src) \
38514 (dst) = ((dst) &\
38531 #define TIMING_CONTROLS_1__FFT_SCALING__MODIFY(dst, src) \
38532 (dst) = ((dst) &\
38538 #define TIMING_CONTROLS_1__FFT_SCALING__SET(dst) \
38539 (dst) = ((dst) &\
38541 #define TIMING_CONTROLS_1__FFT_SCALING__CLR(dst) \
38542 (dst) = ((dst) &\
38568 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MODIFY(dst, src) \
38569 (dst) = ((dst) &\
38586 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MODIFY(dst, src) \
38587 (dst) = ((dst) &\
38593 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__SET(dst) \
38594 (dst) = ((dst) &\
38596 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__CLR(dst) \
38597 (dst) = ((dst) &\
38610 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MODIFY(dst, src) \
38611 (dst) = ((dst) &\
38617 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__SET(dst) \
38618 (dst) = ((dst) &\
38620 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__CLR(dst) \
38621 (dst) = ((dst) &\
38634 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MODIFY(dst, src) \
38635 (dst) = ((dst) &\
38641 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__SET(dst) \
38642 (dst) = ((dst) &\
38644 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__CLR(dst) \
38645 (dst) = ((dst) &\
38658 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MODIFY(dst, src) \
38659 (dst) = ((dst) &\
38665 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__SET(dst) \
38666 (dst) = ((dst) &\
38668 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__CLR(dst) \
38669 (dst) = ((dst) &\
38682 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MODIFY(dst, src) \
38683 (dst) = ((dst) &\
38700 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MODIFY(dst, src) \
38701 (dst) = ((dst) &\
38718 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MODIFY(dst, src) \
38719 (dst) = ((dst) &\
38725 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__SET(dst) \
38726 (dst) = ((dst) &\
38728 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__CLR(dst) \
38729 (dst) = ((dst) &\
38742 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MODIFY(dst, src) \
38743 (dst) = ((dst) &\
38749 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__SET(dst) \
38750 (dst) = ((dst) &\
38752 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__CLR(dst) \
38753 (dst) = ((dst) &\
38766 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MODIFY(dst, src) \
38767 (dst) = ((dst) &\
38773 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__SET(dst) \
38774 (dst) = ((dst) &\
38776 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__CLR(dst) \
38777 (dst) = ((dst) &\
38790 #define TIMING_CONTROLS_2__TRACEBACK128__MODIFY(dst, src) \
38791 (dst) = ((dst) &\
38797 #define TIMING_CONTROLS_2__TRACEBACK128__SET(dst) \
38798 (dst) = ((dst) &\
38800 #define TIMING_CONTROLS_2__TRACEBACK128__CLR(dst) \
38801 (dst) = ((dst) &\
38814 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MODIFY(dst, src) \
38815 (dst) = ((dst) &\
38821 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__SET(dst) \
38822 (dst) = ((dst) &\
38824 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__CLR(dst) \
38825 (dst) = ((dst) &\
38851 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MODIFY(dst, src) \
38852 (dst) = ((dst) &\
38869 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MODIFY(dst, src) \
38870 (dst) = ((dst) &\
38876 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__SET(dst) \
38877 (dst) = ((dst) &\
38879 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__CLR(dst) \
38880 (dst) = ((dst) &\
38893 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MODIFY(dst, src) \
38894 (dst) = ((dst) &\
38900 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__SET(dst) \
38901 (dst) = ((dst) &\
38903 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__CLR(dst) \
38904 (dst) = ((dst) &\
38917 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MODIFY(dst, src) \
38918 (dst) = ((dst) &\
38924 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__SET(dst) \
38925 (dst) = ((dst) &\
38927 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__CLR(dst) \
38928 (dst) = ((dst) &\
38941 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MODIFY(dst, src) \
38942 (dst) = ((dst) &\
38948 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__SET(dst) \
38949 (dst) = ((dst) &\
38951 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__CLR(dst) \
38952 (dst) = ((dst) &\
38965 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MODIFY(dst, src) \
38966 (dst) = ((dst) &\
38972 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__SET(dst) \
38973 (dst) = ((dst) &\
38975 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__CLR(dst) \
38976 (dst) = ((dst) &\
38989 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MODIFY(dst, src) \
38990 (dst) = ((dst) &\
39007 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MODIFY(dst, src) \
39008 (dst) = ((dst) &\
39038 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MODIFY(dst, src) \
39039 (dst) = ((dst) &\
39056 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MODIFY(dst, src) \
39057 (dst) = ((dst) &\
39063 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__SET(dst) \
39064 (dst) = ((dst) &\
39066 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__CLR(dst) \
39067 (dst) = ((dst) &\
39080 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MODIFY(dst, src) \
39081 (dst) = ((dst) &\
39098 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MODIFY(dst, src) \
39099 (dst) = ((dst) &\
39116 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MODIFY(dst, src) \
39117 (dst) = ((dst) &\
39123 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__SET(dst) \
39124 (dst) = ((dst) &\
39126 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__CLR(dst) \
39127 (dst) = ((dst) &\
39140 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MODIFY(dst, src) \
39141 (dst) = ((dst) &\
39147 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__SET(dst) \
39148 (dst) = ((dst) &\
39150 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__CLR(dst) \
39151 (dst) = ((dst) &\
39164 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MODIFY(dst, src) \
39165 (dst) = ((dst) &\
39171 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__SET(dst) \
39172 (dst) = ((dst) &\
39174 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__CLR(dst) \
39175 (dst) = ((dst) &\
39188 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MODIFY(dst, src) \
39189 (dst) = ((dst) &\
39195 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__SET(dst) \
39196 (dst) = ((dst) &\
39198 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__CLR(dst) \
39199 (dst) = ((dst) &\
39225 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MODIFY(dst, src) \
39226 (dst) = ((dst) &\
39232 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__SET(dst) \
39233 (dst) = ((dst) &\
39235 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__CLR(dst) \
39236 (dst) = ((dst) &\
39249 #define TIMING_CONTROL_5__CYCPWR_THR1__MODIFY(dst, src) \
39250 (dst) = ((dst) &\
39267 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MODIFY(dst, src) \
39268 (dst) = ((dst) &\
39274 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__SET(dst) \
39275 (dst) = ((dst) &\
39277 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__CLR(dst) \
39278 (dst) = ((dst) &\
39291 #define TIMING_CONTROL_5__RSSI_THR1A__MODIFY(dst, src) \
39292 (dst) = ((dst) &\
39309 #define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MODIFY(dst, src) \
39310 (dst) = ((dst) &\
39327 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MODIFY(dst, src) \
39328 (dst) = ((dst) &\
39334 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__SET(dst) \
39335 (dst) = ((dst) &\
39337 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__CLR(dst) \
39338 (dst) = ((dst) &\
39351 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MODIFY(dst, src) \
39352 (dst) = ((dst) &\
39358 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__SET(dst) \
39359 (dst) = ((dst) &\
39361 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__CLR(dst) \
39362 (dst) = ((dst) &\
39388 #define TIMING_CONTROL_6__HI_RSSI_THRESH__MODIFY(dst, src) \
39389 (dst) = ((dst) &\
39406 #define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MODIFY(dst, src) \
39407 (dst) = ((dst) &\
39424 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MODIFY(dst, src) \
39425 (dst) = ((dst) &\
39442 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MODIFY(dst, src) \
39443 (dst) = ((dst) &\
39460 #define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MODIFY(dst, src) \
39461 (dst) = ((dst) &\
39491 #define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MODIFY(dst, src) \
39492 (dst) = ((dst) &\
39509 #define TIMING_CONTROL_11__SPUR_FREQ_SD__MODIFY(dst, src) \
39510 (dst) = ((dst) &\
39527 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MODIFY(dst, src) \
39528 (dst) = ((dst) &\
39534 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__SET(dst) \
39535 (dst) = ((dst) &\
39537 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__CLR(dst) \
39538 (dst) = ((dst) &\
39551 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MODIFY(dst, src) \
39552 (dst) = ((dst) &\
39558 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__SET(dst) \
39559 (dst) = ((dst) &\
39561 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__CLR(dst) \
39562 (dst) = ((dst) &\
39588 #define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MODIFY(dst, src) \
39589 (dst) = ((dst) &\
39606 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MODIFY(dst, src) \
39607 (dst) = ((dst) &\
39613 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__SET(dst) \
39614 (dst) = ((dst) &\
39616 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__CLR(dst) \
39617 (dst) = ((dst) &\
39630 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MODIFY(dst, src) \
39631 (dst) = ((dst) &\
39637 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__SET(dst) \
39638 (dst) = ((dst) &\
39640 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__CLR(dst) \
39641 (dst) = ((dst) &\
39654 #define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MODIFY(dst, src) \
39655 (dst) = ((dst) &\
39672 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MODIFY(dst, src) \
39673 (dst) = ((dst) &\
39679 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__SET(dst) \
39680 (dst) = ((dst) &\
39682 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__CLR(dst) \
39683 (dst) = ((dst) &\
39707 #define FIND_SIGNAL_LOW__RELSTEP_LOW__MODIFY(dst, src) \
39708 (dst) = ((dst) &\
39725 #define FIND_SIGNAL_LOW__FIRSTEP_LOW__MODIFY(dst, src) \
39726 (dst) = ((dst) &\
39743 #define FIND_SIGNAL_LOW__FIRPWR_LOW__MODIFY(dst, src) \
39744 (dst) = ((dst) &\
39761 #define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MODIFY(dst, src) \
39762 (dst) = ((dst) &\
39779 #define FIND_SIGNAL_LOW__LONG_SC_THRESH__MODIFY(dst, src) \
39780 (dst) = ((dst) &\
39806 #define SFCORR__M2COUNT_THR__MODIFY(dst, src) \
39807 (dst) = ((dst) &\
39822 #define SFCORR__ADCSAT_THRESH__MODIFY(dst, src) \
39823 (dst) = ((dst) &\
39840 #define SFCORR__ADCSAT_ICOUNT__MODIFY(dst, src) \
39841 (dst) = ((dst) &\
39854 #define SFCORR__M1_THRES__MODIFY(dst, src) \
39855 (dst) = ((dst) &\
39868 #define SFCORR__M2_THRES__MODIFY(dst, src) \
39869 (dst) = ((dst) &\
39899 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__MODIFY(dst, src) \
39900 (dst) = ((dst) &\
39906 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__SET(dst) \
39907 (dst) = ((dst) &\
39909 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__CLR(dst) \
39910 (dst) = ((dst) &\
39923 #define SELF_CORR_LOW__M1COUNT_MAX_LOW__MODIFY(dst, src) \
39924 (dst) = ((dst) &\
39941 #define SELF_CORR_LOW__M2COUNT_THR_LOW__MODIFY(dst, src) \
39942 (dst) = ((dst) &\
39959 #define SELF_CORR_LOW__M1_THRESH_LOW__MODIFY(dst, src) \
39960 (dst) = ((dst) &\
39977 #define SELF_CORR_LOW__M2_THRESH_LOW__MODIFY(dst, src) \
39978 (dst) = ((dst) &\
40008 #define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MODIFY(dst, src) \
40009 (dst) = ((dst) &\
40026 #define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MODIFY(dst, src) \
40027 (dst) = ((dst) &\
40044 #define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MODIFY(dst, src) \
40045 (dst) = ((dst) &\
40062 #define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MODIFY(dst, src) \
40063 (dst) = ((dst) &\
40080 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MODIFY(dst, src) \
40081 (dst) = ((dst) &\
40087 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__SET(dst) \
40088 (dst) = ((dst) &\
40090 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__CLR(dst) \
40091 (dst) = ((dst) &\
40117 #define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MODIFY(dst, src) \
40118 (dst) = ((dst) &\
40135 #define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MODIFY(dst, src) \
40136 (dst) = ((dst) &\
40174 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__MODIFY(dst, src) \
40175 (dst) = ((dst) &\
40181 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__SET(dst) \
40182 (dst) = ((dst) &\
40184 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__CLR(dst) \
40185 (dst) = ((dst) &\
40198 #define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MODIFY(dst, src) \
40199 (dst) = ((dst) &\
40216 #define RADAR_DETECTION__PULSE_RSSI_THRESH__MODIFY(dst, src) \
40217 (dst) = ((dst) &\
40234 #define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MODIFY(dst, src) \
40235 (dst) = ((dst) &\
40252 #define RADAR_DETECTION__RADAR_RSSI_THRESH__MODIFY(dst, src) \
40253 (dst) = ((dst) &\
40270 #define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MODIFY(dst, src) \
40271 (dst) = ((dst) &\
40288 #define RADAR_DETECTION__ENABLE_RADAR_FFT__MODIFY(dst, src) \
40289 (dst) = ((dst) &\
40295 #define RADAR_DETECTION__ENABLE_RADAR_FFT__SET(dst) \
40296 (dst) = ((dst) &\
40298 #define RADAR_DETECTION__ENABLE_RADAR_FFT__CLR(dst) \
40299 (dst) = ((dst) &\
40325 #define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MODIFY(dst, src) \
40326 (dst) = ((dst) &\
40343 #define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MODIFY(dst, src) \
40344 (dst) = ((dst) &\
40361 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MODIFY(dst, src) \
40362 (dst) = ((dst) &\
40368 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__SET(dst) \
40369 (dst) = ((dst) &\
40371 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__CLR(dst) \
40372 (dst) = ((dst) &\
40385 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MODIFY(dst, src) \
40386 (dst) = ((dst) &\
40392 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__SET(dst) \
40393 (dst) = ((dst) &\
40395 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__CLR(dst) \
40396 (dst) = ((dst) &\
40409 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MODIFY(dst, src) \
40410 (dst) = ((dst) &\
40416 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__SET(dst) \
40417 (dst) = ((dst) &\
40419 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__CLR(dst) \
40420 (dst) = ((dst) &\
40433 #define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MODIFY(dst, src) \
40434 (dst) = ((dst) &\
40451 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MODIFY(dst, src) \
40452 (dst) = ((dst) &\
40458 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__SET(dst) \
40459 (dst) = ((dst) &\
40461 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__CLR(dst) \
40462 (dst) = ((dst) &\
40475 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MODIFY(dst, src) \
40476 (dst) = ((dst) &\
40482 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__SET(dst) \
40483 (dst) = ((dst) &\
40485 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__CLR(dst) \
40486 (dst) = ((dst) &\
40499 #define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MODIFY(dst, src) \
40500 (dst) = ((dst) &\
40517 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MODIFY(dst, src) \
40518 (dst) = ((dst) &\
40524 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__SET(dst) \
40525 (dst) = ((dst) &\
40527 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__CLR(dst) \
40528 (dst) = ((dst) &\
40554 #define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MODIFY(dst, src) \
40555 (dst) = ((dst) &\
40572 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__MODIFY(dst, src) \
40573 (dst) = ((dst) &\
40579 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__SET(dst) \
40580 (dst) = ((dst) &\
40582 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__CLR(dst) \
40583 (dst) = ((dst) &\
40596 #define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MODIFY(dst, src) \
40597 (dst) = ((dst) &\
40614 #define EXTENSION_RADAR__RADAR_LB_DC_CAP__MODIFY(dst, src) \
40615 (dst) = ((dst) &\
40632 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MODIFY(dst, src) \
40633 (dst) = ((dst) &\
40639 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__SET(dst) \
40640 (dst) = ((dst) &\
40642 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__CLR(dst) \
40643 (dst) = ((dst) &\
40669 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MODIFY(dst, src) \
40670 (dst) = ((dst) &\
40676 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__SET(dst) \
40677 (dst) = ((dst) &\
40679 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__CLR(dst) \
40680 (dst) = ((dst) &\
40693 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MODIFY(dst, src) \
40694 (dst) = ((dst) &\
40711 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__MODIFY(dst, src) \
40712 (dst) = ((dst) &\
40718 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__SET(dst) \
40719 (dst) = ((dst) &\
40721 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__CLR(dst) \
40722 (dst) = ((dst) &\
40735 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MODIFY(dst, src) \
40736 (dst) = ((dst) &\
40742 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__SET(dst) \
40743 (dst) = ((dst) &\
40745 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__CLR(dst) \
40746 (dst) = ((dst) &\
40759 #define MULTICHAIN_CONTROL__CF_SHORT_SAT__MODIFY(dst, src) \
40760 (dst) = ((dst) &\
40777 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MODIFY(dst, src) \
40778 (dst) = ((dst) &\
40795 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MODIFY(dst, src) \
40796 (dst) = ((dst) &\
40802 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__SET(dst) \
40803 (dst) = ((dst) &\
40805 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__CLR(dst) \
40806 (dst) = ((dst) &\
40832 #define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MODIFY(dst, src) \
40833 (dst) = ((dst) &\
40850 #define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MODIFY(dst, src) \
40851 (dst) = ((dst) &\
40868 #define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MODIFY(dst, src) \
40869 (dst) = ((dst) &\
40917 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MODIFY(dst, src) \
40918 (dst) = ((dst) &\
40935 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MODIFY(dst, src) \
40936 (dst) = ((dst) &\
41000 #define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MODIFY(dst, src) \
41001 (dst) = ((dst) &\
41018 #define TXIQCAL_CONTROL_3__PWR_LOW_DB__MODIFY(dst, src) \
41019 (dst) = ((dst) &\
41036 #define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MODIFY(dst, src) \
41037 (dst) = ((dst) &\
41054 #define TXIQCAL_CONTROL_3__DC_EST_LEN__MODIFY(dst, src) \
41055 (dst) = ((dst) &\
41072 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MODIFY(dst, src) \
41073 (dst) = ((dst) &\
41079 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__SET(dst) \
41080 (dst) = ((dst) &\
41082 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__CLR(dst) \
41083 (dst) = ((dst) &\
41096 #define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MODIFY(dst, src) \
41097 (dst) = ((dst) &\
41114 #define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MODIFY(dst, src) \
41115 (dst) = ((dst) &\
41132 #define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MODIFY(dst, src) \
41133 (dst) = ((dst) &\
41150 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MODIFY(dst, src) \
41151 (dst) = ((dst) &\
41157 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__SET(dst) \
41158 (dst) = ((dst) &\
41160 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__CLR(dst) \
41161 (dst) = ((dst) &\
41267 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MODIFY(dst, src) \
41268 (dst) = ((dst) &\
41274 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__SET(dst) \
41275 (dst) = ((dst) &\
41277 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__CLR(dst) \
41278 (dst) = ((dst) &\
41291 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MODIFY(dst, src) \
41292 (dst) = ((dst) &\
41309 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MODIFY(dst, src) \
41310 (dst) = ((dst) &\
41327 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MODIFY(dst, src) \
41328 (dst) = ((dst) &\
41358 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MODIFY(dst, src) \
41359 (dst) = ((dst) &\
41376 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MODIFY(dst, src) \
41377 (dst) = ((dst) &\
41394 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MODIFY(dst, src) \
41395 (dst) = ((dst) &\
41412 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MODIFY(dst, src) \
41413 (dst) = ((dst) &\
41430 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MODIFY(dst, src) \
41431 (dst) = ((dst) &\
41437 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__SET(dst) \
41438 (dst) = ((dst) &\
41440 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__CLR(dst) \
41441 (dst) = ((dst) &\
41454 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MODIFY(dst, src) \
41455 (dst) = ((dst) &\
41461 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__SET(dst) \
41462 (dst) = ((dst) &\
41464 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__CLR(dst) \
41465 (dst) = ((dst) &\
41491 #define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \
41492 (dst) = ((dst) &\
41509 #define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \
41510 (dst) = ((dst) &\
41527 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MODIFY(dst, src) \
41528 (dst) = ((dst) &\
41534 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__SET(dst) \
41535 (dst) = ((dst) &\
41537 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__CLR(dst) \
41538 (dst) = ((dst) &\
41551 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \
41552 (dst) = ((dst) &\
41569 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \
41570 (dst) = ((dst) &\
41587 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MODIFY(dst, src) \
41588 (dst) = ((dst) &\
41594 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__SET(dst) \
41595 (dst) = ((dst) &\
41597 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__CLR(dst) \
41598 (dst) = ((dst) &\
41624 #define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MODIFY(dst, src) \
41625 (dst) = ((dst) &\
41655 #define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MODIFY(dst, src) \
41656 (dst) = ((dst) &\
41686 #define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MODIFY(dst, src) \
41687 (dst) = ((dst) &\
41717 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MODIFY(dst, src) \
41718 (dst) = ((dst) &\
41724 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__SET(dst) \
41725 (dst) = ((dst) &\
41727 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__CLR(dst) \
41728 (dst) = ((dst) &\
41741 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MODIFY(dst, src) \
41742 (dst) = ((dst) &\
41748 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__SET(dst) \
41749 (dst) = ((dst) &\
41751 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__CLR(dst) \
41752 (dst) = ((dst) &\
41765 #define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MODIFY(dst, src) \
41766 (dst) = ((dst) &\
41783 #define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MODIFY(dst, src) \
41784 (dst) = ((dst) &\
41814 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MODIFY(dst, src) \
41815 (dst) = ((dst) &\
41821 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__SET(dst) \
41822 (dst) = ((dst) &\
41824 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__CLR(dst) \
41825 (dst) = ((dst) &\
41838 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MODIFY(dst, src) \
41839 (dst) = ((dst) &\
41845 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__SET(dst) \
41846 (dst) = ((dst) &\
41848 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__CLR(dst) \
41849 (dst) = ((dst) &\
41862 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MODIFY(dst, src) \
41863 (dst) = ((dst) &\
41869 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__SET(dst) \
41870 (dst) = ((dst) &\
41872 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__CLR(dst) \
41873 (dst) = ((dst) &\
41886 #define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MODIFY(dst, src) \
41887 (dst) = ((dst) &\
41904 #define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MODIFY(dst, src) \
41905 (dst) = ((dst) &\
41922 #define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MODIFY(dst, src) \
41923 (dst) = ((dst) &\
41940 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MODIFY(dst, src) \
41941 (dst) = ((dst) &\
41947 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__SET(dst) \
41948 (dst) = ((dst) &\
41950 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__CLR(dst) \
41951 (dst) = ((dst) &\
41973 #define PA_GAIN123_B0__PA_GAIN1_0__MODIFY(dst, src) \
41974 (dst) = ((dst) &\
41991 #define PA_GAIN123_B0__PA_GAIN2_0__MODIFY(dst, src) \
41992 (dst) = ((dst) &\
42009 #define PA_GAIN123_B0__PA_GAIN3_0__MODIFY(dst, src) \
42010 (dst) = ((dst) &\
42036 #define PA_GAIN45_B0__PA_GAIN4_0__MODIFY(dst, src) \
42037 (dst) = ((dst) &\
42054 #define PA_GAIN45_B0__PA_GAIN5_0__MODIFY(dst, src) \
42055 (dst) = ((dst) &\
42072 #define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MODIFY(dst, src) \
42073 (dst) = ((dst) &\
42103 #define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MODIFY(dst, src) \
42104 (dst) = ((dst) &\
42134 #define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MODIFY(dst, src) \
42135 (dst) = ((dst) &\
42165 #define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MODIFY(dst, src) \
42166 (dst) = ((dst) &\
42196 #define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MODIFY(dst, src) \
42197 (dst) = ((dst) &\
42227 #define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MODIFY(dst, src) \
42228 (dst) = ((dst) &\
42258 #define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MODIFY(dst, src) \
42259 (dst) = ((dst) &\
42289 #define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MODIFY(dst, src) \
42290 (dst) = ((dst) &\
42320 #define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MODIFY(dst, src) \
42321 (dst) = ((dst) &\
42347 #define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
42348 (dst) = ((dst) &\
42398 #define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MODIFY(dst, src) \
42399 (dst) = ((dst) &\
42416 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MODIFY(dst, src) \
42417 (dst) = ((dst) &\
42423 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__SET(dst) \
42424 (dst) = ((dst) &\
42426 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__CLR(dst) \
42427 (dst) = ((dst) &\
42451 #define LDPC_CNTL1__LDPC_LLR_SCALING0__MODIFY(dst, src) \
42452 (dst) = ((dst) &\
42480 #define LDPC_CNTL2__LDPC_LLR_SCALING1__MODIFY(dst, src) \
42481 (dst) = ((dst) &\
42498 #define LDPC_CNTL2__LDPC_LATENCY__MODIFY(dst, src) \
42499 (dst) = ((dst) &\
42529 #define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MODIFY(dst, src) \
42530 (dst) = ((dst) &\
42547 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MODIFY(dst, src) \
42548 (dst) = ((dst) &\
42565 #define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MODIFY(dst, src) \
42566 (dst) = ((dst) &\
42583 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MODIFY(dst, src) \
42584 (dst) = ((dst) &\
42614 #define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MODIFY(dst, src) \
42615 (dst) = ((dst) &\
42632 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MODIFY(dst, src) \
42633 (dst) = ((dst) &\
42650 #define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MODIFY(dst, src) \
42651 (dst) = ((dst) &\
42668 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MODIFY(dst, src) \
42669 (dst) = ((dst) &\
42699 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MODIFY(dst, src) \
42700 (dst) = ((dst) &\
42717 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MODIFY(dst, src) \
42718 (dst) = ((dst) &\
42748 #define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MODIFY(dst, src) \
42749 (dst) = ((dst) &\
42766 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MODIFY(dst, src) \
42767 (dst) = ((dst) &\
42784 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MODIFY(dst, src) \
42785 (dst) = ((dst) &\
42815 #define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MODIFY(dst, src) \
42816 (dst) = ((dst) &\
42872 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MODIFY(dst, src) \
42873 (dst) = ((dst) &\
42890 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MODIFY(dst, src) \
42891 (dst) = ((dst) &\
42908 #define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MODIFY(dst, src) \
42909 (dst) = ((dst) &\
42926 #define BBB_RX_CTRL_1__MAX_BAL_LONG__MODIFY(dst, src) \
42927 (dst) = ((dst) &\
42944 #define BBB_RX_CTRL_1__MAX_BAL_SHORT__MODIFY(dst, src) \
42945 (dst) = ((dst) &\
42962 #define BBB_RX_CTRL_1__RECON_LMS_STEP__MODIFY(dst, src) \
42963 (dst) = ((dst) &\
42980 #define BBB_RX_CTRL_1__SB_CHECK_WIN__MODIFY(dst, src) \
42981 (dst) = ((dst) &\
42998 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MODIFY(dst, src) \
42999 (dst) = ((dst) &\
43005 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__SET(dst) \
43006 (dst) = ((dst) &\
43008 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__CLR(dst) \
43009 (dst) = ((dst) &\
43035 #define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MODIFY(dst, src) \
43036 (dst) = ((dst) &\
43053 #define BBB_RX_CTRL_2__CHAN_AVG_LONG__MODIFY(dst, src) \
43054 (dst) = ((dst) &\
43071 #define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MODIFY(dst, src) \
43072 (dst) = ((dst) &\
43089 #define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MODIFY(dst, src) \
43090 (dst) = ((dst) &\
43107 #define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MODIFY(dst, src) \
43108 (dst) = ((dst) &\
43125 #define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MODIFY(dst, src) \
43126 (dst) = ((dst) &\
43156 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MODIFY(dst, src) \
43157 (dst) = ((dst) &\
43174 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MODIFY(dst, src) \
43175 (dst) = ((dst) &\
43192 #define BBB_RX_CTRL_3__TIMER_N_SFD__MODIFY(dst, src) \
43193 (dst) = ((dst) &\
43221 #define BBB_RX_CTRL_4__TIMER_N_SYNC__MODIFY(dst, src) \
43222 (dst) = ((dst) &\
43239 #define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MODIFY(dst, src) \
43240 (dst) = ((dst) &\
43257 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MODIFY(dst, src) \
43258 (dst) = ((dst) &\
43264 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__SET(dst) \
43265 (dst) = ((dst) &\
43267 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__CLR(dst) \
43268 (dst) = ((dst) &\
43281 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MODIFY(dst, src) \
43282 (dst) = ((dst) &\
43288 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__SET(dst) \
43289 (dst) = ((dst) &\
43291 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__CLR(dst) \
43292 (dst) = ((dst) &\
43305 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__MODIFY(dst, src) \
43306 (dst) = ((dst) &\
43312 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__SET(dst) \
43313 (dst) = ((dst) &\
43315 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__CLR(dst) \
43316 (dst) = ((dst) &\
43329 #define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MODIFY(dst, src) \
43330 (dst) = ((dst) &\
43347 #define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MODIFY(dst, src) \
43348 (dst) = ((dst) &\
43365 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MODIFY(dst, src) \
43366 (dst) = ((dst) &\
43372 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__SET(dst) \
43373 (dst) = ((dst) &\
43375 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__CLR(dst) \
43376 (dst) = ((dst) &\
43402 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MODIFY(dst, src) \
43403 (dst) = ((dst) &\
43420 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MODIFY(dst, src) \
43421 (dst) = ((dst) &\
43438 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MODIFY(dst, src) \
43439 (dst) = ((dst) &\
43456 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MODIFY(dst, src) \
43457 (dst) = ((dst) &\
43474 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MODIFY(dst, src) \
43475 (dst) = ((dst) &\
43505 #define BBB_RX_CTRL_6__SYNC_START_DELAY__MODIFY(dst, src) \
43506 (dst) = ((dst) &\
43523 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__MODIFY(dst, src) \
43524 (dst) = ((dst) &\
43530 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__SET(dst) \
43531 (dst) = ((dst) &\
43533 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__CLR(dst) \
43534 (dst) = ((dst) &\
43547 #define BBB_RX_CTRL_6__START_IIR_DELAY__MODIFY(dst, src) \
43548 (dst) = ((dst) &\
43565 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MODIFY(dst, src) \
43566 (dst) = ((dst) &\
43572 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__SET(dst) \
43573 (dst) = ((dst) &\
43575 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__CLR(dst) \
43576 (dst) = ((dst) &\
43589 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MODIFY(dst, src) \
43590 (dst) = ((dst) &\
43596 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__SET(dst) \
43597 (dst) = ((dst) &\
43599 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__CLR(dst) \
43600 (dst) = ((dst) &\
43613 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MODIFY(dst, src) \
43614 (dst) = ((dst) &\
43620 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__SET(dst) \
43621 (dst) = ((dst) &\
43623 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__CLR(dst) \
43624 (dst) = ((dst) &\
43637 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MODIFY(dst, src) \
43638 (dst) = ((dst) &\
43644 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__SET(dst) \
43645 (dst) = ((dst) &\
43647 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__CLR(dst) \
43648 (dst) = ((dst) &\
43661 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MODIFY(dst, src) \
43662 (dst) = ((dst) &\
43668 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__SET(dst) \
43669 (dst) = ((dst) &\
43671 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__CLR(dst) \
43672 (dst) = ((dst) &\
43698 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MODIFY(dst, src) \
43699 (dst) = ((dst) &\
43705 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__SET(dst) \
43706 (dst) = ((dst) &\
43708 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__CLR(dst) \
43709 (dst) = ((dst) &\
43722 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MODIFY(dst, src) \
43723 (dst) = ((dst) &\
43729 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__SET(dst) \
43730 (dst) = ((dst) &\
43732 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__CLR(dst) \
43733 (dst) = ((dst) &\
43746 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MODIFY(dst, src) \
43747 (dst) = ((dst) &\
43753 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__SET(dst) \
43754 (dst) = ((dst) &\
43756 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__CLR(dst) \
43757 (dst) = ((dst) &\
43770 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MODIFY(dst, src) \
43771 (dst) = ((dst) &\
43777 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__SET(dst) \
43778 (dst) = ((dst) &\
43780 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__CLR(dst) \
43781 (dst) = ((dst) &\
43794 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MODIFY(dst, src) \
43795 (dst) = ((dst) &\
43801 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__SET(dst) \
43802 (dst) = ((dst) &\
43804 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__CLR(dst) \
43805 (dst) = ((dst) &\
43818 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MODIFY(dst, src) \
43819 (dst) = ((dst) &\
43825 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__SET(dst) \
43826 (dst) = ((dst) &\
43828 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__CLR(dst) \
43829 (dst) = ((dst) &\
43853 #define SETTLING_TIME__AGC_SETTLING__MODIFY(dst, src) \
43854 (dst) = ((dst) &\
43871 #define SETTLING_TIME__SWITCH_SETTLING__MODIFY(dst, src) \
43872 (dst) = ((dst) &\
43889 #define SETTLING_TIME__ADCSAT_THRL__MODIFY(dst, src) \
43890 (dst) = ((dst) &\
43907 #define SETTLING_TIME__ADCSAT_THRH__MODIFY(dst, src) \
43908 (dst) = ((dst) &\
43925 #define SETTLING_TIME__LBRESET_ADVANCE__MODIFY(dst, src) \
43926 (dst) = ((dst) &\
43956 #define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MODIFY(dst, src) \
43957 (dst) = ((dst) &\
43974 #define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MODIFY(dst, src) \
43975 (dst) = ((dst) &\
43992 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MODIFY(dst, src) \
43993 (dst) = ((dst) &\
43999 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__SET(dst) \
44000 (dst) = ((dst) &\
44002 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__CLR(dst) \
44003 (dst) = ((dst) &\
44016 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MODIFY(dst, src) \
44017 (dst) = ((dst) &\
44023 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__SET(dst) \
44024 (dst) = ((dst) &\
44026 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__CLR(dst) \
44027 (dst) = ((dst) &\
44040 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MODIFY(dst, src) \
44041 (dst) = ((dst) &\
44058 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MODIFY(dst, src) \
44059 (dst) = ((dst) &\
44087 #define GAINS_MIN_OFFSETS__OFFSETC1__MODIFY(dst, src) \
44088 (dst) = ((dst) &\
44105 #define GAINS_MIN_OFFSETS__OFFSETC2__MODIFY(dst, src) \
44106 (dst) = ((dst) &\
44123 #define GAINS_MIN_OFFSETS__OFFSETC3__MODIFY(dst, src) \
44124 (dst) = ((dst) &\
44141 #define GAINS_MIN_OFFSETS__GAIN_FORCE__MODIFY(dst, src) \
44142 (dst) = ((dst) &\
44148 #define GAINS_MIN_OFFSETS__GAIN_FORCE__SET(dst) \
44149 (dst) = ((dst) &\
44151 #define GAINS_MIN_OFFSETS__GAIN_FORCE__CLR(dst) \
44152 (dst) = ((dst) &\
44165 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MODIFY(dst, src) \
44166 (dst) = ((dst) &\
44172 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__SET(dst) \
44173 (dst) = ((dst) &\
44175 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__CLR(dst) \
44176 (dst) = ((dst) &\
44189 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MODIFY(dst, src) \
44190 (dst) = ((dst) &\
44196 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__SET(dst) \
44197 (dst) = ((dst) &\
44199 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__CLR(dst) \
44200 (dst) = ((dst) &\
44213 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MODIFY(dst, src) \
44214 (dst) = ((dst) &\
44220 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__SET(dst) \
44221 (dst) = ((dst) &\
44223 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__CLR(dst) \
44224 (dst) = ((dst) &\
44237 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MODIFY(dst, src) \
44238 (dst) = ((dst) &\
44244 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__SET(dst) \
44245 (dst) = ((dst) &\
44247 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__CLR(dst) \
44248 (dst) = ((dst) &\
44274 #define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MODIFY(dst, src) \
44275 (dst) = ((dst) &\
44292 #define DESIRED_SIGSIZE__TOTAL_DESIRED__MODIFY(dst, src) \
44293 (dst) = ((dst) &\
44310 #define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MODIFY(dst, src) \
44311 (dst) = ((dst) &\
44328 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MODIFY(dst, src) \
44329 (dst) = ((dst) &\
44335 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__SET(dst) \
44336 (dst) = ((dst) &\
44338 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__CLR(dst) \
44339 (dst) = ((dst) &\
44352 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__MODIFY(dst, src) \
44353 (dst) = ((dst) &\
44359 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__SET(dst) \
44360 (dst) = ((dst) &\
44362 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__CLR(dst) \
44363 (dst) = ((dst) &\
44385 #define FIND_SIGNAL__RELSTEP__MODIFY(dst, src) \
44386 (dst) = ((dst) &\
44399 #define FIND_SIGNAL__RELPWR__MODIFY(dst, src) \
44400 (dst) = ((dst) &\
44417 #define FIND_SIGNAL__FIRSTEP__MODIFY(dst, src) \
44418 (dst) = ((dst) &\
44433 #define FIND_SIGNAL__FIRPWR__MODIFY(dst, src) \
44434 (dst) = ((dst) &\
44451 #define FIND_SIGNAL__M1COUNT_MAX__MODIFY(dst, src) \
44452 (dst) = ((dst) &\
44478 #define AGC__COARSEPWR_CONST__MODIFY(dst, src) \
44479 (dst) = ((dst) &\
44492 #define AGC__COARSE_LOW__MODIFY(dst, src) \
44493 (dst) = ((dst) &\
44506 #define AGC__COARSE_HIGH__MODIFY(dst, src) \
44507 (dst) = ((dst) &\
44520 #define AGC__QUICK_DROP__MODIFY(dst, src) \
44521 (dst) = ((dst) &\
44538 #define AGC__RSSI_OUT_SELECT__MODIFY(dst, src) \
44539 (dst) = ((dst) &\
44569 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MODIFY(dst, src) \
44570 (dst) = ((dst) &\
44587 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MODIFY(dst, src) \
44588 (dst) = ((dst) &\
44605 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MODIFY(dst, src) \
44606 (dst) = ((dst) &\
44623 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MODIFY(dst, src) \
44624 (dst) = ((dst) &\
44641 #define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MODIFY(dst, src) \
44642 (dst) = ((dst) &\
44668 #define CCA_B0__CF_MAXCCAPWR_0__MODIFY(dst, src) \
44669 (dst) = ((dst) &\
44686 #define CCA_B0__CF_CCA_COUNT_MAXC__MODIFY(dst, src) \
44687 (dst) = ((dst) &\
44702 #define CCA_B0__CF_THRESH62__MODIFY(dst, src) \
44703 (dst) = ((dst) &\
44739 #define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MODIFY(dst, src) \
44740 (dst) = ((dst) &\
44757 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MODIFY(dst, src) \
44758 (dst) = ((dst) &\
44764 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__SET(dst) \
44765 (dst) = ((dst) &\
44767 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__CLR(dst) \
44768 (dst) = ((dst) &\
44781 #define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MODIFY(dst, src) \
44782 (dst) = ((dst) &\
44799 #define CCA_CTRL_2_B0__THRESH62_MODE__MODIFY(dst, src) \
44800 (dst) = ((dst) &\
44806 #define CCA_CTRL_2_B0__THRESH62_MODE__SET(dst) \
44807 (dst) = ((dst) &\
44809 #define CCA_CTRL_2_B0__THRESH62_MODE__CLR(dst) \
44810 (dst) = ((dst) &\
44832 #define RESTART__ENABLE_RESTART__MODIFY(dst, src) \
44833 (dst) = ((dst) &\
44839 #define RESTART__ENABLE_RESTART__SET(dst) \
44840 (dst) = ((dst) &\
44842 #define RESTART__ENABLE_RESTART__CLR(dst) \
44843 (dst) = ((dst) &\
44856 #define RESTART__RESTART_LGFIRPWR_DELTA__MODIFY(dst, src) \
44857 (dst) = ((dst) &\
44874 #define RESTART__ENABLE_PWR_DROP_ERR__MODIFY(dst, src) \
44875 (dst) = ((dst) &\
44881 #define RESTART__ENABLE_PWR_DROP_ERR__SET(dst) \
44882 (dst) = ((dst) &\
44884 #define RESTART__ENABLE_PWR_DROP_ERR__CLR(dst) \
44885 (dst) = ((dst) &\
44898 #define RESTART__PWRDROP_LGFIRPWR_DELTA__MODIFY(dst, src) \
44899 (dst) = ((dst) &\
44916 #define RESTART__OFDM_CCK_RSSI_BIAS__MODIFY(dst, src) \
44917 (dst) = ((dst) &\
44934 #define RESTART__ANT_FAST_DIV_GC_LIMIT__MODIFY(dst, src) \
44935 (dst) = ((dst) &\
44952 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MODIFY(dst, src) \
44953 (dst) = ((dst) &\
44959 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__SET(dst) \
44960 (dst) = ((dst) &\
44962 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__CLR(dst) \
44963 (dst) = ((dst) &\
44976 #define RESTART__WEAK_RSSI_VOTE_THR__MODIFY(dst, src) \
44977 (dst) = ((dst) &\
44994 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__MODIFY(dst, src) \
44995 (dst) = ((dst) &\
45001 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__SET(dst) \
45002 (dst) = ((dst) &\
45004 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__CLR(dst) \
45005 (dst) = ((dst) &\
45018 #define RESTART__DISABLE_DC_RESTART__MODIFY(dst, src) \
45019 (dst) = ((dst) &\
45025 #define RESTART__DISABLE_DC_RESTART__SET(dst) \
45026 (dst) = ((dst) &\
45028 #define RESTART__DISABLE_DC_RESTART__CLR(dst) \
45029 (dst) = ((dst) &\
45042 #define RESTART__RESTART_MODE_BW40__MODIFY(dst, src) \
45043 (dst) = ((dst) &\
45049 #define RESTART__RESTART_MODE_BW40__SET(dst) \
45050 (dst) = ((dst) &\
45052 #define RESTART__RESTART_MODE_BW40__CLR(dst) \
45053 (dst) = ((dst) &\
45079 #define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MODIFY(dst, src) \
45080 (dst) = ((dst) &\
45097 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MODIFY(dst, src) \
45098 (dst) = ((dst) &\
45104 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__SET(dst) \
45105 (dst) = ((dst) &\
45107 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__CLR(dst) \
45108 (dst) = ((dst) &\
45121 #define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MODIFY(dst, src) \
45122 (dst) = ((dst) &\
45139 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MODIFY(dst, src) \
45140 (dst) = ((dst) &\
45157 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MODIFY(dst, src) \
45158 (dst) = ((dst) &\
45164 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__SET(dst) \
45165 (dst) = ((dst) &\
45167 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__CLR(dst) \
45168 (dst) = ((dst) &\
45181 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MODIFY(dst, src) \
45182 (dst) = ((dst) &\
45188 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__SET(dst) \
45189 (dst) = ((dst) &\
45191 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__CLR(dst) \
45192 (dst) = ((dst) &\
45205 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MODIFY(dst, src) \
45206 (dst) = ((dst) &\
45212 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SET(dst) \
45213 (dst) = ((dst) &\
45215 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__CLR(dst) \
45216 (dst) = ((dst) &\
45229 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MODIFY(dst, src) \
45230 (dst) = ((dst) &\
45236 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__SET(dst) \
45237 (dst) = ((dst) &\
45239 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__CLR(dst) \
45240 (dst) = ((dst) &\
45253 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MODIFY(dst, src) \
45254 (dst) = ((dst) &\
45271 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MODIFY(dst, src) \
45272 (dst) = ((dst) &\
45289 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MODIFY(dst, src) \
45290 (dst) = ((dst) &\
45296 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__SET(dst) \
45297 (dst) = ((dst) &\
45299 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__CLR(dst) \
45300 (dst) = ((dst) &\
45313 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MODIFY(dst, src) \
45314 (dst) = ((dst) &\
45320 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__SET(dst) \
45321 (dst) = ((dst) &\
45323 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__CLR(dst) \
45324 (dst) = ((dst) &\
45350 #define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MODIFY(dst, src) \
45351 (dst) = ((dst) &\
45368 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MODIFY(dst, src) \
45369 (dst) = ((dst) &\
45386 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MODIFY(dst, src) \
45387 (dst) = ((dst) &\
45404 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MODIFY(dst, src) \
45405 (dst) = ((dst) &\
45435 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MODIFY(dst, src) \
45436 (dst) = ((dst) &\
45453 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MODIFY(dst, src) \
45454 (dst) = ((dst) &\
45471 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MODIFY(dst, src) \
45472 (dst) = ((dst) &\
45489 #define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MODIFY(dst, src) \
45490 (dst) = ((dst) &\
45507 #define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MODIFY(dst, src) \
45508 (dst) = ((dst) &\
45525 #define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MODIFY(dst, src) \
45526 (dst) = ((dst) &\
45543 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MODIFY(dst, src) \
45544 (dst) = ((dst) &\
45574 #define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MODIFY(dst, src) \
45575 (dst) = ((dst) &\
45592 #define PWR_THR_20_40_DET__BLOCKER40_MAX__MODIFY(dst, src) \
45593 (dst) = ((dst) &\
45610 #define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MODIFY(dst, src) \
45611 (dst) = ((dst) &\
45628 #define PWR_THR_20_40_DET__DET40_THR_SNR__MODIFY(dst, src) \
45629 (dst) = ((dst) &\
45646 #define PWR_THR_20_40_DET__DET40_PRI_BIAS__MODIFY(dst, src) \
45647 (dst) = ((dst) &\
45664 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__MODIFY(dst, src) \
45665 (dst) = ((dst) &\
45671 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__SET(dst) \
45672 (dst) = ((dst) &\
45674 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__CLR(dst) \
45675 (dst) = ((dst) &\
45688 #define PWR_THR_20_40_DET__LOWSNR40_ENA__MODIFY(dst, src) \
45689 (dst) = ((dst) &\
45695 #define PWR_THR_20_40_DET__LOWSNR40_ENA__SET(dst) \
45696 (dst) = ((dst) &\
45698 #define PWR_THR_20_40_DET__LOWSNR40_ENA__CLR(dst) \
45699 (dst) = ((dst) &\
45725 #define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MODIFY(dst, src) \
45726 (dst) = ((dst) &\
45743 #define RIFS_SRCH__RIFS_INIT_DELAY__MODIFY(dst, src) \
45744 (dst) = ((dst) &\
45761 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MODIFY(dst, src) \
45762 (dst) = ((dst) &\
45768 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__SET(dst) \
45769 (dst) = ((dst) &\
45771 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__CLR(dst) \
45772 (dst) = ((dst) &\
45785 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MODIFY(dst, src) \
45786 (dst) = ((dst) &\
45792 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__SET(dst) \
45793 (dst) = ((dst) &\
45795 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__CLR(dst) \
45796 (dst) = ((dst) &\
45822 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MODIFY(dst, src) \
45823 (dst) = ((dst) &\
45829 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__SET(dst) \
45830 (dst) = ((dst) &\
45832 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__CLR(dst) \
45833 (dst) = ((dst) &\
45846 #define PEAK_DET_CTRL_1__USE_PEAK_DET__MODIFY(dst, src) \
45847 (dst) = ((dst) &\
45853 #define PEAK_DET_CTRL_1__USE_PEAK_DET__SET(dst) \
45854 (dst) = ((dst) &\
45856 #define PEAK_DET_CTRL_1__USE_PEAK_DET__CLR(dst) \
45857 (dst) = ((dst) &\
45870 #define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MODIFY(dst, src) \
45871 (dst) = ((dst) &\
45888 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__MODIFY(dst, src) \
45889 (dst) = ((dst) &\
45906 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__MODIFY(dst, src) \
45907 (dst) = ((dst) &\
45924 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__MODIFY(dst, src) \
45925 (dst) = ((dst) &\
45942 #define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MODIFY(dst, src) \
45943 (dst) = ((dst) &\
45960 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MODIFY(dst, src) \
45961 (dst) = ((dst) &\
45967 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__SET(dst) \
45968 (dst) = ((dst) &\
45970 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__CLR(dst) \
45971 (dst) = ((dst) &\
45984 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MODIFY(dst, src) \
45985 (dst) = ((dst) &\
45991 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__SET(dst) \
45992 (dst) = ((dst) &\
45994 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__CLR(dst) \
45995 (dst) = ((dst) &\
46021 #define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MODIFY(dst, src) \
46022 (dst) = ((dst) &\
46039 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__MODIFY(dst, src) \
46040 (dst) = ((dst) &\
46057 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__MODIFY(dst, src) \
46058 (dst) = ((dst) &\
46075 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__MODIFY(dst, src) \
46076 (dst) = ((dst) &\
46093 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__MODIFY(dst, src) \
46094 (dst) = ((dst) &\
46124 #define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MODIFY(dst, src) \
46125 (dst) = ((dst) &\
46142 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MODIFY(dst, src) \
46143 (dst) = ((dst) &\
46160 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MODIFY(dst, src) \
46161 (dst) = ((dst) &\
46178 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MODIFY(dst, src) \
46179 (dst) = ((dst) &\
46185 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__SET(dst) \
46186 (dst) = ((dst) &\
46188 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__CLR(dst) \
46189 (dst) = ((dst) &\
46202 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MODIFY(dst, src) \
46203 (dst) = ((dst) &\
46209 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__SET(dst) \
46210 (dst) = ((dst) &\
46212 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__CLR(dst) \
46213 (dst) = ((dst) &\
46239 #define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MODIFY(dst, src) \
46240 (dst) = ((dst) &\
46257 #define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MODIFY(dst, src) \
46258 (dst) = ((dst) &\
46275 #define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MODIFY(dst, src) \
46276 (dst) = ((dst) &\
46293 #define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MODIFY(dst, src) \
46294 (dst) = ((dst) &\
46324 #define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MODIFY(dst, src) \
46325 (dst) = ((dst) &\
46342 #define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MODIFY(dst, src) \
46343 (dst) = ((dst) &\
46360 #define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MODIFY(dst, src) \
46361 (dst) = ((dst) &\
46389 #define AGC_DIG_DC_CTRL__USE_DIG_DC__MODIFY(dst, src) \
46390 (dst) = ((dst) &\
46396 #define AGC_DIG_DC_CTRL__USE_DIG_DC__SET(dst) \
46397 (dst) = ((dst) &\
46399 #define AGC_DIG_DC_CTRL__USE_DIG_DC__CLR(dst) \
46400 (dst) = ((dst) &\
46413 #define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MODIFY(dst, src) \
46414 (dst) = ((dst) &\
46431 #define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MODIFY(dst, src) \
46432 (dst) = ((dst) &\
46449 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MODIFY(dst, src) \
46450 (dst) = ((dst) &\
46456 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__SET(dst) \
46457 (dst) = ((dst) &\
46459 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__CLR(dst) \
46460 (dst) = ((dst) &\
46473 #define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MODIFY(dst, src) \
46474 (dst) = ((dst) &\
46500 #define BT_COEX__ENABLE_BT_COEX__MODIFY(dst, src) \
46501 (dst) = ((dst) &\
46507 #define BT_COEX__ENABLE_BT_COEX__SET(dst) \
46508 (dst) = ((dst) &\
46510 #define BT_COEX__ENABLE_BT_COEX__CLR(dst) \
46511 (dst) = ((dst) &\
46524 #define BT_COEX__WLAN_BT_PRIORITY__MODIFY(dst, src) \
46525 (dst) = ((dst) &\
46531 #define BT_COEX__WLAN_BT_PRIORITY__SET(dst) \
46532 (dst) = ((dst) &\
46534 #define BT_COEX__WLAN_BT_PRIORITY__CLR(dst) \
46535 (dst) = ((dst) &\
46548 #define BT_COEX__RFSAT_RESTART_THRESH__MODIFY(dst, src) \
46549 (dst) = ((dst) &\
46566 #define BT_COEX__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \
46567 (dst) = ((dst) &\
46573 #define BT_COEX__ENABLE_RFSAT_RESTART__SET(dst) \
46574 (dst) = ((dst) &\
46576 #define BT_COEX__ENABLE_RFSAT_RESTART__CLR(dst) \
46577 (dst) = ((dst) &\
46743 #define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MODIFY(dst, src) \
46744 (dst) = ((dst) &\
46761 #define BBB_SIG_DETECT__ANT_SWITCH_TIME__MODIFY(dst, src) \
46762 (dst) = ((dst) &\
46779 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MODIFY(dst, src) \
46780 (dst) = ((dst) &\
46786 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__SET(dst) \
46787 (dst) = ((dst) &\
46789 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__CLR(dst) \
46790 (dst) = ((dst) &\
46803 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MODIFY(dst, src) \
46804 (dst) = ((dst) &\
46810 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__SET(dst) \
46811 (dst) = ((dst) &\
46813 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__CLR(dst) \
46814 (dst) = ((dst) &\
46827 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MODIFY(dst, src) \
46828 (dst) = ((dst) &\
46834 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__SET(dst) \
46835 (dst) = ((dst) &\
46837 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__CLR(dst) \
46838 (dst) = ((dst) &\
46851 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MODIFY(dst, src) \
46852 (dst) = ((dst) &\
46858 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__SET(dst) \
46859 (dst) = ((dst) &\
46861 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__CLR(dst) \
46862 (dst) = ((dst) &\
46875 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MODIFY(dst, src) \
46876 (dst) = ((dst) &\
46882 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__SET(dst) \
46883 (dst) = ((dst) &\
46885 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__CLR(dst) \
46886 (dst) = ((dst) &\
46899 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MODIFY(dst, src) \
46900 (dst) = ((dst) &\
46906 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__SET(dst) \
46907 (dst) = ((dst) &\
46909 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__CLR(dst) \
46910 (dst) = ((dst) &\
46923 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MODIFY(dst, src) \
46924 (dst) = ((dst) &\
46930 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__SET(dst) \
46931 (dst) = ((dst) &\
46933 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__CLR(dst) \
46934 (dst) = ((dst) &\
46947 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MODIFY(dst, src) \
46948 (dst) = ((dst) &\
46954 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__SET(dst) \
46955 (dst) = ((dst) &\
46957 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__CLR(dst) \
46958 (dst) = ((dst) &\
46971 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MODIFY(dst, src) \
46972 (dst) = ((dst) &\
46978 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__SET(dst) \
46979 (dst) = ((dst) &\
46981 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__CLR(dst) \
46982 (dst) = ((dst) &\
46995 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MODIFY(dst, src) \
46996 (dst) = ((dst) &\
47002 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__SET(dst) \
47003 (dst) = ((dst) &\
47005 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__CLR(dst) \
47006 (dst) = ((dst) &\
47019 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MODIFY(dst, src) \
47020 (dst) = ((dst) &\
47026 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__SET(dst) \
47027 (dst) = ((dst) &\
47029 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__CLR(dst) \
47030 (dst) = ((dst) &\
47056 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MODIFY(dst, src) \
47057 (dst) = ((dst) &\
47063 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__SET(dst) \
47064 (dst) = ((dst) &\
47066 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__CLR(dst) \
47067 (dst) = ((dst) &\
47080 #define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MODIFY(dst, src) \
47081 (dst) = ((dst) &\
47098 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MODIFY(dst, src) \
47099 (dst) = ((dst) &\
47105 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__SET(dst) \
47106 (dst) = ((dst) &\
47108 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__CLR(dst) \
47109 (dst) = ((dst) &\
47122 #define BBB_DAGC_CTRL__BARKER_RSSI_THR__MODIFY(dst, src) \
47123 (dst) = ((dst) &\
47140 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MODIFY(dst, src) \
47141 (dst) = ((dst) &\
47147 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__SET(dst) \
47148 (dst) = ((dst) &\
47150 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__CLR(dst) \
47151 (dst) = ((dst) &\
47164 #define BBB_DAGC_CTRL__FIRSTEP_2__MODIFY(dst, src) \
47165 (dst) = ((dst) &\
47182 #define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MODIFY(dst, src) \
47183 (dst) = ((dst) &\
47200 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MODIFY(dst, src) \
47201 (dst) = ((dst) &\
47218 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MODIFY(dst, src) \
47219 (dst) = ((dst) &\
47249 #define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MODIFY(dst, src) \
47250 (dst) = ((dst) &\
47267 #define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MODIFY(dst, src) \
47268 (dst) = ((dst) &\
47285 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MODIFY(dst, src) \
47286 (dst) = ((dst) &\
47292 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__SET(dst) \
47293 (dst) = ((dst) &\
47295 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__CLR(dst) \
47296 (dst) = ((dst) &\
47309 #define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MODIFY(dst, src) \
47310 (dst) = ((dst) &\
47327 #define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MODIFY(dst, src) \
47328 (dst) = ((dst) &\
47345 #define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MODIFY(dst, src) \
47346 (dst) = ((dst) &\
47376 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MODIFY(dst, src) \
47377 (dst) = ((dst) &\
47383 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__SET(dst) \
47384 (dst) = ((dst) &\
47386 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__CLR(dst) \
47387 (dst) = ((dst) &\
47400 #define CCK_SPUR_MIT__SPUR_RSSI_THR__MODIFY(dst, src) \
47401 (dst) = ((dst) &\
47418 #define CCK_SPUR_MIT__CCK_SPUR_FREQ__MODIFY(dst, src) \
47419 (dst) = ((dst) &\
47436 #define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MODIFY(dst, src) \
47437 (dst) = ((dst) &\
47463 #define MRC_CCK_CTRL__BBB_MRC_EN__MODIFY(dst, src) \
47464 (dst) = ((dst) &\
47470 #define MRC_CCK_CTRL__BBB_MRC_EN__SET(dst) \
47471 (dst) = ((dst) &\
47473 #define MRC_CCK_CTRL__BBB_MRC_EN__CLR(dst) \
47474 (dst) = ((dst) &\
47487 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MODIFY(dst, src) \
47488 (dst) = ((dst) &\
47494 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__SET(dst) \
47495 (dst) = ((dst) &\
47497 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__CLR(dst) \
47498 (dst) = ((dst) &\
47511 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MODIFY(dst, src) \
47512 (dst) = ((dst) &\
47529 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MODIFY(dst, src) \
47530 (dst) = ((dst) &\
47547 #define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MODIFY(dst, src) \
47548 (dst) = ((dst) &\
47565 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MODIFY(dst, src) \
47566 (dst) = ((dst) &\
47583 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MODIFY(dst, src) \
47584 (dst) = ((dst) &\
47601 #define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MODIFY(dst, src) \
47602 (dst) = ((dst) &\
47627 #define RX_OCGAIN__GAIN_ENTRY__MODIFY(dst, src) \
47628 (dst) = ((dst) &\
47677 #define GEN_CONTROLS__TURBO__MODIFY(dst, src) \
47678 (dst) = ((dst) &\
47682 #define GEN_CONTROLS__TURBO__SET(dst) \
47683 (dst) = ((dst) &\
47685 #define GEN_CONTROLS__TURBO__CLR(dst) \
47686 (dst) = ((dst) &\
47699 #define GEN_CONTROLS__CF_SHORT20__MODIFY(dst, src) \
47700 (dst) = ((dst) &\
47706 #define GEN_CONTROLS__CF_SHORT20__SET(dst) \
47707 (dst) = ((dst) &\
47709 #define GEN_CONTROLS__CF_SHORT20__CLR(dst) \
47710 (dst) = ((dst) &\
47723 #define GEN_CONTROLS__DYN_20_40__MODIFY(dst, src) \
47724 (dst) = ((dst) &\
47730 #define GEN_CONTROLS__DYN_20_40__SET(dst) \
47731 (dst) = ((dst) &\
47733 #define GEN_CONTROLS__DYN_20_40__CLR(dst) \
47734 (dst) = ((dst) &\
47747 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MODIFY(dst, src) \
47748 (dst) = ((dst) &\
47754 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__SET(dst) \
47755 (dst) = ((dst) &\
47757 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__CLR(dst) \
47758 (dst) = ((dst) &\
47771 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__MODIFY(dst, src) \
47772 (dst) = ((dst) &\
47778 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__SET(dst) \
47779 (dst) = ((dst) &\
47781 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__CLR(dst) \
47782 (dst) = ((dst) &\
47795 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__MODIFY(dst, src) \
47796 (dst) = ((dst) &\
47802 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__SET(dst) \
47803 (dst) = ((dst) &\
47805 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__CLR(dst) \
47806 (dst) = ((dst) &\
47819 #define GEN_CONTROLS__HT_ENABLE__MODIFY(dst, src) \
47820 (dst) = ((dst) &\
47826 #define GEN_CONTROLS__HT_ENABLE__SET(dst) \
47827 (dst) = ((dst) &\
47829 #define GEN_CONTROLS__HT_ENABLE__CLR(dst) \
47830 (dst) = ((dst) &\
47843 #define GEN_CONTROLS__ALLOW_SHORT_GI__MODIFY(dst, src) \
47844 (dst) = ((dst) &\
47850 #define GEN_CONTROLS__ALLOW_SHORT_GI__SET(dst) \
47851 (dst) = ((dst) &\
47853 #define GEN_CONTROLS__ALLOW_SHORT_GI__CLR(dst) \
47854 (dst) = ((dst) &\
47867 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MODIFY(dst, src) \
47868 (dst) = ((dst) &\
47874 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__SET(dst) \
47875 (dst) = ((dst) &\
47877 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__CLR(dst) \
47878 (dst) = ((dst) &\
47891 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MODIFY(dst, src) \
47892 (dst) = ((dst) &\
47898 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__SET(dst) \
47899 (dst) = ((dst) &\
47901 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__CLR(dst) \
47902 (dst) = ((dst) &\
47915 #define GEN_CONTROLS__GF_ENABLE__MODIFY(dst, src) \
47916 (dst) = ((dst) &\
47922 #define GEN_CONTROLS__GF_ENABLE__SET(dst) \
47923 (dst) = ((dst) &\
47925 #define GEN_CONTROLS__GF_ENABLE__CLR(dst) \
47926 (dst) = ((dst) &\
47939 #define GEN_CONTROLS__BYPASS_DAC_FIFO_N__MODIFY(dst, src) \
47940 (dst) = ((dst) &\
47946 #define GEN_CONTROLS__BYPASS_DAC_FIFO_N__SET(dst) \
47947 (dst) = ((dst) &\
47949 #define GEN_CONTROLS__BYPASS_DAC_FIFO_N__CLR(dst) \
47950 (dst) = ((dst) &\
47963 #define GEN_CONTROLS__ML_ENABLE__MODIFY(dst, src) \
47964 (dst) = ((dst) &\
47970 #define GEN_CONTROLS__ML_ENABLE__SET(dst) \
47971 (dst) = ((dst) &\
47973 #define GEN_CONTROLS__ML_ENABLE__CLR(dst) \
47974 (dst) = ((dst) &\
47987 #define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__MODIFY(dst, src) \
47988 (dst) = ((dst) &\
47994 #define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__SET(dst) \
47995 (dst) = ((dst) &\
47997 #define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__CLR(dst) \
47998 (dst) = ((dst) &\
48011 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MODIFY(dst, src) \
48012 (dst) = ((dst) &\
48018 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__SET(dst) \
48019 (dst) = ((dst) &\
48021 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__CLR(dst) \
48022 (dst) = ((dst) &\
48044 #define MODES_SELECT__CCK_MODE__MODIFY(dst, src) \
48045 (dst) = ((dst) &\
48051 #define MODES_SELECT__CCK_MODE__SET(dst) \
48052 (dst) = ((dst) &\
48054 #define MODES_SELECT__CCK_MODE__CLR(dst) \
48055 (dst) = ((dst) &\
48068 #define MODES_SELECT__DYN_OFDM_CCK_MODE__MODIFY(dst, src) \
48069 (dst) = ((dst) &\
48075 #define MODES_SELECT__DYN_OFDM_CCK_MODE__SET(dst) \
48076 (dst) = ((dst) &\
48078 #define MODES_SELECT__DYN_OFDM_CCK_MODE__CLR(dst) \
48079 (dst) = ((dst) &\
48092 #define MODES_SELECT__HALF_RATE_MODE__MODIFY(dst, src) \
48093 (dst) = ((dst) &\
48099 #define MODES_SELECT__HALF_RATE_MODE__SET(dst) \
48100 (dst) = ((dst) &\
48102 #define MODES_SELECT__HALF_RATE_MODE__CLR(dst) \
48103 (dst) = ((dst) &\
48116 #define MODES_SELECT__QUARTER_RATE_MODE__MODIFY(dst, src) \
48117 (dst) = ((dst) &\
48123 #define MODES_SELECT__QUARTER_RATE_MODE__SET(dst) \
48124 (dst) = ((dst) &\
48126 #define MODES_SELECT__QUARTER_RATE_MODE__CLR(dst) \
48127 (dst) = ((dst) &\
48140 #define MODES_SELECT__MAC_CLK_MODE__MODIFY(dst, src) \
48141 (dst) = ((dst) &\
48147 #define MODES_SELECT__MAC_CLK_MODE__SET(dst) \
48148 (dst) = ((dst) &\
48150 #define MODES_SELECT__MAC_CLK_MODE__CLR(dst) \
48151 (dst) = ((dst) &\
48164 #define MODES_SELECT__DISABLE_DYN_CCK_DET__MODIFY(dst, src) \
48165 (dst) = ((dst) &\
48171 #define MODES_SELECT__DISABLE_DYN_CCK_DET__SET(dst) \
48172 (dst) = ((dst) &\
48174 #define MODES_SELECT__DISABLE_DYN_CCK_DET__CLR(dst) \
48175 (dst) = ((dst) &\
48188 #define MODES_SELECT__SVD_HALF_RATE_MODE__MODIFY(dst, src) \
48189 (dst) = ((dst) &\
48195 #define MODES_SELECT__SVD_HALF_RATE_MODE__SET(dst) \
48196 (dst) = ((dst) &\
48198 #define MODES_SELECT__SVD_HALF_RATE_MODE__CLR(dst) \
48199 (dst) = ((dst) &\
48221 #define ACTIVE__CF_ACTIVE__MODIFY(dst, src) \
48222 (dst) = ((dst) &\
48226 #define ACTIVE__CF_ACTIVE__SET(dst) \
48227 (dst) = ((dst) &\
48229 #define ACTIVE__CF_ACTIVE__CLR(dst) \
48230 (dst) = ((dst) &\
48256 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MODIFY(dst, src) \
48257 (dst) = ((dst) &\
48274 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MODIFY(dst, src) \
48275 (dst) = ((dst) &\
48305 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MODIFY(dst, src) \
48306 (dst) = ((dst) &\
48323 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MODIFY(dst, src) \
48324 (dst) = ((dst) &\
48354 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MODIFY(dst, src) \
48355 (dst) = ((dst) &\
48361 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__SET(dst) \
48362 (dst) = ((dst) &\
48364 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__CLR(dst) \
48365 (dst) = ((dst) &\
48378 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MODIFY(dst, src) \
48379 (dst) = ((dst) &\
48385 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__SET(dst) \
48386 (dst) = ((dst) &\
48388 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__CLR(dst) \
48389 (dst) = ((dst) &\
48402 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MODIFY(dst, src) \
48403 (dst) = ((dst) &\
48409 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__SET(dst) \
48410 (dst) = ((dst) &\
48412 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__CLR(dst) \
48413 (dst) = ((dst) &\
48426 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MODIFY(dst, src) \
48427 (dst) = ((dst) &\
48433 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__SET(dst) \
48434 (dst) = ((dst) &\
48436 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__CLR(dst) \
48437 (dst) = ((dst) &\
48450 #define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MODIFY(dst, src) \
48451 (dst) = ((dst) &\
48468 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MODIFY(dst, src) \
48469 (dst) = ((dst) &\
48486 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MODIFY(dst, src) \
48487 (dst) = ((dst) &\
48504 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MODIFY(dst, src) \
48505 (dst) = ((dst) &\
48511 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__SET(dst) \
48512 (dst) = ((dst) &\
48514 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__CLR(dst) \
48515 (dst) = ((dst) &\
48528 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MODIFY(dst, src) \
48529 (dst) = ((dst) &\
48535 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__SET(dst) \
48536 (dst) = ((dst) &\
48538 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__CLR(dst) \
48539 (dst) = ((dst) &\
48552 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MODIFY(dst, src) \
48553 (dst) = ((dst) &\
48559 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__SET(dst) \
48560 (dst) = ((dst) &\
48562 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__CLR(dst) \
48563 (dst) = ((dst) &\
48589 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MODIFY(dst, src) \
48590 (dst) = ((dst) &\
48596 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__SET(dst) \
48597 (dst) = ((dst) &\
48599 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__CLR(dst) \
48600 (dst) = ((dst) &\
48613 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MODIFY(dst, src) \
48614 (dst) = ((dst) &\
48620 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__SET(dst) \
48621 (dst) = ((dst) &\
48623 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__CLR(dst) \
48624 (dst) = ((dst) &\
48637 #define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MODIFY(dst, src) \
48638 (dst) = ((dst) &\
48655 #define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MODIFY(dst, src) \
48656 (dst) = ((dst) &\
48673 #define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MODIFY(dst, src) \
48674 (dst) = ((dst) &\
48691 #define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MODIFY(dst, src) \
48692 (dst) = ((dst) &\
48709 #define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MODIFY(dst, src) \
48710 (dst) = ((dst) &\
48740 #define SEARCH_START_DELAY__SEARCH_START_DELAY__MODIFY(dst, src) \
48741 (dst) = ((dst) &\
48758 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__MODIFY(dst, src) \
48759 (dst) = ((dst) &\
48765 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__SET(dst) \
48766 (dst) = ((dst) &\
48768 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__CLR(dst) \
48769 (dst) = ((dst) &\
48782 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MODIFY(dst, src) \
48783 (dst) = ((dst) &\
48789 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__SET(dst) \
48790 (dst) = ((dst) &\
48792 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__CLR(dst) \
48793 (dst) = ((dst) &\
48817 #define MAX_RX_LENGTH__MAX_RX_LENGTH__MODIFY(dst, src) \
48818 (dst) = ((dst) &\
48835 #define MAX_RX_LENGTH__MAX_HT_LENGTH__MODIFY(dst, src) \
48836 (dst) = ((dst) &\
48866 #define FRAME_CONTROL__CF_OVERLAP_WINDOW__MODIFY(dst, src) \
48867 (dst) = ((dst) &\
48884 #define FRAME_CONTROL__CF_SCALE_SHORT__MODIFY(dst, src) \
48885 (dst) = ((dst) &\
48891 #define FRAME_CONTROL__CF_SCALE_SHORT__SET(dst) \
48892 (dst) = ((dst) &\
48894 #define FRAME_CONTROL__CF_SCALE_SHORT__CLR(dst) \
48895 (dst) = ((dst) &\
48908 #define FRAME_CONTROL__CF_TX_CLIP__MODIFY(dst, src) \
48909 (dst) = ((dst) &\
48926 #define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MODIFY(dst, src) \
48927 (dst) = ((dst) &\
48944 #define FRAME_CONTROL__TX_END_ADJUST__MODIFY(dst, src) \
48945 (dst) = ((dst) &\
48962 #define FRAME_CONTROL__PREPEND_CHAN_INFO__MODIFY(dst, src) \
48963 (dst) = ((dst) &\
48969 #define FRAME_CONTROL__PREPEND_CHAN_INFO__SET(dst) \
48970 (dst) = ((dst) &\
48972 #define FRAME_CONTROL__PREPEND_CHAN_INFO__CLR(dst) \
48973 (dst) = ((dst) &\
48986 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MODIFY(dst, src) \
48987 (dst) = ((dst) &\
48993 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__SET(dst) \
48994 (dst) = ((dst) &\
48996 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__CLR(dst) \
48997 (dst) = ((dst) &\
49010 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MODIFY(dst, src) \
49011 (dst) = ((dst) &\
49017 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__SET(dst) \
49018 (dst) = ((dst) &\
49020 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__CLR(dst) \
49021 (dst) = ((dst) &\
49034 #define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__MODIFY(dst, src) \
49035 (dst) = ((dst) &\
49041 #define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__SET(dst) \
49042 (dst) = ((dst) &\
49044 #define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__CLR(dst) \
49045 (dst) = ((dst) &\
49058 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MODIFY(dst, src) \
49059 (dst) = ((dst) &\
49065 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__SET(dst) \
49066 (dst) = ((dst) &\
49068 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__CLR(dst) \
49069 (dst) = ((dst) &\
49082 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MODIFY(dst, src) \
49083 (dst) = ((dst) &\
49089 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__SET(dst) \
49090 (dst) = ((dst) &\
49092 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__CLR(dst) \
49093 (dst) = ((dst) &\
49106 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__MODIFY(dst, src) \
49107 (dst) = ((dst) &\
49113 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__SET(dst) \
49114 (dst) = ((dst) &\
49116 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__CLR(dst) \
49117 (dst) = ((dst) &\
49130 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MODIFY(dst, src) \
49131 (dst) = ((dst) &\
49137 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__SET(dst) \
49138 (dst) = ((dst) &\
49140 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__CLR(dst) \
49141 (dst) = ((dst) &\
49154 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MODIFY(dst, src) \
49155 (dst) = ((dst) &\
49161 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__SET(dst) \
49162 (dst) = ((dst) &\
49164 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__CLR(dst) \
49165 (dst) = ((dst) &\
49178 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MODIFY(dst, src) \
49179 (dst) = ((dst) &\
49185 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__SET(dst) \
49186 (dst) = ((dst) &\
49188 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__CLR(dst) \
49189 (dst) = ((dst) &\
49202 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MODIFY(dst, src) \
49203 (dst) = ((dst) &\
49209 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__SET(dst) \
49210 (dst) = ((dst) &\
49212 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__CLR(dst) \
49213 (dst) = ((dst) &\
49226 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MODIFY(dst, src) \
49227 (dst) = ((dst) &\
49233 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__SET(dst) \
49234 (dst) = ((dst) &\
49236 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__CLR(dst) \
49237 (dst) = ((dst) &\
49250 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MODIFY(dst, src) \
49251 (dst) = ((dst) &\
49257 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__SET(dst) \
49258 (dst) = ((dst) &\
49260 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__CLR(dst) \
49261 (dst) = ((dst) &\
49274 #define FRAME_CONTROL__EN_ERR_SERVICE__MODIFY(dst, src) \
49275 (dst) = ((dst) &\
49281 #define FRAME_CONTROL__EN_ERR_SERVICE__SET(dst) \
49282 (dst) = ((dst) &\
49284 #define FRAME_CONTROL__EN_ERR_SERVICE__CLR(dst) \
49285 (dst) = ((dst) &\
49298 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MODIFY(dst, src) \
49299 (dst) = ((dst) &\
49305 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__SET(dst) \
49306 (dst) = ((dst) &\
49308 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__CLR(dst) \
49309 (dst) = ((dst) &\
49322 #define FRAME_CONTROL__EN_ERR_RX_ABORT__MODIFY(dst, src) \
49323 (dst) = ((dst) &\
49329 #define FRAME_CONTROL__EN_ERR_RX_ABORT__SET(dst) \
49330 (dst) = ((dst) &\
49332 #define FRAME_CONTROL__EN_ERR_RX_ABORT__CLR(dst) \
49333 (dst) = ((dst) &\
49357 #define RFBUS_REQUEST__RFBUS_REQUEST__MODIFY(dst, src) \
49358 (dst) = ((dst) &\
49364 #define RFBUS_REQUEST__RFBUS_REQUEST__SET(dst) \
49365 (dst) = ((dst) &\
49367 #define RFBUS_REQUEST__RFBUS_REQUEST__CLR(dst) \
49368 (dst) = ((dst) &\
49389 #define RFBUS_GRANT__RFBUS_GRANT__SET(dst) \
49390 (dst) = ((dst) &\
49392 #define RFBUS_GRANT__RFBUS_GRANT__CLR(dst) \
49393 (dst) = ((dst) &\
49401 #define RFBUS_GRANT__BT_ANT__SET(dst) \
49402 (dst) = ((dst) &\
49404 #define RFBUS_GRANT__BT_ANT__CLR(dst) \
49405 (dst) = ((dst) &\
49430 #define RIFS__DISABLE_FCC_FIX__MODIFY(dst, src) \
49431 (dst) = ((dst) &\
49437 #define RIFS__DISABLE_FCC_FIX__SET(dst) \
49438 (dst) = ((dst) &\
49440 #define RIFS__DISABLE_FCC_FIX__CLR(dst) \
49441 (dst) = ((dst) &\
49454 #define RIFS__ENABLE_RESET_TDOMAIN__MODIFY(dst, src) \
49455 (dst) = ((dst) &\
49461 #define RIFS__ENABLE_RESET_TDOMAIN__SET(dst) \
49462 (dst) = ((dst) &\
49464 #define RIFS__ENABLE_RESET_TDOMAIN__CLR(dst) \
49465 (dst) = ((dst) &\
49478 #define RIFS__DISABLE_FCC_FIX2__MODIFY(dst, src) \
49479 (dst) = ((dst) &\
49485 #define RIFS__DISABLE_FCC_FIX2__SET(dst) \
49486 (dst) = ((dst) &\
49488 #define RIFS__DISABLE_FCC_FIX2__CLR(dst) \
49489 (dst) = ((dst) &\
49502 #define RIFS__DISABLE_RIFS_CCK_FIX__MODIFY(dst, src) \
49503 (dst) = ((dst) &\
49509 #define RIFS__DISABLE_RIFS_CCK_FIX__SET(dst) \
49510 (dst) = ((dst) &\
49512 #define RIFS__DISABLE_RIFS_CCK_FIX__CLR(dst) \
49513 (dst) = ((dst) &\
49526 #define RIFS__DISABLE_ERROR_RESET_FIX__MODIFY(dst, src) \
49527 (dst) = ((dst) &\
49533 #define RIFS__DISABLE_ERROR_RESET_FIX__SET(dst) \
49534 (dst) = ((dst) &\
49536 #define RIFS__DISABLE_ERROR_RESET_FIX__CLR(dst) \
49537 (dst) = ((dst) &\
49550 #define RIFS__RADAR_USE_FDOMAIN_RESET__MODIFY(dst, src) \
49551 (dst) = ((dst) &\
49557 #define RIFS__RADAR_USE_FDOMAIN_RESET__SET(dst) \
49558 (dst) = ((dst) &\
49560 #define RIFS__RADAR_USE_FDOMAIN_RESET__CLR(dst) \
49561 (dst) = ((dst) &\
49587 #define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MODIFY(dst, src) \
49588 (dst) = ((dst) &\
49618 #define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MODIFY(dst, src) \
49619 (dst) = ((dst) &\
49649 #define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MODIFY(dst, src) \
49650 (dst) = ((dst) &\
49667 #define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MODIFY(dst, src) \
49668 (dst) = ((dst) &\
49685 #define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MODIFY(dst, src) \
49686 (dst) = ((dst) &\
49703 #define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MODIFY(dst, src) \
49704 (dst) = ((dst) &\
49734 #define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MODIFY(dst, src) \
49735 (dst) = ((dst) &\
49752 #define TX_TIMING_2__TX_FRAME_TO_PA_ON__MODIFY(dst, src) \
49753 (dst) = ((dst) &\
49770 #define TX_TIMING_2__TX_END_TO_PA_OFF__MODIFY(dst, src) \
49771 (dst) = ((dst) &\
49788 #define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MODIFY(dst, src) \
49789 (dst) = ((dst) &\
49819 #define TX_TIMING_3__TX_END_TO_DAC_OFF__MODIFY(dst, src) \
49820 (dst) = ((dst) &\
49837 #define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MODIFY(dst, src) \
49838 (dst) = ((dst) &\
49855 #define TX_TIMING_3__TX_END_TO_A2_RX_ON__MODIFY(dst, src) \
49856 (dst) = ((dst) &\
49873 #define TX_TIMING_3__TX_END_TO_ADC_ON__MODIFY(dst, src) \
49874 (dst) = ((dst) &\
49904 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MODIFY(dst, src) \
49905 (dst) = ((dst) &\
49922 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MODIFY(dst, src) \
49923 (dst) = ((dst) &\
49940 #define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MODIFY(dst, src) \
49941 (dst) = ((dst) &\
49958 #define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MODIFY(dst, src) \
49959 (dst) = ((dst) &\
49989 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MODIFY(dst, src) \
49990 (dst) = ((dst) &\
49996 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__SET(dst) \
49997 (dst) = ((dst) &\
49999 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__CLR(dst) \
50000 (dst) = ((dst) &\
50013 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MODIFY(dst, src) \
50014 (dst) = ((dst) &\
50020 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__SET(dst) \
50021 (dst) = ((dst) &\
50023 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__CLR(dst) \
50024 (dst) = ((dst) &\
50037 #define MISC_PA_CONTROL__ENABLE_XPAA__MODIFY(dst, src) \
50038 (dst) = ((dst) &\
50044 #define MISC_PA_CONTROL__ENABLE_XPAA__SET(dst) \
50045 (dst) = ((dst) &\
50047 #define MISC_PA_CONTROL__ENABLE_XPAA__CLR(dst) \
50048 (dst) = ((dst) &\
50061 #define MISC_PA_CONTROL__ENABLE_XPAB__MODIFY(dst, src) \
50062 (dst) = ((dst) &\
50068 #define MISC_PA_CONTROL__ENABLE_XPAB__SET(dst) \
50069 (dst) = ((dst) &\
50071 #define MISC_PA_CONTROL__ENABLE_XPAB__CLR(dst) \
50072 (dst) = ((dst) &\
50098 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MODIFY(dst, src) \
50099 (dst) = ((dst) &\
50116 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MODIFY(dst, src) \
50117 (dst) = ((dst) &\
50134 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MODIFY(dst, src) \
50135 (dst) = ((dst) &\
50152 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MODIFY(dst, src) \
50153 (dst) = ((dst) &\
50170 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MODIFY(dst, src) \
50171 (dst) = ((dst) &\
50188 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MODIFY(dst, src) \
50189 (dst) = ((dst) &\
50219 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MODIFY(dst, src) \
50220 (dst) = ((dst) &\
50237 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MODIFY(dst, src) \
50238 (dst) = ((dst) &\
50255 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MODIFY(dst, src) \
50256 (dst) = ((dst) &\
50273 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MODIFY(dst, src) \
50274 (dst) = ((dst) &\
50291 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MODIFY(dst, src) \
50292 (dst) = ((dst) &\
50322 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MODIFY(dst, src) \
50323 (dst) = ((dst) &\
50340 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MODIFY(dst, src) \
50341 (dst) = ((dst) &\
50358 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MODIFY(dst, src) \
50359 (dst) = ((dst) &\
50376 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MODIFY(dst, src) \
50377 (dst) = ((dst) &\
50394 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MODIFY(dst, src) \
50395 (dst) = ((dst) &\
50425 #define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MODIFY(dst, src) \
50426 (dst) = ((dst) &\
50456 #define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MODIFY(dst, src) \
50457 (dst) = ((dst) &\
50483 #define AGC_CONTROL__DO_CALIBRATE__MODIFY(dst, src) \
50484 (dst) = ((dst) &\
50490 #define AGC_CONTROL__DO_CALIBRATE__SET(dst) \
50491 (dst) = ((dst) &\
50493 #define AGC_CONTROL__DO_CALIBRATE__CLR(dst) \
50494 (dst) = ((dst) &\
50507 #define AGC_CONTROL__DO_NOISEFLOOR__MODIFY(dst, src) \
50508 (dst) = ((dst) &\
50514 #define AGC_CONTROL__DO_NOISEFLOOR__SET(dst) \
50515 (dst) = ((dst) &\
50517 #define AGC_CONTROL__DO_NOISEFLOOR__CLR(dst) \
50518 (dst) = ((dst) &\
50531 #define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MODIFY(dst, src) \
50532 (dst) = ((dst) &\
50549 #define AGC_CONTROL__YCOK_MAX__MODIFY(dst, src) \
50550 (dst) = ((dst) &\
50567 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MODIFY(dst, src) \
50568 (dst) = ((dst) &\
50574 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__SET(dst) \
50575 (dst) = ((dst) &\
50577 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__CLR(dst) \
50578 (dst) = ((dst) &\
50591 #define AGC_CONTROL__CAL_ENABLE__MODIFY(dst, src) \
50592 (dst) = ((dst) &\
50598 #define AGC_CONTROL__CAL_ENABLE__SET(dst) \
50599 (dst) = ((dst) &\
50601 #define AGC_CONTROL__CAL_ENABLE__CLR(dst) \
50602 (dst) = ((dst) &\
50615 #define AGC_CONTROL__USE_TABLE_SEED__MODIFY(dst, src) \
50616 (dst) = ((dst) &\
50622 #define AGC_CONTROL__USE_TABLE_SEED__SET(dst) \
50623 (dst) = ((dst) &\
50625 #define AGC_CONTROL__USE_TABLE_SEED__CLR(dst) \
50626 (dst) = ((dst) &\
50639 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MODIFY(dst, src) \
50640 (dst) = ((dst) &\
50646 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__SET(dst) \
50647 (dst) = ((dst) &\
50649 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__CLR(dst) \
50650 (dst) = ((dst) &\
50663 #define AGC_CONTROL__ENABLE_NOISEFLOOR__MODIFY(dst, src) \
50664 (dst) = ((dst) &\
50670 #define AGC_CONTROL__ENABLE_NOISEFLOOR__SET(dst) \
50671 (dst) = ((dst) &\
50673 #define AGC_CONTROL__ENABLE_NOISEFLOOR__CLR(dst) \
50674 (dst) = ((dst) &\
50687 #define AGC_CONTROL__ENABLE_FLTR_CAL__MODIFY(dst, src) \
50688 (dst) = ((dst) &\
50694 #define AGC_CONTROL__ENABLE_FLTR_CAL__SET(dst) \
50695 (dst) = ((dst) &\
50697 #define AGC_CONTROL__ENABLE_FLTR_CAL__CLR(dst) \
50698 (dst) = ((dst) &\
50711 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MODIFY(dst, src) \
50712 (dst) = ((dst) &\
50718 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__SET(dst) \
50719 (dst) = ((dst) &\
50721 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__CLR(dst) \
50722 (dst) = ((dst) &\
50735 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MODIFY(dst, src) \
50736 (dst) = ((dst) &\
50742 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__SET(dst) \
50743 (dst) = ((dst) &\
50745 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__CLR(dst) \
50746 (dst) = ((dst) &\
50756 #define AGC_CONTROL__CLC_SUCCESS__SET(dst) \
50757 (dst) = ((dst) &\
50759 #define AGC_CONTROL__CLC_SUCCESS__CLR(dst) \
50760 (dst) = ((dst) &\
50773 #define AGC_CONTROL__ENABLE_PKDET_CAL__MODIFY(dst, src) \
50774 (dst) = ((dst) &\
50780 #define AGC_CONTROL__ENABLE_PKDET_CAL__SET(dst) \
50781 (dst) = ((dst) &\
50783 #define AGC_CONTROL__ENABLE_PKDET_CAL__CLR(dst) \
50784 (dst) = ((dst) &\
50810 #define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MODIFY(dst, src) \
50811 (dst) = ((dst) &\
50828 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MODIFY(dst, src) \
50829 (dst) = ((dst) &\
50835 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__SET(dst) \
50836 (dst) = ((dst) &\
50838 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__CLR(dst) \
50839 (dst) = ((dst) &\
50861 #define FCAL_1__FLC_PB_FSTEP__MODIFY(dst, src) \
50862 (dst) = ((dst) &\
50879 #define FCAL_1__FLC_SB_FSTEP__MODIFY(dst, src) \
50880 (dst) = ((dst) &\
50897 #define FCAL_1__FLC_PB_ATTEN__MODIFY(dst, src) \
50898 (dst) = ((dst) &\
50915 #define FCAL_1__FLC_SB_ATTEN__MODIFY(dst, src) \
50916 (dst) = ((dst) &\
50942 #define FCAL_2_B0__FLC_PWR_THRESH__MODIFY(dst, src) \
50943 (dst) = ((dst) &\
50960 #define FCAL_2_B0__FLC_SW_CAP_VAL_0__MODIFY(dst, src) \
50961 (dst) = ((dst) &\
50978 #define FCAL_2_B0__FLC_BBMISCGAIN__MODIFY(dst, src) \
50979 (dst) = ((dst) &\
50996 #define FCAL_2_B0__FLC_BB1DBGAIN__MODIFY(dst, src) \
50997 (dst) = ((dst) &\
51014 #define FCAL_2_B0__FLC_BB6DBGAIN__MODIFY(dst, src) \
51015 (dst) = ((dst) &\
51032 #define FCAL_2_B0__FLC_SW_CAP_SET__MODIFY(dst, src) \
51033 (dst) = ((dst) &\
51039 #define FCAL_2_B0__FLC_SW_CAP_SET__SET(dst) \
51040 (dst) = ((dst) &\
51042 #define FCAL_2_B0__FLC_SW_CAP_SET__CLR(dst) \
51043 (dst) = ((dst) &\
51056 #define FCAL_2_B0__FLC_MEAS_WIN__MODIFY(dst, src) \
51057 (dst) = ((dst) &\
51095 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MODIFY(dst, src) \
51096 (dst) = ((dst) &\
51102 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__SET(dst) \
51103 (dst) = ((dst) &\
51105 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__CLR(dst) \
51106 (dst) = ((dst) &\
51119 #define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MODIFY(dst, src) \
51120 (dst) = ((dst) &\
51137 #define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MODIFY(dst, src) \
51138 (dst) = ((dst) &\
51168 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MODIFY(dst, src) \
51169 (dst) = ((dst) &\
51175 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__SET(dst) \
51176 (dst) = ((dst) &\
51178 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__CLR(dst) \
51179 (dst) = ((dst) &\
51192 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MODIFY(dst, src) \
51193 (dst) = ((dst) &\
51199 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__SET(dst) \
51200 (dst) = ((dst) &\
51202 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__CLR(dst) \
51203 (dst) = ((dst) &\
51216 #define CL_CAL_CTRL__CF_CLC_TEST_POINT__MODIFY(dst, src) \
51217 (dst) = ((dst) &\
51234 #define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MODIFY(dst, src) \
51235 (dst) = ((dst) &\
51252 #define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MODIFY(dst, src) \
51253 (dst) = ((dst) &\
51270 #define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MODIFY(dst, src) \
51271 (dst) = ((dst) &\
51288 #define CL_CAL_CTRL__CF_ADC_BOUND__MODIFY(dst, src) \
51289 (dst) = ((dst) &\
51306 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MODIFY(dst, src) \
51307 (dst) = ((dst) &\
51313 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__SET(dst) \
51314 (dst) = ((dst) &\
51316 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__CLR(dst) \
51317 (dst) = ((dst) &\
51330 #define CL_CAL_CTRL__CL_MAP_HW_GEN__MODIFY(dst, src) \
51331 (dst) = ((dst) &\
51337 #define CL_CAL_CTRL__CL_MAP_HW_GEN__SET(dst) \
51338 (dst) = ((dst) &\
51340 #define CL_CAL_CTRL__CL_MAP_HW_GEN__CLR(dst) \
51341 (dst) = ((dst) &\
51363 #define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
51364 (dst) = ((dst) &\
51388 #define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
51389 (dst) = ((dst) &\
51413 #define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
51414 (dst) = ((dst) &\
51438 #define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
51439 (dst) = ((dst) &\
51463 #define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
51464 (dst) = ((dst) &\
51490 #define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
51491 (dst) = ((dst) &\
51517 #define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
51518 (dst) = ((dst) &\
51544 #define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
51545 (dst) = ((dst) &\
51571 #define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
51572 (dst) = ((dst) &\
51587 #define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
51588 (dst) = ((dst) &\
51605 #define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
51606 (dst) = ((dst) &\
51619 #define CL_TAB__BB_GAIN__MODIFY(dst, src) \
51620 (dst) = ((dst) &\
51646 #define SYNTH_CONTROL__RFCHANFRAC__MODIFY(dst, src) \
51647 (dst) = ((dst) &\
51664 #define SYNTH_CONTROL__RFCHANNEL__MODIFY(dst, src) \
51665 (dst) = ((dst) &\
51682 #define SYNTH_CONTROL__RFAMODEREFSEL__MODIFY(dst, src) \
51683 (dst) = ((dst) &\
51700 #define SYNTH_CONTROL__RFFRACMODE__MODIFY(dst, src) \
51701 (dst) = ((dst) &\
51707 #define SYNTH_CONTROL__RFFRACMODE__SET(dst) \
51708 (dst) = ((dst) &\
51710 #define SYNTH_CONTROL__RFFRACMODE__CLR(dst) \
51711 (dst) = ((dst) &\
51724 #define SYNTH_CONTROL__RFBMODE__MODIFY(dst, src) \
51725 (dst) = ((dst) &\
51731 #define SYNTH_CONTROL__RFBMODE__SET(dst) \
51732 (dst) = ((dst) &\
51734 #define SYNTH_CONTROL__RFBMODE__CLR(dst) \
51735 (dst) = ((dst) &\
51748 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MODIFY(dst, src) \
51749 (dst) = ((dst) &\
51755 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__SET(dst) \
51756 (dst) = ((dst) &\
51758 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__CLR(dst) \
51759 (dst) = ((dst) &\
51785 #define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MODIFY(dst, src) \
51786 (dst) = ((dst) &\
51803 #define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MODIFY(dst, src) \
51804 (dst) = ((dst) &\
51830 #define PLL_CNTL__BB_PLL_DIV__MODIFY(dst, src) \
51831 (dst) = ((dst) &\
51848 #define PLL_CNTL__BB_PLL_REFDIV__MODIFY(dst, src) \
51849 (dst) = ((dst) &\
51866 #define PLL_CNTL__BB_PLL_CLK_SEL__MODIFY(dst, src) \
51867 (dst) = ((dst) &\
51884 #define PLL_CNTL__BB_PLLBYPASS__MODIFY(dst, src) \
51885 (dst) = ((dst) &\
51891 #define PLL_CNTL__BB_PLLBYPASS__SET(dst) \
51892 (dst) = ((dst) &\
51894 #define PLL_CNTL__BB_PLLBYPASS__CLR(dst) \
51895 (dst) = ((dst) &\
51908 #define PLL_CNTL__BB_PLL_SETTLE_TIME__MODIFY(dst, src) \
51909 (dst) = ((dst) &\
51939 #define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MODIFY(dst, src) \
51940 (dst) = ((dst) &\
51957 #define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MODIFY(dst, src) \
51958 (dst) = ((dst) &\
51975 #define ANALOG_SWAP__SWAP_ALT_CHN__MODIFY(dst, src) \
51976 (dst) = ((dst) &\
51982 #define ANALOG_SWAP__SWAP_ALT_CHN__SET(dst) \
51983 (dst) = ((dst) &\
51985 #define ANALOG_SWAP__SWAP_ALT_CHN__CLR(dst) \
51986 (dst) = ((dst) &\
51999 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MODIFY(dst, src) \
52000 (dst) = ((dst) &\
52006 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__SET(dst) \
52007 (dst) = ((dst) &\
52009 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__CLR(dst) \
52010 (dst) = ((dst) &\
52023 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MODIFY(dst, src) \
52024 (dst) = ((dst) &\
52030 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__SET(dst) \
52031 (dst) = ((dst) &\
52033 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__CLR(dst) \
52034 (dst) = ((dst) &\
52060 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MODIFY(dst, src) \
52061 (dst) = ((dst) &\
52067 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__SET(dst) \
52068 (dst) = ((dst) &\
52070 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__CLR(dst) \
52071 (dst) = ((dst) &\
52084 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MODIFY(dst, src) \
52085 (dst) = ((dst) &\
52091 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__SET(dst) \
52092 (dst) = ((dst) &\
52094 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__CLR(dst) \
52095 (dst) = ((dst) &\
52108 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MODIFY(dst, src) \
52109 (dst) = ((dst) &\
52115 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__SET(dst) \
52116 (dst) = ((dst) &\
52118 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__CLR(dst) \
52119 (dst) = ((dst) &\
52132 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MODIFY(dst, src) \
52133 (dst) = ((dst) &\
52139 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__SET(dst) \
52140 (dst) = ((dst) &\
52142 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__CLR(dst) \
52143 (dst) = ((dst) &\
52156 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MODIFY(dst, src) \
52157 (dst) = ((dst) &\
52163 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__SET(dst) \
52164 (dst) = ((dst) &\
52166 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__CLR(dst) \
52167 (dst) = ((dst) &\
52180 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MODIFY(dst, src) \
52181 (dst) = ((dst) &\
52187 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__SET(dst) \
52188 (dst) = ((dst) &\
52190 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__CLR(dst) \
52191 (dst) = ((dst) &\
52213 #define FORCE_ANALOG__FORCE_XPAON__MODIFY(dst, src) \
52214 (dst) = ((dst) &\
52220 #define FORCE_ANALOG__FORCE_XPAON__SET(dst) \
52221 (dst) = ((dst) &\
52223 #define FORCE_ANALOG__FORCE_XPAON__CLR(dst) \
52224 (dst) = ((dst) &\
52237 #define FORCE_ANALOG__FORCED_XPAON__MODIFY(dst, src) \
52238 (dst) = ((dst) &\
52255 #define FORCE_ANALOG__FORCE_PDADC_PWD__MODIFY(dst, src) \
52256 (dst) = ((dst) &\
52262 #define FORCE_ANALOG__FORCE_PDADC_PWD__SET(dst) \
52263 (dst) = ((dst) &\
52265 #define FORCE_ANALOG__FORCE_PDADC_PWD__CLR(dst) \
52266 (dst) = ((dst) &\
52279 #define FORCE_ANALOG__FORCED_PDADC_PWD__MODIFY(dst, src) \
52280 (dst) = ((dst) &\
52308 #define TEST_CONTROLS__CF_TSTTRIG_SEL__MODIFY(dst, src) \
52309 (dst) = ((dst) &\
52326 #define TEST_CONTROLS__CF_TSTTRIG__MODIFY(dst, src) \
52327 (dst) = ((dst) &\
52333 #define TEST_CONTROLS__CF_TSTTRIG__SET(dst) \
52334 (dst) = ((dst) &\
52336 #define TEST_CONTROLS__CF_TSTTRIG__CLR(dst) \
52337 (dst) = ((dst) &\
52350 #define TEST_CONTROLS__CF_RFSHIFT_SEL__MODIFY(dst, src) \
52351 (dst) = ((dst) &\
52368 #define TEST_CONTROLS__CARDBUS_MODE__MODIFY(dst, src) \
52369 (dst) = ((dst) &\
52386 #define TEST_CONTROLS__CLKOUT_IS_CLK32__MODIFY(dst, src) \
52387 (dst) = ((dst) &\
52393 #define TEST_CONTROLS__CLKOUT_IS_CLK32__SET(dst) \
52394 (dst) = ((dst) &\
52396 #define TEST_CONTROLS__CLKOUT_IS_CLK32__CLR(dst) \
52397 (dst) = ((dst) &\
52410 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__MODIFY(dst, src) \
52411 (dst) = ((dst) &\
52417 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__SET(dst) \
52418 (dst) = ((dst) &\
52420 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__CLR(dst) \
52421 (dst) = ((dst) &\
52434 #define TEST_CONTROLS__ENABLE_MINI_OBS__MODIFY(dst, src) \
52435 (dst) = ((dst) &\
52441 #define TEST_CONTROLS__ENABLE_MINI_OBS__SET(dst) \
52442 (dst) = ((dst) &\
52444 #define TEST_CONTROLS__ENABLE_MINI_OBS__CLR(dst) \
52445 (dst) = ((dst) &\
52458 #define TEST_CONTROLS__SLOW_CLK160__MODIFY(dst, src) \
52459 (dst) = ((dst) &\
52465 #define TEST_CONTROLS__SLOW_CLK160__SET(dst) \
52466 (dst) = ((dst) &\
52468 #define TEST_CONTROLS__SLOW_CLK160__CLR(dst) \
52469 (dst) = ((dst) &\
52482 #define TEST_CONTROLS__AGC_OBS_SEL_3__MODIFY(dst, src) \
52483 (dst) = ((dst) &\
52489 #define TEST_CONTROLS__AGC_OBS_SEL_3__SET(dst) \
52490 (dst) = ((dst) &\
52492 #define TEST_CONTROLS__AGC_OBS_SEL_3__CLR(dst) \
52493 (dst) = ((dst) &\
52506 #define TEST_CONTROLS__CF_BBB_OBS_SEL__MODIFY(dst, src) \
52507 (dst) = ((dst) &\
52524 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MODIFY(dst, src) \
52525 (dst) = ((dst) &\
52531 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__SET(dst) \
52532 (dst) = ((dst) &\
52534 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__CLR(dst) \
52535 (dst) = ((dst) &\
52548 #define TEST_CONTROLS__AGC_OBS_SEL_4__MODIFY(dst, src) \
52549 (dst) = ((dst) &\
52555 #define TEST_CONTROLS__AGC_OBS_SEL_4__SET(dst) \
52556 (dst) = ((dst) &\
52558 #define TEST_CONTROLS__AGC_OBS_SEL_4__CLR(dst) \
52559 (dst) = ((dst) &\
52572 #define TEST_CONTROLS__FORCE_AGC_CLEAR__MODIFY(dst, src) \
52573 (dst) = ((dst) &\
52579 #define TEST_CONTROLS__FORCE_AGC_CLEAR__SET(dst) \
52580 (dst) = ((dst) &\
52582 #define TEST_CONTROLS__FORCE_AGC_CLEAR__CLR(dst) \
52583 (dst) = ((dst) &\
52596 #define TEST_CONTROLS__TSTDAC_OUT_SEL__MODIFY(dst, src) \
52597 (dst) = ((dst) &\
52627 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MODIFY(dst, src) \
52628 (dst) = ((dst) &\
52634 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__SET(dst) \
52635 (dst) = ((dst) &\
52637 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__CLR(dst) \
52638 (dst) = ((dst) &\
52651 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MODIFY(dst, src) \
52652 (dst) = ((dst) &\
52658 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__SET(dst) \
52659 (dst) = ((dst) &\
52661 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__CLR(dst) \
52662 (dst) = ((dst) &\
52675 #define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MODIFY(dst, src) \
52676 (dst) = ((dst) &\
52693 #define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MODIFY(dst, src) \
52694 (dst) = ((dst) &\
52711 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MODIFY(dst, src) \
52712 (dst) = ((dst) &\
52718 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__SET(dst) \
52719 (dst) = ((dst) &\
52721 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__CLR(dst) \
52722 (dst) = ((dst) &\
52735 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MODIFY(dst, src) \
52736 (dst) = ((dst) &\
52742 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__SET(dst) \
52743 (dst) = ((dst) &\
52745 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__CLR(dst) \
52746 (dst) = ((dst) &\
52759 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MODIFY(dst, src) \
52760 (dst) = ((dst) &\
52766 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__SET(dst) \
52767 (dst) = ((dst) &\
52769 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__CLR(dst) \
52770 (dst) = ((dst) &\
52783 #define TEST_CONTROLS_STATUS__RX_OBS_SEL__MODIFY(dst, src) \
52784 (dst) = ((dst) &\
52801 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MODIFY(dst, src) \
52802 (dst) = ((dst) &\
52808 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__SET(dst) \
52809 (dst) = ((dst) &\
52811 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__CLR(dst) \
52812 (dst) = ((dst) &\
52825 #define TEST_CONTROLS_STATUS__RESET_A2__MODIFY(dst, src) \
52826 (dst) = ((dst) &\
52832 #define TEST_CONTROLS_STATUS__RESET_A2__SET(dst) \
52833 (dst) = ((dst) &\
52835 #define TEST_CONTROLS_STATUS__RESET_A2__CLR(dst) \
52836 (dst) = ((dst) &\
52849 #define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MODIFY(dst, src) \
52850 (dst) = ((dst) &\
52867 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MODIFY(dst, src) \
52868 (dst) = ((dst) &\
52874 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__SET(dst) \
52875 (dst) = ((dst) &\
52877 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__CLR(dst) \
52878 (dst) = ((dst) &\
52891 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MODIFY(dst, src) \
52892 (dst) = ((dst) &\
52898 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__SET(dst) \
52899 (dst) = ((dst) &\
52901 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__CLR(dst) \
52902 (dst) = ((dst) &\
52915 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MODIFY(dst, src) \
52916 (dst) = ((dst) &\
52922 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__SET(dst) \
52923 (dst) = ((dst) &\
52925 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__CLR(dst) \
52926 (dst) = ((dst) &\
52939 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MODIFY(dst, src) \
52940 (dst) = ((dst) &\
52946 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__SET(dst) \
52947 (dst) = ((dst) &\
52949 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__CLR(dst) \
52950 (dst) = ((dst) &\
52963 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MODIFY(dst, src) \
52964 (dst) = ((dst) &\
53015 #define CHANNEL_STATUS__BT_ACTIVE__SET(dst) \
53016 (dst) = ((dst) &\
53018 #define CHANNEL_STATUS__BT_ACTIVE__CLR(dst) \
53019 (dst) = ((dst) &\
53029 #define CHANNEL_STATUS__RX_CLEAR_RAW__SET(dst) \
53030 (dst) = ((dst) &\
53032 #define CHANNEL_STATUS__RX_CLEAR_RAW__CLR(dst) \
53033 (dst) = ((dst) &\
53043 #define CHANNEL_STATUS__RX_CLEAR_MAC__SET(dst) \
53044 (dst) = ((dst) &\
53046 #define CHANNEL_STATUS__RX_CLEAR_MAC__CLR(dst) \
53047 (dst) = ((dst) &\
53057 #define CHANNEL_STATUS__RX_CLEAR_PAD__SET(dst) \
53058 (dst) = ((dst) &\
53060 #define CHANNEL_STATUS__RX_CLEAR_PAD__CLR(dst) \
53061 (dst) = ((dst) &\
53126 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MODIFY(dst, src) \
53127 (dst) = ((dst) &\
53133 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__SET(dst) \
53134 (dst) = ((dst) &\
53136 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__CLR(dst) \
53137 (dst) = ((dst) &\
53150 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MODIFY(dst, src) \
53151 (dst) = ((dst) &\
53157 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__SET(dst) \
53158 (dst) = ((dst) &\
53160 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__CLR(dst) \
53161 (dst) = ((dst) &\
53174 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MODIFY(dst, src) \
53175 (dst) = ((dst) &\
53181 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__SET(dst) \
53182 (dst) = ((dst) &\
53184 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__CLR(dst) \
53185 (dst) = ((dst) &\
53198 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MODIFY(dst, src) \
53199 (dst) = ((dst) &\
53205 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__SET(dst) \
53206 (dst) = ((dst) &\
53208 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__CLR(dst) \
53209 (dst) = ((dst) &\
53338 #define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__SET(dst) \
53339 (dst) = ((dst) &\
53341 #define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__CLR(dst) \
53342 (dst) = ((dst) &\
53352 #define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__SET(dst) \
53353 (dst) = ((dst) &\
53355 #define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__CLR(dst) \
53356 (dst) = ((dst) &\
53381 #define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MODIFY(dst, src) \
53382 (dst) = ((dst) &\
53412 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__MODIFY(dst, src) \
53413 (dst) = ((dst) &\
53419 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__SET(dst) \
53420 (dst) = ((dst) &\
53422 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__CLR(dst) \
53423 (dst) = ((dst) &\
53436 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MODIFY(dst, src) \
53437 (dst) = ((dst) &\
53443 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__SET(dst) \
53444 (dst) = ((dst) &\
53446 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__CLR(dst) \
53447 (dst) = ((dst) &\
53460 #define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MODIFY(dst, src) \
53461 (dst) = ((dst) &\
53478 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MODIFY(dst, src) \
53479 (dst) = ((dst) &\
53485 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__SET(dst) \
53486 (dst) = ((dst) &\
53488 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__CLR(dst) \
53489 (dst) = ((dst) &\
53502 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MODIFY(dst, src) \
53503 (dst) = ((dst) &\
53509 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__SET(dst) \
53510 (dst) = ((dst) &\
53512 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__CLR(dst) \
53513 (dst) = ((dst) &\
53526 #define BBB_TX_CTRL__TX_CCK_DELAY_1__MODIFY(dst, src) \
53527 (dst) = ((dst) &\
53544 #define BBB_TX_CTRL__TX_CCK_DELAY_2__MODIFY(dst, src) \
53545 (dst) = ((dst) &\
53573 #define BBB_TXFIR_0__TXFIR_COEFF_H0__MODIFY(dst, src) \
53574 (dst) = ((dst) &\
53591 #define BBB_TXFIR_0__TXFIR_COEFF_H1__MODIFY(dst, src) \
53592 (dst) = ((dst) &\
53609 #define BBB_TXFIR_0__TXFIR_COEFF_H2__MODIFY(dst, src) \
53610 (dst) = ((dst) &\
53627 #define BBB_TXFIR_0__TXFIR_COEFF_H3__MODIFY(dst, src) \
53628 (dst) = ((dst) &\
53656 #define BBB_TXFIR_1__TXFIR_COEFF_H4__MODIFY(dst, src) \
53657 (dst) = ((dst) &\
53674 #define BBB_TXFIR_1__TXFIR_COEFF_H5__MODIFY(dst, src) \
53675 (dst) = ((dst) &\
53692 #define BBB_TXFIR_1__TXFIR_COEFF_H6__MODIFY(dst, src) \
53693 (dst) = ((dst) &\
53710 #define BBB_TXFIR_1__TXFIR_COEFF_H7__MODIFY(dst, src) \
53711 (dst) = ((dst) &\
53739 #define BBB_TXFIR_2__TXFIR_COEFF_H8__MODIFY(dst, src) \
53740 (dst) = ((dst) &\
53757 #define BBB_TXFIR_2__TXFIR_COEFF_H9__MODIFY(dst, src) \
53758 (dst) = ((dst) &\
53775 #define BBB_TXFIR_2__TXFIR_COEFF_H10__MODIFY(dst, src) \
53776 (dst) = ((dst) &\
53793 #define BBB_TXFIR_2__TXFIR_COEFF_H11__MODIFY(dst, src) \
53794 (dst) = ((dst) &\
53824 #define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MODIFY(dst, src) \
53825 (dst) = ((dst) &\
53842 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MODIFY(dst, src) \
53843 (dst) = ((dst) &\
53849 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__SET(dst) \
53850 (dst) = ((dst) &\
53852 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__CLR(dst) \
53853 (dst) = ((dst) &\
53866 #define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MODIFY(dst, src) \
53867 (dst) = ((dst) &\
53897 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MODIFY(dst, src) \
53898 (dst) = ((dst) &\
53915 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MODIFY(dst, src) \
53916 (dst) = ((dst) &\
53933 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MODIFY(dst, src) \
53934 (dst) = ((dst) &\
53951 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MODIFY(dst, src) \
53952 (dst) = ((dst) &\
53982 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MODIFY(dst, src) \
53983 (dst) = ((dst) &\
54000 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MODIFY(dst, src) \
54001 (dst) = ((dst) &\
54018 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MODIFY(dst, src) \
54019 (dst) = ((dst) &\
54036 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MODIFY(dst, src) \
54037 (dst) = ((dst) &\
54064 #define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__SET(dst) \
54065 (dst) = ((dst) &\
54067 #define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__CLR(dst) \
54068 (dst) = ((dst) &\
54089 #define POWERTX_RATE1__POWERTX_0__MODIFY(dst, src) \
54090 (dst) = ((dst) &\
54107 #define POWERTX_RATE1__POWERTX_1__MODIFY(dst, src) \
54108 (dst) = ((dst) &\
54125 #define POWERTX_RATE1__POWERTX_2__MODIFY(dst, src) \
54126 (dst) = ((dst) &\
54143 #define POWERTX_RATE1__POWERTX_3__MODIFY(dst, src) \
54144 (dst) = ((dst) &\
54170 #define POWERTX_RATE2__POWERTX_4__MODIFY(dst, src) \
54171 (dst) = ((dst) &\
54188 #define POWERTX_RATE2__POWERTX_5__MODIFY(dst, src) \
54189 (dst) = ((dst) &\
54206 #define POWERTX_RATE2__POWERTX_6__MODIFY(dst, src) \
54207 (dst) = ((dst) &\
54224 #define POWERTX_RATE2__POWERTX_7__MODIFY(dst, src) \
54225 (dst) = ((dst) &\
54251 #define POWERTX_RATE3__POWERTX_1L__MODIFY(dst, src) \
54252 (dst) = ((dst) &\
54269 #define POWERTX_RATE3__POWERTX_2L__MODIFY(dst, src) \
54270 (dst) = ((dst) &\
54287 #define POWERTX_RATE3__POWERTX_2S__MODIFY(dst, src) \
54288 (dst) = ((dst) &\
54314 #define POWERTX_RATE4__POWERTX_55L__MODIFY(dst, src) \
54315 (dst) = ((dst) &\
54332 #define POWERTX_RATE4__POWERTX_55S__MODIFY(dst, src) \
54333 (dst) = ((dst) &\
54350 #define POWERTX_RATE4__POWERTX_11L__MODIFY(dst, src) \
54351 (dst) = ((dst) &\
54368 #define POWERTX_RATE4__POWERTX_11S__MODIFY(dst, src) \
54369 (dst) = ((dst) &\
54397 #define POWERTX_RATE5__POWERTXHT20_0__MODIFY(dst, src) \
54398 (dst) = ((dst) &\
54415 #define POWERTX_RATE5__POWERTXHT20_1__MODIFY(dst, src) \
54416 (dst) = ((dst) &\
54433 #define POWERTX_RATE5__POWERTXHT20_2__MODIFY(dst, src) \
54434 (dst) = ((dst) &\
54451 #define POWERTX_RATE5__POWERTXHT20_3__MODIFY(dst, src) \
54452 (dst) = ((dst) &\
54480 #define POWERTX_RATE6__POWERTXHT20_4__MODIFY(dst, src) \
54481 (dst) = ((dst) &\
54498 #define POWERTX_RATE6__POWERTXHT20_5__MODIFY(dst, src) \
54499 (dst) = ((dst) &\
54516 #define POWERTX_RATE6__POWERTXHT20_6__MODIFY(dst, src) \
54517 (dst) = ((dst) &\
54534 #define POWERTX_RATE6__POWERTXHT20_7__MODIFY(dst, src) \
54535 (dst) = ((dst) &\
54563 #define POWERTX_RATE7__POWERTXHT40_0__MODIFY(dst, src) \
54564 (dst) = ((dst) &\
54581 #define POWERTX_RATE7__POWERTXHT40_1__MODIFY(dst, src) \
54582 (dst) = ((dst) &\
54599 #define POWERTX_RATE7__POWERTXHT40_2__MODIFY(dst, src) \
54600 (dst) = ((dst) &\
54617 #define POWERTX_RATE7__POWERTXHT40_3__MODIFY(dst, src) \
54618 (dst) = ((dst) &\
54646 #define POWERTX_RATE8__POWERTXHT40_4__MODIFY(dst, src) \
54647 (dst) = ((dst) &\
54664 #define POWERTX_RATE8__POWERTXHT40_5__MODIFY(dst, src) \
54665 (dst) = ((dst) &\
54682 #define POWERTX_RATE8__POWERTXHT40_6__MODIFY(dst, src) \
54683 (dst) = ((dst) &\
54700 #define POWERTX_RATE8__POWERTXHT40_7__MODIFY(dst, src) \
54701 (dst) = ((dst) &\
54731 #define POWERTX_RATE9__POWERTX_DUP40_CCK__MODIFY(dst, src) \
54732 (dst) = ((dst) &\
54749 #define POWERTX_RATE9__POWERTX_DUP40_OFDM__MODIFY(dst, src) \
54750 (dst) = ((dst) &\
54767 #define POWERTX_RATE9__POWERTX_EXT20_CCK__MODIFY(dst, src) \
54768 (dst) = ((dst) &\
54785 #define POWERTX_RATE9__POWERTX_EXT20_OFDM__MODIFY(dst, src) \
54786 (dst) = ((dst) &\
54814 #define POWERTX_RATE10__POWERTXHT20_8__MODIFY(dst, src) \
54815 (dst) = ((dst) &\
54832 #define POWERTX_RATE10__POWERTXHT20_9__MODIFY(dst, src) \
54833 (dst) = ((dst) &\
54850 #define POWERTX_RATE10__POWERTXHT20_10__MODIFY(dst, src) \
54851 (dst) = ((dst) &\
54868 #define POWERTX_RATE10__POWERTXHT20_11__MODIFY(dst, src) \
54869 (dst) = ((dst) &\
54899 #define POWERTX_RATE11__POWERTXHT20_12__MODIFY(dst, src) \
54900 (dst) = ((dst) &\
54917 #define POWERTX_RATE11__POWERTXHT20_13__MODIFY(dst, src) \
54918 (dst) = ((dst) &\
54935 #define POWERTX_RATE11__POWERTXHT40_12__MODIFY(dst, src) \
54936 (dst) = ((dst) &\
54953 #define POWERTX_RATE11__POWERTXHT40_13__MODIFY(dst, src) \
54954 (dst) = ((dst) &\
54982 #define POWERTX_RATE12__POWERTXHT40_8__MODIFY(dst, src) \
54983 (dst) = ((dst) &\
55000 #define POWERTX_RATE12__POWERTXHT40_9__MODIFY(dst, src) \
55001 (dst) = ((dst) &\
55018 #define POWERTX_RATE12__POWERTXHT40_10__MODIFY(dst, src) \
55019 (dst) = ((dst) &\
55036 #define POWERTX_RATE12__POWERTXHT40_11__MODIFY(dst, src) \
55037 (dst) = ((dst) &\
55067 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MODIFY(dst, src) \
55068 (dst) = ((dst) &\
55074 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__SET(dst) \
55075 (dst) = ((dst) &\
55077 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__CLR(dst) \
55078 (dst) = ((dst) &\
55104 #define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MODIFY(dst, src) \
55105 (dst) = ((dst) &\
55122 #define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MODIFY(dst, src) \
55123 (dst) = ((dst) &\
55149 #define TPC_1__FORCE_DAC_GAIN__MODIFY(dst, src) \
55150 (dst) = ((dst) &\
55156 #define TPC_1__FORCE_DAC_GAIN__SET(dst) \
55157 (dst) = ((dst) &\
55159 #define TPC_1__FORCE_DAC_GAIN__CLR(dst) \
55160 (dst) = ((dst) &\
55173 #define TPC_1__FORCED_DAC_GAIN__MODIFY(dst, src) \
55174 (dst) = ((dst) &\
55191 #define TPC_1__PD_DC_OFFSET_TARGET__MODIFY(dst, src) \
55192 (dst) = ((dst) &\
55205 #define TPC_1__NUM_PD_GAIN__MODIFY(dst, src) \
55206 (dst) = ((dst) &\
55223 #define TPC_1__PD_GAIN_SETTING1__MODIFY(dst, src) \
55224 (dst) = ((dst) &\
55241 #define TPC_1__PD_GAIN_SETTING2__MODIFY(dst, src) \
55242 (dst) = ((dst) &\
55259 #define TPC_1__PD_GAIN_SETTING3__MODIFY(dst, src) \
55260 (dst) = ((dst) &\
55277 #define TPC_1__ENABLE_PD_CALIBRATE__MODIFY(dst, src) \
55278 (dst) = ((dst) &\
55284 #define TPC_1__ENABLE_PD_CALIBRATE__SET(dst) \
55285 (dst) = ((dst) &\
55287 #define TPC_1__ENABLE_PD_CALIBRATE__CLR(dst) \
55288 (dst) = ((dst) &\
55301 #define TPC_1__PD_CALIBRATE_WAIT__MODIFY(dst, src) \
55302 (dst) = ((dst) &\
55319 #define TPC_1__FORCE_PDADC_GAIN__MODIFY(dst, src) \
55320 (dst) = ((dst) &\
55326 #define TPC_1__FORCE_PDADC_GAIN__SET(dst) \
55327 (dst) = ((dst) &\
55329 #define TPC_1__FORCE_PDADC_GAIN__CLR(dst) \
55330 (dst) = ((dst) &\
55343 #define TPC_1__FORCED_PDADC_GAIN__MODIFY(dst, src) \
55344 (dst) = ((dst) &\
55372 #define TPC_2__TX_FRAME_TO_PDADC_ON__MODIFY(dst, src) \
55373 (dst) = ((dst) &\
55390 #define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MODIFY(dst, src) \
55391 (dst) = ((dst) &\
55408 #define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MODIFY(dst, src) \
55409 (dst) = ((dst) &\
55435 #define TPC_3__TX_END_TO_PDADC_ON__MODIFY(dst, src) \
55436 (dst) = ((dst) &\
55453 #define TPC_3__TX_END_TO_PD_ACC_ON__MODIFY(dst, src) \
55454 (dst) = ((dst) &\
55471 #define TPC_3__PD_ACC_WINDOW_DC_OFF__MODIFY(dst, src) \
55472 (dst) = ((dst) &\
55489 #define TPC_3__PD_ACC_WINDOW_CAL__MODIFY(dst, src) \
55490 (dst) = ((dst) &\
55507 #define TPC_3__PD_ACC_WINDOW_OFDM__MODIFY(dst, src) \
55508 (dst) = ((dst) &\
55525 #define TPC_3__PD_ACC_WINDOW_CCK__MODIFY(dst, src) \
55526 (dst) = ((dst) &\
55543 #define TPC_3__TPC_CLK_GATE_ENABLE__MODIFY(dst, src) \
55544 (dst) = ((dst) &\
55550 #define TPC_3__TPC_CLK_GATE_ENABLE__SET(dst) \
55551 (dst) = ((dst) &\
55553 #define TPC_3__TPC_CLK_GATE_ENABLE__CLR(dst) \
55554 (dst) = ((dst) &\
55575 #define TPC_4_B0__PD_AVG_VALID_0__SET(dst) \
55576 (dst) = ((dst) &\
55578 #define TPC_4_B0__PD_AVG_VALID_0__CLR(dst) \
55579 (dst) = ((dst) &\
55622 #define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MODIFY(dst, src) \
55623 (dst) = ((dst) &\
55649 #define TPC_5_B0__PD_GAIN_OVERLAP__MODIFY(dst, src) \
55650 (dst) = ((dst) &\
55667 #define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MODIFY(dst, src) \
55668 (dst) = ((dst) &\
55685 #define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MODIFY(dst, src) \
55686 (dst) = ((dst) &\
55703 #define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MODIFY(dst, src) \
55704 (dst) = ((dst) &\
55721 #define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MODIFY(dst, src) \
55722 (dst) = ((dst) &\
55750 #define TPC_6_B0__PD_DAC_SETTING_1_0__MODIFY(dst, src) \
55751 (dst) = ((dst) &\
55768 #define TPC_6_B0__PD_DAC_SETTING_2_0__MODIFY(dst, src) \
55769 (dst) = ((dst) &\
55786 #define TPC_6_B0__PD_DAC_SETTING_3_0__MODIFY(dst, src) \
55787 (dst) = ((dst) &\
55804 #define TPC_6_B0__PD_DAC_SETTING_4_0__MODIFY(dst, src) \
55805 (dst) = ((dst) &\
55822 #define TPC_6_B0__ERROR_EST_MODE__MODIFY(dst, src) \
55823 (dst) = ((dst) &\
55840 #define TPC_6_B0__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
55841 (dst) = ((dst) &\
55867 #define TPC_7__TX_GAIN_TABLE_MAX__MODIFY(dst, src) \
55868 (dst) = ((dst) &\
55885 #define TPC_7__INIT_TX_GAIN_SETTING__MODIFY(dst, src) \
55886 (dst) = ((dst) &\
55903 #define TPC_7__EN_CL_GAIN_MOD__MODIFY(dst, src) \
55904 (dst) = ((dst) &\
55910 #define TPC_7__EN_CL_GAIN_MOD__SET(dst) \
55911 (dst) = ((dst) &\
55913 #define TPC_7__EN_CL_GAIN_MOD__CLR(dst) \
55914 (dst) = ((dst) &\
55927 #define TPC_7__USE_TX_PD_IN_XPA__MODIFY(dst, src) \
55928 (dst) = ((dst) &\
55934 #define TPC_7__USE_TX_PD_IN_XPA__SET(dst) \
55935 (dst) = ((dst) &\
55937 #define TPC_7__USE_TX_PD_IN_XPA__CLR(dst) \
55938 (dst) = ((dst) &\
55951 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MODIFY(dst, src) \
55952 (dst) = ((dst) &\
55958 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__SET(dst) \
55959 (dst) = ((dst) &\
55961 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__CLR(dst) \
55962 (dst) = ((dst) &\
55975 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MODIFY(dst, src) \
55976 (dst) = ((dst) &\
55982 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__SET(dst) \
55983 (dst) = ((dst) &\
55985 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__CLR(dst) \
55986 (dst) = ((dst) &\
56008 #define TPC_8__DESIRED_SCALE_0__MODIFY(dst, src) \
56009 (dst) = ((dst) &\
56026 #define TPC_8__DESIRED_SCALE_1__MODIFY(dst, src) \
56027 (dst) = ((dst) &\
56044 #define TPC_8__DESIRED_SCALE_2__MODIFY(dst, src) \
56045 (dst) = ((dst) &\
56062 #define TPC_8__DESIRED_SCALE_3__MODIFY(dst, src) \
56063 (dst) = ((dst) &\
56080 #define TPC_8__DESIRED_SCALE_4__MODIFY(dst, src) \
56081 (dst) = ((dst) &\
56098 #define TPC_8__DESIRED_SCALE_5__MODIFY(dst, src) \
56099 (dst) = ((dst) &\
56125 #define TPC_9__DESIRED_SCALE_6__MODIFY(dst, src) \
56126 (dst) = ((dst) &\
56143 #define TPC_9__DESIRED_SCALE_7__MODIFY(dst, src) \
56144 (dst) = ((dst) &\
56161 #define TPC_9__DESIRED_SCALE_CCK__MODIFY(dst, src) \
56162 (dst) = ((dst) &\
56179 #define TPC_9__EN_PD_DC_OFFSET_THR__MODIFY(dst, src) \
56180 (dst) = ((dst) &\
56186 #define TPC_9__EN_PD_DC_OFFSET_THR__SET(dst) \
56187 (dst) = ((dst) &\
56189 #define TPC_9__EN_PD_DC_OFFSET_THR__CLR(dst) \
56190 (dst) = ((dst) &\
56203 #define TPC_9__PD_DC_OFFSET_THR__MODIFY(dst, src) \
56204 (dst) = ((dst) &\
56221 #define TPC_9__WAIT_CALTX_SETTLE__MODIFY(dst, src) \
56222 (dst) = ((dst) &\
56239 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MODIFY(dst, src) \
56240 (dst) = ((dst) &\
56246 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__SET(dst) \
56247 (dst) = ((dst) &\
56249 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__CLR(dst) \
56250 (dst) = ((dst) &\
56274 #define TPC_10__DESIRED_SCALE_HT20_0__MODIFY(dst, src) \
56275 (dst) = ((dst) &\
56292 #define TPC_10__DESIRED_SCALE_HT20_1__MODIFY(dst, src) \
56293 (dst) = ((dst) &\
56310 #define TPC_10__DESIRED_SCALE_HT20_2__MODIFY(dst, src) \
56311 (dst) = ((dst) &\
56328 #define TPC_10__DESIRED_SCALE_HT20_3__MODIFY(dst, src) \
56329 (dst) = ((dst) &\
56346 #define TPC_10__DESIRED_SCALE_HT20_4__MODIFY(dst, src) \
56347 (dst) = ((dst) &\
56364 #define TPC_10__DESIRED_SCALE_HT20_5__MODIFY(dst, src) \
56365 (dst) = ((dst) &\
56395 #define TPC_11_B0__DESIRED_SCALE_HT20_6__MODIFY(dst, src) \
56396 (dst) = ((dst) &\
56413 #define TPC_11_B0__DESIRED_SCALE_HT20_7__MODIFY(dst, src) \
56414 (dst) = ((dst) &\
56431 #define TPC_11_B0__OLPC_GAIN_DELTA_0__MODIFY(dst, src) \
56432 (dst) = ((dst) &\
56449 #define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MODIFY(dst, src) \
56450 (dst) = ((dst) &\
56478 #define TPC_12__DESIRED_SCALE_HT40_0__MODIFY(dst, src) \
56479 (dst) = ((dst) &\
56496 #define TPC_12__DESIRED_SCALE_HT40_1__MODIFY(dst, src) \
56497 (dst) = ((dst) &\
56514 #define TPC_12__DESIRED_SCALE_HT40_2__MODIFY(dst, src) \
56515 (dst) = ((dst) &\
56532 #define TPC_12__DESIRED_SCALE_HT40_3__MODIFY(dst, src) \
56533 (dst) = ((dst) &\
56550 #define TPC_12__DESIRED_SCALE_HT40_4__MODIFY(dst, src) \
56551 (dst) = ((dst) &\
56568 #define TPC_12__DESIRED_SCALE_HT40_5__MODIFY(dst, src) \
56569 (dst) = ((dst) &\
56597 #define TPC_13__DESIRED_SCALE_HT40_6__MODIFY(dst, src) \
56598 (dst) = ((dst) &\
56615 #define TPC_13__DESIRED_SCALE_HT40_7__MODIFY(dst, src) \
56616 (dst) = ((dst) &\
56644 #define TPC_14__DESIRED_SCALE_HT20_8__MODIFY(dst, src) \
56645 (dst) = ((dst) &\
56662 #define TPC_14__DESIRED_SCALE_HT20_9__MODIFY(dst, src) \
56663 (dst) = ((dst) &\
56680 #define TPC_14__DESIRED_SCALE_HT20_10__MODIFY(dst, src) \
56681 (dst) = ((dst) &\
56698 #define TPC_14__DESIRED_SCALE_HT20_11__MODIFY(dst, src) \
56699 (dst) = ((dst) &\
56716 #define TPC_14__DESIRED_SCALE_HT20_12__MODIFY(dst, src) \
56717 (dst) = ((dst) &\
56734 #define TPC_14__DESIRED_SCALE_HT20_13__MODIFY(dst, src) \
56735 (dst) = ((dst) &\
56763 #define TPC_15__DESIRED_SCALE_HT40_8__MODIFY(dst, src) \
56764 (dst) = ((dst) &\
56781 #define TPC_15__DESIRED_SCALE_HT40_9__MODIFY(dst, src) \
56782 (dst) = ((dst) &\
56799 #define TPC_15__DESIRED_SCALE_HT40_10__MODIFY(dst, src) \
56800 (dst) = ((dst) &\
56817 #define TPC_15__DESIRED_SCALE_HT40_11__MODIFY(dst, src) \
56818 (dst) = ((dst) &\
56835 #define TPC_15__DESIRED_SCALE_HT40_12__MODIFY(dst, src) \
56836 (dst) = ((dst) &\
56853 #define TPC_15__DESIRED_SCALE_HT40_13__MODIFY(dst, src) \
56854 (dst) = ((dst) &\
56884 #define TPC_16__PDADC_PAR_CORR_CCK__MODIFY(dst, src) \
56885 (dst) = ((dst) &\
56902 #define TPC_16__PDADC_PAR_CORR_OFDM__MODIFY(dst, src) \
56903 (dst) = ((dst) &\
56920 #define TPC_16__PDADC_PAR_CORR_HT40__MODIFY(dst, src) \
56921 (dst) = ((dst) &\
56947 #define TPC_17__ENABLE_PAL__MODIFY(dst, src) \
56948 (dst) = ((dst) &\
56952 #define TPC_17__ENABLE_PAL__SET(dst) \
56953 (dst) = ((dst) &\
56955 #define TPC_17__ENABLE_PAL__CLR(dst) \
56956 (dst) = ((dst) &\
56969 #define TPC_17__ENABLE_PAL_CCK__MODIFY(dst, src) \
56970 (dst) = ((dst) &\
56976 #define TPC_17__ENABLE_PAL_CCK__SET(dst) \
56977 (dst) = ((dst) &\
56979 #define TPC_17__ENABLE_PAL_CCK__CLR(dst) \
56980 (dst) = ((dst) &\
56993 #define TPC_17__ENABLE_PAL_OFDM_20__MODIFY(dst, src) \
56994 (dst) = ((dst) &\
57000 #define TPC_17__ENABLE_PAL_OFDM_20__SET(dst) \
57001 (dst) = ((dst) &\
57003 #define TPC_17__ENABLE_PAL_OFDM_20__CLR(dst) \
57004 (dst) = ((dst) &\
57017 #define TPC_17__ENABLE_PAL_OFDM_40__MODIFY(dst, src) \
57018 (dst) = ((dst) &\
57024 #define TPC_17__ENABLE_PAL_OFDM_40__SET(dst) \
57025 (dst) = ((dst) &\
57027 #define TPC_17__ENABLE_PAL_OFDM_40__CLR(dst) \
57028 (dst) = ((dst) &\
57041 #define TPC_17__PAL_POWER_THRESHOLD__MODIFY(dst, src) \
57042 (dst) = ((dst) &\
57059 #define TPC_17__FORCE_PAL_LOCKED__MODIFY(dst, src) \
57060 (dst) = ((dst) &\
57066 #define TPC_17__FORCE_PAL_LOCKED__SET(dst) \
57067 (dst) = ((dst) &\
57069 #define TPC_17__FORCE_PAL_LOCKED__CLR(dst) \
57070 (dst) = ((dst) &\
57083 #define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MODIFY(dst, src) \
57084 (dst) = ((dst) &\
57110 #define TPC_18__THERM_CAL_VALUE__MODIFY(dst, src) \
57111 (dst) = ((dst) &\
57128 #define TPC_18__VOLT_CAL_VALUE__MODIFY(dst, src) \
57129 (dst) = ((dst) &\
57146 #define TPC_18__USE_LEGACY_TPC__MODIFY(dst, src) \
57147 (dst) = ((dst) &\
57153 #define TPC_18__USE_LEGACY_TPC__SET(dst) \
57154 (dst) = ((dst) &\
57156 #define TPC_18__USE_LEGACY_TPC__CLR(dst) \
57157 (dst) = ((dst) &\
57170 #define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MODIFY(dst, src) \
57171 (dst) = ((dst) &\
57197 #define TPC_19__ALPHA_THERM__MODIFY(dst, src) \
57198 (dst) = ((dst) &\
57213 #define TPC_19__ALPHA_THERM_PAL_ON__MODIFY(dst, src) \
57214 (dst) = ((dst) &\
57227 #define TPC_19__ALPHA_VOLT__MODIFY(dst, src) \
57228 (dst) = ((dst) &\
57245 #define TPC_19__ALPHA_VOLT_PAL_ON__MODIFY(dst, src) \
57246 (dst) = ((dst) &\
57272 #define TPC_20__ENABLE_PAL_MCS_0__MODIFY(dst, src) \
57273 (dst) = ((dst) &\
57279 #define TPC_20__ENABLE_PAL_MCS_0__SET(dst) \
57280 (dst) = ((dst) &\
57282 #define TPC_20__ENABLE_PAL_MCS_0__CLR(dst) \
57283 (dst) = ((dst) &\
57296 #define TPC_20__ENABLE_PAL_MCS_1__MODIFY(dst, src) \
57297 (dst) = ((dst) &\
57303 #define TPC_20__ENABLE_PAL_MCS_1__SET(dst) \
57304 (dst) = ((dst) &\
57306 #define TPC_20__ENABLE_PAL_MCS_1__CLR(dst) \
57307 (dst) = ((dst) &\
57320 #define TPC_20__ENABLE_PAL_MCS_2__MODIFY(dst, src) \
57321 (dst) = ((dst) &\
57327 #define TPC_20__ENABLE_PAL_MCS_2__SET(dst) \
57328 (dst) = ((dst) &\
57330 #define TPC_20__ENABLE_PAL_MCS_2__CLR(dst) \
57331 (dst) = ((dst) &\
57344 #define TPC_20__ENABLE_PAL_MCS_3__MODIFY(dst, src) \
57345 (dst) = ((dst) &\
57351 #define TPC_20__ENABLE_PAL_MCS_3__SET(dst) \
57352 (dst) = ((dst) &\
57354 #define TPC_20__ENABLE_PAL_MCS_3__CLR(dst) \
57355 (dst) = ((dst) &\
57368 #define TPC_20__ENABLE_PAL_MCS_4__MODIFY(dst, src) \
57369 (dst) = ((dst) &\
57375 #define TPC_20__ENABLE_PAL_MCS_4__SET(dst) \
57376 (dst) = ((dst) &\
57378 #define TPC_20__ENABLE_PAL_MCS_4__CLR(dst) \
57379 (dst) = ((dst) &\
57392 #define TPC_20__ENABLE_PAL_MCS_5__MODIFY(dst, src) \
57393 (dst) = ((dst) &\
57399 #define TPC_20__ENABLE_PAL_MCS_5__SET(dst) \
57400 (dst) = ((dst) &\
57402 #define TPC_20__ENABLE_PAL_MCS_5__CLR(dst) \
57403 (dst) = ((dst) &\
57416 #define TPC_20__ENABLE_PAL_MCS_6__MODIFY(dst, src) \
57417 (dst) = ((dst) &\
57423 #define TPC_20__ENABLE_PAL_MCS_6__SET(dst) \
57424 (dst) = ((dst) &\
57426 #define TPC_20__ENABLE_PAL_MCS_6__CLR(dst) \
57427 (dst) = ((dst) &\
57440 #define TPC_20__ENABLE_PAL_MCS_7__MODIFY(dst, src) \
57441 (dst) = ((dst) &\
57447 #define TPC_20__ENABLE_PAL_MCS_7__SET(dst) \
57448 (dst) = ((dst) &\
57450 #define TPC_20__ENABLE_PAL_MCS_7__CLR(dst) \
57451 (dst) = ((dst) &\
57464 #define TPC_20__ENABLE_PAL_MCS_8__MODIFY(dst, src) \
57465 (dst) = ((dst) &\
57471 #define TPC_20__ENABLE_PAL_MCS_8__SET(dst) \
57472 (dst) = ((dst) &\
57474 #define TPC_20__ENABLE_PAL_MCS_8__CLR(dst) \
57475 (dst) = ((dst) &\
57488 #define TPC_20__ENABLE_PAL_MCS_9__MODIFY(dst, src) \
57489 (dst) = ((dst) &\
57495 #define TPC_20__ENABLE_PAL_MCS_9__SET(dst) \
57496 (dst) = ((dst) &\
57498 #define TPC_20__ENABLE_PAL_MCS_9__CLR(dst) \
57499 (dst) = ((dst) &\
57512 #define TPC_20__ENABLE_PAL_MCS_10__MODIFY(dst, src) \
57513 (dst) = ((dst) &\
57519 #define TPC_20__ENABLE_PAL_MCS_10__SET(dst) \
57520 (dst) = ((dst) &\
57522 #define TPC_20__ENABLE_PAL_MCS_10__CLR(dst) \
57523 (dst) = ((dst) &\
57536 #define TPC_20__ENABLE_PAL_MCS_11__MODIFY(dst, src) \
57537 (dst) = ((dst) &\
57543 #define TPC_20__ENABLE_PAL_MCS_11__SET(dst) \
57544 (dst) = ((dst) &\
57546 #define TPC_20__ENABLE_PAL_MCS_11__CLR(dst) \
57547 (dst) = ((dst) &\
57560 #define TPC_20__ENABLE_PAL_MCS_12__MODIFY(dst, src) \
57561 (dst) = ((dst) &\
57567 #define TPC_20__ENABLE_PAL_MCS_12__SET(dst) \
57568 (dst) = ((dst) &\
57570 #define TPC_20__ENABLE_PAL_MCS_12__CLR(dst) \
57571 (dst) = ((dst) &\
57584 #define TPC_20__ENABLE_PAL_MCS_13__MODIFY(dst, src) \
57585 (dst) = ((dst) &\
57591 #define TPC_20__ENABLE_PAL_MCS_13__SET(dst) \
57592 (dst) = ((dst) &\
57594 #define TPC_20__ENABLE_PAL_MCS_13__CLR(dst) \
57595 (dst) = ((dst) &\
57608 #define TPC_20__ENABLE_PAL_MCS_14__MODIFY(dst, src) \
57609 (dst) = ((dst) &\
57615 #define TPC_20__ENABLE_PAL_MCS_14__SET(dst) \
57616 (dst) = ((dst) &\
57618 #define TPC_20__ENABLE_PAL_MCS_14__CLR(dst) \
57619 (dst) = ((dst) &\
57632 #define TPC_20__ENABLE_PAL_MCS_15__MODIFY(dst, src) \
57633 (dst) = ((dst) &\
57639 #define TPC_20__ENABLE_PAL_MCS_15__SET(dst) \
57640 (dst) = ((dst) &\
57642 #define TPC_20__ENABLE_PAL_MCS_15__CLR(dst) \
57643 (dst) = ((dst) &\
57656 #define TPC_20__ENABLE_PAL_MCS_16__MODIFY(dst, src) \
57657 (dst) = ((dst) &\
57663 #define TPC_20__ENABLE_PAL_MCS_16__SET(dst) \
57664 (dst) = ((dst) &\
57666 #define TPC_20__ENABLE_PAL_MCS_16__CLR(dst) \
57667 (dst) = ((dst) &\
57680 #define TPC_20__ENABLE_PAL_MCS_17__MODIFY(dst, src) \
57681 (dst) = ((dst) &\
57687 #define TPC_20__ENABLE_PAL_MCS_17__SET(dst) \
57688 (dst) = ((dst) &\
57690 #define TPC_20__ENABLE_PAL_MCS_17__CLR(dst) \
57691 (dst) = ((dst) &\
57704 #define TPC_20__ENABLE_PAL_MCS_18__MODIFY(dst, src) \
57705 (dst) = ((dst) &\
57711 #define TPC_20__ENABLE_PAL_MCS_18__SET(dst) \
57712 (dst) = ((dst) &\
57714 #define TPC_20__ENABLE_PAL_MCS_18__CLR(dst) \
57715 (dst) = ((dst) &\
57728 #define TPC_20__ENABLE_PAL_MCS_19__MODIFY(dst, src) \
57729 (dst) = ((dst) &\
57735 #define TPC_20__ENABLE_PAL_MCS_19__SET(dst) \
57736 (dst) = ((dst) &\
57738 #define TPC_20__ENABLE_PAL_MCS_19__CLR(dst) \
57739 (dst) = ((dst) &\
57752 #define TPC_20__ENABLE_PAL_MCS_20__MODIFY(dst, src) \
57753 (dst) = ((dst) &\
57759 #define TPC_20__ENABLE_PAL_MCS_20__SET(dst) \
57760 (dst) = ((dst) &\
57762 #define TPC_20__ENABLE_PAL_MCS_20__CLR(dst) \
57763 (dst) = ((dst) &\
57776 #define TPC_20__ENABLE_PAL_MCS_21__MODIFY(dst, src) \
57777 (dst) = ((dst) &\
57783 #define TPC_20__ENABLE_PAL_MCS_21__SET(dst) \
57784 (dst) = ((dst) &\
57786 #define TPC_20__ENABLE_PAL_MCS_21__CLR(dst) \
57787 (dst) = ((dst) &\
57800 #define TPC_20__ENABLE_PAL_MCS_22__MODIFY(dst, src) \
57801 (dst) = ((dst) &\
57807 #define TPC_20__ENABLE_PAL_MCS_22__SET(dst) \
57808 (dst) = ((dst) &\
57810 #define TPC_20__ENABLE_PAL_MCS_22__CLR(dst) \
57811 (dst) = ((dst) &\
57824 #define TPC_20__ENABLE_PAL_MCS_23__MODIFY(dst, src) \
57825 (dst) = ((dst) &\
57831 #define TPC_20__ENABLE_PAL_MCS_23__SET(dst) \
57832 (dst) = ((dst) &\
57834 #define TPC_20__ENABLE_PAL_MCS_23__CLR(dst) \
57835 (dst) = ((dst) &\
57861 #define THERM_ADC_1__INIT_THERM_SETTING__MODIFY(dst, src) \
57862 (dst) = ((dst) &\
57879 #define THERM_ADC_1__INIT_VOLT_SETTING__MODIFY(dst, src) \
57880 (dst) = ((dst) &\
57897 #define THERM_ADC_1__INIT_ATB_SETTING__MODIFY(dst, src) \
57898 (dst) = ((dst) &\
57915 #define THERM_ADC_1__SAMPLES_CNT_CODING__MODIFY(dst, src) \
57916 (dst) = ((dst) &\
57933 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MODIFY(dst, src) \
57934 (dst) = ((dst) &\
57940 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__SET(dst) \
57941 (dst) = ((dst) &\
57943 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__CLR(dst) \
57944 (dst) = ((dst) &\
57957 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MODIFY(dst, src) \
57958 (dst) = ((dst) &\
57964 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__SET(dst) \
57965 (dst) = ((dst) &\
57967 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__CLR(dst) \
57968 (dst) = ((dst) &\
57994 #define THERM_ADC_2__MEASURE_THERM_FREQ__MODIFY(dst, src) \
57995 (dst) = ((dst) &\
58012 #define THERM_ADC_2__MEASURE_VOLT_FREQ__MODIFY(dst, src) \
58013 (dst) = ((dst) &\
58030 #define THERM_ADC_2__MEASURE_ATB_FREQ__MODIFY(dst, src) \
58031 (dst) = ((dst) &\
58059 #define THERM_ADC_3__THERM_ADC_OFFSET__MODIFY(dst, src) \
58060 (dst) = ((dst) &\
58077 #define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MODIFY(dst, src) \
58078 (dst) = ((dst) &\
58095 #define THERM_ADC_3__ADC_INTERVAL__MODIFY(dst, src) \
58096 (dst) = ((dst) &\
58160 #define TX_FORCED_GAIN__FORCE_TX_GAIN__MODIFY(dst, src) \
58161 (dst) = ((dst) &\
58167 #define TX_FORCED_GAIN__FORCE_TX_GAIN__SET(dst) \
58168 (dst) = ((dst) &\
58170 #define TX_FORCED_GAIN__FORCE_TX_GAIN__CLR(dst) \
58171 (dst) = ((dst) &\
58184 #define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MODIFY(dst, src) \
58185 (dst) = ((dst) &\
58202 #define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MODIFY(dst, src) \
58203 (dst) = ((dst) &\
58220 #define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MODIFY(dst, src) \
58221 (dst) = ((dst) &\
58238 #define TX_FORCED_GAIN__FORCED_PADRVGNA__MODIFY(dst, src) \
58239 (dst) = ((dst) &\
58256 #define TX_FORCED_GAIN__FORCED_PADRVGNB__MODIFY(dst, src) \
58257 (dst) = ((dst) &\
58274 #define TX_FORCED_GAIN__FORCED_PADRVGNC__MODIFY(dst, src) \
58275 (dst) = ((dst) &\
58292 #define TX_FORCED_GAIN__FORCED_PADRVGND__MODIFY(dst, src) \
58293 (dst) = ((dst) &\
58310 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MODIFY(dst, src) \
58311 (dst) = ((dst) &\
58317 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__SET(dst) \
58318 (dst) = ((dst) &\
58320 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__CLR(dst) \
58321 (dst) = ((dst) &\
58342 #define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
58343 (dst) = ((dst) &\
58368 #define TX_GAIN_TAB_1__TG_TABLE1__MODIFY(dst, src) \
58369 (dst) = ((dst) &\
58395 #define TX_GAIN_TAB_2__TG_TABLE2__MODIFY(dst, src) \
58396 (dst) = ((dst) &\
58422 #define TX_GAIN_TAB_3__TG_TABLE3__MODIFY(dst, src) \
58423 (dst) = ((dst) &\
58449 #define TX_GAIN_TAB_4__TG_TABLE4__MODIFY(dst, src) \
58450 (dst) = ((dst) &\
58476 #define TX_GAIN_TAB_5__TG_TABLE5__MODIFY(dst, src) \
58477 (dst) = ((dst) &\
58503 #define TX_GAIN_TAB_6__TG_TABLE6__MODIFY(dst, src) \
58504 (dst) = ((dst) &\
58530 #define TX_GAIN_TAB_7__TG_TABLE7__MODIFY(dst, src) \
58531 (dst) = ((dst) &\
58557 #define TX_GAIN_TAB_8__TG_TABLE8__MODIFY(dst, src) \
58558 (dst) = ((dst) &\
58584 #define TX_GAIN_TAB_9__TG_TABLE9__MODIFY(dst, src) \
58585 (dst) = ((dst) &\
58611 #define TX_GAIN_TAB_10__TG_TABLE10__MODIFY(dst, src) \
58612 (dst) = ((dst) &\
58638 #define TX_GAIN_TAB_11__TG_TABLE11__MODIFY(dst, src) \
58639 (dst) = ((dst) &\
58665 #define TX_GAIN_TAB_12__TG_TABLE12__MODIFY(dst, src) \
58666 (dst) = ((dst) &\
58692 #define TX_GAIN_TAB_13__TG_TABLE13__MODIFY(dst, src) \
58693 (dst) = ((dst) &\
58719 #define TX_GAIN_TAB_14__TG_TABLE14__MODIFY(dst, src) \
58720 (dst) = ((dst) &\
58746 #define TX_GAIN_TAB_15__TG_TABLE15__MODIFY(dst, src) \
58747 (dst) = ((dst) &\
58773 #define TX_GAIN_TAB_16__TG_TABLE16__MODIFY(dst, src) \
58774 (dst) = ((dst) &\
58800 #define TX_GAIN_TAB_17__TG_TABLE17__MODIFY(dst, src) \
58801 (dst) = ((dst) &\
58827 #define TX_GAIN_TAB_18__TG_TABLE18__MODIFY(dst, src) \
58828 (dst) = ((dst) &\
58854 #define TX_GAIN_TAB_19__TG_TABLE19__MODIFY(dst, src) \
58855 (dst) = ((dst) &\
58881 #define TX_GAIN_TAB_20__TG_TABLE20__MODIFY(dst, src) \
58882 (dst) = ((dst) &\
58908 #define TX_GAIN_TAB_21__TG_TABLE21__MODIFY(dst, src) \
58909 (dst) = ((dst) &\
58935 #define TX_GAIN_TAB_22__TG_TABLE22__MODIFY(dst, src) \
58936 (dst) = ((dst) &\
58962 #define TX_GAIN_TAB_23__TG_TABLE23__MODIFY(dst, src) \
58963 (dst) = ((dst) &\
58989 #define TX_GAIN_TAB_24__TG_TABLE24__MODIFY(dst, src) \
58990 (dst) = ((dst) &\
59016 #define TX_GAIN_TAB_25__TG_TABLE25__MODIFY(dst, src) \
59017 (dst) = ((dst) &\
59043 #define TX_GAIN_TAB_26__TG_TABLE26__MODIFY(dst, src) \
59044 (dst) = ((dst) &\
59070 #define TX_GAIN_TAB_27__TG_TABLE27__MODIFY(dst, src) \
59071 (dst) = ((dst) &\
59097 #define TX_GAIN_TAB_28__TG_TABLE28__MODIFY(dst, src) \
59098 (dst) = ((dst) &\
59124 #define TX_GAIN_TAB_29__TG_TABLE29__MODIFY(dst, src) \
59125 (dst) = ((dst) &\
59151 #define TX_GAIN_TAB_30__TG_TABLE30__MODIFY(dst, src) \
59152 (dst) = ((dst) &\
59178 #define TX_GAIN_TAB_31__TG_TABLE31__MODIFY(dst, src) \
59179 (dst) = ((dst) &\
59205 #define TX_GAIN_TAB_32__TG_TABLE32__MODIFY(dst, src) \
59206 (dst) = ((dst) &\
59236 #define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__MODIFY(dst, src) \
59237 (dst) = ((dst) &\
59267 #define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__MODIFY(dst, src) \
59268 (dst) = ((dst) &\
59298 #define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__MODIFY(dst, src) \
59299 (dst) = ((dst) &\
59329 #define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__MODIFY(dst, src) \
59330 (dst) = ((dst) &\
59360 #define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__MODIFY(dst, src) \
59361 (dst) = ((dst) &\
59391 #define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__MODIFY(dst, src) \
59392 (dst) = ((dst) &\
59422 #define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__MODIFY(dst, src) \
59423 (dst) = ((dst) &\
59453 #define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__MODIFY(dst, src) \
59454 (dst) = ((dst) &\
59484 #define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__MODIFY(dst, src) \
59485 (dst) = ((dst) &\
59515 #define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__MODIFY(dst, src) \
59516 (dst) = ((dst) &\
59546 #define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__MODIFY(dst, src) \
59547 (dst) = ((dst) &\
59577 #define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__MODIFY(dst, src) \
59578 (dst) = ((dst) &\
59608 #define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__MODIFY(dst, src) \
59609 (dst) = ((dst) &\
59639 #define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__MODIFY(dst, src) \
59640 (dst) = ((dst) &\
59670 #define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__MODIFY(dst, src) \
59671 (dst) = ((dst) &\
59701 #define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__MODIFY(dst, src) \
59702 (dst) = ((dst) &\
59732 #define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__MODIFY(dst, src) \
59733 (dst) = ((dst) &\
59763 #define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__MODIFY(dst, src) \
59764 (dst) = ((dst) &\
59794 #define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__MODIFY(dst, src) \
59795 (dst) = ((dst) &\
59825 #define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__MODIFY(dst, src) \
59826 (dst) = ((dst) &\
59856 #define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__MODIFY(dst, src) \
59857 (dst) = ((dst) &\
59887 #define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__MODIFY(dst, src) \
59888 (dst) = ((dst) &\
59918 #define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__MODIFY(dst, src) \
59919 (dst) = ((dst) &\
59949 #define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__MODIFY(dst, src) \
59950 (dst) = ((dst) &\
59980 #define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__MODIFY(dst, src) \
59981 (dst) = ((dst) &\
60011 #define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__MODIFY(dst, src) \
60012 (dst) = ((dst) &\
60042 #define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__MODIFY(dst, src) \
60043 (dst) = ((dst) &\
60073 #define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__MODIFY(dst, src) \
60074 (dst) = ((dst) &\
60104 #define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__MODIFY(dst, src) \
60105 (dst) = ((dst) &\
60135 #define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__MODIFY(dst, src) \
60136 (dst) = ((dst) &\
60166 #define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__MODIFY(dst, src) \
60167 (dst) = ((dst) &\
60197 #define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__MODIFY(dst, src) \
60198 (dst) = ((dst) &\
60228 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MODIFY(dst, src) \
60229 (dst) = ((dst) &\
60246 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MODIFY(dst, src) \
60247 (dst) = ((dst) &\
60277 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MODIFY(dst, src) \
60278 (dst) = ((dst) &\
60295 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MODIFY(dst, src) \
60296 (dst) = ((dst) &\
60326 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MODIFY(dst, src) \
60327 (dst) = ((dst) &\
60344 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MODIFY(dst, src) \
60345 (dst) = ((dst) &\
60375 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MODIFY(dst, src) \
60376 (dst) = ((dst) &\
60393 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MODIFY(dst, src) \
60394 (dst) = ((dst) &\
60424 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MODIFY(dst, src) \
60425 (dst) = ((dst) &\
60442 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MODIFY(dst, src) \
60443 (dst) = ((dst) &\
60473 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MODIFY(dst, src) \
60474 (dst) = ((dst) &\
60491 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MODIFY(dst, src) \
60492 (dst) = ((dst) &\
60522 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MODIFY(dst, src) \
60523 (dst) = ((dst) &\
60540 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MODIFY(dst, src) \
60541 (dst) = ((dst) &\
60571 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MODIFY(dst, src) \
60572 (dst) = ((dst) &\
60589 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MODIFY(dst, src) \
60590 (dst) = ((dst) &\
60620 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MODIFY(dst, src) \
60621 (dst) = ((dst) &\
60638 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MODIFY(dst, src) \
60639 (dst) = ((dst) &\
60669 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MODIFY(dst, src) \
60670 (dst) = ((dst) &\
60687 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MODIFY(dst, src) \
60688 (dst) = ((dst) &\
60718 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MODIFY(dst, src) \
60719 (dst) = ((dst) &\
60736 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MODIFY(dst, src) \
60737 (dst) = ((dst) &\
60767 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MODIFY(dst, src) \
60768 (dst) = ((dst) &\
60785 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MODIFY(dst, src) \
60786 (dst) = ((dst) &\
60816 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MODIFY(dst, src) \
60817 (dst) = ((dst) &\
60834 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MODIFY(dst, src) \
60835 (dst) = ((dst) &\
60865 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MODIFY(dst, src) \
60866 (dst) = ((dst) &\
60883 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MODIFY(dst, src) \
60884 (dst) = ((dst) &\
60914 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MODIFY(dst, src) \
60915 (dst) = ((dst) &\
60932 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MODIFY(dst, src) \
60933 (dst) = ((dst) &\
60963 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MODIFY(dst, src) \
60964 (dst) = ((dst) &\
60981 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MODIFY(dst, src) \
60982 (dst) = ((dst) &\
61009 #define TXIQCAL_START__DO_TX_IQCAL__MODIFY(dst, src) \
61010 (dst) = ((dst) &\
61016 #define TXIQCAL_START__DO_TX_IQCAL__SET(dst) \
61017 (dst) = ((dst) &\
61019 #define TXIQCAL_START__DO_TX_IQCAL__CLR(dst) \
61020 (dst) = ((dst) &\
61046 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MODIFY(dst, src) \
61047 (dst) = ((dst) &\
61053 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__SET(dst) \
61054 (dst) = ((dst) &\
61056 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__CLR(dst) \
61057 (dst) = ((dst) &\
61070 #define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MODIFY(dst, src) \
61071 (dst) = ((dst) &\
61088 #define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MODIFY(dst, src) \
61089 (dst) = ((dst) &\
61106 #define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MODIFY(dst, src) \
61107 (dst) = ((dst) &\
61124 #define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MODIFY(dst, src) \
61125 (dst) = ((dst) &\
61142 #define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MODIFY(dst, src) \
61143 (dst) = ((dst) &\
61160 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MODIFY(dst, src) \
61161 (dst) = ((dst) &\
61167 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__SET(dst) \
61168 (dst) = ((dst) &\
61170 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__CLR(dst) \
61171 (dst) = ((dst) &\
61197 #define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MODIFY(dst, src) \
61198 (dst) = ((dst) &\
61215 #define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MODIFY(dst, src) \
61216 (dst) = ((dst) &\
61233 #define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MODIFY(dst, src) \
61234 (dst) = ((dst) &\
61251 #define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MODIFY(dst, src) \
61252 (dst) = ((dst) &\
61282 #define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MODIFY(dst, src) \
61283 (dst) = ((dst) &\
61300 #define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MODIFY(dst, src) \
61301 (dst) = ((dst) &\
61318 #define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MODIFY(dst, src) \
61319 (dst) = ((dst) &\
61349 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MODIFY(dst, src) \
61350 (dst) = ((dst) &\
61367 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MODIFY(dst, src) \
61368 (dst) = ((dst) &\
61398 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MODIFY(dst, src) \
61399 (dst) = ((dst) &\
61416 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MODIFY(dst, src) \
61417 (dst) = ((dst) &\
61447 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MODIFY(dst, src) \
61448 (dst) = ((dst) &\
61465 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MODIFY(dst, src) \
61466 (dst) = ((dst) &\
61496 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MODIFY(dst, src) \
61497 (dst) = ((dst) &\
61514 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MODIFY(dst, src) \
61515 (dst) = ((dst) &\
61545 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MODIFY(dst, src) \
61546 (dst) = ((dst) &\
61563 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MODIFY(dst, src) \
61564 (dst) = ((dst) &\
61594 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MODIFY(dst, src) \
61595 (dst) = ((dst) &\
61612 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MODIFY(dst, src) \
61613 (dst) = ((dst) &\
61643 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MODIFY(dst, src) \
61644 (dst) = ((dst) &\
61661 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MODIFY(dst, src) \
61662 (dst) = ((dst) &\
61692 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MODIFY(dst, src) \
61693 (dst) = ((dst) &\
61710 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MODIFY(dst, src) \
61711 (dst) = ((dst) &\
61741 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MODIFY(dst, src) \
61742 (dst) = ((dst) &\
61759 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MODIFY(dst, src) \
61760 (dst) = ((dst) &\
61777 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MODIFY(dst, src) \
61778 (dst) = ((dst) &\
61795 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MODIFY(dst, src) \
61796 (dst) = ((dst) &\
61826 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MODIFY(dst, src) \
61827 (dst) = ((dst) &\
61844 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MODIFY(dst, src) \
61845 (dst) = ((dst) &\
61862 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MODIFY(dst, src) \
61863 (dst) = ((dst) &\
61880 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MODIFY(dst, src) \
61881 (dst) = ((dst) &\
61911 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MODIFY(dst, src) \
61912 (dst) = ((dst) &\
61929 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MODIFY(dst, src) \
61930 (dst) = ((dst) &\
61947 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MODIFY(dst, src) \
61948 (dst) = ((dst) &\
61965 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MODIFY(dst, src) \
61966 (dst) = ((dst) &\
61996 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MODIFY(dst, src) \
61997 (dst) = ((dst) &\
62014 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MODIFY(dst, src) \
62015 (dst) = ((dst) &\
62032 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MODIFY(dst, src) \
62033 (dst) = ((dst) &\
62050 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MODIFY(dst, src) \
62051 (dst) = ((dst) &\
62081 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MODIFY(dst, src) \
62082 (dst) = ((dst) &\
62099 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MODIFY(dst, src) \
62100 (dst) = ((dst) &\
62117 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MODIFY(dst, src) \
62118 (dst) = ((dst) &\
62135 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MODIFY(dst, src) \
62136 (dst) = ((dst) &\
62166 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MODIFY(dst, src) \
62167 (dst) = ((dst) &\
62184 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MODIFY(dst, src) \
62185 (dst) = ((dst) &\
62202 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MODIFY(dst, src) \
62203 (dst) = ((dst) &\
62220 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MODIFY(dst, src) \
62221 (dst) = ((dst) &\
62251 #define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MODIFY(dst, src) \
62252 (dst) = ((dst) &\
62279 #define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__SET(dst) \
62280 (dst) = ((dst) &\
62282 #define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__CLR(dst) \
62283 (dst) = ((dst) &\
62340 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MODIFY(dst, src) \
62341 (dst) = ((dst) &\
62347 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__SET(dst) \
62348 (dst) = ((dst) &\
62350 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__CLR(dst) \
62351 (dst) = ((dst) &\
62364 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MODIFY(dst, src) \
62365 (dst) = ((dst) &\
62382 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MODIFY(dst, src) \
62383 (dst) = ((dst) &\
62389 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__SET(dst) \
62390 (dst) = ((dst) &\
62392 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__CLR(dst) \
62393 (dst) = ((dst) &\
62406 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MODIFY(dst, src) \
62407 (dst) = ((dst) &\
62413 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__SET(dst) \
62414 (dst) = ((dst) &\
62416 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__CLR(dst) \
62417 (dst) = ((dst) &\
62430 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MODIFY(dst, src) \
62431 (dst) = ((dst) &\
62437 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__SET(dst) \
62438 (dst) = ((dst) &\
62440 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__CLR(dst) \
62441 (dst) = ((dst) &\
62454 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MODIFY(dst, src) \
62455 (dst) = ((dst) &\
62461 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__SET(dst) \
62462 (dst) = ((dst) &\
62464 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__CLR(dst) \
62465 (dst) = ((dst) &\
62478 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MODIFY(dst, src) \
62479 (dst) = ((dst) &\
62509 #define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MODIFY(dst, src) \
62510 (dst) = ((dst) &\
62540 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MODIFY(dst, src) \
62541 (dst) = ((dst) &\
62558 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MODIFY(dst, src) \
62559 (dst) = ((dst) &\
62576 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MODIFY(dst, src) \
62577 (dst) = ((dst) &\
62594 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MODIFY(dst, src) \
62595 (dst) = ((dst) &\
62612 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MODIFY(dst, src) \
62613 (dst) = ((dst) &\
62630 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MODIFY(dst, src) \
62631 (dst) = ((dst) &\
62648 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MODIFY(dst, src) \
62649 (dst) = ((dst) &\
62655 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__SET(dst) \
62656 (dst) = ((dst) &\
62658 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__CLR(dst) \
62659 (dst) = ((dst) &\
62672 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MODIFY(dst, src) \
62673 (dst) = ((dst) &\
62679 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__SET(dst) \
62680 (dst) = ((dst) &\
62682 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__CLR(dst) \
62683 (dst) = ((dst) &\
62709 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MODIFY(dst, src) \
62710 (dst) = ((dst) &\
62727 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MODIFY(dst, src) \
62728 (dst) = ((dst) &\
62745 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MODIFY(dst, src) \
62746 (dst) = ((dst) &\
62776 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MODIFY(dst, src) \
62777 (dst) = ((dst) &\
62783 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__SET(dst) \
62784 (dst) = ((dst) &\
62786 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__CLR(dst) \
62787 (dst) = ((dst) &\
62797 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__SET(dst) \
62798 (dst) = ((dst) &\
62800 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__CLR(dst) \
62801 (dst) = ((dst) &\
62811 #define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__SET(dst) \
62812 (dst) = ((dst) &\
62814 #define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__CLR(dst) \
62815 (dst) = ((dst) &\
62825 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__SET(dst) \
62826 (dst) = ((dst) &\
62828 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__CLR(dst) \
62829 (dst) = ((dst) &\
62927 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__MODIFY(dst, src) \
62928 (dst) = ((dst) &\
62945 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__MODIFY(dst, src) \
62946 (dst) = ((dst) &\
62952 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__SET(dst) \
62953 (dst) = ((dst) &\
62955 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__CLR(dst) \
62956 (dst) = ((dst) &\
62969 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__MODIFY(dst, src) \
62970 (dst) = ((dst) &\
62987 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__MODIFY(dst, src) \
62988 (dst) = ((dst) &\
63005 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__MODIFY(dst, src) \
63006 (dst) = ((dst) &\
63023 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__MODIFY(dst, src) \
63024 (dst) = ((dst) &\
63041 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__MODIFY(dst, src) \
63042 (dst) = ((dst) &\
63059 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__MODIFY(dst, src) \
63060 (dst) = ((dst) &\
63077 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__MODIFY(dst, src) \
63078 (dst) = ((dst) &\
63108 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__MODIFY(dst, src) \
63109 (dst) = ((dst) &\
63115 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__SET(dst) \
63116 (dst) = ((dst) &\
63118 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__CLR(dst) \
63119 (dst) = ((dst) &\
63132 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__MODIFY(dst, src) \
63133 (dst) = ((dst) &\
63139 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__SET(dst) \
63140 (dst) = ((dst) &\
63142 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__CLR(dst) \
63143 (dst) = ((dst) &\
63156 #define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__MODIFY(dst, src) \
63157 (dst) = ((dst) &\
63174 #define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__MODIFY(dst, src) \
63175 (dst) = ((dst) &\
63205 #define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MODIFY(dst, src) \
63206 (dst) = ((dst) &\
63212 #define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__SET(dst) \
63213 (dst) = ((dst) &\
63215 #define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__CLR(dst) \
63216 (dst) = ((dst) &\
63229 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__MODIFY(dst, src) \
63230 (dst) = ((dst) &\
63236 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__SET(dst) \
63237 (dst) = ((dst) &\
63239 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__CLR(dst) \
63240 (dst) = ((dst) &\
63253 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__MODIFY(dst, src) \
63254 (dst) = ((dst) &\
63260 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__SET(dst) \
63261 (dst) = ((dst) &\
63263 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__CLR(dst) \
63264 (dst) = ((dst) &\
63290 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MODIFY(dst, src) \
63291 (dst) = ((dst) &\
63297 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__SET(dst) \
63298 (dst) = ((dst) &\
63300 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__CLR(dst) \
63301 (dst) = ((dst) &\
63314 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MODIFY(dst, src) \
63315 (dst) = ((dst) &\
63321 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__SET(dst) \
63322 (dst) = ((dst) &\
63324 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__CLR(dst) \
63325 (dst) = ((dst) &\
63351 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MODIFY(dst, src) \
63352 (dst) = ((dst) &\
63358 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__SET(dst) \
63359 (dst) = ((dst) &\
63361 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__CLR(dst) \
63362 (dst) = ((dst) &\
63388 #define PHYONLY_CONTROL__RX_DRAIN_RATE__MODIFY(dst, src) \
63389 (dst) = ((dst) &\
63395 #define PHYONLY_CONTROL__RX_DRAIN_RATE__SET(dst) \
63396 (dst) = ((dst) &\
63398 #define PHYONLY_CONTROL__RX_DRAIN_RATE__CLR(dst) \
63399 (dst) = ((dst) &\
63412 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MODIFY(dst, src) \
63413 (dst) = ((dst) &\
63419 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__SET(dst) \
63420 (dst) = ((dst) &\
63422 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__CLR(dst) \
63423 (dst) = ((dst) &\
63436 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MODIFY(dst, src) \
63437 (dst) = ((dst) &\
63443 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__SET(dst) \
63444 (dst) = ((dst) &\
63446 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__CLR(dst) \
63447 (dst) = ((dst) &\
63460 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MODIFY(dst, src) \
63461 (dst) = ((dst) &\
63467 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__SET(dst) \
63468 (dst) = ((dst) &\
63470 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__CLR(dst) \
63471 (dst) = ((dst) &\
63484 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MODIFY(dst, src) \
63485 (dst) = ((dst) &\
63491 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__SET(dst) \
63492 (dst) = ((dst) &\
63494 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__CLR(dst) \
63495 (dst) = ((dst) &\
63508 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MODIFY(dst, src) \
63509 (dst) = ((dst) &\
63515 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__SET(dst) \
63516 (dst) = ((dst) &\
63518 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__CLR(dst) \
63519 (dst) = ((dst) &\
63532 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MODIFY(dst, src) \
63533 (dst) = ((dst) &\
63539 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__SET(dst) \
63540 (dst) = ((dst) &\
63542 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__CLR(dst) \
63543 (dst) = ((dst) &\
63556 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MODIFY(dst, src) \
63557 (dst) = ((dst) &\
63563 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__SET(dst) \
63564 (dst) = ((dst) &\
63566 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__CLR(dst) \
63567 (dst) = ((dst) &\
63589 #define ECO_CTRL__ECO_CTRL__MODIFY(dst, src) \
63590 (dst) = ((dst) &\
63613 #define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
63614 #define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
63638 #define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MODIFY(dst, src) \
63639 (dst) = ((dst) &\
63791 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MODIFY(dst, src) \
63792 (dst) = ((dst) &\
63798 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__SET(dst) \
63799 (dst) = ((dst) &\
63801 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__CLR(dst) \
63802 (dst) = ((dst) &\
63815 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MODIFY(dst, src) \
63816 (dst) = ((dst) &\
63833 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MODIFY(dst, src) \
63834 (dst) = ((dst) &\
63851 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MODIFY(dst, src) \
63852 (dst) = ((dst) &\
63882 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MODIFY(dst, src) \
63883 (dst) = ((dst) &\
63900 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MODIFY(dst, src) \
63901 (dst) = ((dst) &\
63918 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MODIFY(dst, src) \
63919 (dst) = ((dst) &\
63936 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MODIFY(dst, src) \
63937 (dst) = ((dst) &\
63967 #define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \
63968 (dst) = ((dst) &\
63985 #define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \
63986 (dst) = ((dst) &\
64003 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \
64004 (dst) = ((dst) &\
64021 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \
64022 (dst) = ((dst) &\
64052 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MODIFY(dst, src) \
64053 (dst) = ((dst) &\
64059 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__SET(dst) \
64060 (dst) = ((dst) &\
64062 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__CLR(dst) \
64063 (dst) = ((dst) &\
64076 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MODIFY(dst, src) \
64077 (dst) = ((dst) &\
64083 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__SET(dst) \
64084 (dst) = ((dst) &\
64086 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__CLR(dst) \
64087 (dst) = ((dst) &\
64100 #define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MODIFY(dst, src) \
64101 (dst) = ((dst) &\
64118 #define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MODIFY(dst, src) \
64119 (dst) = ((dst) &\
64149 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MODIFY(dst, src) \
64150 (dst) = ((dst) &\
64156 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__SET(dst) \
64157 (dst) = ((dst) &\
64159 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__CLR(dst) \
64160 (dst) = ((dst) &\
64173 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MODIFY(dst, src) \
64174 (dst) = ((dst) &\
64180 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__SET(dst) \
64181 (dst) = ((dst) &\
64183 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__CLR(dst) \
64184 (dst) = ((dst) &\
64197 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MODIFY(dst, src) \
64198 (dst) = ((dst) &\
64204 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__SET(dst) \
64205 (dst) = ((dst) &\
64207 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__CLR(dst) \
64208 (dst) = ((dst) &\
64221 #define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MODIFY(dst, src) \
64222 (dst) = ((dst) &\
64239 #define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MODIFY(dst, src) \
64240 (dst) = ((dst) &\
64257 #define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MODIFY(dst, src) \
64258 (dst) = ((dst) &\
64275 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MODIFY(dst, src) \
64276 (dst) = ((dst) &\
64282 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__SET(dst) \
64283 (dst) = ((dst) &\
64285 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__CLR(dst) \
64286 (dst) = ((dst) &\
64308 #define PA_GAIN123_B1__PA_GAIN1_1__MODIFY(dst, src) \
64309 (dst) = ((dst) &\
64326 #define PA_GAIN123_B1__PA_GAIN2_1__MODIFY(dst, src) \
64327 (dst) = ((dst) &\
64344 #define PA_GAIN123_B1__PA_GAIN3_1__MODIFY(dst, src) \
64345 (dst) = ((dst) &\
64371 #define PA_GAIN45_B1__PA_GAIN4_1__MODIFY(dst, src) \
64372 (dst) = ((dst) &\
64389 #define PA_GAIN45_B1__PA_GAIN5_1__MODIFY(dst, src) \
64390 (dst) = ((dst) &\
64407 #define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MODIFY(dst, src) \
64408 (dst) = ((dst) &\
64438 #define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MODIFY(dst, src) \
64439 (dst) = ((dst) &\
64469 #define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MODIFY(dst, src) \
64470 (dst) = ((dst) &\
64500 #define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MODIFY(dst, src) \
64501 (dst) = ((dst) &\
64531 #define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MODIFY(dst, src) \
64532 (dst) = ((dst) &\
64562 #define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MODIFY(dst, src) \
64563 (dst) = ((dst) &\
64593 #define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MODIFY(dst, src) \
64594 (dst) = ((dst) &\
64624 #define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MODIFY(dst, src) \
64625 (dst) = ((dst) &\
64655 #define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MODIFY(dst, src) \
64656 (dst) = ((dst) &\
64682 #define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
64683 (dst) = ((dst) &\
64728 #define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
64729 #define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
64753 #define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MODIFY(dst, src) \
64754 (dst) = ((dst) &\
64771 #define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MODIFY(dst, src) \
64772 (dst) = ((dst) &\
64789 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MODIFY(dst, src) \
64790 (dst) = ((dst) &\
64796 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__SET(dst) \
64797 (dst) = ((dst) &\
64799 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__CLR(dst) \
64800 (dst) = ((dst) &\
64813 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MODIFY(dst, src) \
64814 (dst) = ((dst) &\
64820 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__SET(dst) \
64821 (dst) = ((dst) &\
64823 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__CLR(dst) \
64824 (dst) = ((dst) &\
64837 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MODIFY(dst, src) \
64838 (dst) = ((dst) &\
64855 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MODIFY(dst, src) \
64856 (dst) = ((dst) &\
64886 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MODIFY(dst, src) \
64887 (dst) = ((dst) &\
64904 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MODIFY(dst, src) \
64905 (dst) = ((dst) &\
64922 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MODIFY(dst, src) \
64923 (dst) = ((dst) &\
64940 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MODIFY(dst, src) \
64941 (dst) = ((dst) &\
64958 #define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MODIFY(dst, src) \
64959 (dst) = ((dst) &\
64985 #define CCA_B1__CF_MAXCCAPWR_1__MODIFY(dst, src) \
64986 (dst) = ((dst) &\
65022 #define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MODIFY(dst, src) \
65023 (dst) = ((dst) &\
65040 #define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MODIFY(dst, src) \
65041 (dst) = ((dst) &\
65206 #define RX_OCGAIN2__GAIN_ENTRY2__MODIFY(dst, src) \
65207 (dst) = ((dst) &\
65231 #define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
65232 #define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
65256 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MODIFY(dst, src) \
65257 (dst) = ((dst) &\
65274 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MODIFY(dst, src) \
65275 (dst) = ((dst) &\
65292 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MODIFY(dst, src) \
65293 (dst) = ((dst) &\
65310 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MODIFY(dst, src) \
65311 (dst) = ((dst) &\
65328 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MODIFY(dst, src) \
65329 (dst) = ((dst) &\
65346 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MODIFY(dst, src) \
65347 (dst) = ((dst) &\
65377 #define FCAL_2_B1__FLC_SW_CAP_VAL_1__MODIFY(dst, src) \
65378 (dst) = ((dst) &\
65416 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MODIFY(dst, src) \
65417 (dst) = ((dst) &\
65423 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__SET(dst) \
65424 (dst) = ((dst) &\
65426 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__CLR(dst) \
65427 (dst) = ((dst) &\
65440 #define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MODIFY(dst, src) \
65441 (dst) = ((dst) &\
65458 #define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MODIFY(dst, src) \
65459 (dst) = ((dst) &\
65485 #define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
65486 (dst) = ((dst) &\
65510 #define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
65511 (dst) = ((dst) &\
65535 #define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
65536 (dst) = ((dst) &\
65560 #define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
65561 (dst) = ((dst) &\
65585 #define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
65586 (dst) = ((dst) &\
65612 #define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
65613 (dst) = ((dst) &\
65639 #define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
65640 (dst) = ((dst) &\
65666 #define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
65667 (dst) = ((dst) &\
65693 #define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
65694 (dst) = ((dst) &\
65709 #define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
65710 (dst) = ((dst) &\
65727 #define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
65728 (dst) = ((dst) &\
65741 #define CL_TAB__BB_GAIN__MODIFY(dst, src) \
65742 (dst) = ((dst) &\
65793 #define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__SET(dst) \
65794 (dst) = ((dst) &\
65796 #define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__CLR(dst) \
65797 (dst) = ((dst) &\
65807 #define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__SET(dst) \
65808 (dst) = ((dst) &\
65810 #define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__CLR(dst) \
65811 (dst) = ((dst) &\
65831 #define TPC_4_B1__PD_AVG_VALID_1__SET(dst) \
65832 (dst) = ((dst) &\
65834 #define TPC_4_B1__PD_AVG_VALID_1__CLR(dst) \
65835 (dst) = ((dst) &\
65890 #define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MODIFY(dst, src) \
65891 (dst) = ((dst) &\
65908 #define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MODIFY(dst, src) \
65909 (dst) = ((dst) &\
65926 #define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MODIFY(dst, src) \
65927 (dst) = ((dst) &\
65944 #define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MODIFY(dst, src) \
65945 (dst) = ((dst) &\
65973 #define TPC_6_B1__PD_DAC_SETTING_1_1__MODIFY(dst, src) \
65974 (dst) = ((dst) &\
65991 #define TPC_6_B1__PD_DAC_SETTING_2_1__MODIFY(dst, src) \
65992 (dst) = ((dst) &\
66009 #define TPC_6_B1__PD_DAC_SETTING_3_1__MODIFY(dst, src) \
66010 (dst) = ((dst) &\
66027 #define TPC_6_B1__PD_DAC_SETTING_4_1__MODIFY(dst, src) \
66028 (dst) = ((dst) &\
66045 #define TPC_6_B1__ERROR_EST_MODE__MODIFY(dst, src) \
66046 (dst) = ((dst) &\
66063 #define TPC_6_B1__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
66064 (dst) = ((dst) &\
66094 #define TPC_11_B1__OLPC_GAIN_DELTA_1__MODIFY(dst, src) \
66095 (dst) = ((dst) &\
66112 #define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MODIFY(dst, src) \
66113 (dst) = ((dst) &\
66138 #define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
66139 (dst) = ((dst) &\
66168 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MODIFY(dst, src) \
66169 (dst) = ((dst) &\
66186 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MODIFY(dst, src) \
66187 (dst) = ((dst) &\
66217 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MODIFY(dst, src) \
66218 (dst) = ((dst) &\
66235 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MODIFY(dst, src) \
66236 (dst) = ((dst) &\
66266 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MODIFY(dst, src) \
66267 (dst) = ((dst) &\
66284 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MODIFY(dst, src) \
66285 (dst) = ((dst) &\
66315 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MODIFY(dst, src) \
66316 (dst) = ((dst) &\
66333 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MODIFY(dst, src) \
66334 (dst) = ((dst) &\
66364 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MODIFY(dst, src) \
66365 (dst) = ((dst) &\
66382 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MODIFY(dst, src) \
66383 (dst) = ((dst) &\
66413 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MODIFY(dst, src) \
66414 (dst) = ((dst) &\
66431 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MODIFY(dst, src) \
66432 (dst) = ((dst) &\
66462 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MODIFY(dst, src) \
66463 (dst) = ((dst) &\
66480 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MODIFY(dst, src) \
66481 (dst) = ((dst) &\
66511 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MODIFY(dst, src) \
66512 (dst) = ((dst) &\
66529 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MODIFY(dst, src) \
66530 (dst) = ((dst) &\
66557 #define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__SET(dst) \
66558 (dst) = ((dst) &\
66560 #define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__CLR(dst) \
66561 (dst) = ((dst) &\
66616 #define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
66617 #define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
66641 #define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MODIFY(dst, src) \
66642 (dst) = ((dst) &\
66794 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MODIFY(dst, src) \
66795 (dst) = ((dst) &\
66801 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__SET(dst) \
66802 (dst) = ((dst) &\
66804 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__CLR(dst) \
66805 (dst) = ((dst) &\
66818 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MODIFY(dst, src) \
66819 (dst) = ((dst) &\
66836 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MODIFY(dst, src) \
66837 (dst) = ((dst) &\
66854 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MODIFY(dst, src) \
66855 (dst) = ((dst) &\
66885 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MODIFY(dst, src) \
66886 (dst) = ((dst) &\
66903 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MODIFY(dst, src) \
66904 (dst) = ((dst) &\
66921 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MODIFY(dst, src) \
66922 (dst) = ((dst) &\
66939 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MODIFY(dst, src) \
66940 (dst) = ((dst) &\
66970 #define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \
66971 (dst) = ((dst) &\
66988 #define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \
66989 (dst) = ((dst) &\
67006 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \
67007 (dst) = ((dst) &\
67024 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \
67025 (dst) = ((dst) &\
67055 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MODIFY(dst, src) \
67056 (dst) = ((dst) &\
67062 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__SET(dst) \
67063 (dst) = ((dst) &\
67065 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__CLR(dst) \
67066 (dst) = ((dst) &\
67079 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MODIFY(dst, src) \
67080 (dst) = ((dst) &\
67086 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__SET(dst) \
67087 (dst) = ((dst) &\
67089 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__CLR(dst) \
67090 (dst) = ((dst) &\
67103 #define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MODIFY(dst, src) \
67104 (dst) = ((dst) &\
67121 #define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MODIFY(dst, src) \
67122 (dst) = ((dst) &\
67152 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MODIFY(dst, src) \
67153 (dst) = ((dst) &\
67159 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__SET(dst) \
67160 (dst) = ((dst) &\
67162 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__CLR(dst) \
67163 (dst) = ((dst) &\
67176 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MODIFY(dst, src) \
67177 (dst) = ((dst) &\
67183 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__SET(dst) \
67184 (dst) = ((dst) &\
67186 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__CLR(dst) \
67187 (dst) = ((dst) &\
67200 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MODIFY(dst, src) \
67201 (dst) = ((dst) &\
67207 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__SET(dst) \
67208 (dst) = ((dst) &\
67210 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__CLR(dst) \
67211 (dst) = ((dst) &\
67224 #define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MODIFY(dst, src) \
67225 (dst) = ((dst) &\
67242 #define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MODIFY(dst, src) \
67243 (dst) = ((dst) &\
67260 #define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MODIFY(dst, src) \
67261 (dst) = ((dst) &\
67278 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MODIFY(dst, src) \
67279 (dst) = ((dst) &\
67285 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__SET(dst) \
67286 (dst) = ((dst) &\
67288 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__CLR(dst) \
67289 (dst) = ((dst) &\
67311 #define PA_GAIN123_B2__PA_GAIN1_2__MODIFY(dst, src) \
67312 (dst) = ((dst) &\
67329 #define PA_GAIN123_B2__PA_GAIN2_2__MODIFY(dst, src) \
67330 (dst) = ((dst) &\
67347 #define PA_GAIN123_B2__PA_GAIN3_2__MODIFY(dst, src) \
67348 (dst) = ((dst) &\
67374 #define PA_GAIN45_B2__PA_GAIN4_2__MODIFY(dst, src) \
67375 (dst) = ((dst) &\
67392 #define PA_GAIN45_B2__PA_GAIN5_2__MODIFY(dst, src) \
67393 (dst) = ((dst) &\
67410 #define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MODIFY(dst, src) \
67411 (dst) = ((dst) &\
67441 #define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MODIFY(dst, src) \
67442 (dst) = ((dst) &\
67472 #define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MODIFY(dst, src) \
67473 (dst) = ((dst) &\
67503 #define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MODIFY(dst, src) \
67504 (dst) = ((dst) &\
67534 #define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MODIFY(dst, src) \
67535 (dst) = ((dst) &\
67565 #define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MODIFY(dst, src) \
67566 (dst) = ((dst) &\
67596 #define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MODIFY(dst, src) \
67597 (dst) = ((dst) &\
67627 #define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MODIFY(dst, src) \
67628 (dst) = ((dst) &\
67658 #define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MODIFY(dst, src) \
67659 (dst) = ((dst) &\
67685 #define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
67686 (dst) = ((dst) &\
67731 #define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
67732 #define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
67756 #define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MODIFY(dst, src) \
67757 (dst) = ((dst) &\
67774 #define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MODIFY(dst, src) \
67775 (dst) = ((dst) &\
67792 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MODIFY(dst, src) \
67793 (dst) = ((dst) &\
67799 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__SET(dst) \
67800 (dst) = ((dst) &\
67802 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__CLR(dst) \
67803 (dst) = ((dst) &\
67816 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MODIFY(dst, src) \
67817 (dst) = ((dst) &\
67823 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__SET(dst) \
67824 (dst) = ((dst) &\
67826 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__CLR(dst) \
67827 (dst) = ((dst) &\
67840 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MODIFY(dst, src) \
67841 (dst) = ((dst) &\
67858 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MODIFY(dst, src) \
67859 (dst) = ((dst) &\
67889 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MODIFY(dst, src) \
67890 (dst) = ((dst) &\
67907 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MODIFY(dst, src) \
67908 (dst) = ((dst) &\
67925 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MODIFY(dst, src) \
67926 (dst) = ((dst) &\
67943 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MODIFY(dst, src) \
67944 (dst) = ((dst) &\
67961 #define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MODIFY(dst, src) \
67962 (dst) = ((dst) &\
67988 #define CCA_B2__CF_MAXCCAPWR_2__MODIFY(dst, src) \
67989 (dst) = ((dst) &\
68025 #define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MODIFY(dst, src) \
68026 (dst) = ((dst) &\
68043 #define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MODIFY(dst, src) \
68044 (dst) = ((dst) &\
68165 #define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
68166 #define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
68190 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MODIFY(dst, src) \
68191 (dst) = ((dst) &\
68208 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MODIFY(dst, src) \
68209 (dst) = ((dst) &\
68226 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MODIFY(dst, src) \
68227 (dst) = ((dst) &\
68244 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MODIFY(dst, src) \
68245 (dst) = ((dst) &\
68262 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MODIFY(dst, src) \
68263 (dst) = ((dst) &\
68280 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MODIFY(dst, src) \
68281 (dst) = ((dst) &\
68311 #define FCAL_2_B2__FLC_SW_CAP_VAL_2__MODIFY(dst, src) \
68312 (dst) = ((dst) &\
68350 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MODIFY(dst, src) \
68351 (dst) = ((dst) &\
68357 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__SET(dst) \
68358 (dst) = ((dst) &\
68360 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__CLR(dst) \
68361 (dst) = ((dst) &\
68374 #define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MODIFY(dst, src) \
68375 (dst) = ((dst) &\
68392 #define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MODIFY(dst, src) \
68393 (dst) = ((dst) &\
68419 #define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
68420 (dst) = ((dst) &\
68444 #define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
68445 (dst) = ((dst) &\
68469 #define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
68470 (dst) = ((dst) &\
68494 #define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
68495 (dst) = ((dst) &\
68519 #define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
68520 (dst) = ((dst) &\
68546 #define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
68547 (dst) = ((dst) &\
68573 #define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
68574 (dst) = ((dst) &\
68600 #define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
68601 (dst) = ((dst) &\
68627 #define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
68628 (dst) = ((dst) &\
68643 #define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
68644 (dst) = ((dst) &\
68661 #define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
68662 (dst) = ((dst) &\
68675 #define CL_TAB__BB_GAIN__MODIFY(dst, src) \
68676 (dst) = ((dst) &\
68727 #define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__SET(dst) \
68728 (dst) = ((dst) &\
68730 #define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__CLR(dst) \
68731 (dst) = ((dst) &\
68741 #define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__SET(dst) \
68742 (dst) = ((dst) &\
68744 #define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__CLR(dst) \
68745 (dst) = ((dst) &\
68765 #define TPC_4_B2__PD_AVG_VALID_2__SET(dst) \
68766 (dst) = ((dst) &\
68768 #define TPC_4_B2__PD_AVG_VALID_2__CLR(dst) \
68769 (dst) = ((dst) &\
68824 #define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MODIFY(dst, src) \
68825 (dst) = ((dst) &\
68842 #define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MODIFY(dst, src) \
68843 (dst) = ((dst) &\
68860 #define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MODIFY(dst, src) \
68861 (dst) = ((dst) &\
68878 #define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MODIFY(dst, src) \
68879 (dst) = ((dst) &\
68907 #define TPC_6_B2__PD_DAC_SETTING_1_2__MODIFY(dst, src) \
68908 (dst) = ((dst) &\
68925 #define TPC_6_B2__PD_DAC_SETTING_2_2__MODIFY(dst, src) \
68926 (dst) = ((dst) &\
68943 #define TPC_6_B2__PD_DAC_SETTING_3_2__MODIFY(dst, src) \
68944 (dst) = ((dst) &\
68961 #define TPC_6_B2__PD_DAC_SETTING_4_2__MODIFY(dst, src) \
68962 (dst) = ((dst) &\
68979 #define TPC_6_B2__ERROR_EST_MODE__MODIFY(dst, src) \
68980 (dst) = ((dst) &\
68997 #define TPC_6_B2__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
68998 (dst) = ((dst) &\
69028 #define TPC_11_B2__OLPC_GAIN_DELTA_2__MODIFY(dst, src) \
69029 (dst) = ((dst) &\
69046 #define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MODIFY(dst, src) \
69047 (dst) = ((dst) &\
69072 #define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
69073 (dst) = ((dst) &\
69102 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MODIFY(dst, src) \
69103 (dst) = ((dst) &\
69120 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MODIFY(dst, src) \
69121 (dst) = ((dst) &\
69151 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MODIFY(dst, src) \
69152 (dst) = ((dst) &\
69169 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MODIFY(dst, src) \
69170 (dst) = ((dst) &\
69200 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MODIFY(dst, src) \
69201 (dst) = ((dst) &\
69218 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MODIFY(dst, src) \
69219 (dst) = ((dst) &\
69249 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MODIFY(dst, src) \
69250 (dst) = ((dst) &\
69267 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MODIFY(dst, src) \
69268 (dst) = ((dst) &\
69298 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MODIFY(dst, src) \
69299 (dst) = ((dst) &\
69316 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MODIFY(dst, src) \
69317 (dst) = ((dst) &\
69347 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MODIFY(dst, src) \
69348 (dst) = ((dst) &\
69365 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MODIFY(dst, src) \
69366 (dst) = ((dst) &\
69396 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MODIFY(dst, src) \
69397 (dst) = ((dst) &\
69414 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MODIFY(dst, src) \
69415 (dst) = ((dst) &\
69445 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MODIFY(dst, src) \
69446 (dst) = ((dst) &\
69463 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MODIFY(dst, src) \
69464 (dst) = ((dst) &\
69491 #define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__SET(dst) \
69492 (dst) = ((dst) &\
69494 #define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__CLR(dst) \
69495 (dst) = ((dst) &\
69550 #define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
69551 #define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
69570 #define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
69571 #define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
69614 #define DUMMY__DUMMY__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
69615 #define DUMMY__DUMMY__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
69649 #define TXBF_DBG__MODE__MODIFY(dst, src) \
69650 (dst) = ((dst) &\
69665 #define TXBF_DBG__CLIENT_TABLE__MODIFY(dst, src) \
69666 (dst) = ((dst) &\
69683 #define TXBF_DBG__SW_WR_V_DONE__MODIFY(dst, src) \
69684 (dst) = ((dst) &\
69690 #define TXBF_DBG__SW_WR_V_DONE__SET(dst) \
69691 (dst) = ((dst) &\
69693 #define TXBF_DBG__SW_WR_V_DONE__CLR(dst) \
69694 (dst) = ((dst) &\
69703 #define TXBF_DBG__DBG_IM__MODIFY(dst, src) \
69704 (dst) = ((dst) &\
69710 #define TXBF_DBG__DBG_IM__SET(dst) \
69711 (dst) = ((dst) &\
69713 #define TXBF_DBG__DBG_IM__CLR(dst) \
69714 (dst) = ((dst) &\
69723 #define TXBF_DBG__DBG_BW__MODIFY(dst, src) \
69724 (dst) = ((dst) &\
69730 #define TXBF_DBG__DBG_BW__SET(dst) \
69731 (dst) = ((dst) &\
69733 #define TXBF_DBG__DBG_BW__CLR(dst) \
69734 (dst) = ((dst) &\
69742 #define TXBF_DBG__CLK_CNTL__MODIFY(dst, src) \
69743 (dst) = ((dst) &\
69749 #define TXBF_DBG__CLK_CNTL__SET(dst) \
69750 (dst) = ((dst) &\
69752 #define TXBF_DBG__CLK_CNTL__CLR(dst) \
69753 (dst) = ((dst) &\
69766 #define TXBF_DBG__REGULAR_SOUNDING__MODIFY(dst, src) \
69767 (dst) = ((dst) &\
69773 #define TXBF_DBG__REGULAR_SOUNDING__SET(dst) \
69774 (dst) = ((dst) &\
69776 #define TXBF_DBG__REGULAR_SOUNDING__CLR(dst) \
69777 (dst) = ((dst) &\
69790 #define TXBF_DBG__DBG_NO_WALSH__MODIFY(dst, src) \
69791 (dst) = ((dst) &\
69797 #define TXBF_DBG__DBG_NO_WALSH__SET(dst) \
69798 (dst) = ((dst) &\
69800 #define TXBF_DBG__DBG_NO_WALSH__CLR(dst) \
69801 (dst) = ((dst) &\
69814 #define TXBF_DBG__DBG_NO_CSD__MODIFY(dst, src) \
69815 (dst) = ((dst) &\
69821 #define TXBF_DBG__DBG_NO_CSD__SET(dst) \
69822 (dst) = ((dst) &\
69824 #define TXBF_DBG__DBG_NO_CSD__CLR(dst) \
69825 (dst) = ((dst) &\
69847 #define TXBF__CB_TX__MODIFY(dst, src) \
69848 (dst) = ((dst) &\
69859 #define TXBF__NB_TX__MODIFY(dst, src) \
69860 (dst) = ((dst) &\
69871 #define TXBF__NG_RPT_TX__MODIFY(dst, src) \
69872 (dst) = ((dst) &\
69885 #define TXBF__NG_CVCACHE__MODIFY(dst, src) \
69886 (dst) = ((dst) &\
69903 #define TXBF__TXCV_BFWEIGHT_METHOD__MODIFY(dst, src) \
69904 (dst) = ((dst) &\
69917 #define TXBF__RLR_EN__MODIFY(dst, src) \
69918 (dst) = ((dst) &\
69924 #define TXBF__RLR_EN__SET(dst) \
69925 (dst) = ((dst) &\
69927 #define TXBF__RLR_EN__CLR(dst) \
69928 (dst) = ((dst) &\
69937 #define TXBF__RC_20_U_DONE__MODIFY(dst, src) \
69938 (dst) = ((dst) &\
69944 #define TXBF__RC_20_U_DONE__SET(dst) \
69945 (dst) = ((dst) &\
69947 #define TXBF__RC_20_U_DONE__CLR(dst) \
69948 (dst) = ((dst) &\
69957 #define TXBF__RC_20_L_DONE__MODIFY(dst, src) \
69958 (dst) = ((dst) &\
69964 #define TXBF__RC_20_L_DONE__SET(dst) \
69965 (dst) = ((dst) &\
69967 #define TXBF__RC_20_L_DONE__CLR(dst) \
69968 (dst) = ((dst) &\
69977 #define TXBF__RC_40_DONE__MODIFY(dst, src) \
69978 (dst) = ((dst) &\
69984 #define TXBF__RC_40_DONE__SET(dst) \
69985 (dst) = ((dst) &\
69987 #define TXBF__RC_40_DONE__CLR(dst) \
69988 (dst) = ((dst) &\
70010 #define TXBF_TIMER__TIMEOUT__MODIFY(dst, src) \
70011 (dst) = ((dst) &\
70024 #define TXBF_TIMER__ATIMEOUT__MODIFY(dst, src) \
70025 (dst) = ((dst) &\
70051 #define TXBF_SW__LRU_ACK__MODIFY(dst, src) \
70052 (dst) = ((dst) &\
70056 #define TXBF_SW__LRU_ACK__SET(dst) \
70057 (dst) = ((dst) &\
70059 #define TXBF_SW__LRU_ACK__CLR(dst) \
70060 (dst) = ((dst) &\
70075 #define TXBF_SW__LRU_EN__MODIFY(dst, src) \
70076 (dst) = ((dst) &\
70082 #define TXBF_SW__LRU_EN__SET(dst) \
70083 (dst) = ((dst) &\
70085 #define TXBF_SW__LRU_EN__CLR(dst) \
70086 (dst) = ((dst) &\
70095 #define TXBF_SW__DEST_IDX__MODIFY(dst, src) \
70096 (dst) = ((dst) &\
70111 #define TXBF_SW__LRU_WR_ACK__MODIFY(dst, src) \
70112 (dst) = ((dst) &\
70118 #define TXBF_SW__LRU_WR_ACK__SET(dst) \
70119 (dst) = ((dst) &\
70121 #define TXBF_SW__LRU_WR_ACK__CLR(dst) \
70122 (dst) = ((dst) &\
70133 #define TXBF_SW__LRU_RD_ACK__MODIFY(dst, src) \
70134 (dst) = ((dst) &\
70140 #define TXBF_SW__LRU_RD_ACK__SET(dst) \
70141 (dst) = ((dst) &\
70143 #define TXBF_SW__LRU_RD_ACK__CLR(dst) \
70144 (dst) = ((dst) &\
70157 #define TXBF_SW__WALSH_CSD_MODE__MODIFY(dst, src) \
70158 (dst) = ((dst) &\
70164 #define TXBF_SW__WALSH_CSD_MODE__SET(dst) \
70165 (dst) = ((dst) &\
70167 #define TXBF_SW__WALSH_CSD_MODE__CLR(dst) \
70168 (dst) = ((dst) &\
70181 #define TXBF_SW__CONDITION_NUMBER__MODIFY(dst, src) \
70182 (dst) = ((dst) &\
70370 #define RC0__DATA__MODIFY(dst, src) \
70371 (dst) = ((dst) &\
70395 #define RC1__DATA__MODIFY(dst, src) \
70396 (dst) = ((dst) &\
70420 #define SVD_MEM0__DATA__MODIFY(dst, src) \
70421 (dst) = ((dst) &\
70445 #define SVD_MEM1__DATA__MODIFY(dst, src) \
70446 (dst) = ((dst) &\
70470 #define SVD_MEM2__DATA__MODIFY(dst, src) \
70471 (dst) = ((dst) &\
70495 #define SVD_MEM3__DATA__MODIFY(dst, src) \
70496 (dst) = ((dst) &\
70520 #define SVD_MEM4__DATA__MODIFY(dst, src) \
70521 (dst) = ((dst) &\
70545 #define CVCACHE__DATA__MODIFY(dst, src) \
70546 (dst) = ((dst) &\
70570 #define OTP_MEM__OTP_MEM__MODIFY(dst, src) \
70571 (dst) = ((dst) &\
70599 #define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__MODIFY(dst, src) \
70600 (dst) = ((dst) &\
70628 #define OTP_INTF1__BITMASK_WR_REG_V__MODIFY(dst, src) \
70629 (dst) = ((dst) &\
70657 #define OTP_INTF2__PG_STROBE_PW_REG_V__MODIFY(dst, src) \
70658 (dst) = ((dst) &\
70686 #define OTP_INTF3__RD_STROBE_PW_REG_V__MODIFY(dst, src) \
70687 (dst) = ((dst) &\
70717 #define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__MODIFY(dst, src) \
70718 (dst) = ((dst) &\
70748 #define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__MODIFY(dst, src) \
70749 (dst) = ((dst) &\
70755 #define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__SET(dst) \
70756 (dst) = ((dst) &\
70758 #define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__CLR(dst) \
70759 (dst) = ((dst) &\
70780 #define OTP_STATUS0__OTP_SM_BUSY__SET(dst) \
70781 (dst) = ((dst) &\
70783 #define OTP_STATUS0__OTP_SM_BUSY__CLR(dst) \
70784 (dst) = ((dst) &\
70794 #define OTP_STATUS0__EFUSE_ACCESS_BUSY__SET(dst) \
70795 (dst) = ((dst) &\
70797 #define OTP_STATUS0__EFUSE_ACCESS_BUSY__CLR(dst) \
70798 (dst) = ((dst) &\
70808 #define OTP_STATUS0__EFUSE_READ_DATA_VALID__SET(dst) \
70809 (dst) = ((dst) &\
70811 #define OTP_STATUS0__EFUSE_READ_DATA_VALID__CLR(dst) \
70812 (dst) = ((dst) &\
70855 #define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__MODIFY(dst, src) \
70856 (dst) = ((dst) &\
70882 #define OTP_LDO_CONTROL__ENABLE__MODIFY(dst, src) \
70883 (dst) = ((dst) &\
70889 #define OTP_LDO_CONTROL__ENABLE__SET(dst) \
70890 (dst) = ((dst) &\
70892 #define OTP_LDO_CONTROL__ENABLE__CLR(dst) \
70893 (dst) = ((dst) &\
70915 #define OTP_LDO_POWER_GOOD__DELAY__MODIFY(dst, src) \
70916 (dst) = ((dst) &\
70941 #define OTP_LDO_STATUS__POWER_ON__SET(dst) \
70942 (dst) = ((dst) &\
70944 #define OTP_LDO_STATUS__POWER_ON__CLR(dst) \
70945 (dst) = ((dst) &\
70966 #define OTP_VDDQ_HOLD_TIME__DELAY__MODIFY(dst, src) \
70967 (dst) = ((dst) &\
70997 #define OTP_PGENB_SETUP_HOLD_TIME__DELAY__MODIFY(dst, src) \
70998 (dst) = ((dst) &\
71028 #define OTP_STROBE_PULSE_INTERVAL__DELAY__MODIFY(dst, src) \
71029 (dst) = ((dst) &\
71059 #define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__MODIFY(dst, src) \
71060 (dst) = ((dst) &\
71086 #define RXRF_BIAS1__SPARE__MODIFY(dst, src) \
71087 (dst) = ((dst) &\
71091 #define RXRF_BIAS1__SPARE__SET(dst) \
71092 (dst) = ((dst) &\
71094 #define RXRF_BIAS1__SPARE__CLR(dst) \
71095 (dst) = ((dst) &\
71108 #define RXRF_BIAS1__PWD_IR25SPARE__MODIFY(dst, src) \
71109 (dst) = ((dst) &\
71126 #define RXRF_BIAS1__PWD_IR25LO18__MODIFY(dst, src) \
71127 (dst) = ((dst) &\
71144 #define RXRF_BIAS1__PWD_IC25LO36__MODIFY(dst, src) \
71145 (dst) = ((dst) &\
71162 #define RXRF_BIAS1__PWD_IC25MXR2_5GH__MODIFY(dst, src) \
71163 (dst) = ((dst) &\
71180 #define RXRF_BIAS1__PWD_IC25MXR5GH__MODIFY(dst, src) \
71181 (dst) = ((dst) &\
71198 #define RXRF_BIAS1__PWD_IC25VGA5G__MODIFY(dst, src) \
71199 (dst) = ((dst) &\
71216 #define RXRF_BIAS1__PWD_IC75LNA5G__MODIFY(dst, src) \
71217 (dst) = ((dst) &\
71234 #define RXRF_BIAS1__PWD_IR25LO24__MODIFY(dst, src) \
71235 (dst) = ((dst) &\
71252 #define RXRF_BIAS1__PWD_IC25MXR2GH__MODIFY(dst, src) \
71253 (dst) = ((dst) &\
71270 #define RXRF_BIAS1__PWD_IC75LNA2G__MODIFY(dst, src) \
71271 (dst) = ((dst) &\
71288 #define RXRF_BIAS1__PWD_BIAS__MODIFY(dst, src) \
71289 (dst) = ((dst) &\
71295 #define RXRF_BIAS1__PWD_BIAS__SET(dst) \
71296 (dst) = ((dst) &\
71298 #define RXRF_BIAS1__PWD_BIAS__CLR(dst) \
71299 (dst) = ((dst) &\
71321 #define RXRF_BIAS2__SPARE__MODIFY(dst, src) \
71322 (dst) = ((dst) &\
71326 #define RXRF_BIAS2__SPARE__SET(dst) \
71327 (dst) = ((dst) &\
71329 #define RXRF_BIAS2__SPARE__CLR(dst) \
71330 (dst) = ((dst) &\
71339 #define RXRF_BIAS2__PKEN__MODIFY(dst, src) \
71340 (dst) = ((dst) &\
71355 #define RXRF_BIAS2__VCMVALUE__MODIFY(dst, src) \
71356 (dst) = ((dst) &\
71373 #define RXRF_BIAS2__PWD_VCMBUF__MODIFY(dst, src) \
71374 (dst) = ((dst) &\
71380 #define RXRF_BIAS2__PWD_VCMBUF__SET(dst) \
71381 (dst) = ((dst) &\
71383 #define RXRF_BIAS2__PWD_VCMBUF__CLR(dst) \
71384 (dst) = ((dst) &\
71397 #define RXRF_BIAS2__PWD_IR25SPAREH__MODIFY(dst, src) \
71398 (dst) = ((dst) &\
71415 #define RXRF_BIAS2__PWD_IR25SPARE__MODIFY(dst, src) \
71416 (dst) = ((dst) &\
71433 #define RXRF_BIAS2__PWD_IC25LNABUF__MODIFY(dst, src) \
71434 (dst) = ((dst) &\
71451 #define RXRF_BIAS2__PWD_IR25AGCH__MODIFY(dst, src) \
71452 (dst) = ((dst) &\
71469 #define RXRF_BIAS2__PWD_IR25AGC__MODIFY(dst, src) \
71470 (dst) = ((dst) &\
71487 #define RXRF_BIAS2__PWD_IC25AGC__MODIFY(dst, src) \
71488 (dst) = ((dst) &\
71505 #define RXRF_BIAS2__PWD_IC25VCMBUF__MODIFY(dst, src) \
71506 (dst) = ((dst) &\
71523 #define RXRF_BIAS2__PWD_IR25VCM__MODIFY(dst, src) \
71524 (dst) = ((dst) &\
71550 #define RXRF_GAINSTAGES__SPARE__MODIFY(dst, src) \
71551 (dst) = ((dst) &\
71557 #define RXRF_GAINSTAGES__SPARE__SET(dst) \
71558 (dst) = ((dst) &\
71560 #define RXRF_GAINSTAGES__SPARE__CLR(dst) \
71561 (dst) = ((dst) &\
71574 #define RXRF_GAINSTAGES__LNAON_CALDC__MODIFY(dst, src) \
71575 (dst) = ((dst) &\
71581 #define RXRF_GAINSTAGES__LNAON_CALDC__SET(dst) \
71582 (dst) = ((dst) &\
71584 #define RXRF_GAINSTAGES__LNAON_CALDC__CLR(dst) \
71585 (dst) = ((dst) &\
71598 #define RXRF_GAINSTAGES__VGA5G_CAP__MODIFY(dst, src) \
71599 (dst) = ((dst) &\
71616 #define RXRF_GAINSTAGES__LNA5G_CAP__MODIFY(dst, src) \
71617 (dst) = ((dst) &\
71634 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__MODIFY(dst, src) \
71635 (dst) = ((dst) &\
71641 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__SET(dst) \
71642 (dst) = ((dst) &\
71644 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__CLR(dst) \
71645 (dst) = ((dst) &\
71658 #define RXRF_GAINSTAGES__PWD_LO5G__MODIFY(dst, src) \
71659 (dst) = ((dst) &\
71665 #define RXRF_GAINSTAGES__PWD_LO5G__SET(dst) \
71666 (dst) = ((dst) &\
71668 #define RXRF_GAINSTAGES__PWD_LO5G__CLR(dst) \
71669 (dst) = ((dst) &\
71682 #define RXRF_GAINSTAGES__PWD_VGA5G__MODIFY(dst, src) \
71683 (dst) = ((dst) &\
71689 #define RXRF_GAINSTAGES__PWD_VGA5G__SET(dst) \
71690 (dst) = ((dst) &\
71692 #define RXRF_GAINSTAGES__PWD_VGA5G__CLR(dst) \
71693 (dst) = ((dst) &\
71706 #define RXRF_GAINSTAGES__PWD_MXR5G__MODIFY(dst, src) \
71707 (dst) = ((dst) &\
71713 #define RXRF_GAINSTAGES__PWD_MXR5G__SET(dst) \
71714 (dst) = ((dst) &\
71716 #define RXRF_GAINSTAGES__PWD_MXR5G__CLR(dst) \
71717 (dst) = ((dst) &\
71730 #define RXRF_GAINSTAGES__PWD_LNA5G__MODIFY(dst, src) \
71731 (dst) = ((dst) &\
71737 #define RXRF_GAINSTAGES__PWD_LNA5G__SET(dst) \
71738 (dst) = ((dst) &\
71740 #define RXRF_GAINSTAGES__PWD_LNA5G__CLR(dst) \
71741 (dst) = ((dst) &\
71754 #define RXRF_GAINSTAGES__LNA2G_CAP__MODIFY(dst, src) \
71755 (dst) = ((dst) &\
71772 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__MODIFY(dst, src) \
71773 (dst) = ((dst) &\
71779 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__SET(dst) \
71780 (dst) = ((dst) &\
71782 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__CLR(dst) \
71783 (dst) = ((dst) &\
71796 #define RXRF_GAINSTAGES__LNA2G_LP__MODIFY(dst, src) \
71797 (dst) = ((dst) &\
71803 #define RXRF_GAINSTAGES__LNA2G_LP__SET(dst) \
71804 (dst) = ((dst) &\
71806 #define RXRF_GAINSTAGES__LNA2G_LP__CLR(dst) \
71807 (dst) = ((dst) &\
71820 #define RXRF_GAINSTAGES__PWD_LO2G__MODIFY(dst, src) \
71821 (dst) = ((dst) &\
71827 #define RXRF_GAINSTAGES__PWD_LO2G__SET(dst) \
71828 (dst) = ((dst) &\
71830 #define RXRF_GAINSTAGES__PWD_LO2G__CLR(dst) \
71831 (dst) = ((dst) &\
71844 #define RXRF_GAINSTAGES__PWD_MXR2G__MODIFY(dst, src) \
71845 (dst) = ((dst) &\
71851 #define RXRF_GAINSTAGES__PWD_MXR2G__SET(dst) \
71852 (dst) = ((dst) &\
71854 #define RXRF_GAINSTAGES__PWD_MXR2G__CLR(dst) \
71855 (dst) = ((dst) &\
71868 #define RXRF_GAINSTAGES__PWD_LNA2G__MODIFY(dst, src) \
71869 (dst) = ((dst) &\
71875 #define RXRF_GAINSTAGES__PWD_LNA2G__SET(dst) \
71876 (dst) = ((dst) &\
71878 #define RXRF_GAINSTAGES__PWD_LNA2G__CLR(dst) \
71879 (dst) = ((dst) &\
71892 #define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MODIFY(dst, src) \
71893 (dst) = ((dst) &\
71910 #define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MODIFY(dst, src) \
71911 (dst) = ((dst) &\
71928 #define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MODIFY(dst, src) \
71929 (dst) = ((dst) &\
71946 #define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MODIFY(dst, src) \
71947 (dst) = ((dst) &\
71964 #define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MODIFY(dst, src) \
71965 (dst) = ((dst) &\
71982 #define RXRF_GAINSTAGES__RX_OVERRIDE__MODIFY(dst, src) \
71983 (dst) = ((dst) &\
71989 #define RXRF_GAINSTAGES__RX_OVERRIDE__SET(dst) \
71990 (dst) = ((dst) &\
71992 #define RXRF_GAINSTAGES__RX_OVERRIDE__CLR(dst) \
71993 (dst) = ((dst) &\
72019 #define RXRF_AGC__RF5G_ON_DURING_CALPA__MODIFY(dst, src) \
72020 (dst) = ((dst) &\
72026 #define RXRF_AGC__RF5G_ON_DURING_CALPA__SET(dst) \
72027 (dst) = ((dst) &\
72029 #define RXRF_AGC__RF5G_ON_DURING_CALPA__CLR(dst) \
72030 (dst) = ((dst) &\
72043 #define RXRF_AGC__RF2G_ON_DURING_CALPA__MODIFY(dst, src) \
72044 (dst) = ((dst) &\
72050 #define RXRF_AGC__RF2G_ON_DURING_CALPA__SET(dst) \
72051 (dst) = ((dst) &\
72053 #define RXRF_AGC__RF2G_ON_DURING_CALPA__CLR(dst) \
72054 (dst) = ((dst) &\
72062 #define RXRF_AGC__AGC_OUT__SET(dst) \
72063 (dst) = ((dst) &\
72065 #define RXRF_AGC__AGC_OUT__CLR(dst) \
72066 (dst) = ((dst) &\
72079 #define RXRF_AGC__LNABUFGAIN2X__MODIFY(dst, src) \
72080 (dst) = ((dst) &\
72086 #define RXRF_AGC__LNABUFGAIN2X__SET(dst) \
72087 (dst) = ((dst) &\
72089 #define RXRF_AGC__LNABUFGAIN2X__CLR(dst) \
72090 (dst) = ((dst) &\
72103 #define RXRF_AGC__LNABUF_PWD_OVR__MODIFY(dst, src) \
72104 (dst) = ((dst) &\
72110 #define RXRF_AGC__LNABUF_PWD_OVR__SET(dst) \
72111 (dst) = ((dst) &\
72113 #define RXRF_AGC__LNABUF_PWD_OVR__CLR(dst) \
72114 (dst) = ((dst) &\
72125 #define RXRF_AGC__PWD_LNABUF__MODIFY(dst, src) \
72126 (dst) = ((dst) &\
72132 #define RXRF_AGC__PWD_LNABUF__SET(dst) \
72133 (dst) = ((dst) &\
72135 #define RXRF_AGC__PWD_LNABUF__CLR(dst) \
72136 (dst) = ((dst) &\
72149 #define RXRF_AGC__AGC_FALL_CTRL__MODIFY(dst, src) \
72150 (dst) = ((dst) &\
72167 #define RXRF_AGC__AGC5G_CALDAC_OVR__MODIFY(dst, src) \
72168 (dst) = ((dst) &\
72185 #define RXRF_AGC__AGC5G_DBDAC_OVR__MODIFY(dst, src) \
72186 (dst) = ((dst) &\
72203 #define RXRF_AGC__AGC2G_CALDAC_OVR__MODIFY(dst, src) \
72204 (dst) = ((dst) &\
72221 #define RXRF_AGC__AGC2G_DBDAC_OVR__MODIFY(dst, src) \
72222 (dst) = ((dst) &\
72239 #define RXRF_AGC__AGC_CAL_OVR__MODIFY(dst, src) \
72240 (dst) = ((dst) &\
72246 #define RXRF_AGC__AGC_CAL_OVR__SET(dst) \
72247 (dst) = ((dst) &\
72249 #define RXRF_AGC__AGC_CAL_OVR__CLR(dst) \
72250 (dst) = ((dst) &\
72263 #define RXRF_AGC__AGC_ON_OVR__MODIFY(dst, src) \
72264 (dst) = ((dst) &\
72270 #define RXRF_AGC__AGC_ON_OVR__SET(dst) \
72271 (dst) = ((dst) &\
72273 #define RXRF_AGC__AGC_ON_OVR__CLR(dst) \
72274 (dst) = ((dst) &\
72287 #define RXRF_AGC__AGC_OVERRIDE__MODIFY(dst, src) \
72288 (dst) = ((dst) &\
72294 #define RXRF_AGC__AGC_OVERRIDE__SET(dst) \
72295 (dst) = ((dst) &\
72297 #define RXRF_AGC__AGC_OVERRIDE__CLR(dst) \
72298 (dst) = ((dst) &\
72320 #define TXRF1__PDLOBUF5G__MODIFY(dst, src) \
72321 (dst) = ((dst) &\
72325 #define TXRF1__PDLOBUF5G__SET(dst) \
72326 (dst) = ((dst) &\
72328 #define TXRF1__PDLOBUF5G__CLR(dst) \
72329 (dst) = ((dst) &\
72338 #define TXRF1__PDLODIV5G__MODIFY(dst, src) \
72339 (dst) = ((dst) &\
72345 #define TXRF1__PDLODIV5G__SET(dst) \
72346 (dst) = ((dst) &\
72348 #define TXRF1__PDLODIV5G__CLR(dst) \
72349 (dst) = ((dst) &\
72360 #define TXRF1__LOBUF5GFORCED__MODIFY(dst, src) \
72361 (dst) = ((dst) &\
72367 #define TXRF1__LOBUF5GFORCED__SET(dst) \
72368 (dst) = ((dst) &\
72370 #define TXRF1__LOBUF5GFORCED__CLR(dst) \
72371 (dst) = ((dst) &\
72382 #define TXRF1__LODIV5GFORCED__MODIFY(dst, src) \
72383 (dst) = ((dst) &\
72389 #define TXRF1__LODIV5GFORCED__SET(dst) \
72390 (dst) = ((dst) &\
72392 #define TXRF1__LODIV5GFORCED__CLR(dst) \
72393 (dst) = ((dst) &\
72402 #define TXRF1__PADRV2GN5G__MODIFY(dst, src) \
72403 (dst) = ((dst) &\
72416 #define TXRF1__PADRV3GN5G__MODIFY(dst, src) \
72417 (dst) = ((dst) &\
72430 #define TXRF1__PADRV4GN5G__MODIFY(dst, src) \
72431 (dst) = ((dst) &\
72448 #define TXRF1__LOCALTXGAIN5G__MODIFY(dst, src) \
72449 (dst) = ((dst) &\
72455 #define TXRF1__LOCALTXGAIN5G__SET(dst) \
72456 (dst) = ((dst) &\
72458 #define TXRF1__LOCALTXGAIN5G__CLR(dst) \
72459 (dst) = ((dst) &\
72468 #define TXRF1__PDOUT2G__MODIFY(dst, src) \
72469 (dst) = ((dst) &\
72475 #define TXRF1__PDOUT2G__SET(dst) \
72476 (dst) = ((dst) &\
72478 #define TXRF1__PDOUT2G__CLR(dst) \
72479 (dst) = ((dst) &\
72488 #define TXRF1__PDDR2G__MODIFY(dst, src) \
72489 (dst) = ((dst) &\
72495 #define TXRF1__PDDR2G__SET(dst) \
72496 (dst) = ((dst) &\
72498 #define TXRF1__PDDR2G__CLR(dst) \
72499 (dst) = ((dst) &\
72508 #define TXRF1__PDMXR2G__MODIFY(dst, src) \
72509 (dst) = ((dst) &\
72515 #define TXRF1__PDMXR2G__SET(dst) \
72516 (dst) = ((dst) &\
72518 #define TXRF1__PDMXR2G__CLR(dst) \
72519 (dst) = ((dst) &\
72528 #define TXRF1__PDLOBUF2G__MODIFY(dst, src) \
72529 (dst) = ((dst) &\
72535 #define TXRF1__PDLOBUF2G__SET(dst) \
72536 (dst) = ((dst) &\
72538 #define TXRF1__PDLOBUF2G__CLR(dst) \
72539 (dst) = ((dst) &\
72548 #define TXRF1__PDLODIV2G__MODIFY(dst, src) \
72549 (dst) = ((dst) &\
72555 #define TXRF1__PDLODIV2G__SET(dst) \
72556 (dst) = ((dst) &\
72558 #define TXRF1__PDLODIV2G__CLR(dst) \
72559 (dst) = ((dst) &\
72572 #define TXRF1__LOBUF2GFORCED__MODIFY(dst, src) \
72573 (dst) = ((dst) &\
72579 #define TXRF1__LOBUF2GFORCED__SET(dst) \
72580 (dst) = ((dst) &\
72582 #define TXRF1__LOBUF2GFORCED__CLR(dst) \
72583 (dst) = ((dst) &\
72596 #define TXRF1__LODIV2GFORCED__MODIFY(dst, src) \
72597 (dst) = ((dst) &\
72603 #define TXRF1__LODIV2GFORCED__SET(dst) \
72604 (dst) = ((dst) &\
72606 #define TXRF1__LODIV2GFORCED__CLR(dst) \
72607 (dst) = ((dst) &\
72616 #define TXRF1__PADRVGN2G__MODIFY(dst, src) \
72617 (dst) = ((dst) &\
72634 #define TXRF1__LOCALTXGAIN2G__MODIFY(dst, src) \
72635 (dst) = ((dst) &\
72641 #define TXRF1__LOCALTXGAIN2G__SET(dst) \
72642 (dst) = ((dst) &\
72644 #define TXRF1__LOCALTXGAIN2G__CLR(dst) \
72645 (dst) = ((dst) &\
72667 #define TXRF2__D3B5G__MODIFY(dst, src) \
72668 (dst) = ((dst) &\
72679 #define TXRF2__D4B5G__MODIFY(dst, src) \
72680 (dst) = ((dst) &\
72691 #define TXRF2__OCAS2G__MODIFY(dst, src) \
72692 (dst) = ((dst) &\
72705 #define TXRF2__DCAS2G__MODIFY(dst, src) \
72706 (dst) = ((dst) &\
72719 #define TXRF2__OB2G_PALOFF__MODIFY(dst, src) \
72720 (dst) = ((dst) &\
72733 #define TXRF2__OB2G_QAM__MODIFY(dst, src) \
72734 (dst) = ((dst) &\
72747 #define TXRF2__OB2G_PSK__MODIFY(dst, src) \
72748 (dst) = ((dst) &\
72761 #define TXRF2__OB2G_CCK__MODIFY(dst, src) \
72762 (dst) = ((dst) &\
72775 #define TXRF2__DB2G__MODIFY(dst, src) \
72776 (dst) = ((dst) &\
72787 #define TXRF2__PDOUT5G__MODIFY(dst, src) \
72788 (dst) = ((dst) &\
72801 #define TXRF2__PDMXR5G__MODIFY(dst, src) \
72802 (dst) = ((dst) &\
72808 #define TXRF2__PDMXR5G__SET(dst) \
72809 (dst) = ((dst) &\
72811 #define TXRF2__PDMXR5G__CLR(dst) \
72812 (dst) = ((dst) &\
72834 #define TXRF3__FILTR2G__MODIFY(dst, src) \
72835 (dst) = ((dst) &\
72846 #define TXRF3__PWDFB2_2G__MODIFY(dst, src) \
72847 (dst) = ((dst) &\
72853 #define TXRF3__PWDFB2_2G__SET(dst) \
72854 (dst) = ((dst) &\
72856 #define TXRF3__PWDFB2_2G__CLR(dst) \
72857 (dst) = ((dst) &\
72866 #define TXRF3__PWDFB1_2G__MODIFY(dst, src) \
72867 (dst) = ((dst) &\
72873 #define TXRF3__PWDFB1_2G__SET(dst) \
72874 (dst) = ((dst) &\
72876 #define TXRF3__PWDFB1_2G__CLR(dst) \
72877 (dst) = ((dst) &\
72886 #define TXRF3__PDFB2G__MODIFY(dst, src) \
72887 (dst) = ((dst) &\
72893 #define TXRF3__PDFB2G__SET(dst) \
72894 (dst) = ((dst) &\
72896 #define TXRF3__PDFB2G__CLR(dst) \
72897 (dst) = ((dst) &\
72906 #define TXRF3__RDIV5G__MODIFY(dst, src) \
72907 (dst) = ((dst) &\
72920 #define TXRF3__CAPDIV5G__MODIFY(dst, src) \
72921 (dst) = ((dst) &\
72934 #define TXRF3__PDPREDIST5G__MODIFY(dst, src) \
72935 (dst) = ((dst) &\
72941 #define TXRF3__PDPREDIST5G__SET(dst) \
72942 (dst) = ((dst) &\
72944 #define TXRF3__PDPREDIST5G__CLR(dst) \
72945 (dst) = ((dst) &\
72954 #define TXRF3__RDIV2G__MODIFY(dst, src) \
72955 (dst) = ((dst) &\
72968 #define TXRF3__PDPREDIST2G__MODIFY(dst, src) \
72969 (dst) = ((dst) &\
72975 #define TXRF3__PDPREDIST2G__SET(dst) \
72976 (dst) = ((dst) &\
72978 #define TXRF3__PDPREDIST2G__CLR(dst) \
72979 (dst) = ((dst) &\
72988 #define TXRF3__OCAS5G__MODIFY(dst, src) \
72989 (dst) = ((dst) &\
73002 #define TXRF3__D2CAS5G__MODIFY(dst, src) \
73003 (dst) = ((dst) &\
73016 #define TXRF3__D3CAS5G__MODIFY(dst, src) \
73017 (dst) = ((dst) &\
73030 #define TXRF3__D4CAS5G__MODIFY(dst, src) \
73031 (dst) = ((dst) &\
73044 #define TXRF3__OB5G__MODIFY(dst, src) \
73045 (dst) = ((dst) &\
73056 #define TXRF3__D2B5G__MODIFY(dst, src) \
73057 (dst) = ((dst) &\
73083 #define TXRF4__PK1B2G_CCK__MODIFY(dst, src) \
73084 (dst) = ((dst) &\
73095 #define TXRF4__MIOB2G_QAM__MODIFY(dst, src) \
73096 (dst) = ((dst) &\
73109 #define TXRF4__MIOB2G_PSK__MODIFY(dst, src) \
73110 (dst) = ((dst) &\
73123 #define TXRF4__MIOB2G_CCK__MODIFY(dst, src) \
73124 (dst) = ((dst) &\
73137 #define TXRF4__COMP2G_QAM__MODIFY(dst, src) \
73138 (dst) = ((dst) &\
73151 #define TXRF4__COMP2G_PSK__MODIFY(dst, src) \
73152 (dst) = ((dst) &\
73165 #define TXRF4__COMP2G_CCK__MODIFY(dst, src) \
73166 (dst) = ((dst) &\
73179 #define TXRF4__AMP2B2G_QAM__MODIFY(dst, src) \
73180 (dst) = ((dst) &\
73193 #define TXRF4__AMP2B2G_PSK__MODIFY(dst, src) \
73194 (dst) = ((dst) &\
73207 #define TXRF4__AMP2B2G_CCK__MODIFY(dst, src) \
73208 (dst) = ((dst) &\
73221 #define TXRF4__AMP2CAS2G__MODIFY(dst, src) \
73222 (dst) = ((dst) &\
73248 #define TXRF5__TXMODPALONLY__MODIFY(dst, src) \
73249 (dst) = ((dst) &\
73253 #define TXRF5__TXMODPALONLY__SET(dst) \
73254 (dst) = ((dst) &\
73256 #define TXRF5__TXMODPALONLY__CLR(dst) \
73257 (dst) = ((dst) &\
73265 #define TXRF5__PAL_LOCKED__SET(dst) \
73266 (dst) = ((dst) &\
73268 #define TXRF5__PAL_LOCKED__CLR(dst) \
73269 (dst) = ((dst) &\
73277 #define TXRF5__FBHI2G__SET(dst) \
73278 (dst) = ((dst) &\
73280 #define TXRF5__FBHI2G__CLR(dst) \
73281 (dst) = ((dst) &\
73289 #define TXRF5__FBLO2G__SET(dst) \
73290 (dst) = ((dst) &\
73292 #define TXRF5__FBLO2G__CLR(dst) \
73293 (dst) = ((dst) &\
73302 #define TXRF5__NOPALGAIN2G__MODIFY(dst, src) \
73303 (dst) = ((dst) &\
73309 #define TXRF5__NOPALGAIN2G__SET(dst) \
73310 (dst) = ((dst) &\
73312 #define TXRF5__NOPALGAIN2G__CLR(dst) \
73313 (dst) = ((dst) &\
73322 #define TXRF5__ENPACAL2G__MODIFY(dst, src) \
73323 (dst) = ((dst) &\
73329 #define TXRF5__ENPACAL2G__SET(dst) \
73330 (dst) = ((dst) &\
73332 #define TXRF5__ENPACAL2G__CLR(dst) \
73333 (dst) = ((dst) &\
73342 #define TXRF5__OFFSET2G__MODIFY(dst, src) \
73343 (dst) = ((dst) &\
73360 #define TXRF5__ENOFFSETCAL2G__MODIFY(dst, src) \
73361 (dst) = ((dst) &\
73367 #define TXRF5__ENOFFSETCAL2G__SET(dst) \
73368 (dst) = ((dst) &\
73370 #define TXRF5__ENOFFSETCAL2G__CLR(dst) \
73371 (dst) = ((dst) &\
73380 #define TXRF5__REFHI2G__MODIFY(dst, src) \
73381 (dst) = ((dst) &\
73394 #define TXRF5__REFLO2G__MODIFY(dst, src) \
73395 (dst) = ((dst) &\
73408 #define TXRF5__PALCLAMP2G__MODIFY(dst, src) \
73409 (dst) = ((dst) &\
73422 #define TXRF5__PK2B2G_QAM__MODIFY(dst, src) \
73423 (dst) = ((dst) &\
73436 #define TXRF5__PK2B2G_PSK__MODIFY(dst, src) \
73437 (dst) = ((dst) &\
73450 #define TXRF5__PK2B2G_CCK__MODIFY(dst, src) \
73451 (dst) = ((dst) &\
73464 #define TXRF5__PK1B2G_QAM__MODIFY(dst, src) \
73465 (dst) = ((dst) &\
73478 #define TXRF5__PK1B2G_PSK__MODIFY(dst, src) \
73479 (dst) = ((dst) &\
73505 #define TXRF6__PALCLKGATE2G__MODIFY(dst, src) \
73506 (dst) = ((dst) &\
73510 #define TXRF6__PALCLKGATE2G__SET(dst) \
73511 (dst) = ((dst) &\
73513 #define TXRF6__PALCLKGATE2G__CLR(dst) \
73514 (dst) = ((dst) &\
73527 #define TXRF6__PALFLUCTCOUNT2G__MODIFY(dst, src) \
73528 (dst) = ((dst) &\
73545 #define TXRF6__PALFLUCTGAIN2G__MODIFY(dst, src) \
73546 (dst) = ((dst) &\
73561 #define TXRF6__PALNOFLUCT2G__MODIFY(dst, src) \
73562 (dst) = ((dst) &\
73568 #define TXRF6__PALNOFLUCT2G__SET(dst) \
73569 (dst) = ((dst) &\
73571 #define TXRF6__PALNOFLUCT2G__CLR(dst) \
73572 (dst) = ((dst) &\
73581 #define TXRF6__GAINSTEP2G__MODIFY(dst, src) \
73582 (dst) = ((dst) &\
73599 #define TXRF6__USE_GAIN_DELTA2G__MODIFY(dst, src) \
73600 (dst) = ((dst) &\
73606 #define TXRF6__USE_GAIN_DELTA2G__SET(dst) \
73607 (dst) = ((dst) &\
73609 #define TXRF6__USE_GAIN_DELTA2G__CLR(dst) \
73610 (dst) = ((dst) &\
73619 #define TXRF6__CAPDIV_I2G__MODIFY(dst, src) \
73620 (dst) = ((dst) &\
73637 #define TXRF6__PADRVGN_INDEX_I2G__MODIFY(dst, src) \
73638 (dst) = ((dst) &\
73653 #define TXRF6__VCMONDELAY2G__MODIFY(dst, src) \
73654 (dst) = ((dst) &\
73667 #define TXRF6__CAPDIV2G__MODIFY(dst, src) \
73668 (dst) = ((dst) &\
73681 #define TXRF6__CAPDIV2GOVR__MODIFY(dst, src) \
73682 (dst) = ((dst) &\
73688 #define TXRF6__CAPDIV2GOVR__SET(dst) \
73689 (dst) = ((dst) &\
73691 #define TXRF6__CAPDIV2GOVR__CLR(dst) \
73692 (dst) = ((dst) &\
73714 #define TXRF7__SPARE7__MODIFY(dst, src) \
73715 (dst) = ((dst) &\
73726 #define TXRF7__PADRVGNTAB_4__MODIFY(dst, src) \
73727 (dst) = ((dst) &\
73740 #define TXRF7__PADRVGNTAB_3__MODIFY(dst, src) \
73741 (dst) = ((dst) &\
73756 #define TXRF7__PADRVGNTAB_2__MODIFY(dst, src) \
73757 (dst) = ((dst) &\
73772 #define TXRF7__PADRVGNTAB_1__MODIFY(dst, src) \
73773 (dst) = ((dst) &\
73788 #define TXRF7__PADRVGNTAB_0__MODIFY(dst, src) \
73789 (dst) = ((dst) &\
73815 #define TXRF8__SPARE8__MODIFY(dst, src) \
73816 (dst) = ((dst) &\
73827 #define TXRF8__PADRVGNTAB_9__MODIFY(dst, src) \
73828 (dst) = ((dst) &\
73841 #define TXRF8__PADRVGNTAB_8__MODIFY(dst, src) \
73842 (dst) = ((dst) &\
73857 #define TXRF8__PADRVGNTAB_7__MODIFY(dst, src) \
73858 (dst) = ((dst) &\
73873 #define TXRF8__PADRVGNTAB_6__MODIFY(dst, src) \
73874 (dst) = ((dst) &\
73889 #define TXRF8__PADRVGNTAB_5__MODIFY(dst, src) \
73890 (dst) = ((dst) &\
73916 #define TXRF9__SPARE9__MODIFY(dst, src) \
73917 (dst) = ((dst) &\
73930 #define TXRF9__PADRVGNTAB_14__MODIFY(dst, src) \
73931 (dst) = ((dst) &\
73946 #define TXRF9__PADRVGNTAB_13__MODIFY(dst, src) \
73947 (dst) = ((dst) &\
73964 #define TXRF9__PADRVGNTAB_12__MODIFY(dst, src) \
73965 (dst) = ((dst) &\
73982 #define TXRF9__PADRVGNTAB_11__MODIFY(dst, src) \
73983 (dst) = ((dst) &\
74000 #define TXRF9__PADRVGNTAB_10__MODIFY(dst, src) \
74001 (dst) = ((dst) &\
74027 #define TXRF10__SPARE10__MODIFY(dst, src) \
74028 (dst) = ((dst) &\
74043 #define TXRF10__PDOUT5G_3CALTX__MODIFY(dst, src) \
74044 (dst) = ((dst) &\
74050 #define TXRF10__PDOUT5G_3CALTX__SET(dst) \
74051 (dst) = ((dst) &\
74053 #define TXRF10__PDOUT5G_3CALTX__CLR(dst) \
74054 (dst) = ((dst) &\
74063 #define TXRF10__D3B5GCALTX__MODIFY(dst, src) \
74064 (dst) = ((dst) &\
74077 #define TXRF10__D4B5GCALTX__MODIFY(dst, src) \
74078 (dst) = ((dst) &\
74095 #define TXRF10__PADRVGN2GCALTX__MODIFY(dst, src) \
74096 (dst) = ((dst) &\
74109 #define TXRF10__DB2GCALTX__MODIFY(dst, src) \
74110 (dst) = ((dst) &\
74123 #define TXRF10__CALTXSHIFT__MODIFY(dst, src) \
74124 (dst) = ((dst) &\
74130 #define TXRF10__CALTXSHIFT__SET(dst) \
74131 (dst) = ((dst) &\
74133 #define TXRF10__CALTXSHIFT__CLR(dst) \
74134 (dst) = ((dst) &\
74147 #define TXRF10__CALTXSHIFTOVR__MODIFY(dst, src) \
74148 (dst) = ((dst) &\
74154 #define TXRF10__CALTXSHIFTOVR__SET(dst) \
74155 (dst) = ((dst) &\
74157 #define TXRF10__CALTXSHIFTOVR__CLR(dst) \
74158 (dst) = ((dst) &\
74196 #define TXRF11__SPARE11__MODIFY(dst, src) \
74197 (dst) = ((dst) &\
74212 #define TXRF11__PWD_IR25MIXDIV5G__MODIFY(dst, src) \
74213 (dst) = ((dst) &\
74228 #define TXRF11__PWD_IR25PA2G__MODIFY(dst, src) \
74229 (dst) = ((dst) &\
74246 #define TXRF11__PWD_IR25MIXBIAS2G__MODIFY(dst, src) \
74247 (dst) = ((dst) &\
74264 #define TXRF11__PWD_IR25MIXDIV2G__MODIFY(dst, src) \
74265 (dst) = ((dst) &\
74280 #define TXRF11__PWD_ICSPARE__MODIFY(dst, src) \
74281 (dst) = ((dst) &\
74298 #define TXRF11__PWD_IC25TEMPSEN__MODIFY(dst, src) \
74299 (dst) = ((dst) &\
74316 #define TXRF11__PWD_IC25PA5G2__MODIFY(dst, src) \
74317 (dst) = ((dst) &\
74334 #define TXRF11__PWD_IC25PA5G1__MODIFY(dst, src) \
74335 (dst) = ((dst) &\
74352 #define TXRF11__PWD_IC25MIXBUF5G__MODIFY(dst, src) \
74353 (dst) = ((dst) &\
74370 #define TXRF11__PWD_IC25PA2G__MODIFY(dst, src) \
74371 (dst) = ((dst) &\
74403 #define TXRF12__SPARE12_1__MODIFY(dst, src) \
74404 (dst) = ((dst) &\
74417 #define TXRF12__ATBSEL5G__MODIFY(dst, src) \
74418 (dst) = ((dst) &\
74431 #define TXRF12__ATBSEL2G__MODIFY(dst, src) \
74432 (dst) = ((dst) &\
74447 #define TXRF12__PWD_IRSPARE__MODIFY(dst, src) \
74448 (dst) = ((dst) &\
74465 #define TXRF12__PWD_IR25TEMPSEN__MODIFY(dst, src) \
74466 (dst) = ((dst) &\
74483 #define TXRF12__PWD_IR25PA5G2__MODIFY(dst, src) \
74484 (dst) = ((dst) &\
74501 #define TXRF12__PWD_IR25PA5G1__MODIFY(dst, src) \
74502 (dst) = ((dst) &\
74519 #define TXRF12__PWD_IR25MIXBIAS5G__MODIFY(dst, src) \
74520 (dst) = ((dst) &\
74546 #define SYNTH1__SEL_VCMONABUS__MODIFY(dst, src) \
74547 (dst) = ((dst) &\
74560 #define SYNTH1__SEL_VCOABUS__MODIFY(dst, src) \
74561 (dst) = ((dst) &\
74578 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__MODIFY(dst, src) \
74579 (dst) = ((dst) &\
74585 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__SET(dst) \
74586 (dst) = ((dst) &\
74588 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__CLR(dst) \
74589 (dst) = ((dst) &\
74602 #define SYNTH1__MONITOR_VC2LOW__MODIFY(dst, src) \
74603 (dst) = ((dst) &\
74609 #define SYNTH1__MONITOR_VC2LOW__SET(dst) \
74610 (dst) = ((dst) &\
74612 #define SYNTH1__MONITOR_VC2LOW__CLR(dst) \
74613 (dst) = ((dst) &\
74626 #define SYNTH1__MONITOR_VC2HIGH__MODIFY(dst, src) \
74627 (dst) = ((dst) &\
74633 #define SYNTH1__MONITOR_VC2HIGH__SET(dst) \
74634 (dst) = ((dst) &\
74636 #define SYNTH1__MONITOR_VC2HIGH__CLR(dst) \
74637 (dst) = ((dst) &\
74650 #define SYNTH1__MONITOR_FB_DIV2__MODIFY(dst, src) \
74651 (dst) = ((dst) &\
74657 #define SYNTH1__MONITOR_FB_DIV2__SET(dst) \
74658 (dst) = ((dst) &\
74660 #define SYNTH1__MONITOR_FB_DIV2__CLR(dst) \
74661 (dst) = ((dst) &\
74672 #define SYNTH1__MONITOR_REF__MODIFY(dst, src) \
74673 (dst) = ((dst) &\
74679 #define SYNTH1__MONITOR_REF__SET(dst) \
74680 (dst) = ((dst) &\
74682 #define SYNTH1__MONITOR_REF__CLR(dst) \
74683 (dst) = ((dst) &\
74692 #define SYNTH1__MONITOR_FB__MODIFY(dst, src) \
74693 (dst) = ((dst) &\
74699 #define SYNTH1__MONITOR_FB__SET(dst) \
74700 (dst) = ((dst) &\
74702 #define SYNTH1__MONITOR_FB__CLR(dst) \
74703 (dst) = ((dst) &\
74716 #define SYNTH1__SEVENBITVCOCAP__MODIFY(dst, src) \
74717 (dst) = ((dst) &\
74723 #define SYNTH1__SEVENBITVCOCAP__SET(dst) \
74724 (dst) = ((dst) &\
74726 #define SYNTH1__SEVENBITVCOCAP__CLR(dst) \
74727 (dst) = ((dst) &\
74736 #define SYNTH1__PWUP_PD__MODIFY(dst, src) \
74737 (dst) = ((dst) &\
74750 #define SYNTH1__PWD_VCOBUF__MODIFY(dst, src) \
74751 (dst) = ((dst) &\
74757 #define SYNTH1__PWD_VCOBUF__SET(dst) \
74758 (dst) = ((dst) &\
74760 #define SYNTH1__PWD_VCOBUF__CLR(dst) \
74761 (dst) = ((dst) &\
74770 #define SYNTH1__VCOBUFGAIN__MODIFY(dst, src) \
74771 (dst) = ((dst) &\
74786 #define SYNTH1__VCOREGLEVEL__MODIFY(dst, src) \
74787 (dst) = ((dst) &\
74804 #define SYNTH1__VCOREGBYPASS__MODIFY(dst, src) \
74805 (dst) = ((dst) &\
74811 #define SYNTH1__VCOREGBYPASS__SET(dst) \
74812 (dst) = ((dst) &\
74814 #define SYNTH1__VCOREGBYPASS__CLR(dst) \
74815 (dst) = ((dst) &\
74824 #define SYNTH1__PWUP_LOREF__MODIFY(dst, src) \
74825 (dst) = ((dst) &\
74831 #define SYNTH1__PWUP_LOREF__SET(dst) \
74832 (dst) = ((dst) &\
74834 #define SYNTH1__PWUP_LOREF__CLR(dst) \
74835 (dst) = ((dst) &\
74844 #define SYNTH1__PWD_LOMIX__MODIFY(dst, src) \
74845 (dst) = ((dst) &\
74851 #define SYNTH1__PWD_LOMIX__SET(dst) \
74852 (dst) = ((dst) &\
74854 #define SYNTH1__PWD_LOMIX__CLR(dst) \
74855 (dst) = ((dst) &\
74864 #define SYNTH1__PWD_LODIV__MODIFY(dst, src) \
74865 (dst) = ((dst) &\
74871 #define SYNTH1__PWD_LODIV__SET(dst) \
74872 (dst) = ((dst) &\
74874 #define SYNTH1__PWD_LODIV__CLR(dst) \
74875 (dst) = ((dst) &\
74886 #define SYNTH1__PWD_LOBUF5G__MODIFY(dst, src) \
74887 (dst) = ((dst) &\
74893 #define SYNTH1__PWD_LOBUF5G__SET(dst) \
74894 (dst) = ((dst) &\
74896 #define SYNTH1__PWD_LOBUF5G__CLR(dst) \
74897 (dst) = ((dst) &\
74908 #define SYNTH1__PWD_LOBUF2G__MODIFY(dst, src) \
74909 (dst) = ((dst) &\
74915 #define SYNTH1__PWD_LOBUF2G__SET(dst) \
74916 (dst) = ((dst) &\
74918 #define SYNTH1__PWD_LOBUF2G__CLR(dst) \
74919 (dst) = ((dst) &\
74928 #define SYNTH1__PWD_PRESC__MODIFY(dst, src) \
74929 (dst) = ((dst) &\
74935 #define SYNTH1__PWD_PRESC__SET(dst) \
74936 (dst) = ((dst) &\
74938 #define SYNTH1__PWD_PRESC__CLR(dst) \
74939 (dst) = ((dst) &\
74948 #define SYNTH1__PWD_VCO__MODIFY(dst, src) \
74949 (dst) = ((dst) &\
74955 #define SYNTH1__PWD_VCO__SET(dst) \
74956 (dst) = ((dst) &\
74958 #define SYNTH1__PWD_VCO__CLR(dst) \
74959 (dst) = ((dst) &\
74968 #define SYNTH1__PWD_VCMON__MODIFY(dst, src) \
74969 (dst) = ((dst) &\
74975 #define SYNTH1__PWD_VCMON__SET(dst) \
74976 (dst) = ((dst) &\
74978 #define SYNTH1__PWD_VCMON__CLR(dst) \
74979 (dst) = ((dst) &\
74988 #define SYNTH1__PWD_CP__MODIFY(dst, src) \
74989 (dst) = ((dst) &\
74995 #define SYNTH1__PWD_CP__SET(dst) \
74996 (dst) = ((dst) &\
74998 #define SYNTH1__PWD_CP__CLR(dst) \
74999 (dst) = ((dst) &\
75008 #define SYNTH1__PWD_BIAS__MODIFY(dst, src) \
75009 (dst) = ((dst) &\
75015 #define SYNTH1__PWD_BIAS__SET(dst) \
75016 (dst) = ((dst) &\
75018 #define SYNTH1__PWD_BIAS__CLR(dst) \
75019 (dst) = ((dst) &\
75041 #define SYNTH2__CAPRANGE3__MODIFY(dst, src) \
75042 (dst) = ((dst) &\
75053 #define SYNTH2__CAPRANGE2__MODIFY(dst, src) \
75054 (dst) = ((dst) &\
75067 #define SYNTH2__CAPRANGE1__MODIFY(dst, src) \
75068 (dst) = ((dst) &\
75085 #define SYNTH2__LOOPLEAKCUR_INTN__MODIFY(dst, src) \
75086 (dst) = ((dst) &\
75103 #define SYNTH2__CPLOWLK_INTN__MODIFY(dst, src) \
75104 (dst) = ((dst) &\
75110 #define SYNTH2__CPLOWLK_INTN__SET(dst) \
75111 (dst) = ((dst) &\
75113 #define SYNTH2__CPLOWLK_INTN__CLR(dst) \
75114 (dst) = ((dst) &\
75127 #define SYNTH2__CPSTEERING_EN_INTN__MODIFY(dst, src) \
75128 (dst) = ((dst) &\
75134 #define SYNTH2__CPSTEERING_EN_INTN__SET(dst) \
75135 (dst) = ((dst) &\
75137 #define SYNTH2__CPSTEERING_EN_INTN__CLR(dst) \
75138 (dst) = ((dst) &\
75149 #define SYNTH2__CPBIAS_INTN__MODIFY(dst, src) \
75150 (dst) = ((dst) &\
75163 #define SYNTH2__VC_LOW_REF__MODIFY(dst, src) \
75164 (dst) = ((dst) &\
75177 #define SYNTH2__VC_MID_REF__MODIFY(dst, src) \
75178 (dst) = ((dst) &\
75191 #define SYNTH2__VC_HI_REF__MODIFY(dst, src) \
75192 (dst) = ((dst) &\
75205 #define SYNTH2__VC_CAL_REF__MODIFY(dst, src) \
75206 (dst) = ((dst) &\
75232 #define SYNTH3__WAIT_VC_CHECK__MODIFY(dst, src) \
75233 (dst) = ((dst) &\
75248 #define SYNTH3__WAIT_CAL_LIN__MODIFY(dst, src) \
75249 (dst) = ((dst) &\
75266 #define SYNTH3__WAIT_CAL_BIN__MODIFY(dst, src) \
75267 (dst) = ((dst) &\
75280 #define SYNTH3__WAIT_PWRUP__MODIFY(dst, src) \
75281 (dst) = ((dst) &\
75298 #define SYNTH3__WAIT_SHORTR_PWRUP__MODIFY(dst, src) \
75299 (dst) = ((dst) &\
75316 #define SYNTH3__SEL_CLK_DIV2__MODIFY(dst, src) \
75317 (dst) = ((dst) &\
75323 #define SYNTH3__SEL_CLK_DIV2__SET(dst) \
75324 (dst) = ((dst) &\
75326 #define SYNTH3__SEL_CLK_DIV2__CLR(dst) \
75327 (dst) = ((dst) &\
75340 #define SYNTH3__DIS_CLK_XTAL__MODIFY(dst, src) \
75341 (dst) = ((dst) &\
75347 #define SYNTH3__DIS_CLK_XTAL__SET(dst) \
75348 (dst) = ((dst) &\
75350 #define SYNTH3__DIS_CLK_XTAL__CLR(dst) \
75351 (dst) = ((dst) &\
75373 #define SYNTH4__PS_SINGLE_PULSE__MODIFY(dst, src) \
75374 (dst) = ((dst) &\
75380 #define SYNTH4__PS_SINGLE_PULSE__SET(dst) \
75381 (dst) = ((dst) &\
75383 #define SYNTH4__PS_SINGLE_PULSE__CLR(dst) \
75384 (dst) = ((dst) &\
75395 #define SYNTH4__LONGSHIFTSEL__MODIFY(dst, src) \
75396 (dst) = ((dst) &\
75402 #define SYNTH4__LONGSHIFTSEL__SET(dst) \
75403 (dst) = ((dst) &\
75405 #define SYNTH4__LONGSHIFTSEL__CLR(dst) \
75406 (dst) = ((dst) &\
75419 #define SYNTH4__LOBUF5GTUNE_OVR__MODIFY(dst, src) \
75420 (dst) = ((dst) &\
75437 #define SYNTH4__FORCE_LOBUF5GTUNE__MODIFY(dst, src) \
75438 (dst) = ((dst) &\
75444 #define SYNTH4__FORCE_LOBUF5GTUNE__SET(dst) \
75445 (dst) = ((dst) &\
75447 #define SYNTH4__FORCE_LOBUF5GTUNE__CLR(dst) \
75448 (dst) = ((dst) &\
75461 #define SYNTH4__PSCOUNT_FBSEL__MODIFY(dst, src) \
75462 (dst) = ((dst) &\
75468 #define SYNTH4__PSCOUNT_FBSEL__SET(dst) \
75469 (dst) = ((dst) &\
75471 #define SYNTH4__PSCOUNT_FBSEL__CLR(dst) \
75472 (dst) = ((dst) &\
75481 #define SYNTH4__SDM_DITHER1__MODIFY(dst, src) \
75482 (dst) = ((dst) &\
75495 #define SYNTH4__SDM_MODE__MODIFY(dst, src) \
75496 (dst) = ((dst) &\
75502 #define SYNTH4__SDM_MODE__SET(dst) \
75503 (dst) = ((dst) &\
75505 #define SYNTH4__SDM_MODE__CLR(dst) \
75506 (dst) = ((dst) &\
75515 #define SYNTH4__SDM_DISABLE__MODIFY(dst, src) \
75516 (dst) = ((dst) &\
75522 #define SYNTH4__SDM_DISABLE__SET(dst) \
75523 (dst) = ((dst) &\
75525 #define SYNTH4__SDM_DISABLE__CLR(dst) \
75526 (dst) = ((dst) &\
75537 #define SYNTH4__RESET_PRESC__MODIFY(dst, src) \
75538 (dst) = ((dst) &\
75544 #define SYNTH4__RESET_PRESC__SET(dst) \
75545 (dst) = ((dst) &\
75547 #define SYNTH4__RESET_PRESC__CLR(dst) \
75548 (dst) = ((dst) &\
75557 #define SYNTH4__PRESCSEL__MODIFY(dst, src) \
75558 (dst) = ((dst) &\
75573 #define SYNTH4__PFD_DISABLE__MODIFY(dst, src) \
75574 (dst) = ((dst) &\
75580 #define SYNTH4__PFD_DISABLE__SET(dst) \
75581 (dst) = ((dst) &\
75583 #define SYNTH4__PFD_DISABLE__CLR(dst) \
75584 (dst) = ((dst) &\
75597 #define SYNTH4__PFDDELAY_FRACN__MODIFY(dst, src) \
75598 (dst) = ((dst) &\
75604 #define SYNTH4__PFDDELAY_FRACN__SET(dst) \
75605 (dst) = ((dst) &\
75607 #define SYNTH4__PFDDELAY_FRACN__CLR(dst) \
75608 (dst) = ((dst) &\
75619 #define SYNTH4__FORCE_LO_ON__MODIFY(dst, src) \
75620 (dst) = ((dst) &\
75626 #define SYNTH4__FORCE_LO_ON__SET(dst) \
75627 (dst) = ((dst) &\
75629 #define SYNTH4__FORCE_LO_ON__CLR(dst) \
75630 (dst) = ((dst) &\
75643 #define SYNTH4__CLKXTAL_EDGE_SEL__MODIFY(dst, src) \
75644 (dst) = ((dst) &\
75650 #define SYNTH4__CLKXTAL_EDGE_SEL__SET(dst) \
75651 (dst) = ((dst) &\
75653 #define SYNTH4__CLKXTAL_EDGE_SEL__CLR(dst) \
75654 (dst) = ((dst) &\
75667 #define SYNTH4__VCOCAPPULLUP__MODIFY(dst, src) \
75668 (dst) = ((dst) &\
75674 #define SYNTH4__VCOCAPPULLUP__SET(dst) \
75675 (dst) = ((dst) &\
75677 #define SYNTH4__VCOCAPPULLUP__CLR(dst) \
75678 (dst) = ((dst) &\
75687 #define SYNTH4__VCOCAP_OVR__MODIFY(dst, src) \
75688 (dst) = ((dst) &\
75705 #define SYNTH4__FORCE_VCOCAP__MODIFY(dst, src) \
75706 (dst) = ((dst) &\
75712 #define SYNTH4__FORCE_VCOCAP__SET(dst) \
75713 (dst) = ((dst) &\
75715 #define SYNTH4__FORCE_VCOCAP__CLR(dst) \
75716 (dst) = ((dst) &\
75727 #define SYNTH4__FORCE_PINVC__MODIFY(dst, src) \
75728 (dst) = ((dst) &\
75734 #define SYNTH4__FORCE_PINVC__SET(dst) \
75735 (dst) = ((dst) &\
75737 #define SYNTH4__FORCE_PINVC__CLR(dst) \
75738 (dst) = ((dst) &\
75751 #define SYNTH4__SHORTR_UNTIL_LOCKED__MODIFY(dst, src) \
75752 (dst) = ((dst) &\
75758 #define SYNTH4__SHORTR_UNTIL_LOCKED__SET(dst) \
75759 (dst) = ((dst) &\
75761 #define SYNTH4__SHORTR_UNTIL_LOCKED__CLR(dst) \
75762 (dst) = ((dst) &\
75775 #define SYNTH4__ALWAYS_SHORTR__MODIFY(dst, src) \
75776 (dst) = ((dst) &\
75782 #define SYNTH4__ALWAYS_SHORTR__SET(dst) \
75783 (dst) = ((dst) &\
75785 #define SYNTH4__ALWAYS_SHORTR__CLR(dst) \
75786 (dst) = ((dst) &\
75795 #define SYNTH4__DIS_LOSTVC__MODIFY(dst, src) \
75796 (dst) = ((dst) &\
75802 #define SYNTH4__DIS_LOSTVC__SET(dst) \
75803 (dst) = ((dst) &\
75805 #define SYNTH4__DIS_LOSTVC__CLR(dst) \
75806 (dst) = ((dst) &\
75819 #define SYNTH4__DIS_LIN_CAPSEARCH__MODIFY(dst, src) \
75820 (dst) = ((dst) &\
75826 #define SYNTH4__DIS_LIN_CAPSEARCH__SET(dst) \
75827 (dst) = ((dst) &\
75829 #define SYNTH4__DIS_LIN_CAPSEARCH__CLR(dst) \
75830 (dst) = ((dst) &\
75852 #define SYNTH5__VCOBIAS__MODIFY(dst, src) \
75853 (dst) = ((dst) &\
75868 #define SYNTH5__PWDB_ICLOBUF5G50__MODIFY(dst, src) \
75869 (dst) = ((dst) &\
75886 #define SYNTH5__PWDB_ICLOBUF2G50__MODIFY(dst, src) \
75887 (dst) = ((dst) &\
75902 #define SYNTH5__PWDB_ICVCO25__MODIFY(dst, src) \
75903 (dst) = ((dst) &\
75920 #define SYNTH5__PWDB_ICVCOREG25__MODIFY(dst, src) \
75921 (dst) = ((dst) &\
75938 #define SYNTH5__PWDB_IRVCOREG50__MODIFY(dst, src) \
75939 (dst) = ((dst) &\
75945 #define SYNTH5__PWDB_IRVCOREG50__SET(dst) \
75946 (dst) = ((dst) &\
75948 #define SYNTH5__PWDB_IRVCOREG50__CLR(dst) \
75949 (dst) = ((dst) &\
75962 #define SYNTH5__PWDB_ICLOMIX__MODIFY(dst, src) \
75963 (dst) = ((dst) &\
75980 #define SYNTH5__PWDB_ICLODIV50__MODIFY(dst, src) \
75981 (dst) = ((dst) &\
75998 #define SYNTH5__PWDB_ICPRESC50__MODIFY(dst, src) \
75999 (dst) = ((dst) &\
76016 #define SYNTH5__PWDB_IRVCMON25__MODIFY(dst, src) \
76017 (dst) = ((dst) &\
76034 #define SYNTH5__PWDB_IRPFDCP__MODIFY(dst, src) \
76035 (dst) = ((dst) &\
76050 #define SYNTH5__SDM_DITHER2__MODIFY(dst, src) \
76051 (dst) = ((dst) &\
76088 #define SYNTH6__VC2LOW__SET(dst) \
76089 (dst) = ((dst) &\
76091 #define SYNTH6__VC2LOW__CLR(dst) \
76092 (dst) = ((dst) &\
76100 #define SYNTH6__VC2HIGH__SET(dst) \
76101 (dst) = ((dst) &\
76103 #define SYNTH6__VC2HIGH__CLR(dst) \
76104 (dst) = ((dst) &\
76112 #define SYNTH6__RESET_SDM_B__SET(dst) \
76113 (dst) = ((dst) &\
76115 #define SYNTH6__RESET_SDM_B__CLR(dst) \
76116 (dst) = ((dst) &\
76126 #define SYNTH6__RESET_PSCOUNTERS__SET(dst) \
76127 (dst) = ((dst) &\
76129 #define SYNTH6__RESET_PSCOUNTERS__CLR(dst) \
76130 (dst) = ((dst) &\
76138 #define SYNTH6__RESET_PFD__SET(dst) \
76139 (dst) = ((dst) &\
76141 #define SYNTH6__RESET_PFD__CLR(dst) \
76142 (dst) = ((dst) &\
76150 #define SYNTH6__RESET_RFD__SET(dst) \
76151 (dst) = ((dst) &\
76153 #define SYNTH6__RESET_RFD__CLR(dst) \
76154 (dst) = ((dst) &\
76162 #define SYNTH6__SHORT_R__SET(dst) \
76163 (dst) = ((dst) &\
76165 #define SYNTH6__SHORT_R__CLR(dst) \
76166 (dst) = ((dst) &\
76180 #define SYNTH6__PIN_VC__SET(dst) \
76181 (dst) = ((dst) &\
76183 #define SYNTH6__PIN_VC__CLR(dst) \
76184 (dst) = ((dst) &\
76194 #define SYNTH6__SYNTH_LOCK_VC_OK__SET(dst) \
76195 (dst) = ((dst) &\
76197 #define SYNTH6__SYNTH_LOCK_VC_OK__CLR(dst) \
76198 (dst) = ((dst) &\
76206 #define SYNTH6__CAP_SEARCH__SET(dst) \
76207 (dst) = ((dst) &\
76209 #define SYNTH6__CAP_SEARCH__CLR(dst) \
76210 (dst) = ((dst) &\
76226 #define SYNTH6__SYNTH_ON__SET(dst) \
76227 (dst) = ((dst) &\
76229 #define SYNTH6__SYNTH_ON__CLR(dst) \
76230 (dst) = ((dst) &\
76251 #define SYNTH7__OVRCHANDECODER__MODIFY(dst, src) \
76252 (dst) = ((dst) &\
76258 #define SYNTH7__OVRCHANDECODER__SET(dst) \
76259 (dst) = ((dst) &\
76261 #define SYNTH7__OVRCHANDECODER__CLR(dst) \
76262 (dst) = ((dst) &\
76275 #define SYNTH7__FORCE_FRACLSB__MODIFY(dst, src) \
76276 (dst) = ((dst) &\
76282 #define SYNTH7__FORCE_FRACLSB__SET(dst) \
76283 (dst) = ((dst) &\
76285 #define SYNTH7__FORCE_FRACLSB__CLR(dst) \
76286 (dst) = ((dst) &\
76295 #define SYNTH7__CHANFRAC__MODIFY(dst, src) \
76296 (dst) = ((dst) &\
76309 #define SYNTH7__CHANSEL__MODIFY(dst, src) \
76310 (dst) = ((dst) &\
76325 #define SYNTH7__AMODEREFSEL__MODIFY(dst, src) \
76326 (dst) = ((dst) &\
76339 #define SYNTH7__FRACMODE__MODIFY(dst, src) \
76340 (dst) = ((dst) &\
76346 #define SYNTH7__FRACMODE__SET(dst) \
76347 (dst) = ((dst) &\
76349 #define SYNTH7__FRACMODE__CLR(dst) \
76350 (dst) = ((dst) &\
76363 #define SYNTH7__LOADSYNTHCHANNEL__MODIFY(dst, src) \
76364 (dst) = ((dst) &\
76370 #define SYNTH7__LOADSYNTHCHANNEL__SET(dst) \
76371 (dst) = ((dst) &\
76373 #define SYNTH7__LOADSYNTHCHANNEL__CLR(dst) \
76374 (dst) = ((dst) &\
76398 #define SYNTH8__CPSTEERING_EN_FRACN__MODIFY(dst, src) \
76399 (dst) = ((dst) &\
76405 #define SYNTH8__CPSTEERING_EN_FRACN__SET(dst) \
76406 (dst) = ((dst) &\
76408 #define SYNTH8__CPSTEERING_EN_FRACN__CLR(dst) \
76409 (dst) = ((dst) &\
76418 #define SYNTH8__LOOP_ICPB__MODIFY(dst, src) \
76419 (dst) = ((dst) &\
76432 #define SYNTH8__LOOP_CSB__MODIFY(dst, src) \
76433 (dst) = ((dst) &\
76446 #define SYNTH8__LOOP_RSB__MODIFY(dst, src) \
76447 (dst) = ((dst) &\
76460 #define SYNTH8__LOOP_CPB__MODIFY(dst, src) \
76461 (dst) = ((dst) &\
76478 #define SYNTH8__LOOP_3RD_ORDER_RB__MODIFY(dst, src) \
76479 (dst) = ((dst) &\
76492 #define SYNTH8__REFDIVB__MODIFY(dst, src) \
76493 (dst) = ((dst) &\
76519 #define SYNTH9__PFDDELAY_INTN__MODIFY(dst, src) \
76520 (dst) = ((dst) &\
76526 #define SYNTH9__PFDDELAY_INTN__SET(dst) \
76527 (dst) = ((dst) &\
76529 #define SYNTH9__PFDDELAY_INTN__CLR(dst) \
76530 (dst) = ((dst) &\
76539 #define SYNTH9__SLOPE_ICPA0__MODIFY(dst, src) \
76540 (dst) = ((dst) &\
76553 #define SYNTH9__LOOP_ICPA0__MODIFY(dst, src) \
76554 (dst) = ((dst) &\
76567 #define SYNTH9__LOOP_CSA0__MODIFY(dst, src) \
76568 (dst) = ((dst) &\
76581 #define SYNTH9__LOOP_RSA0__MODIFY(dst, src) \
76582 (dst) = ((dst) &\
76595 #define SYNTH9__LOOP_CPA0__MODIFY(dst, src) \
76596 (dst) = ((dst) &\
76613 #define SYNTH9__LOOP_3RD_ORDER_RA__MODIFY(dst, src) \
76614 (dst) = ((dst) &\
76627 #define SYNTH9__REFDIVA__MODIFY(dst, src) \
76628 (dst) = ((dst) &\
76654 #define SYNTH10__SPARE10A__MODIFY(dst, src) \
76655 (dst) = ((dst) &\
76670 #define SYNTH10__PWDB_ICLOBIAS50__MODIFY(dst, src) \
76671 (dst) = ((dst) &\
76688 #define SYNTH10__PWDB_IRSPARE25__MODIFY(dst, src) \
76689 (dst) = ((dst) &\
76706 #define SYNTH10__PWDB_ICSPARE25__MODIFY(dst, src) \
76707 (dst) = ((dst) &\
76724 #define SYNTH10__SLOPE_ICPA1__MODIFY(dst, src) \
76725 (dst) = ((dst) &\
76740 #define SYNTH10__LOOP_ICPA1__MODIFY(dst, src) \
76741 (dst) = ((dst) &\
76754 #define SYNTH10__LOOP_CSA1__MODIFY(dst, src) \
76755 (dst) = ((dst) &\
76768 #define SYNTH10__LOOP_RSA1__MODIFY(dst, src) \
76769 (dst) = ((dst) &\
76782 #define SYNTH10__LOOP_CPA1__MODIFY(dst, src) \
76783 (dst) = ((dst) &\
76809 #define SYNTH11__SPARE11A__MODIFY(dst, src) \
76810 (dst) = ((dst) &\
76825 #define SYNTH11__FORCE_LOBUF5G_ON__MODIFY(dst, src) \
76826 (dst) = ((dst) &\
76832 #define SYNTH11__FORCE_LOBUF5G_ON__SET(dst) \
76833 (dst) = ((dst) &\
76835 #define SYNTH11__FORCE_LOBUF5G_ON__CLR(dst) \
76836 (dst) = ((dst) &\
76845 #define SYNTH11__LOREFSEL__MODIFY(dst, src) \
76846 (dst) = ((dst) &\
76861 #define SYNTH11__LOBUF2GTUNE__MODIFY(dst, src) \
76862 (dst) = ((dst) &\
76879 #define SYNTH11__CPSTEERING_MODE__MODIFY(dst, src) \
76880 (dst) = ((dst) &\
76886 #define SYNTH11__CPSTEERING_MODE__SET(dst) \
76887 (dst) = ((dst) &\
76889 #define SYNTH11__CPSTEERING_MODE__CLR(dst) \
76890 (dst) = ((dst) &\
76903 #define SYNTH11__SLOPE_ICPA2__MODIFY(dst, src) \
76904 (dst) = ((dst) &\
76919 #define SYNTH11__LOOP_ICPA2__MODIFY(dst, src) \
76920 (dst) = ((dst) &\
76933 #define SYNTH11__LOOP_CSA2__MODIFY(dst, src) \
76934 (dst) = ((dst) &\
76947 #define SYNTH11__LOOP_RSA2__MODIFY(dst, src) \
76948 (dst) = ((dst) &\
76961 #define SYNTH11__LOOP_CPA2__MODIFY(dst, src) \
76962 (dst) = ((dst) &\
76988 #define SYNTH12__SPARE12A__MODIFY(dst, src) \
76989 (dst) = ((dst) &\
77004 #define SYNTH12__LOOPLEAKCUR_FRACN__MODIFY(dst, src) \
77005 (dst) = ((dst) &\
77022 #define SYNTH12__CPLOWLK_FRACN__MODIFY(dst, src) \
77023 (dst) = ((dst) &\
77029 #define SYNTH12__CPLOWLK_FRACN__SET(dst) \
77030 (dst) = ((dst) &\
77032 #define SYNTH12__CPLOWLK_FRACN__CLR(dst) \
77033 (dst) = ((dst) &\
77046 #define SYNTH12__CPBIAS_FRACN__MODIFY(dst, src) \
77047 (dst) = ((dst) &\
77064 #define SYNTH12__SYNTHDIGOUTEN__MODIFY(dst, src) \
77065 (dst) = ((dst) &\
77071 #define SYNTH12__SYNTHDIGOUTEN__SET(dst) \
77072 (dst) = ((dst) &\
77074 #define SYNTH12__SYNTHDIGOUTEN__CLR(dst) \
77075 (dst) = ((dst) &\
77084 #define SYNTH12__STRCONT__MODIFY(dst, src) \
77085 (dst) = ((dst) &\
77091 #define SYNTH12__STRCONT__SET(dst) \
77092 (dst) = ((dst) &\
77094 #define SYNTH12__STRCONT__CLR(dst) \
77095 (dst) = ((dst) &\
77104 #define SYNTH12__VREFMUL3__MODIFY(dst, src) \
77105 (dst) = ((dst) &\
77118 #define SYNTH12__VREFMUL2__MODIFY(dst, src) \
77119 (dst) = ((dst) &\
77132 #define SYNTH12__VREFMUL1__MODIFY(dst, src) \
77133 (dst) = ((dst) &\
77150 #define SYNTH12__CLK_DOUBLER_EN__MODIFY(dst, src) \
77151 (dst) = ((dst) &\
77157 #define SYNTH12__CLK_DOUBLER_EN__SET(dst) \
77158 (dst) = ((dst) &\
77160 #define SYNTH12__CLK_DOUBLER_EN__CLR(dst) \
77161 (dst) = ((dst) &\
77183 #define SYNTH13__SPARE13A__MODIFY(dst, src) \
77184 (dst) = ((dst) &\
77188 #define SYNTH13__SPARE13A__SET(dst) \
77189 (dst) = ((dst) &\
77191 #define SYNTH13__SPARE13A__CLR(dst) \
77192 (dst) = ((dst) &\
77205 #define SYNTH13__SLOPE_ICPA_FRACN__MODIFY(dst, src) \
77206 (dst) = ((dst) &\
77223 #define SYNTH13__LOOP_ICPA_FRACN__MODIFY(dst, src) \
77224 (dst) = ((dst) &\
77241 #define SYNTH13__LOOP_CSA_FRACN__MODIFY(dst, src) \
77242 (dst) = ((dst) &\
77259 #define SYNTH13__LOOP_RSA_FRACN__MODIFY(dst, src) \
77260 (dst) = ((dst) &\
77277 #define SYNTH13__LOOP_CPA_FRACN__MODIFY(dst, src) \
77278 (dst) = ((dst) &\
77295 #define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MODIFY(dst, src) \
77296 (dst) = ((dst) &\
77313 #define SYNTH13__REFDIVA_FRACN__MODIFY(dst, src) \
77314 (dst) = ((dst) &\
77340 #define SYNTH14__SPARE14A__MODIFY(dst, src) \
77341 (dst) = ((dst) &\
77356 #define SYNTH14__LOBUF5GTUNE_3__MODIFY(dst, src) \
77357 (dst) = ((dst) &\
77374 #define SYNTH14__LOBUF2GTUNE_3__MODIFY(dst, src) \
77375 (dst) = ((dst) &\
77392 #define SYNTH14__LOBUF5GTUNE_2__MODIFY(dst, src) \
77393 (dst) = ((dst) &\
77410 #define SYNTH14__LOBUF2GTUNE_2__MODIFY(dst, src) \
77411 (dst) = ((dst) &\
77428 #define SYNTH14__PWD_LOBUF5G_3__MODIFY(dst, src) \
77429 (dst) = ((dst) &\
77435 #define SYNTH14__PWD_LOBUF5G_3__SET(dst) \
77436 (dst) = ((dst) &\
77438 #define SYNTH14__PWD_LOBUF5G_3__CLR(dst) \
77439 (dst) = ((dst) &\
77452 #define SYNTH14__PWD_LOBUF2G_3__MODIFY(dst, src) \
77453 (dst) = ((dst) &\
77459 #define SYNTH14__PWD_LOBUF2G_3__SET(dst) \
77460 (dst) = ((dst) &\
77462 #define SYNTH14__PWD_LOBUF2G_3__CLR(dst) \
77463 (dst) = ((dst) &\
77476 #define SYNTH14__PWD_LOBUF5G_2__MODIFY(dst, src) \
77477 (dst) = ((dst) &\
77483 #define SYNTH14__PWD_LOBUF5G_2__SET(dst) \
77484 (dst) = ((dst) &\
77486 #define SYNTH14__PWD_LOBUF5G_2__CLR(dst) \
77487 (dst) = ((dst) &\
77500 #define SYNTH14__PWD_LOBUF2G_2__MODIFY(dst, src) \
77501 (dst) = ((dst) &\
77507 #define SYNTH14__PWD_LOBUF2G_2__SET(dst) \
77508 (dst) = ((dst) &\
77510 #define SYNTH14__PWD_LOBUF2G_2__CLR(dst) \
77511 (dst) = ((dst) &\
77524 #define SYNTH14__PWUPLO23_PD__MODIFY(dst, src) \
77525 (dst) = ((dst) &\
77542 #define SYNTH14__PWDB_ICLOBUF5G50_3__MODIFY(dst, src) \
77543 (dst) = ((dst) &\
77560 #define SYNTH14__PWDB_ICLOBUF2G50_3__MODIFY(dst, src) \
77561 (dst) = ((dst) &\
77578 #define SYNTH14__PWDB_ICLOBUF5G50_2__MODIFY(dst, src) \
77579 (dst) = ((dst) &\
77596 #define SYNTH14__PWDB_ICLOBUF2G50_2__MODIFY(dst, src) \
77597 (dst) = ((dst) &\
77614 #define SYNTH14__PWDB_ICLVLSHFT__MODIFY(dst, src) \
77615 (dst) = ((dst) &\
77641 #define BIAS1__SPARE1__MODIFY(dst, src) \
77642 (dst) = ((dst) &\
77655 #define BIAS1__PWD_IC100PCIE__MODIFY(dst, src) \
77656 (dst) = ((dst) &\
77669 #define BIAS1__PWD_IC25V2IQ__MODIFY(dst, src) \
77670 (dst) = ((dst) &\
77683 #define BIAS1__PWD_IC25V2II__MODIFY(dst, src) \
77684 (dst) = ((dst) &\
77697 #define BIAS1__PWD_IC25BB__MODIFY(dst, src) \
77698 (dst) = ((dst) &\
77711 #define BIAS1__PWD_IC25DAC__MODIFY(dst, src) \
77712 (dst) = ((dst) &\
77725 #define BIAS1__PWD_IC25FIR__MODIFY(dst, src) \
77726 (dst) = ((dst) &\
77739 #define BIAS1__PWD_IC25ADC__MODIFY(dst, src) \
77740 (dst) = ((dst) &\
77753 #define BIAS1__BIAS_SEL__MODIFY(dst, src) \
77754 (dst) = ((dst) &\
77780 #define BIAS2__SPARE2__MODIFY(dst, src) \
77781 (dst) = ((dst) &\
77796 #define BIAS2__PWD_IC25XTALREG__MODIFY(dst, src) \
77797 (dst) = ((dst) &\
77810 #define BIAS2__PWD_IC25XTAL__MODIFY(dst, src) \
77811 (dst) = ((dst) &\
77826 #define BIAS2__PWD_IC25TXRF__MODIFY(dst, src) \
77827 (dst) = ((dst) &\
77842 #define BIAS2__PWD_IC25RXRF__MODIFY(dst, src) \
77843 (dst) = ((dst) &\
77860 #define BIAS2__PWD_IC25SYNTH__MODIFY(dst, src) \
77861 (dst) = ((dst) &\
77878 #define BIAS2__PWD_IC25PLLREG__MODIFY(dst, src) \
77879 (dst) = ((dst) &\
77896 #define BIAS2__PWD_IC25PLLCP2__MODIFY(dst, src) \
77897 (dst) = ((dst) &\
77914 #define BIAS2__PWD_IC25PLLCP__MODIFY(dst, src) \
77915 (dst) = ((dst) &\
77932 #define BIAS2__PWD_IC25PLLGM__MODIFY(dst, src) \
77933 (dst) = ((dst) &\
77959 #define BIAS3__SPARE3__MODIFY(dst, src) \
77960 (dst) = ((dst) &\
77975 #define BIAS3__PWD_IR25XTALREG__MODIFY(dst, src) \
77976 (dst) = ((dst) &\
77989 #define BIAS3__PWD_IR25TXRF__MODIFY(dst, src) \
77990 (dst) = ((dst) &\
78003 #define BIAS3__PWD_IR25RXRF__MODIFY(dst, src) \
78004 (dst) = ((dst) &\
78021 #define BIAS3__PWD_IR25SYNTH__MODIFY(dst, src) \
78022 (dst) = ((dst) &\
78039 #define BIAS3__PWD_IR25PLLREG__MODIFY(dst, src) \
78040 (dst) = ((dst) &\
78053 #define BIAS3__PWD_IR25BB__MODIFY(dst, src) \
78054 (dst) = ((dst) &\
78067 #define BIAS3__PWD_IR50DAC__MODIFY(dst, src) \
78068 (dst) = ((dst) &\
78081 #define BIAS3__PWD_IR25DAC__MODIFY(dst, src) \
78082 (dst) = ((dst) &\
78095 #define BIAS3__PWD_IR25FIR__MODIFY(dst, src) \
78096 (dst) = ((dst) &\
78109 #define BIAS3__PWD_IR50ADC__MODIFY(dst, src) \
78110 (dst) = ((dst) &\
78136 #define BIAS4__SPARE4__MODIFY(dst, src) \
78137 (dst) = ((dst) &\
78152 #define BIAS4__PWD_IR25XPABIAS__MODIFY(dst, src) \
78153 (dst) = ((dst) &\
78170 #define BIAS4__PWD_IR25THERMADC__MODIFY(dst, src) \
78171 (dst) = ((dst) &\
78188 #define BIAS4__PWD_IR25OTPREG__MODIFY(dst, src) \
78189 (dst) = ((dst) &\
78206 #define BIAS4__PWD_IC25XPABIAS__MODIFY(dst, src) \
78207 (dst) = ((dst) &\
78224 #define BIAS4__PWD_IC25SPAREB__MODIFY(dst, src) \
78225 (dst) = ((dst) &\
78242 #define BIAS4__PWD_IC25SPAREA__MODIFY(dst, src) \
78243 (dst) = ((dst) &\
78269 #define RXTX1__SCFIR_GAIN__MODIFY(dst, src) \
78270 (dst) = ((dst) &\
78274 #define RXTX1__SCFIR_GAIN__SET(dst) \
78275 (dst) = ((dst) &\
78277 #define RXTX1__SCFIR_GAIN__CLR(dst) \
78278 (dst) = ((dst) &\
78287 #define RXTX1__MANRXGAIN__MODIFY(dst, src) \
78288 (dst) = ((dst) &\
78294 #define RXTX1__MANRXGAIN__SET(dst) \
78295 (dst) = ((dst) &\
78297 #define RXTX1__MANRXGAIN__CLR(dst) \
78298 (dst) = ((dst) &\
78307 #define RXTX1__AGC_DBDAC__MODIFY(dst, src) \
78308 (dst) = ((dst) &\
78323 #define RXTX1__OVR_AGC_DBDAC__MODIFY(dst, src) \
78324 (dst) = ((dst) &\
78330 #define RXTX1__OVR_AGC_DBDAC__SET(dst) \
78331 (dst) = ((dst) &\
78333 #define RXTX1__OVR_AGC_DBDAC__CLR(dst) \
78334 (dst) = ((dst) &\
78343 #define RXTX1__ENABLE_PAL__MODIFY(dst, src) \
78344 (dst) = ((dst) &\
78350 #define RXTX1__ENABLE_PAL__SET(dst) \
78351 (dst) = ((dst) &\
78353 #define RXTX1__ENABLE_PAL__CLR(dst) \
78354 (dst) = ((dst) &\
78367 #define RXTX1__ENABLE_PAL_OVR__MODIFY(dst, src) \
78368 (dst) = ((dst) &\
78374 #define RXTX1__ENABLE_PAL_OVR__SET(dst) \
78375 (dst) = ((dst) &\
78377 #define RXTX1__ENABLE_PAL_OVR__CLR(dst) \
78378 (dst) = ((dst) &\
78387 #define RXTX1__TX1DB_BIQUAD__MODIFY(dst, src) \
78388 (dst) = ((dst) &\
78403 #define RXTX1__TX6DB_BIQUAD__MODIFY(dst, src) \
78404 (dst) = ((dst) &\
78421 #define RXTX1__PADRVHALFGN2G__MODIFY(dst, src) \
78422 (dst) = ((dst) &\
78428 #define RXTX1__PADRVHALFGN2G__SET(dst) \
78429 (dst) = ((dst) &\
78431 #define RXTX1__PADRVHALFGN2G__CLR(dst) \
78432 (dst) = ((dst) &\
78441 #define RXTX1__PADRV2GN__MODIFY(dst, src) \
78442 (dst) = ((dst) &\
78455 #define RXTX1__PADRV3GN5G__MODIFY(dst, src) \
78456 (dst) = ((dst) &\
78469 #define RXTX1__PADRV4GN5G__MODIFY(dst, src) \
78470 (dst) = ((dst) &\
78483 #define RXTX1__TXBB_GC__MODIFY(dst, src) \
78484 (dst) = ((dst) &\
78497 #define RXTX1__MANTXGAIN__MODIFY(dst, src) \
78498 (dst) = ((dst) &\
78504 #define RXTX1__MANTXGAIN__SET(dst) \
78505 (dst) = ((dst) &\
78507 #define RXTX1__MANTXGAIN__CLR(dst) \
78508 (dst) = ((dst) &\
78530 #define RXTX2__BMODE__MODIFY(dst, src) \
78531 (dst) = ((dst) &\
78535 #define RXTX2__BMODE__SET(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(1)
78536 #define RXTX2__BMODE__CLR(dst) (dst) = ((dst) & ~0x00000001U) | (u_int32_t)(0)
78544 #define RXTX2__BMODE_OVR__MODIFY(dst, src) \
78545 (dst) = ((dst) &\
78551 #define RXTX2__BMODE_OVR__SET(dst) \
78552 (dst) = ((dst) &\
78554 #define RXTX2__BMODE_OVR__CLR(dst) \
78555 (dst) = ((dst) &\
78564 #define RXTX2__SYNTHON__MODIFY(dst, src) \
78565 (dst) = ((dst) &\
78571 #define RXTX2__SYNTHON__SET(dst) \
78572 (dst) = ((dst) &\
78574 #define RXTX2__SYNTHON__CLR(dst) \
78575 (dst) = ((dst) &\
78584 #define RXTX2__SYNTHON_OVR__MODIFY(dst, src) \
78585 (dst) = ((dst) &\
78591 #define RXTX2__SYNTHON_OVR__SET(dst) \
78592 (dst) = ((dst) &\
78594 #define RXTX2__SYNTHON_OVR__CLR(dst) \
78595 (dst) = ((dst) &\
78604 #define RXTX2__BW_ST__MODIFY(dst, src) \
78605 (dst) = ((dst) &\
78616 #define RXTX2__BW_ST_OVR__MODIFY(dst, src) \
78617 (dst) = ((dst) &\
78623 #define RXTX2__BW_ST_OVR__SET(dst) \
78624 (dst) = ((dst) &\
78626 #define RXTX2__BW_ST_OVR__CLR(dst) \
78627 (dst) = ((dst) &\
78636 #define RXTX2__TXON_OVR__MODIFY(dst, src) \
78637 (dst) = ((dst) &\
78643 #define RXTX2__TXON_OVR__SET(dst) \
78644 (dst) = ((dst) &\
78646 #define RXTX2__TXON_OVR__CLR(dst) \
78647 (dst) = ((dst) &\
78656 #define RXTX2__TXON__MODIFY(dst, src) \
78657 (dst) = ((dst) &\
78661 #define RXTX2__TXON__SET(dst) \
78662 (dst) = ((dst) &\
78664 #define RXTX2__TXON__CLR(dst) \
78665 (dst) = ((dst) &\
78674 #define RXTX2__PAON__MODIFY(dst, src) \
78675 (dst) = ((dst) &\
78679 #define RXTX2__PAON__SET(dst) \
78680 (dst) = ((dst) &\
78682 #define RXTX2__PAON__CLR(dst) \
78683 (dst) = ((dst) &\
78692 #define RXTX2__PAON_OVR__MODIFY(dst, src) \
78693 (dst) = ((dst) &\
78699 #define RXTX2__PAON_OVR__SET(dst) \
78700 (dst) = ((dst) &\
78702 #define RXTX2__PAON_OVR__CLR(dst) \
78703 (dst) = ((dst) &\
78712 #define RXTX2__RXON__MODIFY(dst, src) \
78713 (dst) = ((dst) &\
78717 #define RXTX2__RXON__SET(dst) \
78718 (dst) = ((dst) &\
78720 #define RXTX2__RXON__CLR(dst) \
78721 (dst) = ((dst) &\
78730 #define RXTX2__RXON_OVR__MODIFY(dst, src) \
78731 (dst) = ((dst) &\
78737 #define RXTX2__RXON_OVR__SET(dst) \
78738 (dst) = ((dst) &\
78740 #define RXTX2__RXON_OVR__CLR(dst) \
78741 (dst) = ((dst) &\
78750 #define RXTX2__AGCON__MODIFY(dst, src) \
78751 (dst) = ((dst) &\
78757 #define RXTX2__AGCON__SET(dst) \
78758 (dst) = ((dst) &\
78760 #define RXTX2__AGCON__CLR(dst) \
78761 (dst) = ((dst) &\
78770 #define RXTX2__AGCON_OVR__MODIFY(dst, src) \
78771 (dst) = ((dst) &\
78777 #define RXTX2__AGCON_OVR__SET(dst) \
78778 (dst) = ((dst) &\
78780 #define RXTX2__AGCON_OVR__CLR(dst) \
78781 (dst) = ((dst) &\
78790 #define RXTX2__TXMOD__MODIFY(dst, src) \
78791 (dst) = ((dst) &\
78804 #define RXTX2__TXMOD_OVR__MODIFY(dst, src) \
78805 (dst) = ((dst) &\
78811 #define RXTX2__TXMOD_OVR__SET(dst) \
78812 (dst) = ((dst) &\
78814 #define RXTX2__TXMOD_OVR__CLR(dst) \
78815 (dst) = ((dst) &\
78826 #define RXTX2__RX1DB_BIQUAD__MODIFY(dst, src) \
78827 (dst) = ((dst) &\
78842 #define RXTX2__RX6DB_BIQUAD__MODIFY(dst, src) \
78843 (dst) = ((dst) &\
78856 #define RXTX2__MXRGAIN__MODIFY(dst, src) \
78857 (dst) = ((dst) &\
78870 #define RXTX2__VGAGAIN__MODIFY(dst, src) \
78871 (dst) = ((dst) &\
78884 #define RXTX2__LNAGAIN__MODIFY(dst, src) \
78885 (dst) = ((dst) &\
78911 #define RXTX3__XLNABIAS_PWD__MODIFY(dst, src) \
78912 (dst) = ((dst) &\
78916 #define RXTX3__XLNABIAS_PWD__SET(dst) \
78917 (dst) = ((dst) &\
78919 #define RXTX3__XLNABIAS_PWD__CLR(dst) \
78920 (dst) = ((dst) &\
78929 #define RXTX3__XLNAON__MODIFY(dst, src) \
78930 (dst) = ((dst) &\
78936 #define RXTX3__XLNAON__SET(dst) \
78937 (dst) = ((dst) &\
78939 #define RXTX3__XLNAON__CLR(dst) \
78940 (dst) = ((dst) &\
78949 #define RXTX3__XLNAON_OVR__MODIFY(dst, src) \
78950 (dst) = ((dst) &\
78956 #define RXTX3__XLNAON_OVR__SET(dst) \
78957 (dst) = ((dst) &\
78959 #define RXTX3__XLNAON_OVR__CLR(dst) \
78960 (dst) = ((dst) &\
78969 #define RXTX3__DACFULLSCALE__MODIFY(dst, src) \
78970 (dst) = ((dst) &\
78976 #define RXTX3__DACFULLSCALE__SET(dst) \
78977 (dst) = ((dst) &\
78979 #define RXTX3__DACFULLSCALE__CLR(dst) \
78980 (dst) = ((dst) &\
78989 #define RXTX3__DACRSTB__MODIFY(dst, src) \
78990 (dst) = ((dst) &\
78996 #define RXTX3__DACRSTB__SET(dst) \
78997 (dst) = ((dst) &\
78999 #define RXTX3__DACRSTB__CLR(dst) \
79000 (dst) = ((dst) &\
79011 #define RXTX3__ADDACLOOPBACK__MODIFY(dst, src) \
79012 (dst) = ((dst) &\
79018 #define RXTX3__ADDACLOOPBACK__SET(dst) \
79019 (dst) = ((dst) &\
79021 #define RXTX3__ADDACLOOPBACK__CLR(dst) \
79022 (dst) = ((dst) &\
79031 #define RXTX3__ADCSHORT__MODIFY(dst, src) \
79032 (dst) = ((dst) &\
79038 #define RXTX3__ADCSHORT__SET(dst) \
79039 (dst) = ((dst) &\
79041 #define RXTX3__ADCSHORT__CLR(dst) \
79042 (dst) = ((dst) &\
79051 #define RXTX3__DACPWD__MODIFY(dst, src) \
79052 (dst) = ((dst) &\
79058 #define RXTX3__DACPWD__SET(dst) \
79059 (dst) = ((dst) &\
79061 #define RXTX3__DACPWD__CLR(dst) \
79062 (dst) = ((dst) &\
79071 #define RXTX3__DACPWD_OVR__MODIFY(dst, src) \
79072 (dst) = ((dst) &\
79078 #define RXTX3__DACPWD_OVR__SET(dst) \
79079 (dst) = ((dst) &\
79081 #define RXTX3__DACPWD_OVR__CLR(dst) \
79082 (dst) = ((dst) &\
79091 #define RXTX3__ADCPWD__MODIFY(dst, src) \
79092 (dst) = ((dst) &\
79098 #define RXTX3__ADCPWD__SET(dst) \
79099 (dst) = ((dst) &\
79101 #define RXTX3__ADCPWD__CLR(dst) \
79102 (dst) = ((dst) &\
79111 #define RXTX3__ADCPWD_OVR__MODIFY(dst, src) \
79112 (dst) = ((dst) &\
79118 #define RXTX3__ADCPWD_OVR__SET(dst) \
79119 (dst) = ((dst) &\
79121 #define RXTX3__ADCPWD_OVR__CLR(dst) \
79122 (dst) = ((dst) &\
79131 #define RXTX3__AGC_CALDAC__MODIFY(dst, src) \
79132 (dst) = ((dst) &\
79145 #define RXTX3__AGC_CAL__MODIFY(dst, src) \
79146 (dst) = ((dst) &\
79152 #define RXTX3__AGC_CAL__SET(dst) \
79153 (dst) = ((dst) &\
79155 #define RXTX3__AGC_CAL__CLR(dst) \
79156 (dst) = ((dst) &\
79165 #define RXTX3__AGC_CAL_OVR__MODIFY(dst, src) \
79166 (dst) = ((dst) &\
79172 #define RXTX3__AGC_CAL_OVR__SET(dst) \
79173 (dst) = ((dst) &\
79175 #define RXTX3__AGC_CAL_OVR__CLR(dst) \
79176 (dst) = ((dst) &\
79185 #define RXTX3__LOFORCEDON__MODIFY(dst, src) \
79186 (dst) = ((dst) &\
79192 #define RXTX3__LOFORCEDON__SET(dst) \
79193 (dst) = ((dst) &\
79195 #define RXTX3__LOFORCEDON__CLR(dst) \
79196 (dst) = ((dst) &\
79205 #define RXTX3__CALRESIDUE__MODIFY(dst, src) \
79206 (dst) = ((dst) &\
79212 #define RXTX3__CALRESIDUE__SET(dst) \
79213 (dst) = ((dst) &\
79215 #define RXTX3__CALRESIDUE__CLR(dst) \
79216 (dst) = ((dst) &\
79229 #define RXTX3__CALRESIDUE_OVR__MODIFY(dst, src) \
79230 (dst) = ((dst) &\
79236 #define RXTX3__CALRESIDUE_OVR__SET(dst) \
79237 (dst) = ((dst) &\
79239 #define RXTX3__CALRESIDUE_OVR__CLR(dst) \
79240 (dst) = ((dst) &\
79249 #define RXTX3__CALFC__MODIFY(dst, src) \
79250 (dst) = ((dst) &\
79256 #define RXTX3__CALFC__SET(dst) \
79257 (dst) = ((dst) &\
79259 #define RXTX3__CALFC__CLR(dst) \
79260 (dst) = ((dst) &\
79269 #define RXTX3__CALFC_OVR__MODIFY(dst, src) \
79270 (dst) = ((dst) &\
79276 #define RXTX3__CALFC_OVR__SET(dst) \
79277 (dst) = ((dst) &\
79279 #define RXTX3__CALFC_OVR__CLR(dst) \
79280 (dst) = ((dst) &\
79289 #define RXTX3__CALTX__MODIFY(dst, src) \
79290 (dst) = ((dst) &\
79296 #define RXTX3__CALTX__SET(dst) \
79297 (dst) = ((dst) &\
79299 #define RXTX3__CALTX__CLR(dst) \
79300 (dst) = ((dst) &\
79309 #define RXTX3__CALTX_OVR__MODIFY(dst, src) \
79310 (dst) = ((dst) &\
79316 #define RXTX3__CALTX_OVR__SET(dst) \
79317 (dst) = ((dst) &\
79319 #define RXTX3__CALTX_OVR__CLR(dst) \
79320 (dst) = ((dst) &\
79329 #define RXTX3__CALTXSHIFT__MODIFY(dst, src) \
79330 (dst) = ((dst) &\
79336 #define RXTX3__CALTXSHIFT__SET(dst) \
79337 (dst) = ((dst) &\
79339 #define RXTX3__CALTXSHIFT__CLR(dst) \
79340 (dst) = ((dst) &\
79353 #define RXTX3__CALTXSHIFT_OVR__MODIFY(dst, src) \
79354 (dst) = ((dst) &\
79360 #define RXTX3__CALTXSHIFT_OVR__SET(dst) \
79361 (dst) = ((dst) &\
79363 #define RXTX3__CALTXSHIFT_OVR__CLR(dst) \
79364 (dst) = ((dst) &\
79373 #define RXTX3__CALPA__MODIFY(dst, src) \
79374 (dst) = ((dst) &\
79380 #define RXTX3__CALPA__SET(dst) \
79381 (dst) = ((dst) &\
79383 #define RXTX3__CALPA__CLR(dst) \
79384 (dst) = ((dst) &\
79393 #define RXTX3__CALPA_OVR__MODIFY(dst, src) \
79394 (dst) = ((dst) &\
79400 #define RXTX3__CALPA_OVR__SET(dst) \
79401 (dst) = ((dst) &\
79403 #define RXTX3__CALPA_OVR__CLR(dst) \
79404 (dst) = ((dst) &\
79413 #define RXTX3__SPURON__MODIFY(dst, src) \
79414 (dst) = ((dst) &\
79420 #define RXTX3__SPURON__SET(dst) \
79421 (dst) = ((dst) &\
79423 #define RXTX3__SPURON__CLR(dst) \
79424 (dst) = ((dst) &\
79435 #define RXTX3__PAL_LOCKEDEN__MODIFY(dst, src) \
79436 (dst) = ((dst) &\
79442 #define RXTX3__PAL_LOCKEDEN__SET(dst) \
79443 (dst) = ((dst) &\
79445 #define RXTX3__PAL_LOCKEDEN__CLR(dst) \
79446 (dst) = ((dst) &\
79468 #define RXTX4__SPARE4__MODIFY(dst, src) \
79469 (dst) = ((dst) &\
79480 #define RXTX4__TESTIQ_ON__MODIFY(dst, src) \
79481 (dst) = ((dst) &\
79487 #define RXTX4__TESTIQ_ON__SET(dst) \
79488 (dst) = ((dst) &\
79490 #define RXTX4__TESTIQ_ON__CLR(dst) \
79491 (dst) = ((dst) &\
79502 #define RXTX4__TESTIQ_BUFEN__MODIFY(dst, src) \
79503 (dst) = ((dst) &\
79509 #define RXTX4__TESTIQ_BUFEN__SET(dst) \
79510 (dst) = ((dst) &\
79512 #define RXTX4__TESTIQ_BUFEN__CLR(dst) \
79513 (dst) = ((dst) &\
79522 #define RXTX4__TESTIQ_RSEL__MODIFY(dst, src) \
79523 (dst) = ((dst) &\
79529 #define RXTX4__TESTIQ_RSEL__SET(dst) \
79530 (dst) = ((dst) &\
79532 #define RXTX4__TESTIQ_RSEL__CLR(dst) \
79533 (dst) = ((dst) &\
79542 #define RXTX4__TURBOADC__MODIFY(dst, src) \
79543 (dst) = ((dst) &\
79549 #define RXTX4__TURBOADC__SET(dst) \
79550 (dst) = ((dst) &\
79552 #define RXTX4__TURBOADC__CLR(dst) \
79553 (dst) = ((dst) &\
79564 #define RXTX4__TURBOADC_OVR__MODIFY(dst, src) \
79565 (dst) = ((dst) &\
79571 #define RXTX4__TURBOADC_OVR__SET(dst) \
79572 (dst) = ((dst) &\
79574 #define RXTX4__TURBOADC_OVR__CLR(dst) \
79575 (dst) = ((dst) &\
79584 #define RXTX4__THERMON__MODIFY(dst, src) \
79585 (dst) = ((dst) &\
79591 #define RXTX4__THERMON__SET(dst) \
79592 (dst) = ((dst) &\
79594 #define RXTX4__THERMON__CLR(dst) \
79595 (dst) = ((dst) &\
79604 #define RXTX4__THERMON_OVR__MODIFY(dst, src) \
79605 (dst) = ((dst) &\
79611 #define RXTX4__THERMON_OVR__SET(dst) \
79612 (dst) = ((dst) &\
79614 #define RXTX4__THERMON_OVR__CLR(dst) \
79615 (dst) = ((dst) &\
79628 #define RXTX4__XLNA_STRENGTH__MODIFY(dst, src) \
79629 (dst) = ((dst) &\
79655 #define BB1__I2V_CURR2X__MODIFY(dst, src) \
79656 (dst) = ((dst) &\
79660 #define BB1__I2V_CURR2X__SET(dst) \
79661 (dst) = ((dst) &\
79663 #define BB1__I2V_CURR2X__CLR(dst) \
79664 (dst) = ((dst) &\
79673 #define BB1__ENABLE_LOQ__MODIFY(dst, src) \
79674 (dst) = ((dst) &\
79680 #define BB1__ENABLE_LOQ__SET(dst) \
79681 (dst) = ((dst) &\
79683 #define BB1__ENABLE_LOQ__CLR(dst) \
79684 (dst) = ((dst) &\
79693 #define BB1__FORCE_LOQ__MODIFY(dst, src) \
79694 (dst) = ((dst) &\
79700 #define BB1__FORCE_LOQ__SET(dst) \
79701 (dst) = ((dst) &\
79703 #define BB1__FORCE_LOQ__CLR(dst) \
79704 (dst) = ((dst) &\
79713 #define BB1__ENABLE_NOTCH__MODIFY(dst, src) \
79714 (dst) = ((dst) &\
79720 #define BB1__ENABLE_NOTCH__SET(dst) \
79721 (dst) = ((dst) &\
79723 #define BB1__ENABLE_NOTCH__CLR(dst) \
79724 (dst) = ((dst) &\
79733 #define BB1__FORCE_NOTCH__MODIFY(dst, src) \
79734 (dst) = ((dst) &\
79740 #define BB1__FORCE_NOTCH__SET(dst) \
79741 (dst) = ((dst) &\
79743 #define BB1__FORCE_NOTCH__CLR(dst) \
79744 (dst) = ((dst) &\
79753 #define BB1__ENABLE_BIQUAD__MODIFY(dst, src) \
79754 (dst) = ((dst) &\
79760 #define BB1__ENABLE_BIQUAD__SET(dst) \
79761 (dst) = ((dst) &\
79763 #define BB1__ENABLE_BIQUAD__CLR(dst) \
79764 (dst) = ((dst) &\
79773 #define BB1__FORCE_BIQUAD__MODIFY(dst, src) \
79774 (dst) = ((dst) &\
79780 #define BB1__FORCE_BIQUAD__SET(dst) \
79781 (dst) = ((dst) &\
79783 #define BB1__FORCE_BIQUAD__CLR(dst) \
79784 (dst) = ((dst) &\
79793 #define BB1__ENABLE_OSDAC__MODIFY(dst, src) \
79794 (dst) = ((dst) &\
79800 #define BB1__ENABLE_OSDAC__SET(dst) \
79801 (dst) = ((dst) &\
79803 #define BB1__ENABLE_OSDAC__CLR(dst) \
79804 (dst) = ((dst) &\
79813 #define BB1__FORCE_OSDAC__MODIFY(dst, src) \
79814 (dst) = ((dst) &\
79820 #define BB1__FORCE_OSDAC__SET(dst) \
79821 (dst) = ((dst) &\
79823 #define BB1__FORCE_OSDAC__CLR(dst) \
79824 (dst) = ((dst) &\
79833 #define BB1__ENABLE_V2I__MODIFY(dst, src) \
79834 (dst) = ((dst) &\
79840 #define BB1__ENABLE_V2I__SET(dst) \
79841 (dst) = ((dst) &\
79843 #define BB1__ENABLE_V2I__CLR(dst) \
79844 (dst) = ((dst) &\
79853 #define BB1__FORCE_V2I__MODIFY(dst, src) \
79854 (dst) = ((dst) &\
79860 #define BB1__FORCE_V2I__SET(dst) \
79861 (dst) = ((dst) &\
79863 #define BB1__FORCE_V2I__CLR(dst) \
79864 (dst) = ((dst) &\
79873 #define BB1__ENABLE_I2V__MODIFY(dst, src) \
79874 (dst) = ((dst) &\
79880 #define BB1__ENABLE_I2V__SET(dst) \
79881 (dst) = ((dst) &\
79883 #define BB1__ENABLE_I2V__CLR(dst) \
79884 (dst) = ((dst) &\
79893 #define BB1__FORCE_I2V__MODIFY(dst, src) \
79894 (dst) = ((dst) &\
79900 #define BB1__FORCE_I2V__SET(dst) \
79901 (dst) = ((dst) &\
79903 #define BB1__FORCE_I2V__CLR(dst) \
79904 (dst) = ((dst) &\
79913 #define BB1__CMSEL__MODIFY(dst, src) \
79914 (dst) = ((dst) &\
79925 #define BB1__ATBSEL__MODIFY(dst, src) \
79926 (dst) = ((dst) &\
79941 #define BB1__PD_OSDAC_CALTX_CALPA__MODIFY(dst, src) \
79942 (dst) = ((dst) &\
79948 #define BB1__PD_OSDAC_CALTX_CALPA__SET(dst) \
79949 (dst) = ((dst) &\
79951 #define BB1__PD_OSDAC_CALTX_CALPA__CLR(dst) \
79952 (dst) = ((dst) &\
79961 #define BB1__OFSTCORRI2VQ__MODIFY(dst, src) \
79962 (dst) = ((dst) &\
79975 #define BB1__OFSTCORRI2VI__MODIFY(dst, src) \
79976 (dst) = ((dst) &\
79989 #define BB1__LOCALOFFSET__MODIFY(dst, src) \
79990 (dst) = ((dst) &\
79996 #define BB1__LOCALOFFSET__SET(dst) \
79997 (dst) = ((dst) &\
79999 #define BB1__LOCALOFFSET__CLR(dst) \
80000 (dst) = ((dst) &\
80009 #define BB1__RANGE_OSDAC__MODIFY(dst, src) \
80010 (dst) = ((dst) &\
80036 #define BB2__SPARE__MODIFY(dst, src) \
80037 (dst) = ((dst) &\
80052 #define BB2__MXR_HIGHGAINMASK__MODIFY(dst, src) \
80053 (dst) = ((dst) &\
80066 #define BB2__SEL_TEST__MODIFY(dst, src) \
80067 (dst) = ((dst) &\
80080 #define BB2__RCFILTER_CAP__MODIFY(dst, src) \
80081 (dst) = ((dst) &\
80098 #define BB2__OVERRIDE_RCFILTER_CAP__MODIFY(dst, src) \
80099 (dst) = ((dst) &\
80105 #define BB2__OVERRIDE_RCFILTER_CAP__SET(dst) \
80106 (dst) = ((dst) &\
80108 #define BB2__OVERRIDE_RCFILTER_CAP__CLR(dst) \
80109 (dst) = ((dst) &\
80118 #define BB2__FNOTCH__MODIFY(dst, src) \
80119 (dst) = ((dst) &\
80134 #define BB2__OVERRIDE_FNOTCH__MODIFY(dst, src) \
80135 (dst) = ((dst) &\
80141 #define BB2__OVERRIDE_FNOTCH__SET(dst) \
80142 (dst) = ((dst) &\
80144 #define BB2__OVERRIDE_FNOTCH__CLR(dst) \
80145 (dst) = ((dst) &\
80154 #define BB2__FILTERFC__MODIFY(dst, src) \
80155 (dst) = ((dst) &\
80172 #define BB2__OVERRIDE_FILTERFC__MODIFY(dst, src) \
80173 (dst) = ((dst) &\
80179 #define BB2__OVERRIDE_FILTERFC__SET(dst) \
80180 (dst) = ((dst) &\
80182 #define BB2__OVERRIDE_FILTERFC__CLR(dst) \
80183 (dst) = ((dst) &\
80192 #define BB2__I2V2RXOUT_EN__MODIFY(dst, src) \
80193 (dst) = ((dst) &\
80199 #define BB2__I2V2RXOUT_EN__SET(dst) \
80200 (dst) = ((dst) &\
80202 #define BB2__I2V2RXOUT_EN__CLR(dst) \
80203 (dst) = ((dst) &\
80212 #define BB2__BQ2RXOUT_EN__MODIFY(dst, src) \
80213 (dst) = ((dst) &\
80219 #define BB2__BQ2RXOUT_EN__SET(dst) \
80220 (dst) = ((dst) &\
80222 #define BB2__BQ2RXOUT_EN__CLR(dst) \
80223 (dst) = ((dst) &\
80232 #define BB2__RXIN2I2V_EN__MODIFY(dst, src) \
80233 (dst) = ((dst) &\
80239 #define BB2__RXIN2I2V_EN__SET(dst) \
80240 (dst) = ((dst) &\
80242 #define BB2__RXIN2I2V_EN__CLR(dst) \
80243 (dst) = ((dst) &\
80252 #define BB2__RXIN2BQ_EN__MODIFY(dst, src) \
80253 (dst) = ((dst) &\
80259 #define BB2__RXIN2BQ_EN__SET(dst) \
80260 (dst) = ((dst) &\
80262 #define BB2__RXIN2BQ_EN__CLR(dst) \
80263 (dst) = ((dst) &\
80276 #define BB2__SWITCH_OVERRIDE__MODIFY(dst, src) \
80277 (dst) = ((dst) &\
80283 #define BB2__SWITCH_OVERRIDE__SET(dst) \
80284 (dst) = ((dst) &\
80286 #define BB2__SWITCH_OVERRIDE__CLR(dst) \
80287 (dst) = ((dst) &\
80309 #define BB3__SPARE__MODIFY(dst, src) \
80310 (dst) = ((dst) &\
80323 #define BB3__SEL_OFST_READBK__MODIFY(dst, src) \
80324 (dst) = ((dst) &\
80341 #define BB3__OVERRIDE_RXONLY_FILTERFC__MODIFY(dst, src) \
80342 (dst) = ((dst) &\
80348 #define BB3__OVERRIDE_RXONLY_FILTERFC__SET(dst) \
80349 (dst) = ((dst) &\
80351 #define BB3__OVERRIDE_RXONLY_FILTERFC__CLR(dst) \
80352 (dst) = ((dst) &\
80365 #define BB3__RXONLY_FILTERFC__MODIFY(dst, src) \
80366 (dst) = ((dst) &\
80401 #define BB3__EN_TXBBCONSTCUR__MODIFY(dst, src) \
80402 (dst) = ((dst) &\
80408 #define BB3__EN_TXBBCONSTCUR__SET(dst) \
80409 (dst) = ((dst) &\
80411 #define BB3__EN_TXBBCONSTCUR__CLR(dst) \
80412 (dst) = ((dst) &\
80434 #define PLLCLKMODA__PWD_PLLSDM__MODIFY(dst, src) \
80435 (dst) = ((dst) &\
80441 #define PLLCLKMODA__PWD_PLLSDM__SET(dst) \
80442 (dst) = ((dst) &\
80444 #define PLLCLKMODA__PWD_PLLSDM__CLR(dst) \
80445 (dst) = ((dst) &\
80454 #define PLLCLKMODA__PWDPLL__MODIFY(dst, src) \
80455 (dst) = ((dst) &\
80461 #define PLLCLKMODA__PWDPLL__SET(dst) \
80462 (dst) = ((dst) &\
80464 #define PLLCLKMODA__PWDPLL__CLR(dst) \
80465 (dst) = ((dst) &\
80474 #define PLLCLKMODA__PLLFRAC__MODIFY(dst, src) \
80475 (dst) = ((dst) &\
80488 #define PLLCLKMODA__REFDIV__MODIFY(dst, src) \
80489 (dst) = ((dst) &\
80502 #define PLLCLKMODA__DIV__MODIFY(dst, src) \
80503 (dst) = ((dst) &\
80520 #define PLLCLKMODA__LOCAL_PLL__MODIFY(dst, src) \
80521 (dst) = ((dst) &\
80527 #define PLLCLKMODA__LOCAL_PLL__SET(dst) \
80528 (dst) = ((dst) &\
80530 #define PLLCLKMODA__LOCAL_PLL__CLR(dst) \
80531 (dst) = ((dst) &\
80553 #define PLLCLKMODA2__SPARE__MODIFY(dst, src) \
80554 (dst) = ((dst) &\
80569 #define PLLCLKMODA2__GLOBAL_CLK_EN__MODIFY(dst, src) \
80570 (dst) = ((dst) &\
80576 #define PLLCLKMODA2__GLOBAL_CLK_EN__SET(dst) \
80577 (dst) = ((dst) &\
80579 #define PLLCLKMODA2__GLOBAL_CLK_EN__CLR(dst) \
80580 (dst) = ((dst) &\
80593 #define PLLCLKMODA2__ADC_CLK_SEL__MODIFY(dst, src) \
80594 (dst) = ((dst) &\
80611 #define PLLCLKMODA2__LOCAL_CLKMODA__MODIFY(dst, src) \
80612 (dst) = ((dst) &\
80618 #define PLLCLKMODA2__LOCAL_CLKMODA__SET(dst) \
80619 (dst) = ((dst) &\
80621 #define PLLCLKMODA2__LOCAL_CLKMODA__CLR(dst) \
80622 (dst) = ((dst) &\
80635 #define PLLCLKMODA2__PLLBYPASS__MODIFY(dst, src) \
80636 (dst) = ((dst) &\
80642 #define PLLCLKMODA2__PLLBYPASS__SET(dst) \
80643 (dst) = ((dst) &\
80645 #define PLLCLKMODA2__PLLBYPASS__CLR(dst) \
80646 (dst) = ((dst) &\
80659 #define PLLCLKMODA2__LOCAL_PLLBYPASS__MODIFY(dst, src) \
80660 (dst) = ((dst) &\
80666 #define PLLCLKMODA2__LOCAL_PLLBYPASS__SET(dst) \
80667 (dst) = ((dst) &\
80669 #define PLLCLKMODA2__LOCAL_PLLBYPASS__CLR(dst) \
80670 (dst) = ((dst) &\
80681 #define PLLCLKMODA2__PLLATB__MODIFY(dst, src) \
80682 (dst) = ((dst) &\
80699 #define PLLCLKMODA2__PLL_SVREG__MODIFY(dst, src) \
80700 (dst) = ((dst) &\
80706 #define PLLCLKMODA2__PLL_SVREG__SET(dst) \
80707 (dst) = ((dst) &\
80709 #define PLLCLKMODA2__PLL_SVREG__CLR(dst) \
80710 (dst) = ((dst) &\
80723 #define PLLCLKMODA2__HI_FREQ_EN__MODIFY(dst, src) \
80724 (dst) = ((dst) &\
80730 #define PLLCLKMODA2__HI_FREQ_EN__SET(dst) \
80731 (dst) = ((dst) &\
80733 #define PLLCLKMODA2__HI_FREQ_EN__CLR(dst) \
80734 (dst) = ((dst) &\
80747 #define PLLCLKMODA2__DAC_CLK_SEL__MODIFY(dst, src) \
80748 (dst) = ((dst) &\
80765 #define PLLCLKMODA2__RST_WARM_INT_L__MODIFY(dst, src) \
80766 (dst) = ((dst) &\
80772 #define PLLCLKMODA2__RST_WARM_INT_L__SET(dst) \
80773 (dst) = ((dst) &\
80775 #define PLLCLKMODA2__RST_WARM_INT_L__CLR(dst) \
80776 (dst) = ((dst) &\
80789 #define PLLCLKMODA2__PLL_KVCO__MODIFY(dst, src) \
80790 (dst) = ((dst) &\
80805 #define PLLCLKMODA2__PLLICP__MODIFY(dst, src) \
80806 (dst) = ((dst) &\
80823 #define PLLCLKMODA2__PLLFILTER__MODIFY(dst, src) \
80824 (dst) = ((dst) &\
80850 #define TOP__SEL_TEMPSENSOR__MODIFY(dst, src) \
80851 (dst) = ((dst) &\
80855 #define TOP__SEL_TEMPSENSOR__SET(dst) \
80856 (dst) = ((dst) &\
80858 #define TOP__SEL_TEMPSENSOR__CLR(dst) \
80859 (dst) = ((dst) &\
80868 #define TOP__XPABIAS_BYPASS__MODIFY(dst, src) \
80869 (dst) = ((dst) &\
80875 #define TOP__XPABIAS_BYPASS__SET(dst) \
80876 (dst) = ((dst) &\
80878 #define TOP__XPABIAS_BYPASS__CLR(dst) \
80879 (dst) = ((dst) &\
80888 #define TOP__TESTIQ_RSEL__MODIFY(dst, src) \
80889 (dst) = ((dst) &\
80895 #define TOP__TESTIQ_RSEL__SET(dst) \
80896 (dst) = ((dst) &\
80898 #define TOP__TESTIQ_RSEL__CLR(dst) \
80899 (dst) = ((dst) &\
80908 #define TOP__CLK107_EN__MODIFY(dst, src) \
80909 (dst) = ((dst) &\
80915 #define TOP__CLK107_EN__SET(dst) \
80916 (dst) = ((dst) &\
80918 #define TOP__CLK107_EN__CLR(dst) \
80919 (dst) = ((dst) &\
80928 #define TOP__TEST_PAD_EN__MODIFY(dst, src) \
80929 (dst) = ((dst) &\
80935 #define TOP__TEST_PAD_EN__SET(dst) \
80936 (dst) = ((dst) &\
80938 #define TOP__TEST_PAD_EN__CLR(dst) \
80939 (dst) = ((dst) &\
80948 #define TOP__PWDV2I__MODIFY(dst, src) \
80949 (dst) = ((dst) &\
80953 #define TOP__PWDV2I__SET(dst) \
80954 (dst) = ((dst) &\
80956 #define TOP__PWDV2I__CLR(dst) \
80957 (dst) = ((dst) &\
80966 #define TOP__PWDBIAS__MODIFY(dst, src) \
80967 (dst) = ((dst) &\
80971 #define TOP__PWDBIAS__SET(dst) \
80972 (dst) = ((dst) &\
80974 #define TOP__PWDBIAS__CLR(dst) \
80975 (dst) = ((dst) &\
80984 #define TOP__PWDBG__MODIFY(dst, src) \
80985 (dst) = ((dst) &\
80989 #define TOP__PWDBG__SET(dst) \
80990 (dst) = ((dst) &\
80992 #define TOP__PWDBG__CLR(dst) \
80993 (dst) = ((dst) &\
81002 #define TOP__XPABIASLVL__MODIFY(dst, src) \
81003 (dst) = ((dst) &\
81020 #define TOP__XPAREGULATOR_EN__MODIFY(dst, src) \
81021 (dst) = ((dst) &\
81027 #define TOP__XPAREGULATOR_EN__SET(dst) \
81028 (dst) = ((dst) &\
81030 #define TOP__XPAREGULATOR_EN__CLR(dst) \
81031 (dst) = ((dst) &\
81040 #define TOP__SPARE__MODIFY(dst, src) \
81041 (dst) = ((dst) &\
81056 #define TOP__ADC_CLK_SEL_CH1__MODIFY(dst, src) \
81057 (dst) = ((dst) &\
81070 #define TOP__TESTIQ_OFF__MODIFY(dst, src) \
81071 (dst) = ((dst) &\
81077 #define TOP__TESTIQ_OFF__SET(dst) \
81078 (dst) = ((dst) &\
81080 #define TOP__TESTIQ_OFF__CLR(dst) \
81081 (dst) = ((dst) &\
81090 #define TOP__TESTIQ_BUFEN__MODIFY(dst, src) \
81091 (dst) = ((dst) &\
81097 #define TOP__TESTIQ_BUFEN__SET(dst) \
81098 (dst) = ((dst) &\
81100 #define TOP__TESTIQ_BUFEN__CLR(dst) \
81101 (dst) = ((dst) &\
81110 #define TOP__PAD2GND__MODIFY(dst, src) \
81111 (dst) = ((dst) &\
81117 #define TOP__PAD2GND__SET(dst) \
81118 (dst) = ((dst) &\
81120 #define TOP__PAD2GND__CLR(dst) \
81121 (dst) = ((dst) &\
81130 #define TOP__INTH2PAD__MODIFY(dst, src) \
81131 (dst) = ((dst) &\
81137 #define TOP__INTH2PAD__SET(dst) \
81138 (dst) = ((dst) &\
81140 #define TOP__INTH2PAD__CLR(dst) \
81141 (dst) = ((dst) &\
81150 #define TOP__INTH2GND__MODIFY(dst, src) \
81151 (dst) = ((dst) &\
81157 #define TOP__INTH2GND__SET(dst) \
81158 (dst) = ((dst) &\
81160 #define TOP__INTH2GND__CLR(dst) \
81161 (dst) = ((dst) &\
81170 #define TOP__INT2PAD__MODIFY(dst, src) \
81171 (dst) = ((dst) &\
81177 #define TOP__INT2PAD__SET(dst) \
81178 (dst) = ((dst) &\
81180 #define TOP__INT2PAD__CLR(dst) \
81181 (dst) = ((dst) &\
81190 #define TOP__INT2GND__MODIFY(dst, src) \
81191 (dst) = ((dst) &\
81197 #define TOP__INT2GND__SET(dst) \
81198 (dst) = ((dst) &\
81200 #define TOP__INT2GND__CLR(dst) \
81201 (dst) = ((dst) &\
81210 #define TOP__ENBTCLK__MODIFY(dst, src) \
81211 (dst) = ((dst) &\
81217 #define TOP__ENBTCLK__SET(dst) \
81218 (dst) = ((dst) &\
81220 #define TOP__ENBTCLK__CLR(dst) \
81221 (dst) = ((dst) &\
81230 #define TOP__PWDPALCLK__MODIFY(dst, src) \
81231 (dst) = ((dst) &\
81237 #define TOP__PWDPALCLK__SET(dst) \
81238 (dst) = ((dst) &\
81240 #define TOP__PWDPALCLK__CLR(dst) \
81241 (dst) = ((dst) &\
81252 #define TOP__INV_CLK320_ADC__MODIFY(dst, src) \
81253 (dst) = ((dst) &\
81259 #define TOP__INV_CLK320_ADC__SET(dst) \
81260 (dst) = ((dst) &\
81262 #define TOP__INV_CLK320_ADC__CLR(dst) \
81263 (dst) = ((dst) &\
81272 #define TOP__FLIP_REFCLK40__MODIFY(dst, src) \
81273 (dst) = ((dst) &\
81279 #define TOP__FLIP_REFCLK40__SET(dst) \
81280 (dst) = ((dst) &\
81282 #define TOP__FLIP_REFCLK40__CLR(dst) \
81283 (dst) = ((dst) &\
81294 #define TOP__FLIP_PLLCLK320__MODIFY(dst, src) \
81295 (dst) = ((dst) &\
81301 #define TOP__FLIP_PLLCLK320__SET(dst) \
81302 (dst) = ((dst) &\
81304 #define TOP__FLIP_PLLCLK320__CLR(dst) \
81305 (dst) = ((dst) &\
81316 #define TOP__FLIP_PLLCLK160__MODIFY(dst, src) \
81317 (dst) = ((dst) &\
81323 #define TOP__FLIP_PLLCLK160__SET(dst) \
81324 (dst) = ((dst) &\
81326 #define TOP__FLIP_PLLCLK160__CLR(dst) \
81327 (dst) = ((dst) &\
81336 #define TOP__CLK_SEL__MODIFY(dst, src) \
81337 (dst) = ((dst) &\
81363 #define TOP2__TESTTXIQ_ENBYPASS_B__MODIFY(dst, src) \
81364 (dst) = ((dst) &\
81381 #define TOP2__DAC_CLK_SEL_CH2__MODIFY(dst, src) \
81382 (dst) = ((dst) &\
81399 #define TOP2__DAC_CLK_SEL_CH1__MODIFY(dst, src) \
81400 (dst) = ((dst) &\
81415 #define TOP2__TESTTXIQ_RCTRL__MODIFY(dst, src) \
81416 (dst) = ((dst) &\
81433 #define TOP2__TESTTXIQ_ENLOOPBACK__MODIFY(dst, src) \
81434 (dst) = ((dst) &\
81447 #define TOP2__TESTTXIQ_PWD__MODIFY(dst, src) \
81448 (dst) = ((dst) &\
81461 #define TOP2__DACPWD__MODIFY(dst, src) \
81462 (dst) = ((dst) &\
81475 #define TOP2__ADCPWD__MODIFY(dst, src) \
81476 (dst) = ((dst) &\
81493 #define TOP2__LOCAL_ADDACPWD__MODIFY(dst, src) \
81494 (dst) = ((dst) &\
81500 #define TOP2__LOCAL_ADDACPWD__SET(dst) \
81501 (dst) = ((dst) &\
81503 #define TOP2__LOCAL_ADDACPWD__CLR(dst) \
81504 (dst) = ((dst) &\
81513 #define TOP2__LOCAL_XPAON__MODIFY(dst, src) \
81514 (dst) = ((dst) &\
81520 #define TOP2__LOCAL_XPAON__SET(dst) \
81521 (dst) = ((dst) &\
81523 #define TOP2__LOCAL_XPAON__CLR(dst) \
81524 (dst) = ((dst) &\
81533 #define TOP2__XPA5ON__MODIFY(dst, src) \
81534 (dst) = ((dst) &\
81547 #define TOP2__XPA2ON__MODIFY(dst, src) \
81548 (dst) = ((dst) &\
81574 #define THERM__XPABIASLVL_MSB__MODIFY(dst, src) \
81575 (dst) = ((dst) &\
81588 #define THERM__XPASHORT2GND__MODIFY(dst, src) \
81589 (dst) = ((dst) &\
81595 #define THERM__XPASHORT2GND__SET(dst) \
81596 (dst) = ((dst) &\
81598 #define THERM__XPASHORT2GND__CLR(dst) \
81599 (dst) = ((dst) &\
81612 #define THERM__ADC_CLK_SEL_CH2__MODIFY(dst, src) \
81613 (dst) = ((dst) &\
81625 #define THERM__SAR_ADC_DONE__SET(dst) \
81626 (dst) = ((dst) &\
81628 #define THERM__SAR_ADC_DONE__CLR(dst) \
81629 (dst) = ((dst) &\
81648 #define THERM__SAR_DACTEST_CODE__MODIFY(dst, src) \
81649 (dst) = ((dst) &\
81666 #define THERM__SAR_DACTEST_EN__MODIFY(dst, src) \
81667 (dst) = ((dst) &\
81673 #define THERM__SAR_DACTEST_EN__SET(dst) \
81674 (dst) = ((dst) &\
81676 #define THERM__SAR_DACTEST_EN__CLR(dst) \
81677 (dst) = ((dst) &\
81690 #define THERM__SAR_ADCCAL_EN__MODIFY(dst, src) \
81691 (dst) = ((dst) &\
81697 #define THERM__SAR_ADCCAL_EN__SET(dst) \
81698 (dst) = ((dst) &\
81700 #define THERM__SAR_ADCCAL_EN__CLR(dst) \
81701 (dst) = ((dst) &\
81710 #define THERM__THERMSEL__MODIFY(dst, src) \
81711 (dst) = ((dst) &\
81724 #define THERM__SAR_SLOW_EN__MODIFY(dst, src) \
81725 (dst) = ((dst) &\
81731 #define THERM__SAR_SLOW_EN__SET(dst) \
81732 (dst) = ((dst) &\
81734 #define THERM__SAR_SLOW_EN__CLR(dst) \
81735 (dst) = ((dst) &\
81744 #define THERM__THERMSTART__MODIFY(dst, src) \
81745 (dst) = ((dst) &\
81751 #define THERM__THERMSTART__SET(dst) \
81752 (dst) = ((dst) &\
81754 #define THERM__THERMSTART__CLR(dst) \
81755 (dst) = ((dst) &\
81768 #define THERM__SAR_AUTOPWD_EN__MODIFY(dst, src) \
81769 (dst) = ((dst) &\
81775 #define THERM__SAR_AUTOPWD_EN__SET(dst) \
81776 (dst) = ((dst) &\
81778 #define THERM__SAR_AUTOPWD_EN__CLR(dst) \
81779 (dst) = ((dst) &\
81788 #define THERM__LOCAL_THERM__MODIFY(dst, src) \
81789 (dst) = ((dst) &\
81795 #define THERM__LOCAL_THERM__SET(dst) \
81796 (dst) = ((dst) &\
81798 #define THERM__LOCAL_THERM__CLR(dst) \
81799 (dst) = ((dst) &\
81821 #define XTAL__SPARE__MODIFY(dst, src) \
81822 (dst) = ((dst) &\
81833 #define XTAL__LOCAL_XTAL__MODIFY(dst, src) \
81834 (dst) = ((dst) &\
81840 #define XTAL__LOCAL_XTAL__SET(dst) \
81841 (dst) = ((dst) &\
81843 #define XTAL__LOCAL_XTAL__CLR(dst) \
81844 (dst) = ((dst) &\
81853 #define XTAL__XTAL_PWDCLKIN__MODIFY(dst, src) \
81854 (dst) = ((dst) &\
81860 #define XTAL__XTAL_PWDCLKIN__SET(dst) \
81861 (dst) = ((dst) &\
81863 #define XTAL__XTAL_PWDCLKIN__CLR(dst) \
81864 (dst) = ((dst) &\
81873 #define XTAL__XTAL_OSCON__MODIFY(dst, src) \
81874 (dst) = ((dst) &\
81880 #define XTAL__XTAL_OSCON__SET(dst) \
81881 (dst) = ((dst) &\
81883 #define XTAL__XTAL_OSCON__CLR(dst) \
81884 (dst) = ((dst) &\
81893 #define XTAL__XTAL_SELVREG__MODIFY(dst, src) \
81894 (dst) = ((dst) &\
81900 #define XTAL__XTAL_SELVREG__SET(dst) \
81901 (dst) = ((dst) &\
81903 #define XTAL__XTAL_SELVREG__CLR(dst) \
81904 (dst) = ((dst) &\
81913 #define XTAL__XTAL_LBIAS2X__MODIFY(dst, src) \
81914 (dst) = ((dst) &\
81920 #define XTAL__XTAL_LBIAS2X__SET(dst) \
81921 (dst) = ((dst) &\
81923 #define XTAL__XTAL_LBIAS2X__CLR(dst) \
81924 (dst) = ((dst) &\
81933 #define XTAL__XTAL_BIAS2X__MODIFY(dst, src) \
81934 (dst) = ((dst) &\
81940 #define XTAL__XTAL_BIAS2X__SET(dst) \
81941 (dst) = ((dst) &\
81943 #define XTAL__XTAL_BIAS2X__CLR(dst) \
81944 (dst) = ((dst) &\
81953 #define XTAL__XTAL_PWDCLKD__MODIFY(dst, src) \
81954 (dst) = ((dst) &\
81960 #define XTAL__XTAL_PWDCLKD__SET(dst) \
81961 (dst) = ((dst) &\
81963 #define XTAL__XTAL_PWDCLKD__CLR(dst) \
81964 (dst) = ((dst) &\
81977 #define XTAL__XTAL_LOCALBIAS__MODIFY(dst, src) \
81978 (dst) = ((dst) &\
81984 #define XTAL__XTAL_LOCALBIAS__SET(dst) \
81985 (dst) = ((dst) &\
81987 #define XTAL__XTAL_LOCALBIAS__CLR(dst) \
81988 (dst) = ((dst) &\
81999 #define XTAL__XTAL_SHORTXIN__MODIFY(dst, src) \
82000 (dst) = ((dst) &\
82006 #define XTAL__XTAL_SHORTXIN__SET(dst) \
82007 (dst) = ((dst) &\
82009 #define XTAL__XTAL_SHORTXIN__CLR(dst) \
82010 (dst) = ((dst) &\
82019 #define XTAL__XTAL_DRVSTR__MODIFY(dst, src) \
82020 (dst) = ((dst) &\
82037 #define XTAL__XTAL_CAPOUTDAC__MODIFY(dst, src) \
82038 (dst) = ((dst) &\
82053 #define XTAL__XTAL_CAPINDAC__MODIFY(dst, src) \
82054 (dst) = ((dst) &\
82066 #define XTAL__TCXODET__SET(dst) \
82067 (dst) = ((dst) &\
82069 #define XTAL__TCXODET__CLR(dst) \
82070 (dst) = ((dst) &\
82096 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MODIFY(dst, src) \
82097 (dst) = ((dst) &\
82103 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__SET(dst) \
82104 (dst) = ((dst) &\
82106 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__CLR(dst) \
82107 (dst) = ((dst) &\
82120 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MODIFY(dst, src) \
82121 (dst) = ((dst) &\
82127 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__SET(dst) \
82128 (dst) = ((dst) &\
82130 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__CLR(dst) \
82131 (dst) = ((dst) &\
82144 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MODIFY(dst, src) \
82145 (dst) = ((dst) &\
82151 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__SET(dst) \
82152 (dst) = ((dst) &\
82154 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__CLR(dst) \
82155 (dst) = ((dst) &\
82168 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MODIFY(dst, src) \
82169 (dst) = ((dst) &\
82175 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__SET(dst) \
82176 (dst) = ((dst) &\
82178 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__CLR(dst) \
82179 (dst) = ((dst) &\
82192 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MODIFY(dst, src) \
82193 (dst) = ((dst) &\
82199 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__SET(dst) \
82200 (dst) = ((dst) &\
82202 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__CLR(dst) \
82203 (dst) = ((dst) &\
82216 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MODIFY(dst, src) \
82217 (dst) = ((dst) &\
82223 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__SET(dst) \
82224 (dst) = ((dst) &\
82226 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__CLR(dst) \
82227 (dst) = ((dst) &\
82240 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MODIFY(dst, src) \
82241 (dst) = ((dst) &\
82247 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__SET(dst) \
82248 (dst) = ((dst) &\
82250 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__CLR(dst) \
82251 (dst) = ((dst) &\
82264 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MODIFY(dst, src) \
82265 (dst) = ((dst) &\
82271 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__SET(dst) \
82272 (dst) = ((dst) &\
82274 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__CLR(dst) \
82275 (dst) = ((dst) &\
82288 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MODIFY(dst, src) \
82289 (dst) = ((dst) &\
82295 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__SET(dst) \
82296 (dst) = ((dst) &\
82298 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__CLR(dst) \
82299 (dst) = ((dst) &\
82312 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MODIFY(dst, src) \
82313 (dst) = ((dst) &\
82319 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__SET(dst) \
82320 (dst) = ((dst) &\
82322 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__CLR(dst) \
82323 (dst) = ((dst) &\
82336 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MODIFY(dst, src) \
82337 (dst) = ((dst) &\
82343 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__SET(dst) \
82344 (dst) = ((dst) &\
82346 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__CLR(dst) \
82347 (dst) = ((dst) &\
82360 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MODIFY(dst, src) \
82361 (dst) = ((dst) &\
82367 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__SET(dst) \
82368 (dst) = ((dst) &\
82370 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__CLR(dst) \
82371 (dst) = ((dst) &\
82384 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MODIFY(dst, src) \
82385 (dst) = ((dst) &\
82391 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__SET(dst) \
82392 (dst) = ((dst) &\
82394 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__CLR(dst) \
82395 (dst) = ((dst) &\
82408 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MODIFY(dst, src) \
82409 (dst) = ((dst) &\
82415 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__SET(dst) \
82416 (dst) = ((dst) &\
82418 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__CLR(dst) \
82419 (dst) = ((dst) &\
82432 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MODIFY(dst, src) \
82433 (dst) = ((dst) &\
82439 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__SET(dst) \
82440 (dst) = ((dst) &\
82442 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__CLR(dst) \
82443 (dst) = ((dst) &\
82456 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MODIFY(dst, src) \
82457 (dst) = ((dst) &\
82463 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__SET(dst) \
82464 (dst) = ((dst) &\
82466 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__CLR(dst) \
82467 (dst) = ((dst) &\
82480 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MODIFY(dst, src) \
82481 (dst) = ((dst) &\
82487 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__SET(dst) \
82488 (dst) = ((dst) &\
82490 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__CLR(dst) \
82491 (dst) = ((dst) &\
82517 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MODIFY(dst, src) \
82518 (dst) = ((dst) &\
82535 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MODIFY(dst, src) \
82536 (dst) = ((dst) &\
82566 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MODIFY(dst, src) \
82567 (dst) = ((dst) &\
82584 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MODIFY(dst, src) \
82585 (dst) = ((dst) &\
82602 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MODIFY(dst, src) \
82603 (dst) = ((dst) &\
82620 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MODIFY(dst, src) \
82621 (dst) = ((dst) &\
82657 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MODIFY(dst, src) \
82658 (dst) = ((dst) &\
82675 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MODIFY(dst, src) \
82676 (dst) = ((dst) &\
82693 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MODIFY(dst, src) \
82694 (dst) = ((dst) &\
82727 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MODIFY(dst, src) \
82728 (dst) = ((dst) &\
82745 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MODIFY(dst, src) \
82746 (dst) = ((dst) &\
82776 #define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MODIFY(dst, src) \
82777 (dst) = ((dst) &\
82810 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MODIFY(dst, src) \
82811 (dst) = ((dst) &\
82828 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MODIFY(dst, src) \
82829 (dst) = ((dst) &\
82859 #define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MODIFY(dst, src) \
82860 (dst) = ((dst) &\
82890 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MODIFY(dst, src) \
82891 (dst) = ((dst) &\
82908 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MODIFY(dst, src) \
82909 (dst) = ((dst) &\
82939 #define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MODIFY(dst, src) \
82940 (dst) = ((dst) &\
82970 #define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MODIFY(dst, src) \
82971 (dst) = ((dst) &\
83001 #define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MODIFY(dst, src) \
83002 (dst) = ((dst) &\
83032 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MODIFY(dst, src) \
83033 (dst) = ((dst) &\
83050 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MODIFY(dst, src) \
83051 (dst) = ((dst) &\
83081 #define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MODIFY(dst, src) \
83082 (dst) = ((dst) &\
83099 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MODIFY(dst, src) \
83100 (dst) = ((dst) &\
83106 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__SET(dst) \
83107 (dst) = ((dst) &\
83109 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__CLR(dst) \
83110 (dst) = ((dst) &\
83123 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MODIFY(dst, src) \
83124 (dst) = ((dst) &\
83141 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MODIFY(dst, src) \
83142 (dst) = ((dst) &\
83172 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MODIFY(dst, src) \
83173 (dst) = ((dst) &\
83190 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MODIFY(dst, src) \
83191 (dst) = ((dst) &\
83208 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MODIFY(dst, src) \
83209 (dst) = ((dst) &\
83226 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MODIFY(dst, src) \
83227 (dst) = ((dst) &\
83257 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MODIFY(dst, src) \
83258 (dst) = ((dst) &\
83275 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MODIFY(dst, src) \
83276 (dst) = ((dst) &\
83306 #define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MODIFY(dst, src) \
83307 (dst) = ((dst) &\