Lines Matching refs:src
91 #define MAC_DMA_CR__RXE_LP__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
103 #define MAC_DMA_CR__RXE_HP__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
115 #define MAC_DMA_CR__RXD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
116 #define MAC_DMA_CR__RXD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
117 #define MAC_DMA_CR__RXD__MODIFY(dst, src) \
119 ~0x00000020U) | (((u_int32_t)(src) <<\
121 #define MAC_DMA_CR__RXD__VERIFY(src) \
122 (!((((u_int32_t)(src)\
135 #define MAC_DMA_CR__SWI__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6)
160 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__READ(src) \
161 (u_int32_t)(src)\
163 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__WRITE(src) \
164 ((u_int32_t)(src)\
166 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__MODIFY(dst, src) \
168 ~0x00000001U) | ((u_int32_t)(src) &\
170 #define MAC_DMA_CFG__BE_MODE_XMIT_DESC__VERIFY(src) \
171 (!(((u_int32_t)(src)\
184 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__READ(src) \
185 (((u_int32_t)(src)\
187 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__WRITE(src) \
188 (((u_int32_t)(src)\
190 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__MODIFY(dst, src) \
192 ~0x00000002U) | (((u_int32_t)(src) <<\
194 #define MAC_DMA_CFG__BE_MODE_XMIT_DATA__VERIFY(src) \
195 (!((((u_int32_t)(src)\
208 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__READ(src) \
209 (((u_int32_t)(src)\
211 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__WRITE(src) \
212 (((u_int32_t)(src)\
214 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__MODIFY(dst, src) \
216 ~0x00000004U) | (((u_int32_t)(src) <<\
218 #define MAC_DMA_CFG__BE_MODE_RCV_DESC__VERIFY(src) \
219 (!((((u_int32_t)(src)\
232 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__READ(src) \
233 (((u_int32_t)(src)\
235 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__WRITE(src) \
236 (((u_int32_t)(src)\
238 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__MODIFY(dst, src) \
240 ~0x00000008U) | (((u_int32_t)(src) <<\
242 #define MAC_DMA_CFG__BE_MODE_RCV_DATA__VERIFY(src) \
243 (!((((u_int32_t)(src)\
256 #define MAC_DMA_CFG__BE_MODE_MMR__READ(src) \
257 (((u_int32_t)(src)\
259 #define MAC_DMA_CFG__BE_MODE_MMR__WRITE(src) \
260 (((u_int32_t)(src)\
262 #define MAC_DMA_CFG__BE_MODE_MMR__MODIFY(dst, src) \
264 ~0x00000010U) | (((u_int32_t)(src) <<\
266 #define MAC_DMA_CFG__BE_MODE_MMR__VERIFY(src) \
267 (!((((u_int32_t)(src)\
280 #define MAC_DMA_CFG__ADHOC__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
281 #define MAC_DMA_CFG__ADHOC__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
282 #define MAC_DMA_CFG__ADHOC__MODIFY(dst, src) \
284 ~0x00000020U) | (((u_int32_t)(src) <<\
286 #define MAC_DMA_CFG__ADHOC__VERIFY(src) \
287 (!((((u_int32_t)(src)\
300 #define MAC_DMA_CFG__PHY_OK__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8)
312 #define MAC_DMA_CFG__EEPROM_BUSY__READ(src) \
313 (((u_int32_t)(src)\
326 #define MAC_DMA_CFG__CLKGATE_DIS__READ(src) \
327 (((u_int32_t)(src)\
329 #define MAC_DMA_CFG__CLKGATE_DIS__WRITE(src) \
330 (((u_int32_t)(src)\
332 #define MAC_DMA_CFG__CLKGATE_DIS__MODIFY(dst, src) \
334 ~0x00000400U) | (((u_int32_t)(src) <<\
336 #define MAC_DMA_CFG__CLKGATE_DIS__VERIFY(src) \
337 (!((((u_int32_t)(src)\
350 #define MAC_DMA_CFG__HALT_REQ__READ(src) \
351 (((u_int32_t)(src)\
353 #define MAC_DMA_CFG__HALT_REQ__WRITE(src) \
354 (((u_int32_t)(src)\
356 #define MAC_DMA_CFG__HALT_REQ__MODIFY(dst, src) \
358 ~0x00000800U) | (((u_int32_t)(src) <<\
360 #define MAC_DMA_CFG__HALT_REQ__VERIFY(src) \
361 (!((((u_int32_t)(src)\
374 #define MAC_DMA_CFG__HALT_ACK__READ(src) \
375 (((u_int32_t)(src)\
388 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__READ(src) \
389 (((u_int32_t)(src)\
391 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__WRITE(src) \
392 (((u_int32_t)(src)\
394 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__MODIFY(dst, src) \
396 ~0x00060000U) | (((u_int32_t)(src) <<\
398 #define MAC_DMA_CFG__REQ_Q_FULL_THRESHOLD__VERIFY(src) \
399 (!((((u_int32_t)(src)\
406 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__READ(src) \
407 (((u_int32_t)(src)\
409 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__WRITE(src) \
410 (((u_int32_t)(src)\
412 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__MODIFY(dst, src) \
414 ~0x00080000U) | (((u_int32_t)(src) <<\
416 #define MAC_DMA_CFG__MISSING_TX_INTR_FIX_ENABLE__VERIFY(src) \
417 (!((((u_int32_t)(src)\
443 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__READ(src) \
444 (u_int32_t)(src)\
446 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__WRITE(src) \
447 ((u_int32_t)(src)\
449 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__MODIFY(dst, src) \
451 ~0x0000000fU) | ((u_int32_t)(src) &\
453 #define MAC_DMA_RXBUFPTR_THRESH__HP_DATA__VERIFY(src) \
454 (!(((u_int32_t)(src)\
461 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__READ(src) \
462 (((u_int32_t)(src)\
464 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__WRITE(src) \
465 (((u_int32_t)(src)\
467 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__MODIFY(dst, src) \
469 ~0x00007f00U) | (((u_int32_t)(src) <<\
471 #define MAC_DMA_RXBUFPTR_THRESH__LP_DATA__VERIFY(src) \
472 (!((((u_int32_t)(src)\
492 #define MAC_DMA_TXDPPTR_THRESH__DATA__READ(src) (u_int32_t)(src) & 0x0000000fU
493 #define MAC_DMA_TXDPPTR_THRESH__DATA__WRITE(src) \
494 ((u_int32_t)(src)\
496 #define MAC_DMA_TXDPPTR_THRESH__DATA__MODIFY(dst, src) \
498 ~0x0000000fU) | ((u_int32_t)(src) &\
500 #define MAC_DMA_TXDPPTR_THRESH__DATA__VERIFY(src) \
501 (!(((u_int32_t)(src)\
521 #define MAC_DMA_MIRT__RATE_THRESH__READ(src) (u_int32_t)(src) & 0x0000ffffU
522 #define MAC_DMA_MIRT__RATE_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
523 #define MAC_DMA_MIRT__RATE_THRESH__MODIFY(dst, src) \
525 ~0x0000ffffU) | ((u_int32_t)(src) &\
527 #define MAC_DMA_MIRT__RATE_THRESH__VERIFY(src) \
528 (!(((u_int32_t)(src)\
548 #define MAC_DMA_GLOBAL_IER__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U
549 #define MAC_DMA_GLOBAL_IER__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
550 #define MAC_DMA_GLOBAL_IER__ENABLE__MODIFY(dst, src) \
552 ~0x00000001U) | ((u_int32_t)(src) &\
554 #define MAC_DMA_GLOBAL_IER__ENABLE__VERIFY(src) \
555 (!(((u_int32_t)(src)\
581 #define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__READ(src) \
582 (u_int32_t)(src)\
584 #define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__WRITE(src) \
585 ((u_int32_t)(src)\
587 #define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__MODIFY(dst, src) \
589 ~0x0000ffffU) | ((u_int32_t)(src) &\
591 #define MAC_DMA_TIMT__TX_LAST_PKT_THRESH__VERIFY(src) \
592 (!(((u_int32_t)(src)\
599 #define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__READ(src) \
600 (((u_int32_t)(src)\
602 #define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__WRITE(src) \
603 (((u_int32_t)(src)\
605 #define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__MODIFY(dst, src) \
607 ~0xffff0000U) | (((u_int32_t)(src) <<\
609 #define MAC_DMA_TIMT__TX_FIRST_PKT_THRESH__VERIFY(src) \
610 (!((((u_int32_t)(src)\
630 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__READ(src) \
631 (u_int32_t)(src)\
633 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__WRITE(src) \
634 ((u_int32_t)(src)\
636 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__MODIFY(dst, src) \
638 ~0x0000ffffU) | ((u_int32_t)(src) &\
640 #define MAC_DMA_RIMT__RX_LAST_PKT_THRESH__VERIFY(src) \
641 (!(((u_int32_t)(src)\
648 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__READ(src) \
649 (((u_int32_t)(src)\
651 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__WRITE(src) \
652 (((u_int32_t)(src)\
654 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__MODIFY(dst, src) \
656 ~0xffff0000U) | (((u_int32_t)(src) <<\
658 #define MAC_DMA_RIMT__RX_FIRST_PKT_THRESH__VERIFY(src) \
659 (!((((u_int32_t)(src)\
679 #define MAC_DMA_TXCFG__DMA_SIZE__READ(src) (u_int32_t)(src) & 0x00000007U
680 #define MAC_DMA_TXCFG__DMA_SIZE__WRITE(src) ((u_int32_t)(src) & 0x00000007U)
681 #define MAC_DMA_TXCFG__DMA_SIZE__MODIFY(dst, src) \
683 ~0x00000007U) | ((u_int32_t)(src) &\
685 #define MAC_DMA_TXCFG__DMA_SIZE__VERIFY(src) \
686 (!(((u_int32_t)(src)\
693 #define MAC_DMA_TXCFG__TRIGLVL__READ(src) \
694 (((u_int32_t)(src)\
696 #define MAC_DMA_TXCFG__TRIGLVL__WRITE(src) \
697 (((u_int32_t)(src)\
699 #define MAC_DMA_TXCFG__TRIGLVL__MODIFY(dst, src) \
701 ~0x000003f0U) | (((u_int32_t)(src) <<\
703 #define MAC_DMA_TXCFG__TRIGLVL__VERIFY(src) \
704 (!((((u_int32_t)(src)\
711 #define MAC_DMA_TXCFG__JUMBO_EN__READ(src) \
712 (((u_int32_t)(src)\
714 #define MAC_DMA_TXCFG__JUMBO_EN__WRITE(src) \
715 (((u_int32_t)(src)\
717 #define MAC_DMA_TXCFG__JUMBO_EN__MODIFY(dst, src) \
719 ~0x00000400U) | (((u_int32_t)(src) <<\
721 #define MAC_DMA_TXCFG__JUMBO_EN__VERIFY(src) \
722 (!((((u_int32_t)(src)\
735 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__READ(src) \
736 (((u_int32_t)(src)\
738 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__WRITE(src) \
739 (((u_int32_t)(src)\
741 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__MODIFY(dst, src) \
743 ~0x00000800U) | (((u_int32_t)(src) <<\
745 #define MAC_DMA_TXCFG__BCN_PAST_ATIM_DIS__VERIFY(src) \
746 (!((((u_int32_t)(src)\
759 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__READ(src) \
760 (((u_int32_t)(src)\
762 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__WRITE(src) \
763 (((u_int32_t)(src)\
765 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__MODIFY(dst, src) \
767 ~0x00001000U) | (((u_int32_t)(src) <<\
769 #define MAC_DMA_TXCFG__ATIM_DEFER_DIS__VERIFY(src) \
770 (!((((u_int32_t)(src)\
783 #define MAC_DMA_TXCFG__RTCI_DIS__READ(src) \
784 (((u_int32_t)(src)\
786 #define MAC_DMA_TXCFG__RTCI_DIS__WRITE(src) \
787 (((u_int32_t)(src)\
789 #define MAC_DMA_TXCFG__RTCI_DIS__MODIFY(dst, src) \
791 ~0x00004000U) | (((u_int32_t)(src) <<\
793 #define MAC_DMA_TXCFG__RTCI_DIS__VERIFY(src) \
794 (!((((u_int32_t)(src)\
807 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__READ(src) \
808 (((u_int32_t)(src)\
810 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__WRITE(src) \
811 (((u_int32_t)(src)\
813 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__MODIFY(dst, src) \
815 ~0x00020000U) | (((u_int32_t)(src) <<\
817 #define MAC_DMA_TXCFG__DIS_RETRY_UNDERRUN__VERIFY(src) \
818 (!((((u_int32_t)(src)\
831 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__READ(src) \
832 (((u_int32_t)(src)\
834 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__WRITE(src) \
835 (((u_int32_t)(src)\
837 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__MODIFY(dst, src) \
839 ~0x00040000U) | (((u_int32_t)(src) <<\
841 #define MAC_DMA_TXCFG__DIS_CW_INC_QUIET_COLL__VERIFY(src) \
842 (!((((u_int32_t)(src)\
868 #define MAC_DMA_RXCFG__DMA_SIZE__READ(src) (u_int32_t)(src) & 0x00000007U
869 #define MAC_DMA_RXCFG__DMA_SIZE__WRITE(src) ((u_int32_t)(src) & 0x00000007U)
870 #define MAC_DMA_RXCFG__DMA_SIZE__MODIFY(dst, src) \
872 ~0x00000007U) | ((u_int32_t)(src) &\
874 #define MAC_DMA_RXCFG__DMA_SIZE__VERIFY(src) \
875 (!(((u_int32_t)(src)\
882 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__READ(src) \
883 (((u_int32_t)(src)\
885 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__WRITE(src) \
886 (((u_int32_t)(src)\
888 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__MODIFY(dst, src) \
890 ~0x00000018U) | (((u_int32_t)(src) <<\
892 #define MAC_DMA_RXCFG__ZERO_LEN_DMA_EN__VERIFY(src) \
893 (!((((u_int32_t)(src)\
900 #define MAC_DMA_RXCFG__JUMBO_EN__READ(src) \
901 (((u_int32_t)(src)\
903 #define MAC_DMA_RXCFG__JUMBO_EN__WRITE(src) \
904 (((u_int32_t)(src)\
906 #define MAC_DMA_RXCFG__JUMBO_EN__MODIFY(dst, src) \
908 ~0x00000020U) | (((u_int32_t)(src) <<\
910 #define MAC_DMA_RXCFG__JUMBO_EN__VERIFY(src) \
911 (!((((u_int32_t)(src)\
924 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__READ(src) \
925 (((u_int32_t)(src)\
927 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__WRITE(src) \
928 (((u_int32_t)(src)\
930 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__MODIFY(dst, src) \
932 ~0x00000040U) | (((u_int32_t)(src) <<\
934 #define MAC_DMA_RXCFG__JUMBO_WRAP_EN__VERIFY(src) \
935 (!((((u_int32_t)(src)\
948 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__READ(src) \
949 (((u_int32_t)(src)\
951 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__WRITE(src) \
952 (((u_int32_t)(src)\
954 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__MODIFY(dst, src) \
956 ~0x00000080U) | (((u_int32_t)(src) <<\
958 #define MAC_DMA_RXCFG__SLEEP_RX_PEND_EN__VERIFY(src) \
959 (!((((u_int32_t)(src)\
985 #define MAC_DMA_RXJLA__DATA__READ(src) (((u_int32_t)(src) & 0xfffffffcU) >> 2)
1003 #define MAC_DMA_MIBC__WARNING__READ(src) (u_int32_t)(src) & 0x00000001U
1015 #define MAC_DMA_MIBC__FREEZE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
1016 #define MAC_DMA_MIBC__FREEZE__WRITE(src) \
1017 (((u_int32_t)(src)\
1019 #define MAC_DMA_MIBC__FREEZE__MODIFY(dst, src) \
1021 ~0x00000002U) | (((u_int32_t)(src) <<\
1023 #define MAC_DMA_MIBC__FREEZE__VERIFY(src) \
1024 (!((((u_int32_t)(src)\
1037 #define MAC_DMA_MIBC__CLEAR__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
1038 #define MAC_DMA_MIBC__CLEAR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
1039 #define MAC_DMA_MIBC__CLEAR__MODIFY(dst, src) \
1041 ~0x00000004U) | (((u_int32_t)(src) <<\
1043 #define MAC_DMA_MIBC__CLEAR__VERIFY(src) \
1044 (!((((u_int32_t)(src)\
1057 #define MAC_DMA_MIBC__STROBE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
1082 #define MAC_DMA_TOPS__TIMEOUT__READ(src) (u_int32_t)(src) & 0x0000ffffU
1083 #define MAC_DMA_TOPS__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
1084 #define MAC_DMA_TOPS__TIMEOUT__MODIFY(dst, src) \
1086 ~0x0000ffffU) | ((u_int32_t)(src) &\
1088 #define MAC_DMA_TOPS__TIMEOUT__VERIFY(src) \
1089 (!(((u_int32_t)(src)\
1109 #define MAC_DMA_RXNPTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU
1110 #define MAC_DMA_RXNPTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
1111 #define MAC_DMA_RXNPTO__TIMEOUT__MODIFY(dst, src) \
1113 ~0x000003ffU) | ((u_int32_t)(src) &\
1115 #define MAC_DMA_RXNPTO__TIMEOUT__VERIFY(src) \
1116 (!(((u_int32_t)(src)\
1136 #define MAC_DMA_TXNPTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU
1137 #define MAC_DMA_TXNPTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
1138 #define MAC_DMA_TXNPTO__TIMEOUT__MODIFY(dst, src) \
1140 ~0x000003ffU) | ((u_int32_t)(src) &\
1142 #define MAC_DMA_TXNPTO__TIMEOUT__VERIFY(src) \
1143 (!(((u_int32_t)(src)\
1150 #define MAC_DMA_TXNPTO__MASK__READ(src) \
1151 (((u_int32_t)(src)\
1153 #define MAC_DMA_TXNPTO__MASK__WRITE(src) \
1154 (((u_int32_t)(src)\
1156 #define MAC_DMA_TXNPTO__MASK__MODIFY(dst, src) \
1158 ~0x000ffc00U) | (((u_int32_t)(src) <<\
1160 #define MAC_DMA_TXNPTO__MASK__VERIFY(src) \
1161 (!((((u_int32_t)(src)\
1181 #define MAC_DMA_RPGTO__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000003ffU
1182 #define MAC_DMA_RPGTO__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
1183 #define MAC_DMA_RPGTO__TIMEOUT__MODIFY(dst, src) \
1185 ~0x000003ffU) | ((u_int32_t)(src) &\
1187 #define MAC_DMA_RPGTO__TIMEOUT__VERIFY(src) \
1188 (!(((u_int32_t)(src)\
1208 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__READ(src) \
1209 (((u_int32_t)(src)\
1211 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__WRITE(src) \
1212 (((u_int32_t)(src)\
1214 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__MODIFY(dst, src) \
1216 ~0x00000010U) | (((u_int32_t)(src) <<\
1218 #define MAC_DMA_MACMISC__FORCE_PCI_EXT__VERIFY(src) \
1219 (!((((u_int32_t)(src)\
1232 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__READ(src) \
1233 (((u_int32_t)(src)\
1235 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__WRITE(src) \
1236 (((u_int32_t)(src)\
1238 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__MODIFY(dst, src) \
1240 ~0x000001e0U) | (((u_int32_t)(src) <<\
1242 #define MAC_DMA_MACMISC__DMA_OBS_MUXSEL__VERIFY(src) \
1243 (!((((u_int32_t)(src)\
1250 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__READ(src) \
1251 (((u_int32_t)(src)\
1253 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__WRITE(src) \
1254 (((u_int32_t)(src)\
1256 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__MODIFY(dst, src) \
1258 ~0x00000e00U) | (((u_int32_t)(src) <<\
1260 #define MAC_DMA_MACMISC__MISC_OBS_MUXSEL__VERIFY(src) \
1261 (!((((u_int32_t)(src)\
1268 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__READ(src) \
1269 (((u_int32_t)(src)\
1271 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__WRITE(src) \
1272 (((u_int32_t)(src)\
1274 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__MODIFY(dst, src) \
1276 ~0x00007000U) | (((u_int32_t)(src) <<\
1278 #define MAC_DMA_MACMISC__MISC_F2_OBS_LOW_MUXSEL__VERIFY(src) \
1279 (!((((u_int32_t)(src)\
1286 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__READ(src) \
1287 (((u_int32_t)(src)\
1289 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__WRITE(src) \
1290 (((u_int32_t)(src)\
1292 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__MODIFY(dst, src) \
1294 ~0x00038000U) | (((u_int32_t)(src) <<\
1296 #define MAC_DMA_MACMISC__MISC_F2_OBS_HIGH_MUXSEL__VERIFY(src) \
1297 (!((((u_int32_t)(src)\
1317 #define MAC_DMA_INTER__REQ__READ(src) (u_int32_t)(src) & 0x00000001U
1318 #define MAC_DMA_INTER__REQ__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
1319 #define MAC_DMA_INTER__REQ__MODIFY(dst, src) \
1321 ~0x00000001U) | ((u_int32_t)(src) &\
1323 #define MAC_DMA_INTER__REQ__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
1335 #define MAC_DMA_INTER__MSI_RX_SRC__READ(src) \
1336 (((u_int32_t)(src)\
1338 #define MAC_DMA_INTER__MSI_RX_SRC__WRITE(src) \
1339 (((u_int32_t)(src)\
1341 #define MAC_DMA_INTER__MSI_RX_SRC__MODIFY(dst, src) \
1343 ~0x00000006U) | (((u_int32_t)(src) <<\
1345 #define MAC_DMA_INTER__MSI_RX_SRC__VERIFY(src) \
1346 (!((((u_int32_t)(src)\
1353 #define MAC_DMA_INTER__MSI_TX_SRC__READ(src) \
1354 (((u_int32_t)(src)\
1356 #define MAC_DMA_INTER__MSI_TX_SRC__WRITE(src) \
1357 (((u_int32_t)(src)\
1359 #define MAC_DMA_INTER__MSI_TX_SRC__MODIFY(dst, src) \
1361 ~0x00000018U) | (((u_int32_t)(src) <<\
1363 #define MAC_DMA_INTER__MSI_TX_SRC__VERIFY(src) \
1364 (!((((u_int32_t)(src)\
1384 #define MAC_DMA_DATABUF__LEN__READ(src) (u_int32_t)(src) & 0x00000fffU
1385 #define MAC_DMA_DATABUF__LEN__WRITE(src) ((u_int32_t)(src) & 0x00000fffU)
1386 #define MAC_DMA_DATABUF__LEN__MODIFY(dst, src) \
1388 ~0x00000fffU) | ((u_int32_t)(src) &\
1390 #define MAC_DMA_DATABUF__LEN__VERIFY(src) \
1391 (!(((u_int32_t)(src)\
1411 #define MAC_DMA_GTT__COUNT__READ(src) (u_int32_t)(src) & 0x0000ffffU
1412 #define MAC_DMA_GTT__COUNT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
1413 #define MAC_DMA_GTT__COUNT__MODIFY(dst, src) \
1415 ~0x0000ffffU) | ((u_int32_t)(src) &\
1417 #define MAC_DMA_GTT__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU)))
1423 #define MAC_DMA_GTT__LIMIT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16)
1424 #define MAC_DMA_GTT__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U)
1425 #define MAC_DMA_GTT__LIMIT__MODIFY(dst, src) \
1427 ~0xffff0000U) | (((u_int32_t)(src) <<\
1429 #define MAC_DMA_GTT__LIMIT__VERIFY(src) \
1430 (!((((u_int32_t)(src)\
1450 #define MAC_DMA_GTTM__USEC_STROBE__READ(src) (u_int32_t)(src) & 0x00000001U
1451 #define MAC_DMA_GTTM__USEC_STROBE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
1452 #define MAC_DMA_GTTM__USEC_STROBE__MODIFY(dst, src) \
1454 ~0x00000001U) | ((u_int32_t)(src) &\
1456 #define MAC_DMA_GTTM__USEC_STROBE__VERIFY(src) \
1457 (!(((u_int32_t)(src)\
1470 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__READ(src) \
1471 (((u_int32_t)(src)\
1473 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__WRITE(src) \
1474 (((u_int32_t)(src)\
1476 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__MODIFY(dst, src) \
1478 ~0x00000002U) | (((u_int32_t)(src) <<\
1480 #define MAC_DMA_GTTM__IGNORE_CHAN_IDLE__VERIFY(src) \
1481 (!((((u_int32_t)(src)\
1494 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__READ(src) \
1495 (((u_int32_t)(src)\
1497 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__WRITE(src) \
1498 (((u_int32_t)(src)\
1500 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__MODIFY(dst, src) \
1502 ~0x00000004U) | (((u_int32_t)(src) <<\
1504 #define MAC_DMA_GTTM__RESET_ON_CHAN_IDLE__VERIFY(src) \
1505 (!((((u_int32_t)(src)\
1518 #define MAC_DMA_GTTM__CST_USEC_STROBE__READ(src) \
1519 (((u_int32_t)(src)\
1521 #define MAC_DMA_GTTM__CST_USEC_STROBE__WRITE(src) \
1522 (((u_int32_t)(src)\
1524 #define MAC_DMA_GTTM__CST_USEC_STROBE__MODIFY(dst, src) \
1526 ~0x00000008U) | (((u_int32_t)(src) <<\
1528 #define MAC_DMA_GTTM__CST_USEC_STROBE__VERIFY(src) \
1529 (!((((u_int32_t)(src)\
1542 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__READ(src) \
1543 (((u_int32_t)(src)\
1545 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__WRITE(src) \
1546 (((u_int32_t)(src)\
1548 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__MODIFY(dst, src) \
1550 ~0x00000010U) | (((u_int32_t)(src) <<\
1552 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_GTT__VERIFY(src) \
1553 (!((((u_int32_t)(src)\
1566 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__READ(src) \
1567 (((u_int32_t)(src)\
1569 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__WRITE(src) \
1570 (((u_int32_t)(src)\
1572 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__MODIFY(dst, src) \
1574 ~0x00000020U) | (((u_int32_t)(src) <<\
1576 #define MAC_DMA_GTTM__DISABLE_QCU_FR_ACTIVE_BT__VERIFY(src) \
1577 (!((((u_int32_t)(src)\
1603 #define MAC_DMA_CST__COUNT__READ(src) (u_int32_t)(src) & 0x0000ffffU
1604 #define MAC_DMA_CST__COUNT__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
1605 #define MAC_DMA_CST__COUNT__MODIFY(dst, src) \
1607 ~0x0000ffffU) | ((u_int32_t)(src) &\
1609 #define MAC_DMA_CST__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000ffffU)))
1615 #define MAC_DMA_CST__LIMIT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16)
1616 #define MAC_DMA_CST__LIMIT__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U)
1617 #define MAC_DMA_CST__LIMIT__MODIFY(dst, src) \
1619 ~0xffff0000U) | (((u_int32_t)(src) <<\
1621 #define MAC_DMA_CST__LIMIT__VERIFY(src) \
1622 (!((((u_int32_t)(src)\
1642 #define MAC_DMA_RXDP_SIZE__LP__READ(src) (u_int32_t)(src) & 0x000000ffU
1648 #define MAC_DMA_RXDP_SIZE__HP__READ(src) \
1649 (((u_int32_t)(src)\
1668 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__READ(src) \
1669 (u_int32_t)(src)\
1671 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__WRITE(src) \
1672 ((u_int32_t)(src)\
1674 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__MODIFY(dst, src) \
1676 ~0xffffffffU) | ((u_int32_t)(src) &\
1678 #define MAC_DMA_RX_QUEUE_HP_RXDP__ADDR__VERIFY(src) \
1679 (!(((u_int32_t)(src)\
1699 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__READ(src) \
1700 (u_int32_t)(src)\
1702 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__WRITE(src) \
1703 ((u_int32_t)(src)\
1705 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__MODIFY(dst, src) \
1707 ~0xffffffffU) | ((u_int32_t)(src) &\
1709 #define MAC_DMA_RX_QUEUE_LP_RXDP__ADDR__VERIFY(src) \
1710 (!(((u_int32_t)(src)\
1730 #define MAC_DMA_ISR_P__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
1731 #define MAC_DMA_ISR_P__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1732 #define MAC_DMA_ISR_P__DATA__MODIFY(dst, src) \
1734 ~0xffffffffU) | ((u_int32_t)(src) &\
1736 #define MAC_DMA_ISR_P__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
1755 #define MAC_DMA_ISR_S0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
1756 #define MAC_DMA_ISR_S0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1757 #define MAC_DMA_ISR_S0__DATA__MODIFY(dst, src) \
1759 ~0xffffffffU) | ((u_int32_t)(src) &\
1761 #define MAC_DMA_ISR_S0__DATA__VERIFY(src) \
1762 (!(((u_int32_t)(src)\
1782 #define MAC_DMA_ISR_S1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
1783 #define MAC_DMA_ISR_S1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1784 #define MAC_DMA_ISR_S1__DATA__MODIFY(dst, src) \
1786 ~0xffffffffU) | ((u_int32_t)(src) &\
1788 #define MAC_DMA_ISR_S1__DATA__VERIFY(src) \
1789 (!(((u_int32_t)(src)\
1809 #define MAC_DMA_ISR_S2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
1810 #define MAC_DMA_ISR_S2__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1811 #define MAC_DMA_ISR_S2__DATA__MODIFY(dst, src) \
1813 ~0xffffffffU) | ((u_int32_t)(src) &\
1815 #define MAC_DMA_ISR_S2__DATA__VERIFY(src) \
1816 (!(((u_int32_t)(src)\
1836 #define MAC_DMA_ISR_S3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
1837 #define MAC_DMA_ISR_S3__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1838 #define MAC_DMA_ISR_S3__DATA__MODIFY(dst, src) \
1840 ~0xffffffffU) | ((u_int32_t)(src) &\
1842 #define MAC_DMA_ISR_S3__DATA__VERIFY(src) \
1843 (!(((u_int32_t)(src)\
1863 #define MAC_DMA_ISR_S4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
1864 #define MAC_DMA_ISR_S4__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1865 #define MAC_DMA_ISR_S4__DATA__MODIFY(dst, src) \
1867 ~0xffffffffU) | ((u_int32_t)(src) &\
1869 #define MAC_DMA_ISR_S4__DATA__VERIFY(src) \
1870 (!(((u_int32_t)(src)\
1890 #define MAC_DMA_ISR_S5__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
1891 #define MAC_DMA_ISR_S5__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1892 #define MAC_DMA_ISR_S5__DATA__MODIFY(dst, src) \
1894 ~0xffffffffU) | ((u_int32_t)(src) &\
1896 #define MAC_DMA_ISR_S5__DATA__VERIFY(src) \
1897 (!(((u_int32_t)(src)\
1917 #define MAC_DMA_IMR_P__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU
1918 #define MAC_DMA_IMR_P__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1919 #define MAC_DMA_IMR_P__MASK__MODIFY(dst, src) \
1921 ~0xffffffffU) | ((u_int32_t)(src) &\
1923 #define MAC_DMA_IMR_P__MASK__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
1942 #define MAC_DMA_IMR_S0__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU
1943 #define MAC_DMA_IMR_S0__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1944 #define MAC_DMA_IMR_S0__MASK__MODIFY(dst, src) \
1946 ~0xffffffffU) | ((u_int32_t)(src) &\
1948 #define MAC_DMA_IMR_S0__MASK__VERIFY(src) \
1949 (!(((u_int32_t)(src)\
1969 #define MAC_DMA_IMR_S1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
1970 #define MAC_DMA_IMR_S1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1971 #define MAC_DMA_IMR_S1__DATA__MODIFY(dst, src) \
1973 ~0xffffffffU) | ((u_int32_t)(src) &\
1975 #define MAC_DMA_IMR_S1__DATA__VERIFY(src) \
1976 (!(((u_int32_t)(src)\
1996 #define MAC_DMA_IMR_S2__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU
1997 #define MAC_DMA_IMR_S2__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
1998 #define MAC_DMA_IMR_S2__MASK__MODIFY(dst, src) \
2000 ~0xffffffffU) | ((u_int32_t)(src) &\
2002 #define MAC_DMA_IMR_S2__MASK__VERIFY(src) \
2003 (!(((u_int32_t)(src)\
2023 #define MAC_DMA_IMR_S3__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU
2024 #define MAC_DMA_IMR_S3__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
2025 #define MAC_DMA_IMR_S3__MASK__MODIFY(dst, src) \
2027 ~0xffffffffU) | ((u_int32_t)(src) &\
2029 #define MAC_DMA_IMR_S3__MASK__VERIFY(src) \
2030 (!(((u_int32_t)(src)\
2050 #define MAC_DMA_IMR_S4__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU
2051 #define MAC_DMA_IMR_S4__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
2052 #define MAC_DMA_IMR_S4__MASK__MODIFY(dst, src) \
2054 ~0xffffffffU) | ((u_int32_t)(src) &\
2056 #define MAC_DMA_IMR_S4__MASK__VERIFY(src) \
2057 (!(((u_int32_t)(src)\
2077 #define MAC_DMA_IMR_S5__MASK__READ(src) (u_int32_t)(src) & 0xffffffffU
2078 #define MAC_DMA_IMR_S5__MASK__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
2079 #define MAC_DMA_IMR_S5__MASK__MODIFY(dst, src) \
2081 ~0xffffffffU) | ((u_int32_t)(src) &\
2083 #define MAC_DMA_IMR_S5__MASK__VERIFY(src) \
2084 (!(((u_int32_t)(src)\
2104 #define MAC_DMA_ISR_P_RAC__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
2122 #define MAC_DMA_ISR_S0_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU
2140 #define MAC_DMA_ISR_S1_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU
2158 #define MAC_DMA_ISR_S2_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU
2176 #define MAC_DMA_ISR_S3_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU
2194 #define MAC_DMA_ISR_S4_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU
2212 #define MAC_DMA_ISR_S5_S__SHADOW__READ(src) (u_int32_t)(src) & 0xffffffffU
2230 #define MAC_DMA_DMADBG_0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
2248 #define MAC_DMA_DMADBG_1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
2266 #define MAC_DMA_DMADBG_2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
2284 #define MAC_DMA_DMADBG_3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
2302 #define MAC_DMA_DMADBG_4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
2320 #define MAC_DMA_DMADBG_5__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
2338 #define MAC_DMA_DMADBG_6__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
2356 #define MAC_DMA_DMADBG_7__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
2374 #define MAC_DMA_QCU_TXDP_REMAINING_QCU_7_0__DATA__READ(src) \
2375 (u_int32_t)(src)\
2394 #define MAC_DMA_QCU_TXDP_REMAINING_QCU_9_8__DATA__READ(src) \
2395 (u_int32_t)(src)\
2414 #define MAC_QCU_TXDP__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
2415 #define MAC_QCU_TXDP__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
2416 #define MAC_QCU_TXDP__DATA__MODIFY(dst, src) \
2418 ~0xffffffffU) | ((u_int32_t)(src) &\
2420 #define MAC_QCU_TXDP__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
2439 #define MAC_QCU_STATUS_RING_START__ADDR__READ(src) \
2440 (u_int32_t)(src)\
2442 #define MAC_QCU_STATUS_RING_START__ADDR__WRITE(src) \
2443 ((u_int32_t)(src)\
2445 #define MAC_QCU_STATUS_RING_START__ADDR__MODIFY(dst, src) \
2447 ~0xffffffffU) | ((u_int32_t)(src) &\
2449 #define MAC_QCU_STATUS_RING_START__ADDR__VERIFY(src) \
2450 (!(((u_int32_t)(src)\
2470 #define MAC_QCU_STATUS_RING_END__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU
2471 #define MAC_QCU_STATUS_RING_END__ADDR__WRITE(src) \
2472 ((u_int32_t)(src)\
2474 #define MAC_QCU_STATUS_RING_END__ADDR__MODIFY(dst, src) \
2476 ~0xffffffffU) | ((u_int32_t)(src) &\
2478 #define MAC_QCU_STATUS_RING_END__ADDR__VERIFY(src) \
2479 (!(((u_int32_t)(src)\
2499 #define MAC_QCU_STATUS_RING_CURRENT__ADDRESS__READ(src) \
2500 (u_int32_t)(src)\
2519 #define MAC_QCU_TXE__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU
2537 #define MAC_QCU_TXD__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU
2538 #define MAC_QCU_TXD__DATA__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
2539 #define MAC_QCU_TXD__DATA__MODIFY(dst, src) \
2541 ~0x000003ffU) | ((u_int32_t)(src) &\
2543 #define MAC_QCU_TXD__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU)))
2562 #define MAC_QCU_CBR__INTERVAL__READ(src) (u_int32_t)(src) & 0x00ffffffU
2563 #define MAC_QCU_CBR__INTERVAL__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU)
2564 #define MAC_QCU_CBR__INTERVAL__MODIFY(dst, src) \
2566 ~0x00ffffffU) | ((u_int32_t)(src) &\
2568 #define MAC_QCU_CBR__INTERVAL__VERIFY(src) \
2569 (!(((u_int32_t)(src)\
2576 #define MAC_QCU_CBR__OVF_THRESH__READ(src) \
2577 (((u_int32_t)(src)\
2579 #define MAC_QCU_CBR__OVF_THRESH__WRITE(src) \
2580 (((u_int32_t)(src)\
2582 #define MAC_QCU_CBR__OVF_THRESH__MODIFY(dst, src) \
2584 ~0xff000000U) | (((u_int32_t)(src) <<\
2586 #define MAC_QCU_CBR__OVF_THRESH__VERIFY(src) \
2587 (!((((u_int32_t)(src)\
2607 #define MAC_QCU_RDYTIME__DURATION__READ(src) (u_int32_t)(src) & 0x00ffffffU
2608 #define MAC_QCU_RDYTIME__DURATION__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU)
2609 #define MAC_QCU_RDYTIME__DURATION__MODIFY(dst, src) \
2611 ~0x00ffffffU) | ((u_int32_t)(src) &\
2613 #define MAC_QCU_RDYTIME__DURATION__VERIFY(src) \
2614 (!(((u_int32_t)(src)\
2621 #define MAC_QCU_RDYTIME__EN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24)
2622 #define MAC_QCU_RDYTIME__EN__WRITE(src) \
2623 (((u_int32_t)(src)\
2625 #define MAC_QCU_RDYTIME__EN__MODIFY(dst, src) \
2627 ~0x01000000U) | (((u_int32_t)(src) <<\
2629 #define MAC_QCU_RDYTIME__EN__VERIFY(src) \
2630 (!((((u_int32_t)(src)\
2656 #define MAC_QCU_ONESHOT_ARM_SC__SET__READ(src) (u_int32_t)(src) & 0x000003ffU
2657 #define MAC_QCU_ONESHOT_ARM_SC__SET__WRITE(src) \
2658 ((u_int32_t)(src)\
2660 #define MAC_QCU_ONESHOT_ARM_SC__SET__MODIFY(dst, src) \
2662 ~0x000003ffU) | ((u_int32_t)(src) &\
2664 #define MAC_QCU_ONESHOT_ARM_SC__SET__VERIFY(src) \
2665 (!(((u_int32_t)(src)\
2685 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__READ(src) (u_int32_t)(src) & 0x000003ffU
2686 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__WRITE(src) \
2687 ((u_int32_t)(src)\
2689 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__MODIFY(dst, src) \
2691 ~0x000003ffU) | ((u_int32_t)(src) &\
2693 #define MAC_QCU_ONESHOT_ARM_CC__CLEAR__VERIFY(src) \
2694 (!(((u_int32_t)(src)\
2714 #define MAC_QCU_MISC__FSP__READ(src) (u_int32_t)(src) & 0x0000000fU
2715 #define MAC_QCU_MISC__FSP__WRITE(src) ((u_int32_t)(src) & 0x0000000fU)
2716 #define MAC_QCU_MISC__FSP__MODIFY(dst, src) \
2718 ~0x0000000fU) | ((u_int32_t)(src) &\
2720 #define MAC_QCU_MISC__FSP__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU)))
2726 #define MAC_QCU_MISC__ONESHOT_EN__READ(src) \
2727 (((u_int32_t)(src)\
2729 #define MAC_QCU_MISC__ONESHOT_EN__WRITE(src) \
2730 (((u_int32_t)(src)\
2732 #define MAC_QCU_MISC__ONESHOT_EN__MODIFY(dst, src) \
2734 ~0x00000010U) | (((u_int32_t)(src) <<\
2736 #define MAC_QCU_MISC__ONESHOT_EN__VERIFY(src) \
2737 (!((((u_int32_t)(src)\
2750 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__READ(src) \
2751 (((u_int32_t)(src)\
2753 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__WRITE(src) \
2754 (((u_int32_t)(src)\
2756 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__MODIFY(dst, src) \
2758 ~0x00000020U) | (((u_int32_t)(src) <<\
2760 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOFR__VERIFY(src) \
2761 (!((((u_int32_t)(src)\
2774 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__READ(src) \
2775 (((u_int32_t)(src)\
2777 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__WRITE(src) \
2778 (((u_int32_t)(src)\
2780 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__MODIFY(dst, src) \
2782 ~0x00000040U) | (((u_int32_t)(src) <<\
2784 #define MAC_QCU_MISC__CBR_EXP_INC_DIS_NOBCNFR__VERIFY(src) \
2785 (!((((u_int32_t)(src)\
2798 #define MAC_QCU_MISC__IS_BCN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7)
2799 #define MAC_QCU_MISC__IS_BCN__WRITE(src) \
2800 (((u_int32_t)(src)\
2802 #define MAC_QCU_MISC__IS_BCN__MODIFY(dst, src) \
2804 ~0x00000080U) | (((u_int32_t)(src) <<\
2806 #define MAC_QCU_MISC__IS_BCN__VERIFY(src) \
2807 (!((((u_int32_t)(src)\
2820 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__READ(src) \
2821 (((u_int32_t)(src)\
2823 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__WRITE(src) \
2824 (((u_int32_t)(src)\
2826 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__MODIFY(dst, src) \
2828 ~0x00000100U) | (((u_int32_t)(src) <<\
2830 #define MAC_QCU_MISC__CBR_EXP_INC_LIMIT__VERIFY(src) \
2831 (!((((u_int32_t)(src)\
2844 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__READ(src) \
2845 (((u_int32_t)(src)\
2847 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__WRITE(src) \
2848 (((u_int32_t)(src)\
2850 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__MODIFY(dst, src) \
2852 ~0x00000200U) | (((u_int32_t)(src) <<\
2854 #define MAC_QCU_MISC__TXE_CLR_ON_CBR_END__VERIFY(src) \
2855 (!((((u_int32_t)(src)\
2868 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__READ(src) \
2869 (((u_int32_t)(src)\
2871 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__WRITE(src) \
2872 (((u_int32_t)(src)\
2874 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__MODIFY(dst, src) \
2876 ~0x00000400U) | (((u_int32_t)(src) <<\
2878 #define MAC_QCU_MISC__MMR_CBR_EXP_CNT_CLR_EN__VERIFY(src) \
2879 (!((((u_int32_t)(src)\
2892 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__READ(src) \
2893 (((u_int32_t)(src)\
2895 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__WRITE(src) \
2896 (((u_int32_t)(src)\
2898 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__MODIFY(dst, src) \
2900 ~0x00000800U) | (((u_int32_t)(src) <<\
2902 #define MAC_QCU_MISC__FR_ABORT_REQ_EN__VERIFY(src) \
2903 (!((((u_int32_t)(src)\
2929 #define MAC_QCU_CNT__FR_PEND__READ(src) (u_int32_t)(src) & 0x00000003U
2935 #define MAC_QCU_CNT__CBR_EXP__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
2953 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__READ(src) \
2954 (u_int32_t)(src)\
2956 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__WRITE(src) \
2957 ((u_int32_t)(src)\
2959 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__MODIFY(dst, src) \
2961 ~0x000003ffU) | ((u_int32_t)(src) &\
2963 #define MAC_QCU_RDYTIME_SHDN__SHUTDOWN__VERIFY(src) \
2964 (!(((u_int32_t)(src)\
2985 #define MAC_QCU_DESC_CRC_CHK__EN__READ(src) (u_int32_t)(src) & 0x00000001U
2986 #define MAC_QCU_DESC_CRC_CHK__EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
2987 #define MAC_QCU_DESC_CRC_CHK__EN__MODIFY(dst, src) \
2989 ~0x00000001U) | ((u_int32_t)(src) &\
2991 #define MAC_QCU_DESC_CRC_CHK__EN__VERIFY(src) \
2992 (!(((u_int32_t)(src)\
3018 #define MAC_DCU_QCUMASK__DATA__READ(src) (u_int32_t)(src) & 0x000003ffU
3019 #define MAC_DCU_QCUMASK__DATA__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
3020 #define MAC_DCU_QCUMASK__DATA__MODIFY(dst, src) \
3022 ~0x000003ffU) | ((u_int32_t)(src) &\
3024 #define MAC_DCU_QCUMASK__DATA__VERIFY(src) \
3025 (!(((u_int32_t)(src)\
3045 #define MAC_DCU_GBL_IFS_SIFS__DURATION__READ(src) \
3046 (u_int32_t)(src)\
3048 #define MAC_DCU_GBL_IFS_SIFS__DURATION__WRITE(src) \
3049 ((u_int32_t)(src)\
3051 #define MAC_DCU_GBL_IFS_SIFS__DURATION__MODIFY(dst, src) \
3053 ~0x0000ffffU) | ((u_int32_t)(src) &\
3055 #define MAC_DCU_GBL_IFS_SIFS__DURATION__VERIFY(src) \
3056 (!(((u_int32_t)(src)\
3076 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__READ(src) \
3077 (u_int32_t)(src)\
3079 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__WRITE(src) \
3080 ((u_int32_t)(src)\
3082 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__MODIFY(dst, src) \
3084 ~0xffffffffU) | ((u_int32_t)(src) &\
3086 #define MAC_DCU_TXFILTER_DCU0_31_0__DATA__VERIFY(src) \
3087 (!(((u_int32_t)(src)\
3107 #define MAC_DCU_TXFILTER_DCU8_31_0__DATA__READ(src) \
3108 (u_int32_t)(src)\
3127 #define MAC_DCU_LCL_IFS__CW_MIN__READ(src) (u_int32_t)(src) & 0x000003ffU
3128 #define MAC_DCU_LCL_IFS__CW_MIN__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
3129 #define MAC_DCU_LCL_IFS__CW_MIN__MODIFY(dst, src) \
3131 ~0x000003ffU) | ((u_int32_t)(src) &\
3133 #define MAC_DCU_LCL_IFS__CW_MIN__VERIFY(src) \
3134 (!(((u_int32_t)(src)\
3141 #define MAC_DCU_LCL_IFS__CW_MAX__READ(src) \
3142 (((u_int32_t)(src)\
3144 #define MAC_DCU_LCL_IFS__CW_MAX__WRITE(src) \
3145 (((u_int32_t)(src)\
3147 #define MAC_DCU_LCL_IFS__CW_MAX__MODIFY(dst, src) \
3149 ~0x000ffc00U) | (((u_int32_t)(src) <<\
3151 #define MAC_DCU_LCL_IFS__CW_MAX__VERIFY(src) \
3152 (!((((u_int32_t)(src)\
3159 #define MAC_DCU_LCL_IFS__AIFS__READ(src) \
3160 (((u_int32_t)(src)\
3162 #define MAC_DCU_LCL_IFS__AIFS__WRITE(src) \
3163 (((u_int32_t)(src)\
3165 #define MAC_DCU_LCL_IFS__AIFS__MODIFY(dst, src) \
3167 ~0x0ff00000U) | (((u_int32_t)(src) <<\
3169 #define MAC_DCU_LCL_IFS__AIFS__VERIFY(src) \
3170 (!((((u_int32_t)(src)\
3177 #define MAC_DCU_LCL_IFS__LONG_AIFS__READ(src) \
3178 (((u_int32_t)(src)\
3180 #define MAC_DCU_LCL_IFS__LONG_AIFS__WRITE(src) \
3181 (((u_int32_t)(src)\
3183 #define MAC_DCU_LCL_IFS__LONG_AIFS__MODIFY(dst, src) \
3185 ~0x10000000U) | (((u_int32_t)(src) <<\
3187 #define MAC_DCU_LCL_IFS__LONG_AIFS__VERIFY(src) \
3188 (!((((u_int32_t)(src)\
3214 #define MAC_DCU_GBL_IFS_SLOT__DURATION__READ(src) \
3215 (u_int32_t)(src)\
3217 #define MAC_DCU_GBL_IFS_SLOT__DURATION__WRITE(src) \
3218 ((u_int32_t)(src)\
3220 #define MAC_DCU_GBL_IFS_SLOT__DURATION__MODIFY(dst, src) \
3222 ~0x0000ffffU) | ((u_int32_t)(src) &\
3224 #define MAC_DCU_GBL_IFS_SLOT__DURATION__VERIFY(src) \
3225 (!(((u_int32_t)(src)\
3245 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__READ(src) \
3246 (u_int32_t)(src)\
3248 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__WRITE(src) \
3249 ((u_int32_t)(src)\
3251 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__MODIFY(dst, src) \
3253 ~0xffffffffU) | ((u_int32_t)(src) &\
3255 #define MAC_DCU_TXFILTER_DCU0_63_32__DATA__VERIFY(src) \
3256 (!(((u_int32_t)(src)\
3276 #define MAC_DCU_TXFILTER_DCU8_63_32__DATA__READ(src) \
3277 (u_int32_t)(src)\
3296 #define MAC_DCU_RETRY_LIMIT__FRFL__READ(src) (u_int32_t)(src) & 0x0000000fU
3297 #define MAC_DCU_RETRY_LIMIT__FRFL__WRITE(src) ((u_int32_t)(src) & 0x0000000fU)
3298 #define MAC_DCU_RETRY_LIMIT__FRFL__MODIFY(dst, src) \
3300 ~0x0000000fU) | ((u_int32_t)(src) &\
3302 #define MAC_DCU_RETRY_LIMIT__FRFL__VERIFY(src) \
3303 (!(((u_int32_t)(src)\
3310 #define MAC_DCU_RETRY_LIMIT__SRFL__READ(src) \
3311 (((u_int32_t)(src)\
3313 #define MAC_DCU_RETRY_LIMIT__SRFL__WRITE(src) \
3314 (((u_int32_t)(src)\
3316 #define MAC_DCU_RETRY_LIMIT__SRFL__MODIFY(dst, src) \
3318 ~0x00003f00U) | (((u_int32_t)(src) <<\
3320 #define MAC_DCU_RETRY_LIMIT__SRFL__VERIFY(src) \
3321 (!((((u_int32_t)(src)\
3328 #define MAC_DCU_RETRY_LIMIT__SDFL__READ(src) \
3329 (((u_int32_t)(src)\
3331 #define MAC_DCU_RETRY_LIMIT__SDFL__WRITE(src) \
3332 (((u_int32_t)(src)\
3334 #define MAC_DCU_RETRY_LIMIT__SDFL__MODIFY(dst, src) \
3336 ~0x000fc000U) | (((u_int32_t)(src) <<\
3338 #define MAC_DCU_RETRY_LIMIT__SDFL__VERIFY(src) \
3339 (!((((u_int32_t)(src)\
3359 #define MAC_DCU_GBL_IFS_EIFS__DURATION__READ(src) \
3360 (u_int32_t)(src)\
3362 #define MAC_DCU_GBL_IFS_EIFS__DURATION__WRITE(src) \
3363 ((u_int32_t)(src)\
3365 #define MAC_DCU_GBL_IFS_EIFS__DURATION__MODIFY(dst, src) \
3367 ~0x0000ffffU) | ((u_int32_t)(src) &\
3369 #define MAC_DCU_GBL_IFS_EIFS__DURATION__VERIFY(src) \
3370 (!(((u_int32_t)(src)\
3390 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__READ(src) \
3391 (u_int32_t)(src)\
3393 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__WRITE(src) \
3394 ((u_int32_t)(src)\
3396 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__MODIFY(dst, src) \
3398 ~0xffffffffU) | ((u_int32_t)(src) &\
3400 #define MAC_DCU_TXFILTER_DCU0_95_64__DATA__VERIFY(src) \
3401 (!(((u_int32_t)(src)\
3421 #define MAC_DCU_TXFILTER_DCU8_95_64__DATA__READ(src) \
3422 (u_int32_t)(src)\
3441 #define MAC_DCU_CHANNEL_TIME__DURATION__READ(src) \
3442 (u_int32_t)(src)\
3444 #define MAC_DCU_CHANNEL_TIME__DURATION__WRITE(src) \
3445 ((u_int32_t)(src)\
3447 #define MAC_DCU_CHANNEL_TIME__DURATION__MODIFY(dst, src) \
3449 ~0x000fffffU) | ((u_int32_t)(src) &\
3451 #define MAC_DCU_CHANNEL_TIME__DURATION__VERIFY(src) \
3452 (!(((u_int32_t)(src)\
3459 #define MAC_DCU_CHANNEL_TIME__ENABLE__READ(src) \
3460 (((u_int32_t)(src)\
3462 #define MAC_DCU_CHANNEL_TIME__ENABLE__WRITE(src) \
3463 (((u_int32_t)(src)\
3465 #define MAC_DCU_CHANNEL_TIME__ENABLE__MODIFY(dst, src) \
3467 ~0x00100000U) | (((u_int32_t)(src) <<\
3469 #define MAC_DCU_CHANNEL_TIME__ENABLE__VERIFY(src) \
3470 (!((((u_int32_t)(src)\
3496 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__READ(src) \
3497 (u_int32_t)(src)\
3499 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__WRITE(src) \
3500 ((u_int32_t)(src)\
3502 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__MODIFY(dst, src) \
3504 ~0x00000007U) | ((u_int32_t)(src) &\
3506 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_SEL__VERIFY(src) \
3507 (!(((u_int32_t)(src)\
3514 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__READ(src) \
3515 (((u_int32_t)(src)\
3517 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__WRITE(src) \
3518 (((u_int32_t)(src)\
3520 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__MODIFY(dst, src) \
3522 ~0x00000008U) | (((u_int32_t)(src) <<\
3524 #define MAC_DCU_GBL_IFS_MISC__TURBO_MODE__VERIFY(src) \
3525 (!((((u_int32_t)(src)\
3538 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__READ(src) \
3539 (((u_int32_t)(src)\
3541 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__WRITE(src) \
3542 (((u_int32_t)(src)\
3544 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__MODIFY(dst, src) \
3546 ~0x000003f0U) | (((u_int32_t)(src) <<\
3548 #define MAC_DCU_GBL_IFS_MISC__SIFS_DUR_USEC__VERIFY(src) \
3549 (!((((u_int32_t)(src)\
3556 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__READ(src) \
3557 (((u_int32_t)(src)\
3559 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__WRITE(src) \
3560 (((u_int32_t)(src)\
3562 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__MODIFY(dst, src) \
3564 ~0x00300000U) | (((u_int32_t)(src) <<\
3566 #define MAC_DCU_GBL_IFS_MISC__ARB_DLY__VERIFY(src) \
3567 (!((((u_int32_t)(src)\
3574 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__READ(src) \
3575 (((u_int32_t)(src)\
3577 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__WRITE(src) \
3578 (((u_int32_t)(src)\
3580 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__MODIFY(dst, src) \
3582 ~0x00400000U) | (((u_int32_t)(src) <<\
3584 #define MAC_DCU_GBL_IFS_MISC__SIFS_RST_UNCOND__VERIFY(src) \
3585 (!((((u_int32_t)(src)\
3598 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__READ(src) \
3599 (((u_int32_t)(src)\
3601 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__WRITE(src) \
3602 (((u_int32_t)(src)\
3604 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__MODIFY(dst, src) \
3606 ~0x00800000U) | (((u_int32_t)(src) <<\
3608 #define MAC_DCU_GBL_IFS_MISC__AIFS_RST_UNCOND__VERIFY(src) \
3609 (!((((u_int32_t)(src)\
3622 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__READ(src) \
3623 (((u_int32_t)(src)\
3625 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__WRITE(src) \
3626 (((u_int32_t)(src)\
3628 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__MODIFY(dst, src) \
3630 ~0x01000000U) | (((u_int32_t)(src) <<\
3632 #define MAC_DCU_GBL_IFS_MISC__LFSR_SLICE_RANDOM_DIS__VERIFY(src) \
3633 (!((((u_int32_t)(src)\
3646 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__READ(src) \
3647 (((u_int32_t)(src)\
3649 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__WRITE(src) \
3650 (((u_int32_t)(src)\
3652 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__MODIFY(dst, src) \
3654 ~0x06000000U) | (((u_int32_t)(src) <<\
3656 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_WIN_DUR__VERIFY(src) \
3657 (!((((u_int32_t)(src)\
3664 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__READ(src) \
3665 (((u_int32_t)(src)\
3667 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__WRITE(src) \
3668 (((u_int32_t)(src)\
3670 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__MODIFY(dst, src) \
3672 ~0x08000000U) | (((u_int32_t)(src) <<\
3674 #define MAC_DCU_GBL_IFS_MISC__CHAN_SLOT_ALWAYS__VERIFY(src) \
3675 (!((((u_int32_t)(src)\
3688 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__READ(src) \
3689 (((u_int32_t)(src)\
3691 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__WRITE(src) \
3692 (((u_int32_t)(src)\
3694 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__MODIFY(dst, src) \
3696 ~0x10000000U) | (((u_int32_t)(src) <<\
3698 #define MAC_DCU_GBL_IFS_MISC__IGNORE_BACKOFF__VERIFY(src) \
3699 (!((((u_int32_t)(src)\
3725 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__READ(src) \
3726 (u_int32_t)(src)\
3728 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__WRITE(src) \
3729 ((u_int32_t)(src)\
3731 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__MODIFY(dst, src) \
3733 ~0xffffffffU) | ((u_int32_t)(src) &\
3735 #define MAC_DCU_TXFILTER_DCU0_127_96__DATA__VERIFY(src) \
3736 (!(((u_int32_t)(src)\
3756 #define MAC_DCU_TXFILTER_DCU8_127_96__DATA__READ(src) \
3757 (u_int32_t)(src)\
3776 #define MAC_DCU_MISC__BKOFF_THRESH__READ(src) (u_int32_t)(src) & 0x0000003fU
3777 #define MAC_DCU_MISC__BKOFF_THRESH__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
3778 #define MAC_DCU_MISC__BKOFF_THRESH__MODIFY(dst, src) \
3780 ~0x0000003fU) | ((u_int32_t)(src) &\
3782 #define MAC_DCU_MISC__BKOFF_THRESH__VERIFY(src) \
3783 (!(((u_int32_t)(src)\
3790 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__READ(src) \
3791 (((u_int32_t)(src)\
3793 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__WRITE(src) \
3794 (((u_int32_t)(src)\
3796 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__MODIFY(dst, src) \
3798 ~0x00000040U) | (((u_int32_t)(src) <<\
3800 #define MAC_DCU_MISC__SFC_RST_AT_TS_END_EN__VERIFY(src) \
3801 (!((((u_int32_t)(src)\
3814 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__READ(src) \
3815 (((u_int32_t)(src)\
3817 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__WRITE(src) \
3818 (((u_int32_t)(src)\
3820 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__MODIFY(dst, src) \
3822 ~0x00000080U) | (((u_int32_t)(src) <<\
3824 #define MAC_DCU_MISC__CW_RST_AT_TS_END_DIS__VERIFY(src) \
3825 (!((((u_int32_t)(src)\
3838 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__READ(src) \
3839 (((u_int32_t)(src)\
3841 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__WRITE(src) \
3842 (((u_int32_t)(src)\
3844 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__MODIFY(dst, src) \
3846 ~0x00000100U) | (((u_int32_t)(src) <<\
3848 #define MAC_DCU_MISC__FRAG_BURST_WAIT_QCU_EN__VERIFY(src) \
3849 (!((((u_int32_t)(src)\
3862 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__READ(src) \
3863 (((u_int32_t)(src)\
3865 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__WRITE(src) \
3866 (((u_int32_t)(src)\
3868 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__MODIFY(dst, src) \
3870 ~0x00000200U) | (((u_int32_t)(src) <<\
3872 #define MAC_DCU_MISC__FRAG_BURST_BKOFF_EN__VERIFY(src) \
3873 (!((((u_int32_t)(src)\
3886 #define MAC_DCU_MISC__HCF_POLL_EN__READ(src) \
3887 (((u_int32_t)(src)\
3889 #define MAC_DCU_MISC__HCF_POLL_EN__WRITE(src) \
3890 (((u_int32_t)(src)\
3892 #define MAC_DCU_MISC__HCF_POLL_EN__MODIFY(dst, src) \
3894 ~0x00000800U) | (((u_int32_t)(src) <<\
3896 #define MAC_DCU_MISC__HCF_POLL_EN__VERIFY(src) \
3897 (!((((u_int32_t)(src)\
3910 #define MAC_DCU_MISC__BKOFF_PF__READ(src) \
3911 (((u_int32_t)(src)\
3913 #define MAC_DCU_MISC__BKOFF_PF__WRITE(src) \
3914 (((u_int32_t)(src)\
3916 #define MAC_DCU_MISC__BKOFF_PF__MODIFY(dst, src) \
3918 ~0x00001000U) | (((u_int32_t)(src) <<\
3920 #define MAC_DCU_MISC__BKOFF_PF__VERIFY(src) \
3921 (!((((u_int32_t)(src)\
3934 #define MAC_DCU_MISC__VIRT_COLL_POLICY__READ(src) \
3935 (((u_int32_t)(src)\
3937 #define MAC_DCU_MISC__VIRT_COLL_POLICY__WRITE(src) \
3938 (((u_int32_t)(src)\
3940 #define MAC_DCU_MISC__VIRT_COLL_POLICY__MODIFY(dst, src) \
3942 ~0x0000c000U) | (((u_int32_t)(src) <<\
3944 #define MAC_DCU_MISC__VIRT_COLL_POLICY__VERIFY(src) \
3945 (!((((u_int32_t)(src)\
3952 #define MAC_DCU_MISC__IS_BCN__READ(src) \
3953 (((u_int32_t)(src)\
3955 #define MAC_DCU_MISC__IS_BCN__WRITE(src) \
3956 (((u_int32_t)(src)\
3958 #define MAC_DCU_MISC__IS_BCN__MODIFY(dst, src) \
3960 ~0x00010000U) | (((u_int32_t)(src) <<\
3962 #define MAC_DCU_MISC__IS_BCN__VERIFY(src) \
3963 (!((((u_int32_t)(src)\
3976 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__READ(src) \
3977 (((u_int32_t)(src)\
3979 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__WRITE(src) \
3980 (((u_int32_t)(src)\
3982 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__MODIFY(dst, src) \
3984 ~0x00020000U) | (((u_int32_t)(src) <<\
3986 #define MAC_DCU_MISC__ARB_LOCKOUT_IF_EN__VERIFY(src) \
3987 (!((((u_int32_t)(src)\
4000 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__READ(src) \
4001 (((u_int32_t)(src)\
4003 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__WRITE(src) \
4004 (((u_int32_t)(src)\
4006 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__MODIFY(dst, src) \
4008 ~0x00040000U) | (((u_int32_t)(src) <<\
4010 #define MAC_DCU_MISC__LOCKOUT_GBL_EN__VERIFY(src) \
4011 (!((((u_int32_t)(src)\
4024 #define MAC_DCU_MISC__LOCKOUT_IGNORE__READ(src) \
4025 (((u_int32_t)(src)\
4027 #define MAC_DCU_MISC__LOCKOUT_IGNORE__WRITE(src) \
4028 (((u_int32_t)(src)\
4030 #define MAC_DCU_MISC__LOCKOUT_IGNORE__MODIFY(dst, src) \
4032 ~0x00080000U) | (((u_int32_t)(src) <<\
4034 #define MAC_DCU_MISC__LOCKOUT_IGNORE__VERIFY(src) \
4035 (!((((u_int32_t)(src)\
4048 #define MAC_DCU_MISC__SEQNUM_FREEZE__READ(src) \
4049 (((u_int32_t)(src)\
4051 #define MAC_DCU_MISC__SEQNUM_FREEZE__WRITE(src) \
4052 (((u_int32_t)(src)\
4054 #define MAC_DCU_MISC__SEQNUM_FREEZE__MODIFY(dst, src) \
4056 ~0x00100000U) | (((u_int32_t)(src) <<\
4058 #define MAC_DCU_MISC__SEQNUM_FREEZE__VERIFY(src) \
4059 (!((((u_int32_t)(src)\
4072 #define MAC_DCU_MISC__POST_BKOFF_SKIP__READ(src) \
4073 (((u_int32_t)(src)\
4075 #define MAC_DCU_MISC__POST_BKOFF_SKIP__WRITE(src) \
4076 (((u_int32_t)(src)\
4078 #define MAC_DCU_MISC__POST_BKOFF_SKIP__MODIFY(dst, src) \
4080 ~0x00200000U) | (((u_int32_t)(src) <<\
4082 #define MAC_DCU_MISC__POST_BKOFF_SKIP__VERIFY(src) \
4083 (!((((u_int32_t)(src)\
4096 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__READ(src) \
4097 (((u_int32_t)(src)\
4099 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__WRITE(src) \
4100 (((u_int32_t)(src)\
4102 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__MODIFY(dst, src) \
4104 ~0x00400000U) | (((u_int32_t)(src) <<\
4106 #define MAC_DCU_MISC__VIRT_COLL_CW_INC_EN__VERIFY(src) \
4107 (!((((u_int32_t)(src)\
4120 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__READ(src) \
4121 (((u_int32_t)(src)\
4123 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__WRITE(src) \
4124 (((u_int32_t)(src)\
4126 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__MODIFY(dst, src) \
4128 ~0x00800000U) | (((u_int32_t)(src) <<\
4130 #define MAC_DCU_MISC__RETRY_ON_BLOWN_IFS_EN__VERIFY(src) \
4131 (!((((u_int32_t)(src)\
4144 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__READ(src) \
4145 (((u_int32_t)(src)\
4147 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__WRITE(src) \
4148 (((u_int32_t)(src)\
4150 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__MODIFY(dst, src) \
4152 ~0x01000000U) | (((u_int32_t)(src) <<\
4154 #define MAC_DCU_MISC__SIFS_BURST_CHAN_BUSY_IGNORE__VERIFY(src) \
4155 (!((((u_int32_t)(src)\
4181 #define MAC_DCU_TXFILTER_DCU1_31_0__DATA__READ(src) \
4182 (u_int32_t)(src)\
4201 #define MAC_DCU_TXFILTER_DCU9_31_0__DATA__READ(src) \
4202 (u_int32_t)(src)\
4221 #define MAC_DCU_SEQ__NUM__READ(src) (u_int32_t)(src) & 0xffffffffU
4222 #define MAC_DCU_SEQ__NUM__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
4223 #define MAC_DCU_SEQ__NUM__MODIFY(dst, src) \
4225 ~0xffffffffU) | ((u_int32_t)(src) &\
4227 #define MAC_DCU_SEQ__NUM__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
4246 #define MAC_DCU_TXFILTER_DCU1_63_32__DATA__READ(src) \
4247 (u_int32_t)(src)\
4266 #define MAC_DCU_TXFILTER_DCU9_63_32__DATA__READ(src) \
4267 (u_int32_t)(src)\
4286 #define MAC_DCU_TXFILTER_DCU1_95_64__DATA__READ(src) \
4287 (u_int32_t)(src)\
4306 #define MAC_DCU_TXFILTER_DCU9_95_64__DATA__READ(src) \
4307 (u_int32_t)(src)\
4326 #define MAC_DCU_TXFILTER_DCU1_127_96__DATA__READ(src) \
4327 (u_int32_t)(src)\
4346 #define MAC_DCU_TXFILTER_DCU9_127_96__DATA__READ(src) \
4347 (u_int32_t)(src)\
4366 #define MAC_DCU_TXFILTER_DCU2_31_0__DATA__READ(src) \
4367 (u_int32_t)(src)\
4386 #define MAC_DCU_PAUSE__REQUEST__READ(src) (u_int32_t)(src) & 0x000003ffU
4387 #define MAC_DCU_PAUSE__REQUEST__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
4388 #define MAC_DCU_PAUSE__REQUEST__MODIFY(dst, src) \
4390 ~0x000003ffU) | ((u_int32_t)(src) &\
4392 #define MAC_DCU_PAUSE__REQUEST__VERIFY(src) \
4393 (!(((u_int32_t)(src)\
4400 #define MAC_DCU_PAUSE__STATUS__READ(src) \
4401 (((u_int32_t)(src)\
4427 #define MAC_DCU_TXFILTER_DCU2_63_32__DATA__READ(src) \
4428 (u_int32_t)(src)\
4447 #define MAC_DCU_WOW_KACFG__TX_EN__READ(src) (u_int32_t)(src) & 0x00000001U
4448 #define MAC_DCU_WOW_KACFG__TX_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
4449 #define MAC_DCU_WOW_KACFG__TX_EN__MODIFY(dst, src) \
4451 ~0x00000001U) | ((u_int32_t)(src) &\
4453 #define MAC_DCU_WOW_KACFG__TX_EN__VERIFY(src) \
4454 (!(((u_int32_t)(src)\
4467 #define MAC_DCU_WOW_KACFG__TIM_EN__READ(src) \
4468 (((u_int32_t)(src)\
4470 #define MAC_DCU_WOW_KACFG__TIM_EN__WRITE(src) \
4471 (((u_int32_t)(src)\
4473 #define MAC_DCU_WOW_KACFG__TIM_EN__MODIFY(dst, src) \
4475 ~0x00000002U) | (((u_int32_t)(src) <<\
4477 #define MAC_DCU_WOW_KACFG__TIM_EN__VERIFY(src) \
4478 (!((((u_int32_t)(src)\
4491 #define MAC_DCU_WOW_KACFG__BCN_CNT__READ(src) \
4492 (((u_int32_t)(src)\
4494 #define MAC_DCU_WOW_KACFG__BCN_CNT__WRITE(src) \
4495 (((u_int32_t)(src)\
4497 #define MAC_DCU_WOW_KACFG__BCN_CNT__MODIFY(dst, src) \
4499 ~0x00000ff0U) | (((u_int32_t)(src) <<\
4501 #define MAC_DCU_WOW_KACFG__BCN_CNT__VERIFY(src) \
4502 (!((((u_int32_t)(src)\
4509 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__READ(src) \
4510 (((u_int32_t)(src)\
4512 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__WRITE(src) \
4513 (((u_int32_t)(src)\
4515 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__MODIFY(dst, src) \
4517 ~0x00fff000U) | (((u_int32_t)(src) <<\
4519 #define MAC_DCU_WOW_KACFG__RX_TIMEOUT_CNT__VERIFY(src) \
4520 (!((((u_int32_t)(src)\
4540 #define MAC_DCU_TXFILTER_DCU2_95_64__DATA__READ(src) \
4541 (u_int32_t)(src)\
4560 #define MAC_DCU_TXSLOT__MASK__READ(src) (u_int32_t)(src) & 0x0000ffffU
4561 #define MAC_DCU_TXSLOT__MASK__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
4562 #define MAC_DCU_TXSLOT__MASK__MODIFY(dst, src) \
4564 ~0x0000ffffU) | ((u_int32_t)(src) &\
4566 #define MAC_DCU_TXSLOT__MASK__VERIFY(src) \
4567 (!(((u_int32_t)(src)\
4587 #define MAC_DCU_TXFILTER_DCU2_127_96__DATA__READ(src) \
4588 (u_int32_t)(src)\
4607 #define MAC_DCU_TXFILTER_DCU3_31_0__DATA__READ(src) \
4608 (u_int32_t)(src)\
4627 #define MAC_DCU_TXFILTER_DCU3_63_32__DATA__READ(src) \
4628 (u_int32_t)(src)\
4647 #define MAC_DCU_TXFILTER_DCU3_95_64__DATA__READ(src) \
4648 (u_int32_t)(src)\
4667 #define MAC_DCU_TXFILTER_DCU3_127_96__DATA__READ(src) \
4668 (u_int32_t)(src)\
4687 #define MAC_DCU_TXFILTER_DCU4_31_0__DATA__READ(src) \
4688 (u_int32_t)(src)\
4707 #define MAC_DCU_TXFILTER_CLEAR__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
4708 #define MAC_DCU_TXFILTER_CLEAR__DATA__WRITE(src) \
4709 ((u_int32_t)(src)\
4711 #define MAC_DCU_TXFILTER_CLEAR__DATA__MODIFY(dst, src) \
4713 ~0xffffffffU) | ((u_int32_t)(src) &\
4715 #define MAC_DCU_TXFILTER_CLEAR__DATA__VERIFY(src) \
4716 (!(((u_int32_t)(src)\
4736 #define MAC_DCU_TXFILTER_DCU4_63_32__DATA__READ(src) \
4737 (u_int32_t)(src)\
4756 #define MAC_DCU_TXFILTER_SET__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
4757 #define MAC_DCU_TXFILTER_SET__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
4758 #define MAC_DCU_TXFILTER_SET__DATA__MODIFY(dst, src) \
4760 ~0xffffffffU) | ((u_int32_t)(src) &\
4762 #define MAC_DCU_TXFILTER_SET__DATA__VERIFY(src) \
4763 (!(((u_int32_t)(src)\
4783 #define MAC_DCU_TXFILTER_DCU4_95_64__DATA__READ(src) \
4784 (u_int32_t)(src)\
4803 #define MAC_DCU_TXFILTER_DCU4_127_96__DATA__READ(src) \
4804 (u_int32_t)(src)\
4823 #define MAC_DCU_TXFILTER_DCU5_31_0__DATA__READ(src) \
4824 (u_int32_t)(src)\
4843 #define MAC_DCU_TXFILTER_DCU5_63_32__DATA__READ(src) \
4844 (u_int32_t)(src)\
4863 #define MAC_DCU_TXFILTER_DCU5_95_64__DATA__READ(src) \
4864 (u_int32_t)(src)\
4883 #define MAC_DCU_TXFILTER_DCU5_127_96__DATA__READ(src) \
4884 (u_int32_t)(src)\
4903 #define MAC_DCU_TXFILTER_DCU6_31_0__DATA__READ(src) \
4904 (u_int32_t)(src)\
4923 #define MAC_DCU_TXFILTER_DCU6_63_32__DATA__READ(src) \
4924 (u_int32_t)(src)\
4943 #define MAC_DCU_TXFILTER_DCU6_95_64__DATA__READ(src) \
4944 (u_int32_t)(src)\
4963 #define MAC_DCU_TXFILTER_DCU6_127_96__DATA__READ(src) \
4964 (u_int32_t)(src)\
4983 #define MAC_DCU_TXFILTER_DCU7_31_0__DATA__READ(src) \
4984 (u_int32_t)(src)\
5003 #define MAC_DCU_TXFILTER_DCU7_63_32__DATA__READ(src) \
5004 (u_int32_t)(src)\
5023 #define MAC_DCU_TXFILTER_DCU7_95_64__DATA__READ(src) \
5024 (u_int32_t)(src)\
5043 #define MAC_DCU_TXFILTER_DCU7_127_96__DATA__READ(src) \
5044 (u_int32_t)(src)\
5063 #define HOST_INTF_RESET_CONTROL__AHB_RESET__READ(src) \
5064 (u_int32_t)(src)\
5066 #define HOST_INTF_RESET_CONTROL__AHB_RESET__WRITE(src) \
5067 ((u_int32_t)(src)\
5069 #define HOST_INTF_RESET_CONTROL__AHB_RESET__MODIFY(dst, src) \
5071 ~0x00000001U) | ((u_int32_t)(src) &\
5073 #define HOST_INTF_RESET_CONTROL__AHB_RESET__VERIFY(src) \
5074 (!(((u_int32_t)(src)\
5087 #define HOST_INTF_RESET_CONTROL__APB_RESET__READ(src) \
5088 (((u_int32_t)(src)\
5090 #define HOST_INTF_RESET_CONTROL__APB_RESET__WRITE(src) \
5091 (((u_int32_t)(src)\
5093 #define HOST_INTF_RESET_CONTROL__APB_RESET__MODIFY(dst, src) \
5095 ~0x00000002U) | (((u_int32_t)(src) <<\
5097 #define HOST_INTF_RESET_CONTROL__APB_RESET__VERIFY(src) \
5098 (!((((u_int32_t)(src)\
5111 #define HOST_INTF_RESET_CONTROL__LOCAL_RESET__READ(src) \
5112 (((u_int32_t)(src)\
5114 #define HOST_INTF_RESET_CONTROL__LOCAL_RESET__WRITE(src) \
5115 (((u_int32_t)(src)\
5117 #define HOST_INTF_RESET_CONTROL__LOCAL_RESET__MODIFY(dst, src) \
5119 ~0x00000100U) | (((u_int32_t)(src) <<\
5121 #define HOST_INTF_RESET_CONTROL__LOCAL_RESET__VERIFY(src) \
5122 (!((((u_int32_t)(src)\
5148 #define HOST_INTF_WORK_AROUND__TS1_WA_EN__READ(src) \
5149 (u_int32_t)(src)\
5151 #define HOST_INTF_WORK_AROUND__TS1_WA_EN__WRITE(src) \
5152 ((u_int32_t)(src)\
5154 #define HOST_INTF_WORK_AROUND__TS1_WA_EN__MODIFY(dst, src) \
5156 ~0x00000001U) | ((u_int32_t)(src) &\
5158 #define HOST_INTF_WORK_AROUND__TS1_WA_EN__VERIFY(src) \
5159 (!(((u_int32_t)(src)\
5172 #define HOST_INTF_WORK_AROUND__TS2_WA_EN__READ(src) \
5173 (((u_int32_t)(src)\
5175 #define HOST_INTF_WORK_AROUND__TS2_WA_EN__WRITE(src) \
5176 (((u_int32_t)(src)\
5178 #define HOST_INTF_WORK_AROUND__TS2_WA_EN__MODIFY(dst, src) \
5180 ~0x00000002U) | (((u_int32_t)(src) <<\
5182 #define HOST_INTF_WORK_AROUND__TS2_WA_EN__VERIFY(src) \
5183 (!((((u_int32_t)(src)\
5196 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__READ(src) \
5197 (((u_int32_t)(src)\
5199 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__WRITE(src) \
5200 (((u_int32_t)(src)\
5202 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__MODIFY(dst, src) \
5204 ~0x00000004U) | (((u_int32_t)(src) <<\
5206 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_EN__VERIFY(src) \
5207 (!((((u_int32_t)(src)\
5220 #define HOST_INTF_WORK_AROUND__GDATA_WA_EN__READ(src) \
5221 (((u_int32_t)(src)\
5223 #define HOST_INTF_WORK_AROUND__GDATA_WA_EN__WRITE(src) \
5224 (((u_int32_t)(src)\
5226 #define HOST_INTF_WORK_AROUND__GDATA_WA_EN__MODIFY(dst, src) \
5228 ~0x00000008U) | (((u_int32_t)(src) <<\
5230 #define HOST_INTF_WORK_AROUND__GDATA_WA_EN__VERIFY(src) \
5231 (!((((u_int32_t)(src)\
5244 #define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__READ(src) \
5245 (((u_int32_t)(src)\
5247 #define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__WRITE(src) \
5248 (((u_int32_t)(src)\
5250 #define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__MODIFY(dst, src) \
5252 ~0x00000010U) | (((u_int32_t)(src) <<\
5254 #define HOST_INTF_WORK_AROUND__NO_NAK_WA_EN__VERIFY(src) \
5255 (!((((u_int32_t)(src)\
5268 #define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__READ(src) \
5269 (((u_int32_t)(src)\
5271 #define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__WRITE(src) \
5272 (((u_int32_t)(src)\
5274 #define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__MODIFY(dst, src) \
5276 ~0x00000200U) | (((u_int32_t)(src) <<\
5278 #define HOST_INTF_WORK_AROUND__FORCE_L1L0_DMA__VERIFY(src) \
5279 (!((((u_int32_t)(src)\
5292 #define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__READ(src) \
5293 (((u_int32_t)(src)\
5295 #define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__WRITE(src) \
5296 (((u_int32_t)(src)\
5298 #define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__MODIFY(dst, src) \
5300 ~0x00002000U) | (((u_int32_t)(src) <<\
5302 #define HOST_INTF_WORK_AROUND__PCIE_COLD_RESET_OVRRD__VERIFY(src) \
5303 (!((((u_int32_t)(src)\
5316 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__READ(src) \
5317 (((u_int32_t)(src)\
5319 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__WRITE(src) \
5320 (((u_int32_t)(src)\
5322 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__MODIFY(dst, src) \
5324 ~0x00004000U) | (((u_int32_t)(src) <<\
5326 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE__VERIFY(src) \
5327 (!((((u_int32_t)(src)\
5340 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__READ(src) \
5341 (((u_int32_t)(src)\
5343 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__WRITE(src) \
5344 (((u_int32_t)(src)\
5346 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__MODIFY(dst, src) \
5348 ~0x00008000U) | (((u_int32_t)(src) <<\
5350 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHORT__VERIFY(src) \
5351 (!((((u_int32_t)(src)\
5364 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__READ(src) \
5365 (((u_int32_t)(src)\
5367 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__WRITE(src) \
5368 (((u_int32_t)(src)\
5370 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__MODIFY(dst, src) \
5372 ~0x00010000U) | (((u_int32_t)(src) <<\
5374 #define HOST_INTF_WORK_AROUND__D3_TO_L1_DISABLE_REAL__VERIFY(src) \
5375 (!((((u_int32_t)(src)\
5388 #define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__READ(src) \
5389 (((u_int32_t)(src)\
5391 #define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__WRITE(src) \
5392 (((u_int32_t)(src)\
5394 #define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__MODIFY(dst, src) \
5396 ~0x00020000U) | (((u_int32_t)(src) <<\
5398 #define HOST_INTF_WORK_AROUND__ASPM_TIMER_BASED_L1_DISABLE__VERIFY(src) \
5399 (!((((u_int32_t)(src)\
5412 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__READ(src) \
5413 (((u_int32_t)(src)\
5415 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__WRITE(src) \
5416 (((u_int32_t)(src)\
5418 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__MODIFY(dst, src) \
5420 ~0x00040000U) | (((u_int32_t)(src) <<\
5422 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SW_CNTL__VERIFY(src) \
5423 (!((((u_int32_t)(src)\
5436 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__READ(src) \
5437 (((u_int32_t)(src)\
5439 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__WRITE(src) \
5440 (((u_int32_t)(src)\
5442 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__MODIFY(dst, src) \
5444 ~0x00100000U) | (((u_int32_t)(src) <<\
5446 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_SHIFT__VERIFY(src) \
5447 (!((((u_int32_t)(src)\
5460 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__READ(src) \
5461 (((u_int32_t)(src)\
5463 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__WRITE(src) \
5464 (((u_int32_t)(src)\
5466 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__MODIFY(dst, src) \
5468 ~0x00200000U) | (((u_int32_t)(src) <<\
5470 #define HOST_INTF_WORK_AROUND__PCIERST_PORRST_PHY__VERIFY(src) \
5471 (!((((u_int32_t)(src)\
5484 #define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__READ(src) \
5485 (((u_int32_t)(src)\
5487 #define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__WRITE(src) \
5488 (((u_int32_t)(src)\
5490 #define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__MODIFY(dst, src) \
5492 ~0x00800000U) | (((u_int32_t)(src) <<\
5494 #define HOST_INTF_WORK_AROUND__PCIE_NFTS_CNTL_EN__VERIFY(src) \
5495 (!((((u_int32_t)(src)\
5508 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__READ(src) \
5509 (((u_int32_t)(src)\
5511 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__WRITE(src) \
5512 (((u_int32_t)(src)\
5514 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__MODIFY(dst, src) \
5516 ~0xff000000U) | (((u_int32_t)(src) <<\
5518 #define HOST_INTF_WORK_AROUND__RESET_SERDES_WA_TIMEOUT__VERIFY(src) \
5519 (!((((u_int32_t)(src)\
5539 #define HOST_INTF_PM_STATE__PCIE_PM_XTLH_BLOCK_TLP__READ(src) \
5540 (u_int32_t)(src)\
5553 #define HOST_INTF_PM_STATE__PCIE_PM_CURNT_STATE__READ(src) \
5554 (((u_int32_t)(src)\
5561 #define HOST_INTF_PM_STATE__PCIE_PM_DSTATE__READ(src) \
5562 (((u_int32_t)(src)\
5569 #define HOST_INTF_PM_STATE__PCIE_PM_PME_EN__READ(src) \
5570 (((u_int32_t)(src)\
5583 #define HOST_INTF_PM_STATE__PCIE_PM_STATUS__READ(src) \
5584 (((u_int32_t)(src)\
5597 #define HOST_INTF_PM_STATE__PCIE_AUX_PM_EN__READ(src) \
5598 (((u_int32_t)(src)\
5611 #define HOST_INTF_PM_STATE__PCIE_XMLH_LTSSM_STATE__READ(src) \
5612 (((u_int32_t)(src)\
5619 #define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_MAC__READ(src) \
5620 (((u_int32_t)(src)\
5633 #define HOST_INTF_PM_STATE__CLKMISC_MULTI_PIPE_MODE_PHY__READ(src) \
5634 (((u_int32_t)(src)\
5647 #define HOST_INTF_PM_STATE__CLKMISC_MULTI_PCIE_PHY_TEST__READ(src) \
5648 (((u_int32_t)(src)\
5673 #define HOST_INTF_CXPL_DEBUG_INFOL__DATA__READ(src) \
5674 (u_int32_t)(src)\
5693 #define HOST_INTF_CXPL_DEBUG_INFOH__DATA__READ(src) \
5694 (u_int32_t)(src)\
5713 #define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__READ(src) \
5714 (u_int32_t)(src)\
5716 #define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__WRITE(src) \
5717 ((u_int32_t)(src)\
5719 #define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__MODIFY(dst, src) \
5721 ~0x00000001U) | ((u_int32_t)(src) &\
5723 #define HOST_INTF_PM_CTRL__PCIE_PM_OVERRIDE__VERIFY(src) \
5724 (!(((u_int32_t)(src)\
5737 #define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__READ(src) \
5738 (((u_int32_t)(src)\
5740 #define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__WRITE(src) \
5741 (((u_int32_t)(src)\
5743 #define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__MODIFY(dst, src) \
5745 ~0x0003fffcU) | (((u_int32_t)(src) <<\
5747 #define HOST_INTF_PM_CTRL__PCIE_PM_DELAY__VERIFY(src) \
5748 (!((((u_int32_t)(src)\
5755 #define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__READ(src) \
5756 (((u_int32_t)(src)\
5758 #define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__WRITE(src) \
5759 (((u_int32_t)(src)\
5761 #define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__MODIFY(dst, src) \
5763 ~0x00040000U) | (((u_int32_t)(src) <<\
5765 #define HOST_INTF_PM_CTRL__PCIE_PM_DISABLE__VERIFY(src) \
5766 (!((((u_int32_t)(src)\
5779 #define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__READ(src) \
5780 (((u_int32_t)(src)\
5782 #define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__WRITE(src) \
5783 (((u_int32_t)(src)\
5785 #define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__MODIFY(dst, src) \
5787 ~0x00080000U) | (((u_int32_t)(src) <<\
5789 #define HOST_INTF_PM_CTRL__PCIE_ENTER_L1_EN__VERIFY(src) \
5790 (!((((u_int32_t)(src)\
5803 #define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__READ(src) \
5804 (((u_int32_t)(src)\
5806 #define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__WRITE(src) \
5807 (((u_int32_t)(src)\
5809 #define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__MODIFY(dst, src) \
5811 ~0x00100000U) | (((u_int32_t)(src) <<\
5813 #define HOST_INTF_PM_CTRL__PCIE_PME_DISABLE_CLK__VERIFY(src) \
5814 (!((((u_int32_t)(src)\
5827 #define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__READ(src) \
5828 (((u_int32_t)(src)\
5830 #define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__WRITE(src) \
5831 (((u_int32_t)(src)\
5833 #define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__MODIFY(dst, src) \
5835 ~0x00200000U) | (((u_int32_t)(src) <<\
5837 #define HOST_INTF_PM_CTRL__HOST_MAC_WOW_CLEAR__VERIFY(src) \
5838 (!((((u_int32_t)(src)\
5851 #define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__READ(src) \
5852 (((u_int32_t)(src)\
5854 #define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__WRITE(src) \
5855 (((u_int32_t)(src)\
5857 #define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__MODIFY(dst, src) \
5859 ~0x00400000U) | (((u_int32_t)(src) <<\
5861 #define HOST_INTF_PM_CTRL__HOST_PME_ENABLE__VERIFY(src) \
5862 (!((((u_int32_t)(src)\
5875 #define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__READ(src) \
5876 (((u_int32_t)(src)\
5878 #define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__WRITE(src) \
5879 (((u_int32_t)(src)\
5881 #define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__MODIFY(dst, src) \
5883 ~0x0f000000U) | (((u_int32_t)(src) <<\
5885 #define HOST_INTF_PM_CTRL__PME_POWER_STATE_MASK__VERIFY(src) \
5886 (!((((u_int32_t)(src)\
5893 #define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__READ(src) \
5894 (((u_int32_t)(src)\
5896 #define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__WRITE(src) \
5897 (((u_int32_t)(src)\
5899 #define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__MODIFY(dst, src) \
5901 ~0x10000000U) | (((u_int32_t)(src) <<\
5903 #define HOST_INTF_PM_CTRL__SYS_AUX_PWR_DET__VERIFY(src) \
5904 (!((((u_int32_t)(src)\
5917 #define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__READ(src) \
5918 (((u_int32_t)(src)\
5920 #define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__WRITE(src) \
5921 (((u_int32_t)(src)\
5923 #define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__MODIFY(dst, src) \
5925 ~0x20000000U) | (((u_int32_t)(src) <<\
5927 #define HOST_INTF_PM_CTRL__PCIE_PWDBIAS_OVRD__VERIFY(src) \
5928 (!((((u_int32_t)(src)\
5941 #define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__READ(src) \
5942 (((u_int32_t)(src)\
5944 #define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__WRITE(src) \
5945 (((u_int32_t)(src)\
5947 #define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__MODIFY(dst, src) \
5949 ~0x40000000U) | (((u_int32_t)(src) <<\
5951 #define HOST_INTF_PM_CTRL__PCIE_CLKREQ_OVRD__VERIFY(src) \
5952 (!((((u_int32_t)(src)\
5978 #define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__READ(src) \
5979 (u_int32_t)(src)\
5981 #define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__WRITE(src) \
5982 ((u_int32_t)(src)\
5984 #define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__MODIFY(dst, src) \
5986 ~0x0000ffffU) | ((u_int32_t)(src) &\
5988 #define HOST_INTF_TIMEOUT__APB_TIMEOUT_VAL__VERIFY(src) \
5989 (!(((u_int32_t)(src)\
5996 #define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__READ(src) \
5997 (((u_int32_t)(src)\
5999 #define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__WRITE(src) \
6000 (((u_int32_t)(src)\
6002 #define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__MODIFY(dst, src) \
6004 ~0xffff0000U) | (((u_int32_t)(src) <<\
6006 #define HOST_INTF_TIMEOUT__AXI_TIMEOUT_VAL__VERIFY(src) \
6007 (!((((u_int32_t)(src)\
6027 #define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__READ(src) \
6028 (u_int32_t)(src)\
6030 #define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__WRITE(src) \
6031 ((u_int32_t)(src)\
6033 #define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__MODIFY(dst, src) \
6035 ~0x00000001U) | ((u_int32_t)(src) &\
6037 #define HOST_INTF_EEPROM_CTRL__FAST_FLASH_MODE__VERIFY(src) \
6038 (!(((u_int32_t)(src)\
6051 #define HOST_INTF_EEPROM_CTRL__FORCE_RESET__READ(src) \
6052 (((u_int32_t)(src)\
6054 #define HOST_INTF_EEPROM_CTRL__FORCE_RESET__WRITE(src) \
6055 (((u_int32_t)(src)\
6057 #define HOST_INTF_EEPROM_CTRL__FORCE_RESET__MODIFY(dst, src) \
6059 ~0x00000002U) | (((u_int32_t)(src) <<\
6061 #define HOST_INTF_EEPROM_CTRL__FORCE_RESET__VERIFY(src) \
6062 (!((((u_int32_t)(src)\
6075 #define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__READ(src) \
6076 (((u_int32_t)(src)\
6078 #define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__WRITE(src) \
6079 (((u_int32_t)(src)\
6081 #define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__MODIFY(dst, src) \
6083 ~0x000000fcU) | (((u_int32_t)(src) <<\
6085 #define HOST_INTF_EEPROM_CTRL__CLKDIV_RST_VAL__VERIFY(src) \
6086 (!((((u_int32_t)(src)\
6093 #define HOST_INTF_EEPROM_CTRL__NOT_PRESENT__READ(src) \
6094 (((u_int32_t)(src)\
6107 #define HOST_INTF_EEPROM_CTRL__IS_CORRUPT__READ(src) \
6108 (((u_int32_t)(src)\
6121 #define HOST_INTF_EEPROM_CTRL__PROTECT__READ(src) \
6122 (((u_int32_t)(src)\
6142 #define HOST_INTF_SREV__MAC_ID__READ(src) (u_int32_t)(src) & 0xffffffffU
6160 #define HOST_INTF_INTR_SYNC_CAUSE__DATA__READ(src) \
6161 (u_int32_t)(src)\
6163 #define HOST_INTF_INTR_SYNC_CAUSE__DATA__WRITE(src) \
6164 ((u_int32_t)(src)\
6166 #define HOST_INTF_INTR_SYNC_CAUSE__DATA__MODIFY(dst, src) \
6168 ~0xffffffffU) | ((u_int32_t)(src) &\
6170 #define HOST_INTF_INTR_SYNC_CAUSE__DATA__VERIFY(src) \
6171 (!(((u_int32_t)(src)\
6191 #define HOST_INTF_INTR_SYNC_ENABLE__DATA__READ(src) \
6192 (u_int32_t)(src)\
6194 #define HOST_INTF_INTR_SYNC_ENABLE__DATA__WRITE(src) \
6195 ((u_int32_t)(src)\
6197 #define HOST_INTF_INTR_SYNC_ENABLE__DATA__MODIFY(dst, src) \
6199 ~0xffffffffU) | ((u_int32_t)(src) &\
6201 #define HOST_INTF_INTR_SYNC_ENABLE__DATA__VERIFY(src) \
6202 (!(((u_int32_t)(src)\
6222 #define HOST_INTF_INTR_ASYNC_MASK__DATA__READ(src) \
6223 (u_int32_t)(src)\
6225 #define HOST_INTF_INTR_ASYNC_MASK__DATA__WRITE(src) \
6226 ((u_int32_t)(src)\
6228 #define HOST_INTF_INTR_ASYNC_MASK__DATA__MODIFY(dst, src) \
6230 ~0xffffffffU) | ((u_int32_t)(src) &\
6232 #define HOST_INTF_INTR_ASYNC_MASK__DATA__VERIFY(src) \
6233 (!(((u_int32_t)(src)\
6253 #define HOST_INTF_INTR_SYNC_MASK__DATA__READ(src) \
6254 (u_int32_t)(src)\
6256 #define HOST_INTF_INTR_SYNC_MASK__DATA__WRITE(src) \
6257 ((u_int32_t)(src)\
6259 #define HOST_INTF_INTR_SYNC_MASK__DATA__MODIFY(dst, src) \
6261 ~0xffffffffU) | ((u_int32_t)(src) &\
6263 #define HOST_INTF_INTR_SYNC_MASK__DATA__VERIFY(src) \
6264 (!(((u_int32_t)(src)\
6284 #define HOST_INTF_INTR_ASYNC_CAUSE__DATA__READ(src) \
6285 (u_int32_t)(src)\
6304 #define HOST_INTF_INTR_ASYNC_ENABLE__DATA__READ(src) \
6305 (u_int32_t)(src)\
6307 #define HOST_INTF_INTR_ASYNC_ENABLE__DATA__WRITE(src) \
6308 ((u_int32_t)(src)\
6310 #define HOST_INTF_INTR_ASYNC_ENABLE__DATA__MODIFY(dst, src) \
6312 ~0xffffffffU) | ((u_int32_t)(src) &\
6314 #define HOST_INTF_INTR_ASYNC_ENABLE__DATA__VERIFY(src) \
6315 (!(((u_int32_t)(src)\
6335 #define HOST_INTF_PCIE_PHY_RW__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
6336 #define HOST_INTF_PCIE_PHY_RW__DATA__WRITE(src) \
6337 ((u_int32_t)(src)\
6339 #define HOST_INTF_PCIE_PHY_RW__DATA__MODIFY(dst, src) \
6341 ~0xffffffffU) | ((u_int32_t)(src) &\
6343 #define HOST_INTF_PCIE_PHY_RW__DATA__VERIFY(src) \
6344 (!(((u_int32_t)(src)\
6364 #define HOST_INTF_PCIE_PHY_LOAD__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
6365 #define HOST_INTF_PCIE_PHY_LOAD__DATA__WRITE(src) \
6366 ((u_int32_t)(src)\
6368 #define HOST_INTF_PCIE_PHY_LOAD__DATA__MODIFY(dst, src) \
6370 ~0xffffffffU) | ((u_int32_t)(src) &\
6372 #define HOST_INTF_PCIE_PHY_LOAD__DATA__VERIFY(src) \
6373 (!(((u_int32_t)(src)\
6393 #define HOST_INTF_GPIO_OUT__OUT__READ(src) (u_int32_t)(src) & 0x0001ffffU
6394 #define HOST_INTF_GPIO_OUT__OUT__WRITE(src) ((u_int32_t)(src) & 0x0001ffffU)
6395 #define HOST_INTF_GPIO_OUT__OUT__MODIFY(dst, src) \
6397 ~0x0001ffffU) | ((u_int32_t)(src) &\
6399 #define HOST_INTF_GPIO_OUT__OUT__VERIFY(src) \
6400 (!(((u_int32_t)(src)\
6420 #define HOST_INTF_GPIO_IN__IN__READ(src) (u_int32_t)(src) & 0x0001ffffU
6438 #define HOST_INTF_GPIO_OE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
6439 #define HOST_INTF_GPIO_OE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
6440 #define HOST_INTF_GPIO_OE__DATA__MODIFY(dst, src) \
6442 ~0xffffffffU) | ((u_int32_t)(src) &\
6444 #define HOST_INTF_GPIO_OE__DATA__VERIFY(src) \
6445 (!(((u_int32_t)(src)\
6465 #define HOST_INTF_GPIO_OE1__DATA__READ(src) (u_int32_t)(src) & 0x00000003U
6466 #define HOST_INTF_GPIO_OE1__DATA__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
6467 #define HOST_INTF_GPIO_OE1__DATA__MODIFY(dst, src) \
6469 ~0x00000003U) | ((u_int32_t)(src) &\
6471 #define HOST_INTF_GPIO_OE1__DATA__VERIFY(src) \
6472 (!(((u_int32_t)(src)\
6492 #define HOST_INTF_GPIO_INTR_POLAR__DATA__READ(src) \
6493 (u_int32_t)(src)\
6495 #define HOST_INTF_GPIO_INTR_POLAR__DATA__WRITE(src) \
6496 ((u_int32_t)(src)\
6498 #define HOST_INTF_GPIO_INTR_POLAR__DATA__MODIFY(dst, src) \
6500 ~0x0001ffffU) | ((u_int32_t)(src) &\
6502 #define HOST_INTF_GPIO_INTR_POLAR__DATA__VERIFY(src) \
6503 (!(((u_int32_t)(src)\
6523 #define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__READ(src) \
6524 (u_int32_t)(src)\
6526 #define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__WRITE(src) \
6527 ((u_int32_t)(src)\
6529 #define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__MODIFY(dst, src) \
6531 ~0x00000001U) | ((u_int32_t)(src) &\
6533 #define HOST_INTF_GPIO_INPUT_VALUE__RST_TSF_VAL__VERIFY(src) \
6534 (!(((u_int32_t)(src)\
6547 #define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__READ(src) \
6548 (((u_int32_t)(src)\
6550 #define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__WRITE(src) \
6551 (((u_int32_t)(src)\
6553 #define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__MODIFY(dst, src) \
6555 ~0x00000002U) | (((u_int32_t)(src) <<\
6557 #define HOST_INTF_GPIO_INPUT_VALUE__RST_AZM_TS_VAL__VERIFY(src) \
6558 (!((((u_int32_t)(src)\
6571 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__READ(src) \
6572 (((u_int32_t)(src)\
6574 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__WRITE(src) \
6575 (((u_int32_t)(src)\
6577 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__MODIFY(dst, src) \
6579 ~0x00000004U) | (((u_int32_t)(src) <<\
6581 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_VAL__VERIFY(src) \
6582 (!((((u_int32_t)(src)\
6595 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__READ(src) \
6596 (((u_int32_t)(src)\
6598 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__WRITE(src) \
6599 (((u_int32_t)(src)\
6601 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__MODIFY(dst, src) \
6603 ~0x00000008U) | (((u_int32_t)(src) <<\
6605 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_VAL__VERIFY(src) \
6606 (!((((u_int32_t)(src)\
6619 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__READ(src) \
6620 (((u_int32_t)(src)\
6622 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__WRITE(src) \
6623 (((u_int32_t)(src)\
6625 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__MODIFY(dst, src) \
6627 ~0x00000010U) | (((u_int32_t)(src) <<\
6629 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_VAL__VERIFY(src) \
6630 (!((((u_int32_t)(src)\
6643 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__READ(src) \
6644 (((u_int32_t)(src)\
6646 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__WRITE(src) \
6647 (((u_int32_t)(src)\
6649 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__MODIFY(dst, src) \
6651 ~0x00000020U) | (((u_int32_t)(src) <<\
6653 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_VAL__VERIFY(src) \
6654 (!((((u_int32_t)(src)\
6667 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__READ(src) \
6668 (((u_int32_t)(src)\
6670 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__WRITE(src) \
6671 (((u_int32_t)(src)\
6673 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__MODIFY(dst, src) \
6675 ~0x00000040U) | (((u_int32_t)(src) <<\
6677 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_VAL__VERIFY(src) \
6678 (!((((u_int32_t)(src)\
6691 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__READ(src) \
6692 (((u_int32_t)(src)\
6694 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__WRITE(src) \
6695 (((u_int32_t)(src)\
6697 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__MODIFY(dst, src) \
6699 ~0x00000080U) | (((u_int32_t)(src) <<\
6701 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_VAL__VERIFY(src) \
6702 (!((((u_int32_t)(src)\
6715 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__READ(src) \
6716 (((u_int32_t)(src)\
6718 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__WRITE(src) \
6719 (((u_int32_t)(src)\
6721 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__MODIFY(dst, src) \
6723 ~0x00000100U) | (((u_int32_t)(src) <<\
6725 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_TSF_ENABLE__VERIFY(src) \
6726 (!((((u_int32_t)(src)\
6739 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__READ(src) \
6740 (((u_int32_t)(src)\
6742 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__WRITE(src) \
6743 (((u_int32_t)(src)\
6745 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__MODIFY(dst, src) \
6747 ~0x00000200U) | (((u_int32_t)(src) <<\
6749 #define HOST_INTF_GPIO_INPUT_VALUE__GPIO_RST_AZM_TS_ENABLE__VERIFY(src) \
6750 (!((((u_int32_t)(src)\
6763 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__READ(src) \
6764 (((u_int32_t)(src)\
6766 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__WRITE(src) \
6767 (((u_int32_t)(src)\
6769 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__MODIFY(dst, src) \
6771 ~0x00000400U) | (((u_int32_t)(src) <<\
6773 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_ENABLE__VERIFY(src) \
6774 (!((((u_int32_t)(src)\
6787 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__READ(src) \
6788 (((u_int32_t)(src)\
6790 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__WRITE(src) \
6791 (((u_int32_t)(src)\
6793 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__MODIFY(dst, src) \
6795 ~0x00000800U) | (((u_int32_t)(src) <<\
6797 #define HOST_INTF_GPIO_INPUT_VALUE__BT_FREQUENCY_ENABLE__VERIFY(src) \
6798 (!((((u_int32_t)(src)\
6811 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__READ(src) \
6812 (((u_int32_t)(src)\
6814 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__WRITE(src) \
6815 (((u_int32_t)(src)\
6817 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__MODIFY(dst, src) \
6819 ~0x00001000U) | (((u_int32_t)(src) <<\
6821 #define HOST_INTF_GPIO_INPUT_VALUE__BT_ACTIVE_ENABLE__VERIFY(src) \
6822 (!((((u_int32_t)(src)\
6835 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__READ(src) \
6836 (((u_int32_t)(src)\
6838 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__WRITE(src) \
6839 (((u_int32_t)(src)\
6841 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__MODIFY(dst, src) \
6843 ~0x00002000U) | (((u_int32_t)(src) <<\
6845 #define HOST_INTF_GPIO_INPUT_VALUE__ATT_BUT_ENABLE__VERIFY(src) \
6846 (!((((u_int32_t)(src)\
6859 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__READ(src) \
6860 (((u_int32_t)(src)\
6862 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__WRITE(src) \
6863 (((u_int32_t)(src)\
6865 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__MODIFY(dst, src) \
6867 ~0x00004000U) | (((u_int32_t)(src) <<\
6869 #define HOST_INTF_GPIO_INPUT_VALUE__CLK25_ENABLE__VERIFY(src) \
6870 (!((((u_int32_t)(src)\
6883 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__READ(src) \
6884 (((u_int32_t)(src)\
6886 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__WRITE(src) \
6887 (((u_int32_t)(src)\
6889 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__MODIFY(dst, src) \
6891 ~0x00008000U) | (((u_int32_t)(src) <<\
6893 #define HOST_INTF_GPIO_INPUT_VALUE__RFSILENT_BB_L_ENABLE__VERIFY(src) \
6894 (!((((u_int32_t)(src)\
6907 #define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__READ(src) \
6908 (((u_int32_t)(src)\
6910 #define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__WRITE(src) \
6911 (((u_int32_t)(src)\
6913 #define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__MODIFY(dst, src) \
6915 ~0x00010000U) | (((u_int32_t)(src) <<\
6917 #define HOST_INTF_GPIO_INPUT_VALUE__RTC_RESET_OVRD_ENABLE__VERIFY(src) \
6918 (!((((u_int32_t)(src)\
6931 #define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__READ(src) \
6932 (((u_int32_t)(src)\
6934 #define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__WRITE(src) \
6935 (((u_int32_t)(src)\
6937 #define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__MODIFY(dst, src) \
6939 ~0x00020000U) | (((u_int32_t)(src) <<\
6941 #define HOST_INTF_GPIO_INPUT_VALUE__DS_JTAG_DISABLE__VERIFY(src) \
6942 (!((((u_int32_t)(src)\
6955 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__READ(src) \
6956 (((u_int32_t)(src)\
6958 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__WRITE(src) \
6959 (((u_int32_t)(src)\
6961 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__MODIFY(dst, src) \
6963 ~0x00040000U) | (((u_int32_t)(src) <<\
6965 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_VAL__VERIFY(src) \
6966 (!((((u_int32_t)(src)\
6979 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__READ(src) \
6980 (((u_int32_t)(src)\
6982 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__WRITE(src) \
6983 (((u_int32_t)(src)\
6985 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__MODIFY(dst, src) \
6987 ~0x00080000U) | (((u_int32_t)(src) <<\
6989 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_2_ENABLE__VERIFY(src) \
6990 (!((((u_int32_t)(src)\
7003 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__READ(src) \
7004 (((u_int32_t)(src)\
7006 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__WRITE(src) \
7007 (((u_int32_t)(src)\
7009 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__MODIFY(dst, src) \
7011 ~0x00100000U) | (((u_int32_t)(src) <<\
7013 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_VAL__VERIFY(src) \
7014 (!((((u_int32_t)(src)\
7027 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__READ(src) \
7028 (((u_int32_t)(src)\
7030 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__WRITE(src) \
7031 (((u_int32_t)(src)\
7033 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__MODIFY(dst, src) \
7035 ~0x00200000U) | (((u_int32_t)(src) <<\
7037 #define HOST_INTF_GPIO_INPUT_VALUE__BT_PRIORITY_3_ENABLE__VERIFY(src) \
7038 (!((((u_int32_t)(src)\
7064 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__READ(src) \
7065 (u_int32_t)(src)\
7067 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__WRITE(src) \
7068 ((u_int32_t)(src)\
7070 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__MODIFY(dst, src) \
7072 ~0x0000000fU) | ((u_int32_t)(src) &\
7074 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_0__VERIFY(src) \
7075 (!(((u_int32_t)(src)\
7082 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__READ(src) \
7083 (((u_int32_t)(src)\
7085 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__WRITE(src) \
7086 (((u_int32_t)(src)\
7088 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__MODIFY(dst, src) \
7090 ~0x000000f0U) | (((u_int32_t)(src) <<\
7092 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_1__VERIFY(src) \
7093 (!((((u_int32_t)(src)\
7100 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__READ(src) \
7101 (((u_int32_t)(src)\
7103 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__WRITE(src) \
7104 (((u_int32_t)(src)\
7106 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__MODIFY(dst, src) \
7108 ~0x00000f00U) | (((u_int32_t)(src) <<\
7110 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_2__VERIFY(src) \
7111 (!((((u_int32_t)(src)\
7118 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__READ(src) \
7119 (((u_int32_t)(src)\
7121 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__WRITE(src) \
7122 (((u_int32_t)(src)\
7124 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__MODIFY(dst, src) \
7126 ~0x0000f000U) | (((u_int32_t)(src) <<\
7128 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_3__VERIFY(src) \
7129 (!((((u_int32_t)(src)\
7136 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__READ(src) \
7137 (((u_int32_t)(src)\
7139 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__WRITE(src) \
7140 (((u_int32_t)(src)\
7142 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__MODIFY(dst, src) \
7144 ~0x000f0000U) | (((u_int32_t)(src) <<\
7146 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_4__VERIFY(src) \
7147 (!((((u_int32_t)(src)\
7154 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__READ(src) \
7155 (((u_int32_t)(src)\
7157 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__WRITE(src) \
7158 (((u_int32_t)(src)\
7160 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__MODIFY(dst, src) \
7162 ~0x00f00000U) | (((u_int32_t)(src) <<\
7164 #define HOST_INTF_GPIO_INPUT_MUX1__SEL_5__VERIFY(src) \
7165 (!((((u_int32_t)(src)\
7185 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__READ(src) \
7186 (u_int32_t)(src)\
7188 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__WRITE(src) \
7189 ((u_int32_t)(src)\
7191 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__MODIFY(dst, src) \
7193 ~0x0000000fU) | ((u_int32_t)(src) &\
7195 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_6__VERIFY(src) \
7196 (!(((u_int32_t)(src)\
7203 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__READ(src) \
7204 (((u_int32_t)(src)\
7206 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__WRITE(src) \
7207 (((u_int32_t)(src)\
7209 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__MODIFY(dst, src) \
7211 ~0x000000f0U) | (((u_int32_t)(src) <<\
7213 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_7__VERIFY(src) \
7214 (!((((u_int32_t)(src)\
7221 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__READ(src) \
7222 (((u_int32_t)(src)\
7224 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__WRITE(src) \
7225 (((u_int32_t)(src)\
7227 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__MODIFY(dst, src) \
7229 ~0x00000f00U) | (((u_int32_t)(src) <<\
7231 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_8__VERIFY(src) \
7232 (!((((u_int32_t)(src)\
7239 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__READ(src) \
7240 (((u_int32_t)(src)\
7242 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__WRITE(src) \
7243 (((u_int32_t)(src)\
7245 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__MODIFY(dst, src) \
7247 ~0x0000f000U) | (((u_int32_t)(src) <<\
7249 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_9__VERIFY(src) \
7250 (!((((u_int32_t)(src)\
7257 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__READ(src) \
7258 (((u_int32_t)(src)\
7260 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__WRITE(src) \
7261 (((u_int32_t)(src)\
7263 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__MODIFY(dst, src) \
7265 ~0x000f0000U) | (((u_int32_t)(src) <<\
7267 #define HOST_INTF_GPIO_INPUT_MUX2__SEL_10__VERIFY(src) \
7268 (!((((u_int32_t)(src)\
7288 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__READ(src) \
7289 (u_int32_t)(src)\
7291 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__WRITE(src) \
7292 ((u_int32_t)(src)\
7294 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__MODIFY(dst, src) \
7296 ~0x0000001fU) | ((u_int32_t)(src) &\
7298 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_0__VERIFY(src) \
7299 (!(((u_int32_t)(src)\
7306 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__READ(src) \
7307 (((u_int32_t)(src)\
7309 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__WRITE(src) \
7310 (((u_int32_t)(src)\
7312 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__MODIFY(dst, src) \
7314 ~0x000003e0U) | (((u_int32_t)(src) <<\
7316 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_1__VERIFY(src) \
7317 (!((((u_int32_t)(src)\
7324 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__READ(src) \
7325 (((u_int32_t)(src)\
7327 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__WRITE(src) \
7328 (((u_int32_t)(src)\
7330 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__MODIFY(dst, src) \
7332 ~0x00007c00U) | (((u_int32_t)(src) <<\
7334 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_2__VERIFY(src) \
7335 (!((((u_int32_t)(src)\
7342 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__READ(src) \
7343 (((u_int32_t)(src)\
7345 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__WRITE(src) \
7346 (((u_int32_t)(src)\
7348 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__MODIFY(dst, src) \
7350 ~0x000f8000U) | (((u_int32_t)(src) <<\
7352 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_3__VERIFY(src) \
7353 (!((((u_int32_t)(src)\
7360 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__READ(src) \
7361 (((u_int32_t)(src)\
7363 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__WRITE(src) \
7364 (((u_int32_t)(src)\
7366 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__MODIFY(dst, src) \
7368 ~0x01f00000U) | (((u_int32_t)(src) <<\
7370 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_4__VERIFY(src) \
7371 (!((((u_int32_t)(src)\
7378 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__READ(src) \
7379 (((u_int32_t)(src)\
7381 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__WRITE(src) \
7382 (((u_int32_t)(src)\
7384 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__MODIFY(dst, src) \
7386 ~0x3e000000U) | (((u_int32_t)(src) <<\
7388 #define HOST_INTF_GPIO_OUTPUT_MUX1__SEL_5__VERIFY(src) \
7389 (!((((u_int32_t)(src)\
7409 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__READ(src) \
7410 (u_int32_t)(src)\
7412 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__WRITE(src) \
7413 ((u_int32_t)(src)\
7415 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__MODIFY(dst, src) \
7417 ~0x0000001fU) | ((u_int32_t)(src) &\
7419 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_6__VERIFY(src) \
7420 (!(((u_int32_t)(src)\
7427 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__READ(src) \
7428 (((u_int32_t)(src)\
7430 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__WRITE(src) \
7431 (((u_int32_t)(src)\
7433 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__MODIFY(dst, src) \
7435 ~0x000003e0U) | (((u_int32_t)(src) <<\
7437 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_7__VERIFY(src) \
7438 (!((((u_int32_t)(src)\
7445 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__READ(src) \
7446 (((u_int32_t)(src)\
7448 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__WRITE(src) \
7449 (((u_int32_t)(src)\
7451 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__MODIFY(dst, src) \
7453 ~0x00007c00U) | (((u_int32_t)(src) <<\
7455 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_8__VERIFY(src) \
7456 (!((((u_int32_t)(src)\
7463 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__READ(src) \
7464 (((u_int32_t)(src)\
7466 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__WRITE(src) \
7467 (((u_int32_t)(src)\
7469 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__MODIFY(dst, src) \
7471 ~0x000f8000U) | (((u_int32_t)(src) <<\
7473 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_9__VERIFY(src) \
7474 (!((((u_int32_t)(src)\
7481 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__READ(src) \
7482 (((u_int32_t)(src)\
7484 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__WRITE(src) \
7485 (((u_int32_t)(src)\
7487 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__MODIFY(dst, src) \
7489 ~0x01f00000U) | (((u_int32_t)(src) <<\
7491 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_10__VERIFY(src) \
7492 (!((((u_int32_t)(src)\
7499 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__READ(src) \
7500 (((u_int32_t)(src)\
7502 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__WRITE(src) \
7503 (((u_int32_t)(src)\
7505 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__MODIFY(dst, src) \
7507 ~0x3e000000U) | (((u_int32_t)(src) <<\
7509 #define HOST_INTF_GPIO_OUTPUT_MUX2__SEL_11__VERIFY(src) \
7510 (!((((u_int32_t)(src)\
7530 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__READ(src) \
7531 (u_int32_t)(src)\
7533 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__WRITE(src) \
7534 ((u_int32_t)(src)\
7536 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__MODIFY(dst, src) \
7538 ~0x0000001fU) | ((u_int32_t)(src) &\
7540 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_12__VERIFY(src) \
7541 (!(((u_int32_t)(src)\
7548 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__READ(src) \
7549 (((u_int32_t)(src)\
7551 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__WRITE(src) \
7552 (((u_int32_t)(src)\
7554 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__MODIFY(dst, src) \
7556 ~0x000003e0U) | (((u_int32_t)(src) <<\
7558 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_13__VERIFY(src) \
7559 (!((((u_int32_t)(src)\
7566 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__READ(src) \
7567 (((u_int32_t)(src)\
7569 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__WRITE(src) \
7570 (((u_int32_t)(src)\
7572 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__MODIFY(dst, src) \
7574 ~0x00007c00U) | (((u_int32_t)(src) <<\
7576 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_14__VERIFY(src) \
7577 (!((((u_int32_t)(src)\
7584 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__READ(src) \
7585 (((u_int32_t)(src)\
7587 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__WRITE(src) \
7588 (((u_int32_t)(src)\
7590 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__MODIFY(dst, src) \
7592 ~0x000f8000U) | (((u_int32_t)(src) <<\
7594 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_15__VERIFY(src) \
7595 (!((((u_int32_t)(src)\
7602 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__READ(src) \
7603 (((u_int32_t)(src)\
7605 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__WRITE(src) \
7606 (((u_int32_t)(src)\
7608 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__MODIFY(dst, src) \
7610 ~0x01f00000U) | (((u_int32_t)(src) <<\
7612 #define HOST_INTF_GPIO_OUTPUT_MUX3__SEL_16__VERIFY(src) \
7613 (!((((u_int32_t)(src)\
7633 #define HOST_INTF_GPIO_INPUT_STATE__ATT_LED__READ(src) \
7634 (u_int32_t)(src)\
7647 #define HOST_INTF_GPIO_INPUT_STATE__PWR_LED__READ(src) \
7648 (((u_int32_t)(src)\
7661 #define HOST_INTF_GPIO_INPUT_STATE__WAKE_N__READ(src) \
7662 (((u_int32_t)(src)\
7675 #define HOST_INTF_GPIO_INPUT_STATE__LED_NETWORK_EN__READ(src) \
7676 (((u_int32_t)(src)\
7689 #define HOST_INTF_GPIO_INPUT_STATE__LED_POWER_EN__READ(src) \
7690 (((u_int32_t)(src)\
7703 #define HOST_INTF_GPIO_INPUT_STATE__RX_CLEAR_EXTERNAL__READ(src) \
7704 (((u_int32_t)(src)\
7717 #define HOST_INTF_GPIO_INPUT_STATE__TX_FRAME__READ(src) \
7718 (((u_int32_t)(src)\
7731 #define HOST_INTF_GPIO_INPUT_STATE__BB_RADIO_XLNAON__READ(src) \
7732 (((u_int32_t)(src)\
7757 #define HOST_INTF_SPARE__SUPER_CONDOR_L1__READ(src) \
7758 (u_int32_t)(src)\
7760 #define HOST_INTF_SPARE__SUPER_CONDOR_L1__WRITE(src) \
7761 ((u_int32_t)(src)\
7763 #define HOST_INTF_SPARE__SUPER_CONDOR_L1__MODIFY(dst, src) \
7765 ~0xffffffffU) | ((u_int32_t)(src) &\
7767 #define HOST_INTF_SPARE__SUPER_CONDOR_L1__VERIFY(src) \
7768 (!(((u_int32_t)(src)\
7788 #define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__READ(src) \
7789 (u_int32_t)(src)\
7791 #define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__WRITE(src) \
7792 ((u_int32_t)(src)\
7794 #define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__MODIFY(dst, src) \
7796 ~0x00000001U) | ((u_int32_t)(src) &\
7798 #define HOST_INTF_PCIE_CORE_RST_EN__TRAINING_RST_EN__VERIFY(src) \
7799 (!(((u_int32_t)(src)\
7812 #define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__READ(src) \
7813 (((u_int32_t)(src)\
7815 #define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__WRITE(src) \
7816 (((u_int32_t)(src)\
7818 #define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__MODIFY(dst, src) \
7820 ~0x00000002U) | (((u_int32_t)(src) <<\
7822 #define HOST_INTF_PCIE_CORE_RST_EN__XMLH_LINK_RST_EN__VERIFY(src) \
7823 (!((((u_int32_t)(src)\
7836 #define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__READ(src) \
7837 (((u_int32_t)(src)\
7839 #define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__WRITE(src) \
7840 (((u_int32_t)(src)\
7842 #define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__MODIFY(dst, src) \
7844 ~0x00000004U) | (((u_int32_t)(src) <<\
7846 #define HOST_INTF_PCIE_CORE_RST_EN__RDLH_LINK_RST_EN__VERIFY(src) \
7847 (!((((u_int32_t)(src)\
7860 #define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__READ(src) \
7861 (((u_int32_t)(src)\
7863 #define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__WRITE(src) \
7864 (((u_int32_t)(src)\
7866 #define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__MODIFY(dst, src) \
7868 ~0x00000008U) | (((u_int32_t)(src) <<\
7870 #define HOST_INTF_PCIE_CORE_RST_EN__LINK_REQ_RST_EN__VERIFY(src) \
7871 (!((((u_int32_t)(src)\
7897 #define HOST_INTF_CLKRUN__FORCE__READ(src) (u_int32_t)(src) & 0x00000001U
7898 #define HOST_INTF_CLKRUN__FORCE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
7899 #define HOST_INTF_CLKRUN__FORCE__MODIFY(dst, src) \
7901 ~0x00000001U) | ((u_int32_t)(src) &\
7903 #define HOST_INTF_CLKRUN__FORCE__VERIFY(src) \
7904 (!(((u_int32_t)(src)\
7917 #define HOST_INTF_CLKRUN__CNT__READ(src) \
7918 (((u_int32_t)(src)\
7920 #define HOST_INTF_CLKRUN__CNT__WRITE(src) \
7921 (((u_int32_t)(src)\
7923 #define HOST_INTF_CLKRUN__CNT__MODIFY(dst, src) \
7925 ~0xfffffffeU) | (((u_int32_t)(src) <<\
7927 #define HOST_INTF_CLKRUN__CNT__VERIFY(src) \
7928 (!((((u_int32_t)(src)\
7948 #define HOST_INTF_EEPROM_STS__RD_DATA__READ(src) (u_int32_t)(src) & 0x0000ffffU
7954 #define HOST_INTF_EEPROM_STS__BUSY__READ(src) \
7955 (((u_int32_t)(src)\
7968 #define HOST_INTF_EEPROM_STS__BUSY_ACCESS__READ(src) \
7969 (((u_int32_t)(src)\
7982 #define HOST_INTF_EEPROM_STS__MASK_ACCESS__READ(src) \
7983 (((u_int32_t)(src)\
8008 #define HOST_INTF_OBS_CTRL__OBS_SEL__READ(src) (u_int32_t)(src) & 0x0000000fU
8009 #define HOST_INTF_OBS_CTRL__OBS_SEL__WRITE(src) \
8010 ((u_int32_t)(src)\
8012 #define HOST_INTF_OBS_CTRL__OBS_SEL__MODIFY(dst, src) \
8014 ~0x0000000fU) | ((u_int32_t)(src) &\
8016 #define HOST_INTF_OBS_CTRL__OBS_SEL__VERIFY(src) \
8017 (!(((u_int32_t)(src)\
8024 #define HOST_INTF_OBS_CTRL__ANT_SEL__READ(src) \
8025 (((u_int32_t)(src)\
8027 #define HOST_INTF_OBS_CTRL__ANT_SEL__WRITE(src) \
8028 (((u_int32_t)(src)\
8030 #define HOST_INTF_OBS_CTRL__ANT_SEL__MODIFY(dst, src) \
8032 ~0x00000030U) | (((u_int32_t)(src) <<\
8034 #define HOST_INTF_OBS_CTRL__ANT_SEL__VERIFY(src) \
8035 (!((((u_int32_t)(src)\
8042 #define HOST_INTF_OBS_CTRL__OBS_MODE__READ(src) \
8043 (((u_int32_t)(src)\
8045 #define HOST_INTF_OBS_CTRL__OBS_MODE__WRITE(src) \
8046 (((u_int32_t)(src)\
8048 #define HOST_INTF_OBS_CTRL__OBS_MODE__MODIFY(dst, src) \
8050 ~0x000000c0U) | (((u_int32_t)(src) <<\
8052 #define HOST_INTF_OBS_CTRL__OBS_MODE__VERIFY(src) \
8053 (!((((u_int32_t)(src)\
8073 #define HOST_INTF_RFSILENT__FORCE__READ(src) (u_int32_t)(src) & 0x00000001U
8074 #define HOST_INTF_RFSILENT__FORCE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
8075 #define HOST_INTF_RFSILENT__FORCE__MODIFY(dst, src) \
8077 ~0x00000001U) | ((u_int32_t)(src) &\
8079 #define HOST_INTF_RFSILENT__FORCE__VERIFY(src) \
8080 (!(((u_int32_t)(src)\
8093 #define HOST_INTF_RFSILENT__INVERT__READ(src) \
8094 (((u_int32_t)(src)\
8096 #define HOST_INTF_RFSILENT__INVERT__WRITE(src) \
8097 (((u_int32_t)(src)\
8099 #define HOST_INTF_RFSILENT__INVERT__MODIFY(dst, src) \
8101 ~0x00000002U) | (((u_int32_t)(src) <<\
8103 #define HOST_INTF_RFSILENT__INVERT__VERIFY(src) \
8104 (!((((u_int32_t)(src)\
8117 #define HOST_INTF_RFSILENT__RTC_RESET_INVERT__READ(src) \
8118 (((u_int32_t)(src)\
8120 #define HOST_INTF_RFSILENT__RTC_RESET_INVERT__WRITE(src) \
8121 (((u_int32_t)(src)\
8123 #define HOST_INTF_RFSILENT__RTC_RESET_INVERT__MODIFY(dst, src) \
8125 ~0x00000004U) | (((u_int32_t)(src) <<\
8127 #define HOST_INTF_RFSILENT__RTC_RESET_INVERT__VERIFY(src) \
8128 (!((((u_int32_t)(src)\
8154 #define HOST_INTF_GPIO_PDPU__INT__READ(src) (u_int32_t)(src) & 0xffffffffU
8155 #define HOST_INTF_GPIO_PDPU__INT__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
8156 #define HOST_INTF_GPIO_PDPU__INT__MODIFY(dst, src) \
8158 ~0xffffffffU) | ((u_int32_t)(src) &\
8160 #define HOST_INTF_GPIO_PDPU__INT__VERIFY(src) \
8161 (!(((u_int32_t)(src)\
8181 #define HOST_INTF_GPIO_PDPU1__INT__READ(src) (u_int32_t)(src) & 0x00000003U
8182 #define HOST_INTF_GPIO_PDPU1__INT__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
8183 #define HOST_INTF_GPIO_PDPU1__INT__MODIFY(dst, src) \
8185 ~0x00000003U) | ((u_int32_t)(src) &\
8187 #define HOST_INTF_GPIO_PDPU1__INT__VERIFY(src) \
8188 (!(((u_int32_t)(src)\
8208 #define HOST_INTF_GPIO_DS__INT__READ(src) (u_int32_t)(src) & 0xffffffffU
8209 #define HOST_INTF_GPIO_DS__INT__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
8210 #define HOST_INTF_GPIO_DS__INT__MODIFY(dst, src) \
8212 ~0xffffffffU) | ((u_int32_t)(src) &\
8214 #define HOST_INTF_GPIO_DS__INT__VERIFY(src) \
8215 (!(((u_int32_t)(src)\
8235 #define HOST_INTF_GPIO_DS1__INT__READ(src) (u_int32_t)(src) & 0x00000003U
8236 #define HOST_INTF_GPIO_DS1__INT__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
8237 #define HOST_INTF_GPIO_DS1__INT__MODIFY(dst, src) \
8239 ~0x00000003U) | ((u_int32_t)(src) &\
8241 #define HOST_INTF_GPIO_DS1__INT__VERIFY(src) \
8242 (!(((u_int32_t)(src)\
8262 #define HOST_INTF_MISC__AT_SPEED_EN__READ(src) (u_int32_t)(src) & 0x00000001U
8263 #define HOST_INTF_MISC__AT_SPEED_EN__WRITE(src) \
8264 ((u_int32_t)(src)\
8266 #define HOST_INTF_MISC__AT_SPEED_EN__MODIFY(dst, src) \
8268 ~0x00000001U) | ((u_int32_t)(src) &\
8270 #define HOST_INTF_MISC__AT_SPEED_EN__VERIFY(src) \
8271 (!(((u_int32_t)(src)\
8284 #define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__READ(src) \
8285 (((u_int32_t)(src)\
8287 #define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__WRITE(src) \
8288 (((u_int32_t)(src)\
8290 #define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__MODIFY(dst, src) \
8292 ~0x00000002U) | (((u_int32_t)(src) <<\
8294 #define HOST_INTF_MISC__OTP_DEBUG_MODE_SEL__VERIFY(src) \
8295 (!((((u_int32_t)(src)\
8308 #define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__READ(src) \
8309 (((u_int32_t)(src)\
8311 #define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__WRITE(src) \
8312 (((u_int32_t)(src)\
8314 #define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__MODIFY(dst, src) \
8316 ~0x00000004U) | (((u_int32_t)(src) <<\
8318 #define HOST_INTF_MISC__OTP_DEBUG_EFUSE_MEM_SEL__VERIFY(src) \
8319 (!((((u_int32_t)(src)\
8345 #define HOST_INTF_PCIE_MSI__INT_EN__READ(src) (u_int32_t)(src) & 0x00000001U
8346 #define HOST_INTF_PCIE_MSI__INT_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
8347 #define HOST_INTF_PCIE_MSI__INT_EN__MODIFY(dst, src) \
8349 ~0x00000001U) | ((u_int32_t)(src) &\
8351 #define HOST_INTF_PCIE_MSI__INT_EN__VERIFY(src) \
8352 (!(((u_int32_t)(src)\
8365 #define HOST_INTF_PCIE_MSI__MULTI_MSI__READ(src) \
8366 (((u_int32_t)(src)\
8368 #define HOST_INTF_PCIE_MSI__MULTI_MSI__WRITE(src) \
8369 (((u_int32_t)(src)\
8371 #define HOST_INTF_PCIE_MSI__MULTI_MSI__MODIFY(dst, src) \
8373 ~0x000001feU) | (((u_int32_t)(src) <<\
8375 #define HOST_INTF_PCIE_MSI__MULTI_MSI__VERIFY(src) \
8376 (!((((u_int32_t)(src)\
8383 #define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__READ(src) \
8384 (((u_int32_t)(src)\
8386 #define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__WRITE(src) \
8387 (((u_int32_t)(src)\
8389 #define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__MODIFY(dst, src) \
8391 ~0x01fffe00U) | (((u_int32_t)(src) <<\
8393 #define HOST_INTF_PCIE_MSI__INT_PENDING_ADDR__VERIFY(src) \
8394 (!((((u_int32_t)(src)\
8401 #define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__READ(src) \
8402 (((u_int32_t)(src)\
8404 #define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__WRITE(src) \
8405 (((u_int32_t)(src)\
8407 #define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__MODIFY(dst, src) \
8409 ~0x02000000U) | (((u_int32_t)(src) <<\
8411 #define HOST_INTF_PCIE_MSI__HW_DBI_WR_EN__VERIFY(src) \
8412 (!((((u_int32_t)(src)\
8425 #define HOST_INTF_PCIE_MSI__IRQ_PENDING__READ(src) \
8426 (((u_int32_t)(src)\
8446 #define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__READ(src) \
8447 (u_int32_t)(src)\
8449 #define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__WRITE(src) \
8450 ((u_int32_t)(src)\
8452 #define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__MODIFY(dst, src) \
8454 ~0x00ffffffU) | ((u_int32_t)(src) &\
8456 #define HOST_INTF_PCIE_PHY_LATENCY_NFTS_ADJ__DATA__VERIFY(src) \
8457 (!(((u_int32_t)(src)\
8477 #define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__READ(src) \
8478 (u_int32_t)(src)\
8480 #define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__WRITE(src) \
8481 ((u_int32_t)(src)\
8483 #define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__MODIFY(dst, src) \
8485 ~0x00000003U) | ((u_int32_t)(src) &\
8487 #define HOST_INTF_MAC_TDMA_CCA_CNTL__DATA__VERIFY(src) \
8488 (!(((u_int32_t)(src)\
8508 #define HOST_INTF_MAC_TXAPSYNC__ENABLE__READ(src) \
8509 (u_int32_t)(src)\
8511 #define HOST_INTF_MAC_TXAPSYNC__ENABLE__WRITE(src) \
8512 ((u_int32_t)(src)\
8514 #define HOST_INTF_MAC_TXAPSYNC__ENABLE__MODIFY(dst, src) \
8516 ~0x00000001U) | ((u_int32_t)(src) &\
8518 #define HOST_INTF_MAC_TXAPSYNC__ENABLE__VERIFY(src) \
8519 (!(((u_int32_t)(src)\
8545 #define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__READ(src) \
8546 (u_int32_t)(src)\
8548 #define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__WRITE(src) \
8549 ((u_int32_t)(src)\
8551 #define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__MODIFY(dst, src) \
8553 ~0x0000ffffU) | ((u_int32_t)(src) &\
8555 #define HOST_INTF_MAC_TXSYNC_INITIAL_SYNC_TMR__DATA__VERIFY(src) \
8556 (!(((u_int32_t)(src)\
8576 #define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__READ(src) \
8577 (u_int32_t)(src)\
8579 #define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__WRITE(src) \
8580 ((u_int32_t)(src)\
8582 #define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__MODIFY(dst, src) \
8584 ~0x00000007U) | ((u_int32_t)(src) &\
8586 #define HOST_INTF_INTR_PRIORITY_SYNC_CAUSE__DATA__VERIFY(src) \
8587 (!(((u_int32_t)(src)\
8607 #define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__READ(src) \
8608 (u_int32_t)(src)\
8610 #define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__WRITE(src) \
8611 ((u_int32_t)(src)\
8613 #define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__MODIFY(dst, src) \
8615 ~0x00000007U) | ((u_int32_t)(src) &\
8617 #define HOST_INTF_INTR_PRIORITY_SYNC_ENABLE__DATA__VERIFY(src) \
8618 (!(((u_int32_t)(src)\
8638 #define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__READ(src) \
8639 (u_int32_t)(src)\
8641 #define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__WRITE(src) \
8642 ((u_int32_t)(src)\
8644 #define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__MODIFY(dst, src) \
8646 ~0x00000007U) | ((u_int32_t)(src) &\
8648 #define HOST_INTF_INTR_PRIORITY_ASYNC_MASK__DATA__VERIFY(src) \
8649 (!(((u_int32_t)(src)\
8669 #define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__READ(src) \
8670 (u_int32_t)(src)\
8672 #define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__WRITE(src) \
8673 ((u_int32_t)(src)\
8675 #define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__MODIFY(dst, src) \
8677 ~0x00000007U) | ((u_int32_t)(src) &\
8679 #define HOST_INTF_INTR_PRIORITY_SYNC_MASK__DATA__VERIFY(src) \
8680 (!(((u_int32_t)(src)\
8700 #define HOST_INTF_INTR_PRIORITY_ASYNC_CAUSE__DATA__READ(src) \
8701 (u_int32_t)(src)\
8720 #define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__READ(src) \
8721 (u_int32_t)(src)\
8723 #define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__WRITE(src) \
8724 ((u_int32_t)(src)\
8726 #define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__MODIFY(dst, src) \
8728 ~0x00000007U) | ((u_int32_t)(src) &\
8730 #define HOST_INTF_INTR_PRIORITY_ASYNC_ENABLE__DATA__VERIFY(src) \
8731 (!(((u_int32_t)(src)\
8751 #define HOST_INTF_OTP__BOND_OPTION__READ(src) (u_int32_t)(src) & 0xffffffffU
8769 #define PCIE_CO_ERR_CTR0__RCVD_ERR__READ(src) (u_int32_t)(src) & 0x000000ffU
8770 #define PCIE_CO_ERR_CTR0__RCVD_ERR__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
8771 #define PCIE_CO_ERR_CTR0__RCVD_ERR__MODIFY(dst, src) \
8773 ~0x000000ffU) | ((u_int32_t)(src) &\
8775 #define PCIE_CO_ERR_CTR0__RCVD_ERR__VERIFY(src) \
8776 (!(((u_int32_t)(src)\
8783 #define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__READ(src) \
8784 (((u_int32_t)(src)\
8786 #define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__WRITE(src) \
8787 (((u_int32_t)(src)\
8789 #define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__MODIFY(dst, src) \
8791 ~0x0000ff00U) | (((u_int32_t)(src) <<\
8793 #define PCIE_CO_ERR_CTR0__BAD_TLP_ERR__VERIFY(src) \
8794 (!((((u_int32_t)(src)\
8801 #define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__READ(src) \
8802 (((u_int32_t)(src)\
8804 #define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__WRITE(src) \
8805 (((u_int32_t)(src)\
8807 #define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__MODIFY(dst, src) \
8809 ~0x00ff0000U) | (((u_int32_t)(src) <<\
8811 #define PCIE_CO_ERR_CTR0__BAD_DLLP_ERR__VERIFY(src) \
8812 (!((((u_int32_t)(src)\
8832 #define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__READ(src) (u_int32_t)(src) & 0x000000ffU
8833 #define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__WRITE(src) \
8834 ((u_int32_t)(src)\
8836 #define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__MODIFY(dst, src) \
8838 ~0x000000ffU) | ((u_int32_t)(src) &\
8840 #define PCIE_CO_ERR_CTR1__RPLY_TO_ERR__VERIFY(src) \
8841 (!(((u_int32_t)(src)\
8848 #define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__READ(src) \
8849 (((u_int32_t)(src)\
8851 #define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__WRITE(src) \
8852 (((u_int32_t)(src)\
8854 #define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__MODIFY(dst, src) \
8856 ~0x0000ff00U) | (((u_int32_t)(src) <<\
8858 #define PCIE_CO_ERR_CTR1__RPLY_NUM_RO_ERR__VERIFY(src) \
8859 (!((((u_int32_t)(src)\
8879 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__READ(src) \
8880 (u_int32_t)(src)\
8882 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__WRITE(src) \
8883 ((u_int32_t)(src)\
8885 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__MODIFY(dst, src) \
8887 ~0x00000001U) | ((u_int32_t)(src) &\
8889 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_RUN__VERIFY(src) \
8890 (!(((u_int32_t)(src)\
8903 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__READ(src) \
8904 (((u_int32_t)(src)\
8906 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__WRITE(src) \
8907 (((u_int32_t)(src)\
8909 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \
8911 ~0x00000002U) | (((u_int32_t)(src) <<\
8913 #define PCIE_CO_ERR_CTR_CTRL__RCVD_ERR_CTR_AUTO_STOP__VERIFY(src) \
8914 (!((((u_int32_t)(src)\
8927 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__READ(src) \
8928 (((u_int32_t)(src)\
8930 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__WRITE(src) \
8931 (((u_int32_t)(src)\
8933 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__MODIFY(dst, src) \
8935 ~0x00000004U) | (((u_int32_t)(src) <<\
8937 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_RUN__VERIFY(src) \
8938 (!((((u_int32_t)(src)\
8951 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__READ(src) \
8952 (((u_int32_t)(src)\
8954 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__WRITE(src) \
8955 (((u_int32_t)(src)\
8957 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \
8959 ~0x00000008U) | (((u_int32_t)(src) <<\
8961 #define PCIE_CO_ERR_CTR_CTRL__BAD_TLP_ERR_CTR_AUTO_STOP__VERIFY(src) \
8962 (!((((u_int32_t)(src)\
8975 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__READ(src) \
8976 (((u_int32_t)(src)\
8978 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__WRITE(src) \
8979 (((u_int32_t)(src)\
8981 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__MODIFY(dst, src) \
8983 ~0x00000010U) | (((u_int32_t)(src) <<\
8985 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_RUN__VERIFY(src) \
8986 (!((((u_int32_t)(src)\
8999 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__READ(src) \
9000 (((u_int32_t)(src)\
9002 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__WRITE(src) \
9003 (((u_int32_t)(src)\
9005 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \
9007 ~0x00000020U) | (((u_int32_t)(src) <<\
9009 #define PCIE_CO_ERR_CTR_CTRL__BAD_DLLP_ERR_CTR_AUTO_STOP__VERIFY(src) \
9010 (!((((u_int32_t)(src)\
9023 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__READ(src) \
9024 (((u_int32_t)(src)\
9026 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__WRITE(src) \
9027 (((u_int32_t)(src)\
9029 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__MODIFY(dst, src) \
9031 ~0x00000040U) | (((u_int32_t)(src) <<\
9033 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_RUN__VERIFY(src) \
9034 (!((((u_int32_t)(src)\
9047 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__READ(src) \
9048 (((u_int32_t)(src)\
9050 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__WRITE(src) \
9051 (((u_int32_t)(src)\
9053 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \
9055 ~0x00000080U) | (((u_int32_t)(src) <<\
9057 #define PCIE_CO_ERR_CTR_CTRL__RPLY_TO_ERR_CTR_AUTO_STOP__VERIFY(src) \
9058 (!((((u_int32_t)(src)\
9071 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__READ(src) \
9072 (((u_int32_t)(src)\
9074 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__WRITE(src) \
9075 (((u_int32_t)(src)\
9077 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__MODIFY(dst, src) \
9079 ~0x00000100U) | (((u_int32_t)(src) <<\
9081 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_RUN__VERIFY(src) \
9082 (!((((u_int32_t)(src)\
9095 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__READ(src) \
9096 (((u_int32_t)(src)\
9098 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__WRITE(src) \
9099 (((u_int32_t)(src)\
9101 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__MODIFY(dst, src) \
9103 ~0x00000200U) | (((u_int32_t)(src) <<\
9105 #define PCIE_CO_ERR_CTR_CTRL__RPLY_NUM_RO_ERR_CTR_AUTO_STOP__VERIFY(src) \
9106 (!((((u_int32_t)(src)\
9132 #define FPGA_PHY_LAYER_REVID__FPGA_RADIO_FEATURE_INDEX__READ(src) \
9133 (u_int32_t)(src)\
9140 #define FPGA_PHY_LAYER_REVID__FPGA_BASEBAND_FEATURE_INDEX__READ(src) \
9141 (((u_int32_t)(src)\
9160 #define FPGA_LINK_LAYER_REVID__FPGA_MAC_FEATURE_INDEX__READ(src) \
9161 (u_int32_t)(src)\
9168 #define FPGA_LINK_LAYER_REVID__FPGA_SOC_FEATURE_INDEX__READ(src) \
9169 (((u_int32_t)(src)\
9188 #define FPGA_REG1__SPARE_REG1_BIT0__READ(src) (u_int32_t)(src) & 0x00000001U
9189 #define FPGA_REG1__SPARE_REG1_BIT0__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
9190 #define FPGA_REG1__SPARE_REG1_BIT0__MODIFY(dst, src) \
9192 ~0x00000001U) | ((u_int32_t)(src) &\
9194 #define FPGA_REG1__SPARE_REG1_BIT0__VERIFY(src) \
9195 (!(((u_int32_t)(src)\
9208 #define FPGA_REG1__MASK_RX_RF__READ(src) \
9209 (((u_int32_t)(src)\
9211 #define FPGA_REG1__MASK_RX_RF__WRITE(src) \
9212 (((u_int32_t)(src)\
9214 #define FPGA_REG1__MASK_RX_RF__MODIFY(dst, src) \
9216 ~0x00000002U) | (((u_int32_t)(src) <<\
9218 #define FPGA_REG1__MASK_RX_RF__VERIFY(src) \
9219 (!((((u_int32_t)(src)\
9232 #define FPGA_REG1__DCM_RELEASE__READ(src) \
9233 (((u_int32_t)(src)\
9246 #define FPGA_REG1__SPARE0__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
9247 #define FPGA_REG1__SPARE0__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U)
9248 #define FPGA_REG1__SPARE0__MODIFY(dst, src) \
9250 ~0x00000008U) | (((u_int32_t)(src) <<\
9252 #define FPGA_REG1__SPARE0__VERIFY(src) \
9253 (!((((u_int32_t)(src)\
9266 #define FPGA_REG1__EMULATION_CLOCK_RATIO__READ(src) \
9267 (((u_int32_t)(src)\
9269 #define FPGA_REG1__EMULATION_CLOCK_RATIO__WRITE(src) \
9270 (((u_int32_t)(src)\
9272 #define FPGA_REG1__EMULATION_CLOCK_RATIO__MODIFY(dst, src) \
9274 ~0x000000f0U) | (((u_int32_t)(src) <<\
9276 #define FPGA_REG1__EMULATION_CLOCK_RATIO__VERIFY(src) \
9277 (!((((u_int32_t)(src)\
9284 #define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__READ(src) \
9285 (((u_int32_t)(src)\
9287 #define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__WRITE(src) \
9288 (((u_int32_t)(src)\
9290 #define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__MODIFY(dst, src) \
9292 ~0x00000300U) | (((u_int32_t)(src) <<\
9294 #define FPGA_REG1__LONG_SHIFT_CHAIN_OVERRIDE_INDEX__VERIFY(src) \
9295 (!((((u_int32_t)(src)\
9302 #define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__READ(src) \
9303 (((u_int32_t)(src)\
9305 #define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__WRITE(src) \
9306 (((u_int32_t)(src)\
9308 #define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__MODIFY(dst, src) \
9310 ~0x00000400U) | (((u_int32_t)(src) <<\
9312 #define FPGA_REG1__ENABLE_LONG_SHIFT_CHAIN_OVERRIDE_INDEX__VERIFY(src) \
9313 (!((((u_int32_t)(src)\
9326 #define FPGA_REG1__SPARE1__READ(src) (((u_int32_t)(src) & 0xfffff800U) >> 11)
9327 #define FPGA_REG1__SPARE1__WRITE(src) (((u_int32_t)(src) << 11) & 0xfffff800U)
9328 #define FPGA_REG1__SPARE1__MODIFY(dst, src) \
9330 ~0xfffff800U) | (((u_int32_t)(src) <<\
9332 #define FPGA_REG1__SPARE1__VERIFY(src) \
9333 (!((((u_int32_t)(src)\
9353 #define FPGA_REG2__RXPIPEIFERRINJEN__READ(src) (u_int32_t)(src) & 0x00000001U
9354 #define FPGA_REG2__RXPIPEIFERRINJEN__WRITE(src) \
9355 ((u_int32_t)(src)\
9357 #define FPGA_REG2__RXPIPEIFERRINJEN__MODIFY(dst, src) \
9359 ~0x00000001U) | ((u_int32_t)(src) &\
9361 #define FPGA_REG2__RXPIPEIFERRINJEN__VERIFY(src) \
9362 (!(((u_int32_t)(src)\
9375 #define FPGA_REG2__TXPIPEIFERRINJEN__READ(src) \
9376 (((u_int32_t)(src)\
9378 #define FPGA_REG2__TXPIPEIFERRINJEN__WRITE(src) \
9379 (((u_int32_t)(src)\
9381 #define FPGA_REG2__TXPIPEIFERRINJEN__MODIFY(dst, src) \
9383 ~0x00000002U) | (((u_int32_t)(src) <<\
9385 #define FPGA_REG2__TXPIPEIFERRINJEN__VERIFY(src) \
9386 (!((((u_int32_t)(src)\
9399 #define FPGA_REG2__RXPIPEIFINJERRINDATAK__READ(src) \
9400 (((u_int32_t)(src)\
9402 #define FPGA_REG2__RXPIPEIFINJERRINDATAK__WRITE(src) \
9403 (((u_int32_t)(src)\
9405 #define FPGA_REG2__RXPIPEIFINJERRINDATAK__MODIFY(dst, src) \
9407 ~0x00000004U) | (((u_int32_t)(src) <<\
9409 #define FPGA_REG2__RXPIPEIFINJERRINDATAK__VERIFY(src) \
9410 (!((((u_int32_t)(src)\
9423 #define FPGA_REG2__TXPIPEIFINJERRINDATAK__READ(src) \
9424 (((u_int32_t)(src)\
9426 #define FPGA_REG2__TXPIPEIFINJERRINDATAK__WRITE(src) \
9427 (((u_int32_t)(src)\
9429 #define FPGA_REG2__TXPIPEIFINJERRINDATAK__MODIFY(dst, src) \
9431 ~0x00000008U) | (((u_int32_t)(src) <<\
9433 #define FPGA_REG2__TXPIPEIFINJERRINDATAK__VERIFY(src) \
9434 (!((((u_int32_t)(src)\
9447 #define FPGA_REG2__DUMMY_ERROR_INJECTION__READ(src) \
9448 (((u_int32_t)(src)\
9450 #define FPGA_REG2__DUMMY_ERROR_INJECTION__WRITE(src) \
9451 (((u_int32_t)(src)\
9453 #define FPGA_REG2__DUMMY_ERROR_INJECTION__MODIFY(dst, src) \
9455 ~0xfffffff0U) | (((u_int32_t)(src) <<\
9457 #define FPGA_REG2__DUMMY_ERROR_INJECTION__VERIFY(src) \
9458 (!((((u_int32_t)(src)\
9478 #define FPGA_REG3__FPGA_CHANGELIST__READ(src) (u_int32_t)(src) & 0xffffffffU
9496 #define FPGA_REG4__RADIO_0_TCK__READ(src) (u_int32_t)(src) & 0x00000001U
9497 #define FPGA_REG4__RADIO_0_TCK__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
9498 #define FPGA_REG4__RADIO_0_TCK__MODIFY(dst, src) \
9500 ~0x00000001U) | ((u_int32_t)(src) &\
9502 #define FPGA_REG4__RADIO_0_TCK__VERIFY(src) \
9503 (!(((u_int32_t)(src)\
9516 #define FPGA_REG4__RADIO_0_TDI__READ(src) \
9517 (((u_int32_t)(src)\
9519 #define FPGA_REG4__RADIO_0_TDI__WRITE(src) \
9520 (((u_int32_t)(src)\
9522 #define FPGA_REG4__RADIO_0_TDI__MODIFY(dst, src) \
9524 ~0x00000002U) | (((u_int32_t)(src) <<\
9526 #define FPGA_REG4__RADIO_0_TDI__VERIFY(src) \
9527 (!((((u_int32_t)(src)\
9540 #define FPGA_REG4__RADIO_0_TMS__READ(src) \
9541 (((u_int32_t)(src)\
9543 #define FPGA_REG4__RADIO_0_TMS__WRITE(src) \
9544 (((u_int32_t)(src)\
9546 #define FPGA_REG4__RADIO_0_TMS__MODIFY(dst, src) \
9548 ~0x00000004U) | (((u_int32_t)(src) <<\
9550 #define FPGA_REG4__RADIO_0_TMS__VERIFY(src) \
9551 (!((((u_int32_t)(src)\
9564 #define FPGA_REG4__RADIO_0_TDO__READ(src) \
9565 (((u_int32_t)(src)\
9578 #define FPGA_REG4__RADIO_1_TCK__READ(src) \
9579 (((u_int32_t)(src)\
9581 #define FPGA_REG4__RADIO_1_TCK__WRITE(src) \
9582 (((u_int32_t)(src)\
9584 #define FPGA_REG4__RADIO_1_TCK__MODIFY(dst, src) \
9586 ~0x00000010U) | (((u_int32_t)(src) <<\
9588 #define FPGA_REG4__RADIO_1_TCK__VERIFY(src) \
9589 (!((((u_int32_t)(src)\
9602 #define FPGA_REG4__RADIO_1_TDI__READ(src) \
9603 (((u_int32_t)(src)\
9605 #define FPGA_REG4__RADIO_1_TDI__WRITE(src) \
9606 (((u_int32_t)(src)\
9608 #define FPGA_REG4__RADIO_1_TDI__MODIFY(dst, src) \
9610 ~0x00000020U) | (((u_int32_t)(src) <<\
9612 #define FPGA_REG4__RADIO_1_TDI__VERIFY(src) \
9613 (!((((u_int32_t)(src)\
9626 #define FPGA_REG4__RADIO_1_TMS__READ(src) \
9627 (((u_int32_t)(src)\
9629 #define FPGA_REG4__RADIO_1_TMS__WRITE(src) \
9630 (((u_int32_t)(src)\
9632 #define FPGA_REG4__RADIO_1_TMS__MODIFY(dst, src) \
9634 ~0x00000040U) | (((u_int32_t)(src) <<\
9636 #define FPGA_REG4__RADIO_1_TMS__VERIFY(src) \
9637 (!((((u_int32_t)(src)\
9650 #define FPGA_REG4__RADIO_1_TDO__READ(src) \
9651 (((u_int32_t)(src)\
9664 #define FPGA_REG4__RADIO_2_TCK__READ(src) \
9665 (((u_int32_t)(src)\
9667 #define FPGA_REG4__RADIO_2_TCK__WRITE(src) \
9668 (((u_int32_t)(src)\
9670 #define FPGA_REG4__RADIO_2_TCK__MODIFY(dst, src) \
9672 ~0x00000100U) | (((u_int32_t)(src) <<\
9674 #define FPGA_REG4__RADIO_2_TCK__VERIFY(src) \
9675 (!((((u_int32_t)(src)\
9688 #define FPGA_REG4__RADIO_2_TDI__READ(src) \
9689 (((u_int32_t)(src)\
9691 #define FPGA_REG4__RADIO_2_TDI__WRITE(src) \
9692 (((u_int32_t)(src)\
9694 #define FPGA_REG4__RADIO_2_TDI__MODIFY(dst, src) \
9696 ~0x00000200U) | (((u_int32_t)(src) <<\
9698 #define FPGA_REG4__RADIO_2_TDI__VERIFY(src) \
9699 (!((((u_int32_t)(src)\
9712 #define FPGA_REG4__RADIO_2_TMS__READ(src) \
9713 (((u_int32_t)(src)\
9715 #define FPGA_REG4__RADIO_2_TMS__WRITE(src) \
9716 (((u_int32_t)(src)\
9718 #define FPGA_REG4__RADIO_2_TMS__MODIFY(dst, src) \
9720 ~0x00000400U) | (((u_int32_t)(src) <<\
9722 #define FPGA_REG4__RADIO_2_TMS__VERIFY(src) \
9723 (!((((u_int32_t)(src)\
9736 #define FPGA_REG4__RADIO_2_TDO__READ(src) \
9737 (((u_int32_t)(src)\
9750 #define FPGA_REG4__RADIO_3_TCK__READ(src) \
9751 (((u_int32_t)(src)\
9753 #define FPGA_REG4__RADIO_3_TCK__WRITE(src) \
9754 (((u_int32_t)(src)\
9756 #define FPGA_REG4__RADIO_3_TCK__MODIFY(dst, src) \
9758 ~0x00001000U) | (((u_int32_t)(src) <<\
9760 #define FPGA_REG4__RADIO_3_TCK__VERIFY(src) \
9761 (!((((u_int32_t)(src)\
9774 #define FPGA_REG4__RADIO_3_TDI__READ(src) \
9775 (((u_int32_t)(src)\
9777 #define FPGA_REG4__RADIO_3_TDI__WRITE(src) \
9778 (((u_int32_t)(src)\
9780 #define FPGA_REG4__RADIO_3_TDI__MODIFY(dst, src) \
9782 ~0x00002000U) | (((u_int32_t)(src) <<\
9784 #define FPGA_REG4__RADIO_3_TDI__VERIFY(src) \
9785 (!((((u_int32_t)(src)\
9798 #define FPGA_REG4__RADIO_3_TMS__READ(src) \
9799 (((u_int32_t)(src)\
9801 #define FPGA_REG4__RADIO_3_TMS__WRITE(src) \
9802 (((u_int32_t)(src)\
9804 #define FPGA_REG4__RADIO_3_TMS__MODIFY(dst, src) \
9806 ~0x00004000U) | (((u_int32_t)(src) <<\
9808 #define FPGA_REG4__RADIO_3_TMS__VERIFY(src) \
9809 (!((((u_int32_t)(src)\
9822 #define FPGA_REG4__RADIO_3_TDO__READ(src) \
9823 (((u_int32_t)(src)\
9849 #define FPGA_REG5__DRP_DEN__READ(src) (u_int32_t)(src) & 0x00000001U
9850 #define FPGA_REG5__DRP_DEN__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
9851 #define FPGA_REG5__DRP_DEN__MODIFY(dst, src) \
9853 ~0x00000001U) | ((u_int32_t)(src) &\
9855 #define FPGA_REG5__DRP_DEN__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
9867 #define FPGA_REG5__DRP_DWE__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
9868 #define FPGA_REG5__DRP_DWE__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
9869 #define FPGA_REG5__DRP_DWE__MODIFY(dst, src) \
9871 ~0x00000002U) | (((u_int32_t)(src) <<\
9873 #define FPGA_REG5__DRP_DWE__VERIFY(src) \
9874 (!((((u_int32_t)(src)\
9887 #define FPGA_REG5__DRP_RESET__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
9888 #define FPGA_REG5__DRP_RESET__WRITE(src) \
9889 (((u_int32_t)(src)\
9891 #define FPGA_REG5__DRP_RESET__MODIFY(dst, src) \
9893 ~0x00000004U) | (((u_int32_t)(src) <<\
9895 #define FPGA_REG5__DRP_RESET__VERIFY(src) \
9896 (!((((u_int32_t)(src)\
9909 #define FPGA_REG5__DRP_ADDRESS__READ(src) \
9910 (((u_int32_t)(src)\
9912 #define FPGA_REG5__DRP_ADDRESS__WRITE(src) \
9913 (((u_int32_t)(src)\
9915 #define FPGA_REG5__DRP_ADDRESS__MODIFY(dst, src) \
9917 ~0x000000f8U) | (((u_int32_t)(src) <<\
9919 #define FPGA_REG5__DRP_ADDRESS__VERIFY(src) \
9920 (!((((u_int32_t)(src)\
9927 #define FPGA_REG5__DRP_RESERVED__READ(src) \
9928 (((u_int32_t)(src)\
9930 #define FPGA_REG5__DRP_RESERVED__WRITE(src) \
9931 (((u_int32_t)(src)\
9933 #define FPGA_REG5__DRP_RESERVED__MODIFY(dst, src) \
9935 ~0x0000ff00U) | (((u_int32_t)(src) <<\
9937 #define FPGA_REG5__DRP_RESERVED__VERIFY(src) \
9938 (!((((u_int32_t)(src)\
9945 #define FPGA_REG5__DRP_DIN__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16)
9946 #define FPGA_REG5__DRP_DIN__WRITE(src) (((u_int32_t)(src) << 16) & 0xffff0000U)
9947 #define FPGA_REG5__DRP_DIN__MODIFY(dst, src) \
9949 ~0xffff0000U) | (((u_int32_t)(src) <<\
9951 #define FPGA_REG5__DRP_DIN__VERIFY(src) \
9952 (!((((u_int32_t)(src)\
9972 #define FPGA_REG6__DRP_DRDY__READ(src) (u_int32_t)(src) & 0x00000001U
9984 #define FPGA_REG6__DRP_DOUT__READ(src) (((u_int32_t)(src) & 0xffff0000U) >> 16)
10002 #define FPGA_REG7__RXPIPEIFERRINJMSK__READ(src) (u_int32_t)(src) & 0xffffffffU
10003 #define FPGA_REG7__RXPIPEIFERRINJMSK__WRITE(src) \
10004 ((u_int32_t)(src)\
10006 #define FPGA_REG7__RXPIPEIFERRINJMSK__MODIFY(dst, src) \
10008 ~0xffffffffU) | ((u_int32_t)(src) &\
10010 #define FPGA_REG7__RXPIPEIFERRINJMSK__VERIFY(src) \
10011 (!(((u_int32_t)(src)\
10031 #define FPGA_REG8__TXPIPEIFERRINJMSK__READ(src) (u_int32_t)(src) & 0xffffffffU
10032 #define FPGA_REG8__TXPIPEIFERRINJMSK__WRITE(src) \
10033 ((u_int32_t)(src)\
10035 #define FPGA_REG8__TXPIPEIFERRINJMSK__MODIFY(dst, src) \
10037 ~0xffffffffU) | ((u_int32_t)(src) &\
10039 #define FPGA_REG8__TXPIPEIFERRINJMSK__VERIFY(src) \
10040 (!(((u_int32_t)(src)\
10060 #define FPGA_REG9__RXPIPEIFDATAERRMSK__READ(src) (u_int32_t)(src) & 0x0000ffffU
10061 #define FPGA_REG9__RXPIPEIFDATAERRMSK__WRITE(src) \
10062 ((u_int32_t)(src)\
10064 #define FPGA_REG9__RXPIPEIFDATAERRMSK__MODIFY(dst, src) \
10066 ~0x0000ffffU) | ((u_int32_t)(src) &\
10068 #define FPGA_REG9__RXPIPEIFDATAERRMSK__VERIFY(src) \
10069 (!(((u_int32_t)(src)\
10076 #define FPGA_REG9__TXPIPEIFDATAERRMSK__READ(src) \
10077 (((u_int32_t)(src)\
10079 #define FPGA_REG9__TXPIPEIFDATAERRMSK__WRITE(src) \
10080 (((u_int32_t)(src)\
10082 #define FPGA_REG9__TXPIPEIFDATAERRMSK__MODIFY(dst, src) \
10084 ~0xffff0000U) | (((u_int32_t)(src) <<\
10086 #define FPGA_REG9__TXPIPEIFDATAERRMSK__VERIFY(src) \
10087 (!((((u_int32_t)(src)\
10107 #define FPGA_REG10__RXPIPEIFSPDMSK__READ(src) (u_int32_t)(src) & 0x0000ffffU
10108 #define FPGA_REG10__RXPIPEIFSPDMSK__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
10109 #define FPGA_REG10__RXPIPEIFSPDMSK__MODIFY(dst, src) \
10111 ~0x0000ffffU) | ((u_int32_t)(src) &\
10113 #define FPGA_REG10__RXPIPEIFSPDMSK__VERIFY(src) \
10114 (!(((u_int32_t)(src)\
10121 #define FPGA_REG10__TXPIPEIFSPDMSK__READ(src) \
10122 (((u_int32_t)(src)\
10124 #define FPGA_REG10__TXPIPEIFSPDMSK__WRITE(src) \
10125 (((u_int32_t)(src)\
10127 #define FPGA_REG10__TXPIPEIFSPDMSK__MODIFY(dst, src) \
10129 ~0xffff0000U) | (((u_int32_t)(src) <<\
10131 #define FPGA_REG10__TXPIPEIFSPDMSK__VERIFY(src) \
10132 (!((((u_int32_t)(src)\
10152 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__VENDORID__READ(src) \
10153 (u_int32_t)(src)\
10160 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__ID__DEVICEID__READ(src) \
10161 (((u_int32_t)(src)\
10182 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__CMD_RGSTR__READ(src) \
10183 (u_int32_t)(src)\
10193 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__STS_CMD_RGSTR__STS_RGSTR__READ(src) \
10194 (((u_int32_t)(src)\
10214 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__REVID__READ(src) \
10215 (u_int32_t)(src)\
10223 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CLS_REV_ID__CLS_CD__READ(src) \
10224 (((u_int32_t)(src)\
10246 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__CACH_LN_SZE__READ(src) \
10247 (u_int32_t)(src)\
10257 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__LAT_TIM__READ(src) \
10258 (((u_int32_t)(src)\
10268 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__HEAD_TYP__READ(src) \
10269 (((u_int32_t)(src)\
10278 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BIST_HEAD_LAT_CACH__BIST__READ(src) \
10279 (((u_int32_t)(src)\
10300 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_0__RDL__READ(src) \
10301 (u_int32_t)(src)\
10320 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_1__RDL__READ(src) \
10321 (u_int32_t)(src)\
10340 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_2__RDL__READ(src) \
10341 (u_int32_t)(src)\
10360 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_3__RDL__READ(src) \
10361 (u_int32_t)(src)\
10380 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_4__RDL__READ(src) \
10381 (u_int32_t)(src)\
10400 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__BAS_ADR_5__RDL__READ(src) \
10401 (u_int32_t)(src)\
10421 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CRD_CIS_PTR__RDL__READ(src) \
10422 (u_int32_t)(src)\
10442 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__SUBSYS_VENID__READ(src) \
10443 (u_int32_t)(src)\
10451 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__SUB_VENID__SUBSYSID__READ(src) \
10452 (((u_int32_t)(src)\
10472 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__EXP_ROM_ADDR__RDL__READ(src) \
10473 (u_int32_t)(src)\
10492 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__CAPTR__READ(src) \
10493 (u_int32_t)(src)\
10501 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__CAPPTR__RESERVE1__READ(src) \
10502 (((u_int32_t)(src)\
10521 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__RESERVE2__RDL__READ(src) \
10522 (u_int32_t)(src)\
10542 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__INT_LIN__READ(src) \
10543 (u_int32_t)(src)\
10551 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__INT_PIN__READ(src) \
10552 (((u_int32_t)(src)\
10560 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__MIN_GRNT__READ(src) \
10561 (((u_int32_t)(src)\
10568 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_0__LAT_INT__MX_LAT__READ(src) \
10569 (((u_int32_t)(src)\
10589 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__CAP_ID__READ(src) \
10590 (u_int32_t)(src)\
10598 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__PM_NX_PTR__READ(src) \
10599 (((u_int32_t)(src)\
10607 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__CFG_PWR_CAP__PMC__READ(src) \
10608 (((u_int32_t)(src)\
10627 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__PMCSR__READ(src) \
10628 (u_int32_t)(src)\
10635 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__PM_BSE__READ(src) \
10636 (((u_int32_t)(src)\
10643 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_1__PWR_CSR__DATA1__READ(src) \
10644 (((u_int32_t)(src)\
10663 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__CAP_ID__READ(src) \
10664 (u_int32_t)(src)\
10672 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__MSI_NX_PTR__READ(src) \
10673 (((u_int32_t)(src)\
10681 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSG_CTR__MSG_CTR_RGS__READ(src) \
10682 (((u_int32_t)(src)\
10701 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_L32__RDL__READ(src) \
10702 (u_int32_t)(src)\
10721 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_U32__RDL__READ(src) \
10722 (u_int32_t)(src)\
10742 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_2__MSI_DATA__MSI_DATA_F__READ(src) \
10743 (u_int32_t)(src)\
10763 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__CAP_ID__READ(src) \
10764 (u_int32_t)(src)\
10772 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__PCIE_NX_PTR__READ(src) \
10773 (((u_int32_t)(src)\
10781 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__PCIE_CAP__PCIE_CAP_R__READ(src) \
10782 (((u_int32_t)(src)\
10801 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_CAP__RDL__READ(src) \
10802 (u_int32_t)(src)\
10822 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__DEV_CTRL__READ(src) \
10823 (u_int32_t)(src)\
10831 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__DEV_STS_CTRL__DEV_STS__READ(src) \
10832 (((u_int32_t)(src)\
10851 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_CAP__RDL__READ(src) \
10852 (u_int32_t)(src)\
10872 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__LNK_CTRL__READ(src) \
10873 (u_int32_t)(src)\
10881 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__LNK_STS_CTRL__LNK_STS__READ(src) \
10882 (((u_int32_t)(src)\
10901 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_CAP__RDL__READ(src) \
10902 (u_int32_t)(src)\
10922 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__SLT_CTRL__READ(src) \
10923 (u_int32_t)(src)\
10931 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_3__SLT_STS_CTRL__SLT_STS__READ(src) \
10932 (((u_int32_t)(src)\
10951 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_CAP__RDL__READ(src) \
10952 (u_int32_t)(src)\
10971 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_5__VPD_DATA__RDL__READ(src) \
10972 (u_int32_t)(src)\
10992 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__PCIE_EN_CAP_AER__RDL__READ(src) \
10993 (u_int32_t)(src)\
11013 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_ST_R__RDL__READ(src) \
11014 (u_int32_t)(src)\
11034 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_MS_R__RDL__READ(src) \
11035 (u_int32_t)(src)\
11055 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__UN_ERR_SV_R__RDL__READ(src) \
11056 (u_int32_t)(src)\
11076 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_ST_R__RDL__READ(src) \
11077 (u_int32_t)(src)\
11097 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__CO_ERR_MS_R__RDL__READ(src) \
11098 (u_int32_t)(src)\
11118 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__ADERR_CAP_CR__RDL__READ(src) \
11119 (u_int32_t)(src)\
11138 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R0__RDL__READ(src) \
11139 (u_int32_t)(src)\
11158 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R4__RDL__READ(src) \
11159 (u_int32_t)(src)\
11178 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R8__RDL__READ(src) \
11179 (u_int32_t)(src)\
11198 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_6__HD_L_R12__RDL__READ(src) \
11199 (u_int32_t)(src)\
11219 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PCIE_EN_CAP_VC__RDL__READ(src) \
11220 (u_int32_t)(src)\
11239 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_CAP_R1__RDL__READ(src) \
11240 (u_int32_t)(src)\
11259 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__P_CAP_R2__RDL__READ(src) \
11260 (u_int32_t)(src)\
11280 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__PVC_CTRL__READ(src) \
11281 (u_int32_t)(src)\
11289 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__PVC_STS_CTRL__PVC_STS__READ(src) \
11290 (((u_int32_t)(src)\
11309 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CAP_R__RDL__READ(src) \
11310 (u_int32_t)(src)\
11329 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_CTL_R__RDL__READ(src) \
11330 (u_int32_t)(src)\
11350 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__RSVDP__READ(src) \
11351 (u_int32_t)(src)\
11359 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VC_STS_RSV__VC_STS__READ(src) \
11360 (((u_int32_t)(src)\
11379 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CAP_R1__RDL__READ(src) \
11380 (u_int32_t)(src)\
11400 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_CTRL_R1__RDL__READ(src) \
11401 (u_int32_t)(src)\
11421 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__RSVDP1__READ(src) \
11422 (u_int32_t)(src)\
11430 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_7__VCR_STS_R1__VC_STS1__READ(src) \
11431 (((u_int32_t)(src)\
11450 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__DEV_EN_CAP__RDL__READ(src) \
11451 (u_int32_t)(src)\
11470 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R1__RDL__READ(src) \
11471 (u_int32_t)(src)\
11490 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_8__SN_R2__RDL__READ(src) \
11491 (u_int32_t)(src)\
11511 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__READ(src) \
11512 (u_int32_t)(src)\
11514 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__WRITE(src) \
11515 ((u_int32_t)(src)\
11517 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__MODIFY(dst, src) \
11519 ~0xffffffffU) | ((u_int32_t)(src) &\
11521 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LAT_REL_TIM__RDL__VERIFY(src) \
11522 (!(((u_int32_t)(src)\
11542 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__READ(src) \
11543 (u_int32_t)(src)\
11545 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__WRITE(src) \
11546 ((u_int32_t)(src)\
11548 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__MODIFY(dst, src) \
11550 ~0xffffffffU) | ((u_int32_t)(src) &\
11552 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__OT_MSG_R__RDL__VERIFY(src) \
11553 (!(((u_int32_t)(src)\
11573 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__READ(src) \
11574 (u_int32_t)(src)\
11576 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__WRITE(src) \
11577 ((u_int32_t)(src)\
11579 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__MODIFY(dst, src) \
11581 ~0xffffffffU) | ((u_int32_t)(src) &\
11583 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_R__RDL__VERIFY(src) \
11584 (!(((u_int32_t)(src)\
11604 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__READ(src) \
11605 (u_int32_t)(src)\
11607 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__WRITE(src) \
11608 ((u_int32_t)(src)\
11610 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__MODIFY(dst, src) \
11612 ~0xffffffffU) | ((u_int32_t)(src) &\
11614 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__ACK_FREQ_R__RDL__VERIFY(src) \
11615 (!(((u_int32_t)(src)\
11636 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__READ(src) \
11637 (u_int32_t)(src)\
11639 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__WRITE(src) \
11640 ((u_int32_t)(src)\
11642 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__MODIFY(dst, src) \
11644 ~0xffffffffU) | ((u_int32_t)(src) &\
11646 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PT_LNK_CTRL_R__RDL__VERIFY(src) \
11647 (!(((u_int32_t)(src)\
11667 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__READ(src) \
11668 (u_int32_t)(src)\
11670 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__WRITE(src) \
11671 ((u_int32_t)(src)\
11673 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__MODIFY(dst, src) \
11675 ~0xffffffffU) | ((u_int32_t)(src) &\
11677 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__LN_SKW_R__RDL__VERIFY(src) \
11678 (!(((u_int32_t)(src)\
11698 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__READ(src) \
11699 (u_int32_t)(src)\
11701 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__WRITE(src) \
11702 ((u_int32_t)(src)\
11704 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__MODIFY(dst, src) \
11706 ~0xffffffffU) | ((u_int32_t)(src) &\
11708 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_N_R__RDL__VERIFY(src) \
11709 (!(((u_int32_t)(src)\
11729 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__READ(src) \
11730 (u_int32_t)(src)\
11732 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__WRITE(src) \
11733 ((u_int32_t)(src)\
11735 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__MODIFY(dst, src) \
11737 ~0xffffffffU) | ((u_int32_t)(src) &\
11739 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__SYMB_T_R__RDL__VERIFY(src) \
11740 (!(((u_int32_t)(src)\
11760 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__READ(src) \
11761 (u_int32_t)(src)\
11763 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__WRITE(src) \
11764 ((u_int32_t)(src)\
11766 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__MODIFY(dst, src) \
11768 ~0xffffffffU) | ((u_int32_t)(src) &\
11770 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__FL_MSK_R2__RDL__VERIFY(src) \
11771 (!(((u_int32_t)(src)\
11791 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R0__RDL__READ(src) \
11792 (u_int32_t)(src)\
11811 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__DB_R1__RDL__READ(src) \
11812 (u_int32_t)(src)\
11831 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_P_STS_R__RDL__READ(src) \
11832 (u_int32_t)(src)\
11852 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_NP_STS_R__RDL__READ(src) \
11853 (u_int32_t)(src)\
11872 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__TR_C_STS_R__RDL__READ(src) \
11873 (u_int32_t)(src)\
11892 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__Q_STS_R__RDL__READ(src) \
11893 (u_int32_t)(src)\
11912 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__READ(src) \
11913 (u_int32_t)(src)\
11915 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__WRITE(src) \
11916 ((u_int32_t)(src)\
11918 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__MODIFY(dst, src) \
11920 ~0xffffffffU) | ((u_int32_t)(src) &\
11922 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R1__RDL__VERIFY(src) \
11923 (!(((u_int32_t)(src)\
11943 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__READ(src) \
11944 (u_int32_t)(src)\
11946 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__WRITE(src) \
11947 ((u_int32_t)(src)\
11949 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__MODIFY(dst, src) \
11951 ~0xffffffffU) | ((u_int32_t)(src) &\
11953 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC_TR_A_R2__RDL__VERIFY(src) \
11954 (!(((u_int32_t)(src)\
11974 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PR_Q_C__RDL__READ(src) \
11975 (u_int32_t)(src)\
11995 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPR_Q_C__RDL__READ(src) \
11996 (u_int32_t)(src)\
12015 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CR_Q_C__RDL__READ(src) \
12016 (u_int32_t)(src)\
12035 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PR_Q_C__RDL__READ(src) \
12036 (u_int32_t)(src)\
12056 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPR_Q_C__RDL__READ(src) \
12057 (u_int32_t)(src)\
12076 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CR_Q_C__RDL__READ(src) \
12077 (u_int32_t)(src)\
12096 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PR_Q_C__RDL__READ(src) \
12097 (u_int32_t)(src)\
12117 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPR_Q_C__RDL__READ(src) \
12118 (u_int32_t)(src)\
12137 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CR_Q_C__RDL__READ(src) \
12138 (u_int32_t)(src)\
12157 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PR_Q_C__RDL__READ(src) \
12158 (u_int32_t)(src)\
12178 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPR_Q_C__RDL__READ(src) \
12179 (u_int32_t)(src)\
12198 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CR_Q_C__RDL__READ(src) \
12199 (u_int32_t)(src)\
12218 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PR_Q_C__RDL__READ(src) \
12219 (u_int32_t)(src)\
12239 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPR_Q_C__RDL__READ(src) \
12240 (u_int32_t)(src)\
12259 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CR_Q_C__RDL__READ(src) \
12260 (u_int32_t)(src)\
12279 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PR_Q_C__RDL__READ(src) \
12280 (u_int32_t)(src)\
12300 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPR_Q_C__RDL__READ(src) \
12301 (u_int32_t)(src)\
12320 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CR_Q_C__RDL__READ(src) \
12321 (u_int32_t)(src)\
12340 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PR_Q_C__RDL__READ(src) \
12341 (u_int32_t)(src)\
12361 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPR_Q_C__RDL__READ(src) \
12362 (u_int32_t)(src)\
12381 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CR_Q_C__RDL__READ(src) \
12382 (u_int32_t)(src)\
12401 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PR_Q_C__RDL__READ(src) \
12402 (u_int32_t)(src)\
12422 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPR_Q_C__RDL__READ(src) \
12423 (u_int32_t)(src)\
12442 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CR_Q_C__RDL__READ(src) \
12443 (u_int32_t)(src)\
12462 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__READ(src) \
12463 (u_int32_t)(src)\
12465 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__WRITE(src) \
12466 ((u_int32_t)(src)\
12468 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__MODIFY(dst, src) \
12470 ~0xffffffffU) | ((u_int32_t)(src) &\
12472 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_PB_D__RDL__VERIFY(src) \
12473 (!(((u_int32_t)(src)\
12493 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__READ(src) \
12494 (u_int32_t)(src)\
12496 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__WRITE(src) \
12497 ((u_int32_t)(src)\
12499 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__MODIFY(dst, src) \
12501 ~0xffffffffU) | ((u_int32_t)(src) &\
12503 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_NPB_D__RDL__VERIFY(src) \
12504 (!(((u_int32_t)(src)\
12524 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__READ(src) \
12525 (u_int32_t)(src)\
12527 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__WRITE(src) \
12528 ((u_int32_t)(src)\
12530 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__MODIFY(dst, src) \
12532 ~0xffffffffU) | ((u_int32_t)(src) &\
12534 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC0_CB_D__RDL__VERIFY(src) \
12535 (!(((u_int32_t)(src)\
12555 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__READ(src) \
12556 (u_int32_t)(src)\
12558 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__WRITE(src) \
12559 ((u_int32_t)(src)\
12561 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__MODIFY(dst, src) \
12563 ~0xffffffffU) | ((u_int32_t)(src) &\
12565 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_PB_D__RDL__VERIFY(src) \
12566 (!(((u_int32_t)(src)\
12586 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__READ(src) \
12587 (u_int32_t)(src)\
12589 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__WRITE(src) \
12590 ((u_int32_t)(src)\
12592 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__MODIFY(dst, src) \
12594 ~0xffffffffU) | ((u_int32_t)(src) &\
12596 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_NPB_D__RDL__VERIFY(src) \
12597 (!(((u_int32_t)(src)\
12617 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__READ(src) \
12618 (u_int32_t)(src)\
12620 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__WRITE(src) \
12621 ((u_int32_t)(src)\
12623 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__MODIFY(dst, src) \
12625 ~0xffffffffU) | ((u_int32_t)(src) &\
12627 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC1_CB_D__RDL__VERIFY(src) \
12628 (!(((u_int32_t)(src)\
12648 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__READ(src) \
12649 (u_int32_t)(src)\
12651 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__WRITE(src) \
12652 ((u_int32_t)(src)\
12654 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__MODIFY(dst, src) \
12656 ~0xffffffffU) | ((u_int32_t)(src) &\
12658 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_PB_D__RDL__VERIFY(src) \
12659 (!(((u_int32_t)(src)\
12679 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__READ(src) \
12680 (u_int32_t)(src)\
12682 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__WRITE(src) \
12683 ((u_int32_t)(src)\
12685 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__MODIFY(dst, src) \
12687 ~0xffffffffU) | ((u_int32_t)(src) &\
12689 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_NPB_D__RDL__VERIFY(src) \
12690 (!(((u_int32_t)(src)\
12710 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__READ(src) \
12711 (u_int32_t)(src)\
12713 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__WRITE(src) \
12714 ((u_int32_t)(src)\
12716 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__MODIFY(dst, src) \
12718 ~0xffffffffU) | ((u_int32_t)(src) &\
12720 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC2_CB_D__RDL__VERIFY(src) \
12721 (!(((u_int32_t)(src)\
12741 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__READ(src) \
12742 (u_int32_t)(src)\
12744 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__WRITE(src) \
12745 ((u_int32_t)(src)\
12747 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__MODIFY(dst, src) \
12749 ~0xffffffffU) | ((u_int32_t)(src) &\
12751 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_PB_D__RDL__VERIFY(src) \
12752 (!(((u_int32_t)(src)\
12772 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__READ(src) \
12773 (u_int32_t)(src)\
12775 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__WRITE(src) \
12776 ((u_int32_t)(src)\
12778 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__MODIFY(dst, src) \
12780 ~0xffffffffU) | ((u_int32_t)(src) &\
12782 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_NPB_D__RDL__VERIFY(src) \
12783 (!(((u_int32_t)(src)\
12803 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__READ(src) \
12804 (u_int32_t)(src)\
12806 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__WRITE(src) \
12807 ((u_int32_t)(src)\
12809 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__MODIFY(dst, src) \
12811 ~0xffffffffU) | ((u_int32_t)(src) &\
12813 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC3_CB_D__RDL__VERIFY(src) \
12814 (!(((u_int32_t)(src)\
12834 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__READ(src) \
12835 (u_int32_t)(src)\
12837 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__WRITE(src) \
12838 ((u_int32_t)(src)\
12840 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__MODIFY(dst, src) \
12842 ~0xffffffffU) | ((u_int32_t)(src) &\
12844 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_PB_D__RDL__VERIFY(src) \
12845 (!(((u_int32_t)(src)\
12865 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__READ(src) \
12866 (u_int32_t)(src)\
12868 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__WRITE(src) \
12869 ((u_int32_t)(src)\
12871 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__MODIFY(dst, src) \
12873 ~0xffffffffU) | ((u_int32_t)(src) &\
12875 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_NPB_D__RDL__VERIFY(src) \
12876 (!(((u_int32_t)(src)\
12896 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__READ(src) \
12897 (u_int32_t)(src)\
12899 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__WRITE(src) \
12900 ((u_int32_t)(src)\
12902 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__MODIFY(dst, src) \
12904 ~0xffffffffU) | ((u_int32_t)(src) &\
12906 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC4_CB_D__RDL__VERIFY(src) \
12907 (!(((u_int32_t)(src)\
12927 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__READ(src) \
12928 (u_int32_t)(src)\
12930 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__WRITE(src) \
12931 ((u_int32_t)(src)\
12933 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__MODIFY(dst, src) \
12935 ~0xffffffffU) | ((u_int32_t)(src) &\
12937 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_PB_D__RDL__VERIFY(src) \
12938 (!(((u_int32_t)(src)\
12958 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__READ(src) \
12959 (u_int32_t)(src)\
12961 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__WRITE(src) \
12962 ((u_int32_t)(src)\
12964 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__MODIFY(dst, src) \
12966 ~0xffffffffU) | ((u_int32_t)(src) &\
12968 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_NPB_D__RDL__VERIFY(src) \
12969 (!(((u_int32_t)(src)\
12989 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__READ(src) \
12990 (u_int32_t)(src)\
12992 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__WRITE(src) \
12993 ((u_int32_t)(src)\
12995 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__MODIFY(dst, src) \
12997 ~0xffffffffU) | ((u_int32_t)(src) &\
12999 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC5_CB_D__RDL__VERIFY(src) \
13000 (!(((u_int32_t)(src)\
13020 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__READ(src) \
13021 (u_int32_t)(src)\
13023 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__WRITE(src) \
13024 ((u_int32_t)(src)\
13026 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__MODIFY(dst, src) \
13028 ~0xffffffffU) | ((u_int32_t)(src) &\
13030 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_PB_D__RDL__VERIFY(src) \
13031 (!(((u_int32_t)(src)\
13051 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__READ(src) \
13052 (u_int32_t)(src)\
13054 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__WRITE(src) \
13055 ((u_int32_t)(src)\
13057 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__MODIFY(dst, src) \
13059 ~0xffffffffU) | ((u_int32_t)(src) &\
13061 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_NPB_D__RDL__VERIFY(src) \
13062 (!(((u_int32_t)(src)\
13082 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__READ(src) \
13083 (u_int32_t)(src)\
13085 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__WRITE(src) \
13086 ((u_int32_t)(src)\
13088 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__MODIFY(dst, src) \
13090 ~0xffffffffU) | ((u_int32_t)(src) &\
13092 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC6_CB_D__RDL__VERIFY(src) \
13093 (!(((u_int32_t)(src)\
13113 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__READ(src) \
13114 (u_int32_t)(src)\
13116 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__WRITE(src) \
13117 ((u_int32_t)(src)\
13119 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__MODIFY(dst, src) \
13121 ~0xffffffffU) | ((u_int32_t)(src) &\
13123 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_PB_D__RDL__VERIFY(src) \
13124 (!(((u_int32_t)(src)\
13144 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__READ(src) \
13145 (u_int32_t)(src)\
13147 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__WRITE(src) \
13148 ((u_int32_t)(src)\
13150 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__MODIFY(dst, src) \
13152 ~0xffffffffU) | ((u_int32_t)(src) &\
13154 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_NPB_D__RDL__VERIFY(src) \
13155 (!(((u_int32_t)(src)\
13175 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__READ(src) \
13176 (u_int32_t)(src)\
13178 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__WRITE(src) \
13179 ((u_int32_t)(src)\
13181 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__MODIFY(dst, src) \
13183 ~0xffffffffU) | ((u_int32_t)(src) &\
13185 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__VC7_CB_D__RDL__VERIFY(src) \
13186 (!(((u_int32_t)(src)\
13206 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__READ(src) \
13207 (u_int32_t)(src)\
13209 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__WRITE(src) \
13210 ((u_int32_t)(src)\
13212 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__MODIFY(dst, src) \
13214 ~0xffffffffU) | ((u_int32_t)(src) &\
13216 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__GEN2__RDL__VERIFY(src) \
13217 (!(((u_int32_t)(src)\
13237 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__READ(src) \
13238 (u_int32_t)(src)\
13240 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__WRITE(src) \
13241 ((u_int32_t)(src)\
13243 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__MODIFY(dst, src) \
13245 ~0xffffffffU) | ((u_int32_t)(src) &\
13247 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_STS_R__RDL__VERIFY(src) \
13248 (!(((u_int32_t)(src)\
13268 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__READ(src) \
13269 (u_int32_t)(src)\
13271 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__WRITE(src) \
13272 ((u_int32_t)(src)\
13274 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__MODIFY(dst, src) \
13276 ~0xffffffffU) | ((u_int32_t)(src) &\
13278 #define DWC_PCIE_DBI_AXI__DWC_PCIE_DBI_AXI_9__PHY_CTRL_R__RDL__VERIFY(src) \
13279 (!(((u_int32_t)(src)\
13308 #define RESET_CONTROL__MAC_WARM_RST__READ(src) (u_int32_t)(src) & 0x00000001U
13309 #define RESET_CONTROL__MAC_WARM_RST__WRITE(src) \
13310 ((u_int32_t)(src)\
13312 #define RESET_CONTROL__MAC_WARM_RST__MODIFY(dst, src) \
13314 ~0x00000001U) | ((u_int32_t)(src) &\
13316 #define RESET_CONTROL__MAC_WARM_RST__VERIFY(src) \
13317 (!(((u_int32_t)(src)\
13330 #define RESET_CONTROL__MAC_COLD_RST__READ(src) \
13331 (((u_int32_t)(src)\
13333 #define RESET_CONTROL__MAC_COLD_RST__WRITE(src) \
13334 (((u_int32_t)(src)\
13336 #define RESET_CONTROL__MAC_COLD_RST__MODIFY(dst, src) \
13338 ~0x00000002U) | (((u_int32_t)(src) <<\
13340 #define RESET_CONTROL__MAC_COLD_RST__VERIFY(src) \
13341 (!((((u_int32_t)(src)\
13354 #define RESET_CONTROL__WARM_RST__READ(src) \
13355 (((u_int32_t)(src)\
13357 #define RESET_CONTROL__WARM_RST__WRITE(src) \
13358 (((u_int32_t)(src)\
13360 #define RESET_CONTROL__WARM_RST__MODIFY(dst, src) \
13362 ~0x00000004U) | (((u_int32_t)(src) <<\
13364 #define RESET_CONTROL__WARM_RST__VERIFY(src) \
13365 (!((((u_int32_t)(src)\
13378 #define RESET_CONTROL__COLD_RST__READ(src) \
13379 (((u_int32_t)(src)\
13381 #define RESET_CONTROL__COLD_RST__WRITE(src) \
13382 (((u_int32_t)(src)\
13384 #define RESET_CONTROL__COLD_RST__MODIFY(dst, src) \
13386 ~0x00000008U) | (((u_int32_t)(src) <<\
13388 #define RESET_CONTROL__COLD_RST__VERIFY(src) \
13389 (!((((u_int32_t)(src)\
13415 #define XTAL_CONTROL__TCXO__READ(src) (u_int32_t)(src) & 0x00000001U
13416 #define XTAL_CONTROL__TCXO__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
13417 #define XTAL_CONTROL__TCXO__MODIFY(dst, src) \
13419 ~0x00000001U) | ((u_int32_t)(src) &\
13421 #define XTAL_CONTROL__TCXO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
13446 #define REG_CONTROL0__SWREG_BITS__READ(src) (u_int32_t)(src) & 0xffffffffU
13447 #define REG_CONTROL0__SWREG_BITS__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
13448 #define REG_CONTROL0__SWREG_BITS__MODIFY(dst, src) \
13450 ~0xffffffffU) | ((u_int32_t)(src) &\
13452 #define REG_CONTROL0__SWREG_BITS__VERIFY(src) \
13453 (!(((u_int32_t)(src)\
13473 #define REG_CONTROL1__SWREG_PROGRAM__READ(src) (u_int32_t)(src) & 0x00000001U
13474 #define REG_CONTROL1__SWREG_PROGRAM__WRITE(src) \
13475 ((u_int32_t)(src)\
13477 #define REG_CONTROL1__SWREG_PROGRAM__MODIFY(dst, src) \
13479 ~0x00000001U) | ((u_int32_t)(src) &\
13481 #define REG_CONTROL1__SWREG_PROGRAM__VERIFY(src) \
13482 (!(((u_int32_t)(src)\
13495 #define REG_CONTROL1__OTPREG_LVL__READ(src) \
13496 (((u_int32_t)(src)\
13498 #define REG_CONTROL1__OTPREG_LVL__WRITE(src) \
13499 (((u_int32_t)(src)\
13501 #define REG_CONTROL1__OTPREG_LVL__MODIFY(dst, src) \
13503 ~0x00000006U) | (((u_int32_t)(src) <<\
13505 #define REG_CONTROL1__OTPREG_LVL__VERIFY(src) \
13506 (!((((u_int32_t)(src)\
13526 #define QUADRATURE__DAC__READ(src) (u_int32_t)(src) & 0x00000007U
13527 #define QUADRATURE__DAC__WRITE(src) ((u_int32_t)(src) & 0x00000007U)
13528 #define QUADRATURE__DAC__MODIFY(dst, src) \
13530 ~0x00000007U) | ((u_int32_t)(src) &\
13532 #define QUADRATURE__DAC__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U)))
13538 #define QUADRATURE__ADC__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4)
13539 #define QUADRATURE__ADC__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U)
13540 #define QUADRATURE__ADC__MODIFY(dst, src) \
13542 ~0x000000f0U) | (((u_int32_t)(src) <<\
13544 #define QUADRATURE__ADC__VERIFY(src) \
13545 (!((((u_int32_t)(src)\
13565 #define PLL_CONTROL__DIV__READ(src) (u_int32_t)(src) & 0x000003ffU
13566 #define PLL_CONTROL__DIV__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
13567 #define PLL_CONTROL__DIV__MODIFY(dst, src) \
13569 ~0x000003ffU) | ((u_int32_t)(src) &\
13571 #define PLL_CONTROL__DIV__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU)))
13577 #define PLL_CONTROL__REFDIV__READ(src) (((u_int32_t)(src) & 0x00003c00U) >> 10)
13578 #define PLL_CONTROL__REFDIV__WRITE(src) \
13579 (((u_int32_t)(src)\
13581 #define PLL_CONTROL__REFDIV__MODIFY(dst, src) \
13583 ~0x00003c00U) | (((u_int32_t)(src) <<\
13585 #define PLL_CONTROL__REFDIV__VERIFY(src) \
13586 (!((((u_int32_t)(src)\
13593 #define PLL_CONTROL__CLK_SEL__READ(src) \
13594 (((u_int32_t)(src)\
13596 #define PLL_CONTROL__CLK_SEL__WRITE(src) \
13597 (((u_int32_t)(src)\
13599 #define PLL_CONTROL__CLK_SEL__MODIFY(dst, src) \
13601 ~0x0000c000U) | (((u_int32_t)(src) <<\
13603 #define PLL_CONTROL__CLK_SEL__VERIFY(src) \
13604 (!((((u_int32_t)(src)\
13611 #define PLL_CONTROL__BYPASS__READ(src) (((u_int32_t)(src) & 0x00010000U) >> 16)
13612 #define PLL_CONTROL__BYPASS__WRITE(src) \
13613 (((u_int32_t)(src)\
13615 #define PLL_CONTROL__BYPASS__MODIFY(dst, src) \
13617 ~0x00010000U) | (((u_int32_t)(src) <<\
13619 #define PLL_CONTROL__BYPASS__VERIFY(src) \
13620 (!((((u_int32_t)(src)\
13633 #define PLL_CONTROL__UPDATING__READ(src) \
13634 (((u_int32_t)(src)\
13647 #define PLL_CONTROL__NOPWD__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18)
13648 #define PLL_CONTROL__NOPWD__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U)
13649 #define PLL_CONTROL__NOPWD__MODIFY(dst, src) \
13651 ~0x00040000U) | (((u_int32_t)(src) <<\
13653 #define PLL_CONTROL__NOPWD__VERIFY(src) \
13654 (!((((u_int32_t)(src)\
13667 #define PLL_CONTROL__MAC_OVERRIDE__READ(src) \
13668 (((u_int32_t)(src)\
13670 #define PLL_CONTROL__MAC_OVERRIDE__WRITE(src) \
13671 (((u_int32_t)(src)\
13673 #define PLL_CONTROL__MAC_OVERRIDE__MODIFY(dst, src) \
13675 ~0x00080000U) | (((u_int32_t)(src) <<\
13677 #define PLL_CONTROL__MAC_OVERRIDE__VERIFY(src) \
13678 (!((((u_int32_t)(src)\
13704 #define PLL_SETTLE__TIME__READ(src) (u_int32_t)(src) & 0x000007ffU
13705 #define PLL_SETTLE__TIME__WRITE(src) ((u_int32_t)(src) & 0x000007ffU)
13706 #define PLL_SETTLE__TIME__MODIFY(dst, src) \
13708 ~0x000007ffU) | ((u_int32_t)(src) &\
13710 #define PLL_SETTLE__TIME__VERIFY(src) (!(((u_int32_t)(src) & ~0x000007ffU)))
13729 #define XTAL_SETTLE__TIME__READ(src) (u_int32_t)(src) & 0x0000007fU
13730 #define XTAL_SETTLE__TIME__WRITE(src) ((u_int32_t)(src) & 0x0000007fU)
13731 #define XTAL_SETTLE__TIME__MODIFY(dst, src) \
13733 ~0x0000007fU) | ((u_int32_t)(src) &\
13735 #define XTAL_SETTLE__TIME__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU)))
13754 #define CLOCK_OUT__SELECT__READ(src) (u_int32_t)(src) & 0x0000000fU
13755 #define CLOCK_OUT__SELECT__WRITE(src) ((u_int32_t)(src) & 0x0000000fU)
13756 #define CLOCK_OUT__SELECT__MODIFY(dst, src) \
13758 ~0x0000000fU) | ((u_int32_t)(src) &\
13760 #define CLOCK_OUT__SELECT__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU)))
13766 #define CLOCK_OUT__DELAY__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4)
13767 #define CLOCK_OUT__DELAY__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000070U)
13768 #define CLOCK_OUT__DELAY__MODIFY(dst, src) \
13770 ~0x00000070U) | (((u_int32_t)(src) <<\
13772 #define CLOCK_OUT__DELAY__VERIFY(src) \
13773 (!((((u_int32_t)(src)\
13793 #define BIAS_OVERRIDE__ON__READ(src) (u_int32_t)(src) & 0x00000001U
13794 #define BIAS_OVERRIDE__ON__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
13795 #define BIAS_OVERRIDE__ON__MODIFY(dst, src) \
13797 ~0x00000001U) | ((u_int32_t)(src) &\
13799 #define BIAS_OVERRIDE__ON__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
13824 #define RESET_CAUSE__LAST__READ(src) (u_int32_t)(src) & 0x00000003U
13842 #define SYSTEM_SLEEP__DISABLE__READ(src) (u_int32_t)(src) & 0x00000001U
13843 #define SYSTEM_SLEEP__DISABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
13844 #define SYSTEM_SLEEP__DISABLE__MODIFY(dst, src) \
13846 ~0x00000001U) | ((u_int32_t)(src) &\
13848 #define SYSTEM_SLEEP__DISABLE__VERIFY(src) \
13849 (!(((u_int32_t)(src)\
13862 #define SYSTEM_SLEEP__LIGHT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
13863 #define SYSTEM_SLEEP__LIGHT__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
13864 #define SYSTEM_SLEEP__LIGHT__MODIFY(dst, src) \
13866 ~0x00000002U) | (((u_int32_t)(src) <<\
13868 #define SYSTEM_SLEEP__LIGHT__VERIFY(src) \
13869 (!((((u_int32_t)(src)\
13882 #define SYSTEM_SLEEP__MAC_IF__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
13907 #define MAC_SLEEP_CONTROL__ENABLE__READ(src) (u_int32_t)(src) & 0x00000003U
13908 #define MAC_SLEEP_CONTROL__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
13909 #define MAC_SLEEP_CONTROL__ENABLE__MODIFY(dst, src) \
13911 ~0x00000003U) | ((u_int32_t)(src) &\
13913 #define MAC_SLEEP_CONTROL__ENABLE__VERIFY(src) \
13914 (!(((u_int32_t)(src)\
13934 #define KEEP_AWAKE__COUNT__READ(src) (u_int32_t)(src) & 0x000000ffU
13935 #define KEEP_AWAKE__COUNT__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
13936 #define KEEP_AWAKE__COUNT__MODIFY(dst, src) \
13938 ~0x000000ffU) | ((u_int32_t)(src) &\
13940 #define KEEP_AWAKE__COUNT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
13959 #define DERIVED_RTC_CLK__PERIOD__READ(src) \
13960 (((u_int32_t)(src)\
13962 #define DERIVED_RTC_CLK__PERIOD__WRITE(src) \
13963 (((u_int32_t)(src)\
13965 #define DERIVED_RTC_CLK__PERIOD__MODIFY(dst, src) \
13967 ~0x0000fffeU) | (((u_int32_t)(src) <<\
13969 #define DERIVED_RTC_CLK__PERIOD__VERIFY(src) \
13970 (!((((u_int32_t)(src)\
13977 #define DERIVED_RTC_CLK__EXTERNAL_DETECT__READ(src) \
13978 (((u_int32_t)(src)\
14004 #define RTC_SYNC_RESET__RESET_L__READ(src) (u_int32_t)(src) & 0x00000001U
14005 #define RTC_SYNC_RESET__RESET_L__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
14006 #define RTC_SYNC_RESET__RESET_L__MODIFY(dst, src) \
14008 ~0x00000001U) | ((u_int32_t)(src) &\
14010 #define RTC_SYNC_RESET__RESET_L__VERIFY(src) \
14011 (!(((u_int32_t)(src)\
14037 #define RTC_SYNC_STATUS__SHUTDOWN_STATE__READ(src) \
14038 (u_int32_t)(src)\
14051 #define RTC_SYNC_STATUS__ON_STATE__READ(src) \
14052 (((u_int32_t)(src)\
14065 #define RTC_SYNC_STATUS__SLEEP_STATE__READ(src) \
14066 (((u_int32_t)(src)\
14079 #define RTC_SYNC_STATUS__WAKEUP_STATE__READ(src) \
14080 (((u_int32_t)(src)\
14093 #define RTC_SYNC_STATUS__WRESET__READ(src) \
14094 (((u_int32_t)(src)\
14107 #define RTC_SYNC_STATUS__PLL_CHANGING__READ(src) \
14108 (((u_int32_t)(src)\
14133 #define RTC_SYNC_DERIVED__BYPASS__READ(src) (u_int32_t)(src) & 0x00000001U
14134 #define RTC_SYNC_DERIVED__BYPASS__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
14135 #define RTC_SYNC_DERIVED__BYPASS__MODIFY(dst, src) \
14137 ~0x00000001U) | ((u_int32_t)(src) &\
14139 #define RTC_SYNC_DERIVED__BYPASS__VERIFY(src) \
14140 (!(((u_int32_t)(src)\
14153 #define RTC_SYNC_DERIVED__FORCE__READ(src) \
14154 (((u_int32_t)(src)\
14156 #define RTC_SYNC_DERIVED__FORCE__WRITE(src) \
14157 (((u_int32_t)(src)\
14159 #define RTC_SYNC_DERIVED__FORCE__MODIFY(dst, src) \
14161 ~0x00000002U) | (((u_int32_t)(src) <<\
14163 #define RTC_SYNC_DERIVED__FORCE__VERIFY(src) \
14164 (!((((u_int32_t)(src)\
14177 #define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__WRITE(src) \
14178 (((u_int32_t)(src)\
14180 #define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__MODIFY(dst, src) \
14182 ~0x00000004U) | (((u_int32_t)(src) <<\
14184 #define RTC_SYNC_DERIVED__FORCE_SWREG_PWD__VERIFY(src) \
14185 (!((((u_int32_t)(src)\
14198 #define RTC_SYNC_DERIVED__FORCE_LPO_PWD__WRITE(src) \
14199 (((u_int32_t)(src)\
14201 #define RTC_SYNC_DERIVED__FORCE_LPO_PWD__MODIFY(dst, src) \
14203 ~0x00000008U) | (((u_int32_t)(src) <<\
14205 #define RTC_SYNC_DERIVED__FORCE_LPO_PWD__VERIFY(src) \
14206 (!((((u_int32_t)(src)\
14232 #define RTC_SYNC_FORCE_WAKE__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U
14244 #define RTC_SYNC_FORCE_WAKE__INTR__READ(src) \
14245 (((u_int32_t)(src)\
14247 #define RTC_SYNC_FORCE_WAKE__INTR__WRITE(src) \
14248 (((u_int32_t)(src)\
14250 #define RTC_SYNC_FORCE_WAKE__INTR__MODIFY(dst, src) \
14252 ~0x00000002U) | (((u_int32_t)(src) <<\
14254 #define RTC_SYNC_FORCE_WAKE__INTR__VERIFY(src) \
14255 (!((((u_int32_t)(src)\
14281 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__READ(src) \
14282 (u_int32_t)(src)\
14284 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__WRITE(src) \
14285 ((u_int32_t)(src)\
14287 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__MODIFY(dst, src) \
14289 ~0x00000001U) | ((u_int32_t)(src) &\
14291 #define RTC_SYNC_INTR_CAUSE__SHUTDOWN_STATE__VERIFY(src) \
14292 (!(((u_int32_t)(src)\
14305 #define RTC_SYNC_INTR_CAUSE__ON_STATE__READ(src) \
14306 (((u_int32_t)(src)\
14308 #define RTC_SYNC_INTR_CAUSE__ON_STATE__WRITE(src) \
14309 (((u_int32_t)(src)\
14311 #define RTC_SYNC_INTR_CAUSE__ON_STATE__MODIFY(dst, src) \
14313 ~0x00000002U) | (((u_int32_t)(src) <<\
14315 #define RTC_SYNC_INTR_CAUSE__ON_STATE__VERIFY(src) \
14316 (!((((u_int32_t)(src)\
14329 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__READ(src) \
14330 (((u_int32_t)(src)\
14332 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__WRITE(src) \
14333 (((u_int32_t)(src)\
14335 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__MODIFY(dst, src) \
14337 ~0x00000004U) | (((u_int32_t)(src) <<\
14339 #define RTC_SYNC_INTR_CAUSE__SLEEP_STATE__VERIFY(src) \
14340 (!((((u_int32_t)(src)\
14353 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__READ(src) \
14354 (((u_int32_t)(src)\
14356 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__WRITE(src) \
14357 (((u_int32_t)(src)\
14359 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__MODIFY(dst, src) \
14361 ~0x00000008U) | (((u_int32_t)(src) <<\
14363 #define RTC_SYNC_INTR_CAUSE__WAKEUP_STATE__VERIFY(src) \
14364 (!((((u_int32_t)(src)\
14377 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__READ(src) \
14378 (((u_int32_t)(src)\
14380 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__WRITE(src) \
14381 (((u_int32_t)(src)\
14383 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__MODIFY(dst, src) \
14385 ~0x00000010U) | (((u_int32_t)(src) <<\
14387 #define RTC_SYNC_INTR_CAUSE__SLEEP_ACCESS__VERIFY(src) \
14388 (!((((u_int32_t)(src)\
14401 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__READ(src) \
14402 (((u_int32_t)(src)\
14404 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__WRITE(src) \
14405 (((u_int32_t)(src)\
14407 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__MODIFY(dst, src) \
14409 ~0x00000020U) | (((u_int32_t)(src) <<\
14411 #define RTC_SYNC_INTR_CAUSE__PLL_CHANGING__VERIFY(src) \
14412 (!((((u_int32_t)(src)\
14438 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__READ(src) \
14439 (u_int32_t)(src)\
14441 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__WRITE(src) \
14442 ((u_int32_t)(src)\
14444 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__MODIFY(dst, src) \
14446 ~0x00000001U) | ((u_int32_t)(src) &\
14448 #define RTC_SYNC_INTR_ENABLE__SHUTDOWN_STATE__VERIFY(src) \
14449 (!(((u_int32_t)(src)\
14462 #define RTC_SYNC_INTR_ENABLE__ON_STATE__READ(src) \
14463 (((u_int32_t)(src)\
14465 #define RTC_SYNC_INTR_ENABLE__ON_STATE__WRITE(src) \
14466 (((u_int32_t)(src)\
14468 #define RTC_SYNC_INTR_ENABLE__ON_STATE__MODIFY(dst, src) \
14470 ~0x00000002U) | (((u_int32_t)(src) <<\
14472 #define RTC_SYNC_INTR_ENABLE__ON_STATE__VERIFY(src) \
14473 (!((((u_int32_t)(src)\
14486 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__READ(src) \
14487 (((u_int32_t)(src)\
14489 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__WRITE(src) \
14490 (((u_int32_t)(src)\
14492 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__MODIFY(dst, src) \
14494 ~0x00000004U) | (((u_int32_t)(src) <<\
14496 #define RTC_SYNC_INTR_ENABLE__SLEEP_STATE__VERIFY(src) \
14497 (!((((u_int32_t)(src)\
14510 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__READ(src) \
14511 (((u_int32_t)(src)\
14513 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__WRITE(src) \
14514 (((u_int32_t)(src)\
14516 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__MODIFY(dst, src) \
14518 ~0x00000008U) | (((u_int32_t)(src) <<\
14520 #define RTC_SYNC_INTR_ENABLE__WAKEUP_STATE__VERIFY(src) \
14521 (!((((u_int32_t)(src)\
14534 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__READ(src) \
14535 (((u_int32_t)(src)\
14537 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__WRITE(src) \
14538 (((u_int32_t)(src)\
14540 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__MODIFY(dst, src) \
14542 ~0x00000010U) | (((u_int32_t)(src) <<\
14544 #define RTC_SYNC_INTR_ENABLE__SLEEP_ACCESS__VERIFY(src) \
14545 (!((((u_int32_t)(src)\
14558 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__READ(src) \
14559 (((u_int32_t)(src)\
14561 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__WRITE(src) \
14562 (((u_int32_t)(src)\
14564 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__MODIFY(dst, src) \
14566 ~0x00000020U) | (((u_int32_t)(src) <<\
14568 #define RTC_SYNC_INTR_ENABLE__PLL_CHANGING__VERIFY(src) \
14569 (!((((u_int32_t)(src)\
14595 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__READ(src) \
14596 (u_int32_t)(src)\
14598 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__WRITE(src) \
14599 ((u_int32_t)(src)\
14601 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__MODIFY(dst, src) \
14603 ~0x00000001U) | ((u_int32_t)(src) &\
14605 #define RTC_SYNC_INTR_MASK__SHUTDOWN_STATE__VERIFY(src) \
14606 (!(((u_int32_t)(src)\
14619 #define RTC_SYNC_INTR_MASK__ON_STATE__READ(src) \
14620 (((u_int32_t)(src)\
14622 #define RTC_SYNC_INTR_MASK__ON_STATE__WRITE(src) \
14623 (((u_int32_t)(src)\
14625 #define RTC_SYNC_INTR_MASK__ON_STATE__MODIFY(dst, src) \
14627 ~0x00000002U) | (((u_int32_t)(src) <<\
14629 #define RTC_SYNC_INTR_MASK__ON_STATE__VERIFY(src) \
14630 (!((((u_int32_t)(src)\
14643 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__READ(src) \
14644 (((u_int32_t)(src)\
14646 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__WRITE(src) \
14647 (((u_int32_t)(src)\
14649 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__MODIFY(dst, src) \
14651 ~0x00000004U) | (((u_int32_t)(src) <<\
14653 #define RTC_SYNC_INTR_MASK__SLEEP_STATE__VERIFY(src) \
14654 (!((((u_int32_t)(src)\
14667 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__READ(src) \
14668 (((u_int32_t)(src)\
14670 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__WRITE(src) \
14671 (((u_int32_t)(src)\
14673 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__MODIFY(dst, src) \
14675 ~0x00000008U) | (((u_int32_t)(src) <<\
14677 #define RTC_SYNC_INTR_MASK__WAKEUP_STATE__VERIFY(src) \
14678 (!((((u_int32_t)(src)\
14691 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__READ(src) \
14692 (((u_int32_t)(src)\
14694 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__WRITE(src) \
14695 (((u_int32_t)(src)\
14697 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__MODIFY(dst, src) \
14699 ~0x00000010U) | (((u_int32_t)(src) <<\
14701 #define RTC_SYNC_INTR_MASK__SLEEP_ACCESS__VERIFY(src) \
14702 (!((((u_int32_t)(src)\
14715 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__READ(src) \
14716 (((u_int32_t)(src)\
14718 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__WRITE(src) \
14719 (((u_int32_t)(src)\
14721 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__MODIFY(dst, src) \
14723 ~0x00000020U) | (((u_int32_t)(src) <<\
14725 #define RTC_SYNC_INTR_MASK__PLL_CHANGING__VERIFY(src) \
14726 (!((((u_int32_t)(src)\
14752 #define RADIO130NM_RXTXBB1_CH1__PDHIQ__READ(src) (u_int32_t)(src) & 0x00000001U
14753 #define RADIO130NM_RXTXBB1_CH1__PDHIQ__WRITE(src) \
14754 ((u_int32_t)(src)\
14756 #define RADIO130NM_RXTXBB1_CH1__PDHIQ__MODIFY(dst, src) \
14758 ~0x00000001U) | ((u_int32_t)(src) &\
14760 #define RADIO130NM_RXTXBB1_CH1__PDHIQ__VERIFY(src) \
14761 (!(((u_int32_t)(src)\
14774 #define RADIO130NM_RXTXBB1_CH1__PDLOQ__READ(src) \
14775 (((u_int32_t)(src)\
14777 #define RADIO130NM_RXTXBB1_CH1__PDLOQ__WRITE(src) \
14778 (((u_int32_t)(src)\
14780 #define RADIO130NM_RXTXBB1_CH1__PDLOQ__MODIFY(dst, src) \
14782 ~0x00000002U) | (((u_int32_t)(src) <<\
14784 #define RADIO130NM_RXTXBB1_CH1__PDLOQ__VERIFY(src) \
14785 (!((((u_int32_t)(src)\
14798 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__READ(src) \
14799 (((u_int32_t)(src)\
14801 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__WRITE(src) \
14802 (((u_int32_t)(src)\
14804 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__MODIFY(dst, src) \
14806 ~0x00000004U) | (((u_int32_t)(src) <<\
14808 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETI2V__VERIFY(src) \
14809 (!((((u_int32_t)(src)\
14822 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__READ(src) \
14823 (((u_int32_t)(src)\
14825 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__WRITE(src) \
14826 (((u_int32_t)(src)\
14828 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__MODIFY(dst, src) \
14830 ~0x00000008U) | (((u_int32_t)(src) <<\
14832 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETHIQ__VERIFY(src) \
14833 (!((((u_int32_t)(src)\
14846 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__READ(src) \
14847 (((u_int32_t)(src)\
14849 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__WRITE(src) \
14850 (((u_int32_t)(src)\
14852 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__MODIFY(dst, src) \
14854 ~0x00000010U) | (((u_int32_t)(src) <<\
14856 #define RADIO130NM_RXTXBB1_CH1__PDOFFSETLOQ__VERIFY(src) \
14857 (!((((u_int32_t)(src)\
14870 #define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__READ(src) \
14871 (((u_int32_t)(src)\
14873 #define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__WRITE(src) \
14874 (((u_int32_t)(src)\
14876 #define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__MODIFY(dst, src) \
14878 ~0x00000020U) | (((u_int32_t)(src) <<\
14880 #define RADIO130NM_RXTXBB1_CH1__PDRXTXBB__VERIFY(src) \
14881 (!((((u_int32_t)(src)\
14894 #define RADIO130NM_RXTXBB1_CH1__PDI2V__READ(src) \
14895 (((u_int32_t)(src)\
14897 #define RADIO130NM_RXTXBB1_CH1__PDI2V__WRITE(src) \
14898 (((u_int32_t)(src)\
14900 #define RADIO130NM_RXTXBB1_CH1__PDI2V__MODIFY(dst, src) \
14902 ~0x00000040U) | (((u_int32_t)(src) <<\
14904 #define RADIO130NM_RXTXBB1_CH1__PDI2V__VERIFY(src) \
14905 (!((((u_int32_t)(src)\
14918 #define RADIO130NM_RXTXBB1_CH1__PDV2I__READ(src) \
14919 (((u_int32_t)(src)\
14921 #define RADIO130NM_RXTXBB1_CH1__PDV2I__WRITE(src) \
14922 (((u_int32_t)(src)\
14924 #define RADIO130NM_RXTXBB1_CH1__PDV2I__MODIFY(dst, src) \
14926 ~0x00000080U) | (((u_int32_t)(src) <<\
14928 #define RADIO130NM_RXTXBB1_CH1__PDV2I__VERIFY(src) \
14929 (!((((u_int32_t)(src)\
14942 #define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__READ(src) \
14943 (((u_int32_t)(src)\
14945 #define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__WRITE(src) \
14946 (((u_int32_t)(src)\
14948 #define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__MODIFY(dst, src) \
14950 ~0x00000100U) | (((u_int32_t)(src) <<\
14952 #define RADIO130NM_RXTXBB1_CH1__PDDACINTERFACE__VERIFY(src) \
14953 (!((((u_int32_t)(src)\
14966 #define RADIO130NM_RXTXBB1_CH1__SEL_ATB__READ(src) \
14967 (((u_int32_t)(src)\
14969 #define RADIO130NM_RXTXBB1_CH1__SEL_ATB__WRITE(src) \
14970 (((u_int32_t)(src)\
14972 #define RADIO130NM_RXTXBB1_CH1__SEL_ATB__MODIFY(dst, src) \
14974 ~0x0001fe00U) | (((u_int32_t)(src) <<\
14976 #define RADIO130NM_RXTXBB1_CH1__SEL_ATB__VERIFY(src) \
14977 (!((((u_int32_t)(src)\
14984 #define RADIO130NM_RXTXBB1_CH1__FNOTCH__READ(src) \
14985 (((u_int32_t)(src)\
14987 #define RADIO130NM_RXTXBB1_CH1__FNOTCH__WRITE(src) \
14988 (((u_int32_t)(src)\
14990 #define RADIO130NM_RXTXBB1_CH1__FNOTCH__MODIFY(dst, src) \
14992 ~0x00060000U) | (((u_int32_t)(src) <<\
14994 #define RADIO130NM_RXTXBB1_CH1__FNOTCH__VERIFY(src) \
14995 (!((((u_int32_t)(src)\
15002 #define RADIO130NM_RXTXBB1_CH1__SPARE__READ(src) \
15003 (((u_int32_t)(src)\
15005 #define RADIO130NM_RXTXBB1_CH1__SPARE__WRITE(src) \
15006 (((u_int32_t)(src)\
15008 #define RADIO130NM_RXTXBB1_CH1__SPARE__MODIFY(dst, src) \
15010 ~0xfff80000U) | (((u_int32_t)(src) <<\
15012 #define RADIO130NM_RXTXBB1_CH1__SPARE__VERIFY(src) \
15013 (!((((u_int32_t)(src)\
15033 #define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__READ(src) \
15034 (u_int32_t)(src)\
15036 #define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__WRITE(src) \
15037 ((u_int32_t)(src)\
15039 #define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__MODIFY(dst, src) \
15041 ~0x00000001U) | ((u_int32_t)(src) &\
15043 #define RADIO130NM_RXTXBB2_CH1__PATH_OVERRIDE__VERIFY(src) \
15044 (!(((u_int32_t)(src)\
15057 #define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__READ(src) \
15058 (((u_int32_t)(src)\
15060 #define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__WRITE(src) \
15061 (((u_int32_t)(src)\
15063 #define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__MODIFY(dst, src) \
15065 ~0x00000002U) | (((u_int32_t)(src) <<\
15067 #define RADIO130NM_RXTXBB2_CH1__PATH1LOQ_EN__VERIFY(src) \
15068 (!((((u_int32_t)(src)\
15081 #define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__READ(src) \
15082 (((u_int32_t)(src)\
15084 #define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__WRITE(src) \
15085 (((u_int32_t)(src)\
15087 #define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__MODIFY(dst, src) \
15089 ~0x00000004U) | (((u_int32_t)(src) <<\
15091 #define RADIO130NM_RXTXBB2_CH1__PATH2LOQ_EN__VERIFY(src) \
15092 (!((((u_int32_t)(src)\
15105 #define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__READ(src) \
15106 (((u_int32_t)(src)\
15108 #define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__WRITE(src) \
15109 (((u_int32_t)(src)\
15111 #define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__MODIFY(dst, src) \
15113 ~0x00000008U) | (((u_int32_t)(src) <<\
15115 #define RADIO130NM_RXTXBB2_CH1__PATH3LOQ_EN__VERIFY(src) \
15116 (!((((u_int32_t)(src)\
15129 #define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__READ(src) \
15130 (((u_int32_t)(src)\
15132 #define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__WRITE(src) \
15133 (((u_int32_t)(src)\
15135 #define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__MODIFY(dst, src) \
15137 ~0x00000010U) | (((u_int32_t)(src) <<\
15139 #define RADIO130NM_RXTXBB2_CH1__PATH1HIQ_EN__VERIFY(src) \
15140 (!((((u_int32_t)(src)\
15153 #define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__READ(src) \
15154 (((u_int32_t)(src)\
15156 #define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__WRITE(src) \
15157 (((u_int32_t)(src)\
15159 #define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__MODIFY(dst, src) \
15161 ~0x00000020U) | (((u_int32_t)(src) <<\
15163 #define RADIO130NM_RXTXBB2_CH1__PATH2HIQ_EN__VERIFY(src) \
15164 (!((((u_int32_t)(src)\
15177 #define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__READ(src) \
15178 (((u_int32_t)(src)\
15180 #define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__WRITE(src) \
15181 (((u_int32_t)(src)\
15183 #define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__MODIFY(dst, src) \
15185 ~0x00000040U) | (((u_int32_t)(src) <<\
15187 #define RADIO130NM_RXTXBB2_CH1__FILTERDOUBLEBW__VERIFY(src) \
15188 (!((((u_int32_t)(src)\
15201 #define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__READ(src) \
15202 (((u_int32_t)(src)\
15204 #define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__WRITE(src) \
15205 (((u_int32_t)(src)\
15207 #define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__MODIFY(dst, src) \
15209 ~0x00000080U) | (((u_int32_t)(src) <<\
15211 #define RADIO130NM_RXTXBB2_CH1__LOCALFILTERTUNING__VERIFY(src) \
15212 (!((((u_int32_t)(src)\
15225 #define RADIO130NM_RXTXBB2_CH1__FILTERFC__READ(src) \
15226 (((u_int32_t)(src)\
15228 #define RADIO130NM_RXTXBB2_CH1__FILTERFC__WRITE(src) \
15229 (((u_int32_t)(src)\
15231 #define RADIO130NM_RXTXBB2_CH1__FILTERFC__MODIFY(dst, src) \
15233 ~0x00001f00U) | (((u_int32_t)(src) <<\
15235 #define RADIO130NM_RXTXBB2_CH1__FILTERFC__VERIFY(src) \
15236 (!((((u_int32_t)(src)\
15243 #define RADIO130NM_RXTXBB2_CH1__CMSEL__READ(src) \
15244 (((u_int32_t)(src)\
15246 #define RADIO130NM_RXTXBB2_CH1__CMSEL__WRITE(src) \
15247 (((u_int32_t)(src)\
15249 #define RADIO130NM_RXTXBB2_CH1__CMSEL__MODIFY(dst, src) \
15251 ~0x00006000U) | (((u_int32_t)(src) <<\
15253 #define RADIO130NM_RXTXBB2_CH1__CMSEL__VERIFY(src) \
15254 (!((((u_int32_t)(src)\
15261 #define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__READ(src) \
15262 (((u_int32_t)(src)\
15264 #define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__WRITE(src) \
15265 (((u_int32_t)(src)\
15267 #define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__MODIFY(dst, src) \
15269 ~0x00008000U) | (((u_int32_t)(src) <<\
15271 #define RADIO130NM_RXTXBB2_CH1__SEL_I2V_TEST__VERIFY(src) \
15272 (!((((u_int32_t)(src)\
15285 #define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__READ(src) \
15286 (((u_int32_t)(src)\
15288 #define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__WRITE(src) \
15289 (((u_int32_t)(src)\
15291 #define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__MODIFY(dst, src) \
15293 ~0x00010000U) | (((u_int32_t)(src) <<\
15295 #define RADIO130NM_RXTXBB2_CH1__SEL_HIQ_TEST__VERIFY(src) \
15296 (!((((u_int32_t)(src)\
15309 #define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__READ(src) \
15310 (((u_int32_t)(src)\
15312 #define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__WRITE(src) \
15313 (((u_int32_t)(src)\
15315 #define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__MODIFY(dst, src) \
15317 ~0x00020000U) | (((u_int32_t)(src) <<\
15319 #define RADIO130NM_RXTXBB2_CH1__SEL_LOQ_TEST__VERIFY(src) \
15320 (!((((u_int32_t)(src)\
15333 #define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__READ(src) \
15334 (((u_int32_t)(src)\
15336 #define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__WRITE(src) \
15337 (((u_int32_t)(src)\
15339 #define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__MODIFY(dst, src) \
15341 ~0x00040000U) | (((u_int32_t)(src) <<\
15343 #define RADIO130NM_RXTXBB2_CH1__SEL_DAC_TEST__VERIFY(src) \
15344 (!((((u_int32_t)(src)\
15357 #define RADIO130NM_RXTXBB2_CH1__SELBUFFER__READ(src) \
15358 (((u_int32_t)(src)\
15360 #define RADIO130NM_RXTXBB2_CH1__SELBUFFER__WRITE(src) \
15361 (((u_int32_t)(src)\
15363 #define RADIO130NM_RXTXBB2_CH1__SELBUFFER__MODIFY(dst, src) \
15365 ~0x00080000U) | (((u_int32_t)(src) <<\
15367 #define RADIO130NM_RXTXBB2_CH1__SELBUFFER__VERIFY(src) \
15368 (!((((u_int32_t)(src)\
15381 #define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__READ(src) \
15382 (((u_int32_t)(src)\
15384 #define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__WRITE(src) \
15385 (((u_int32_t)(src)\
15387 #define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__MODIFY(dst, src) \
15389 ~0x00100000U) | (((u_int32_t)(src) <<\
15391 #define RADIO130NM_RXTXBB2_CH1__SHORTBUFFER__VERIFY(src) \
15392 (!((((u_int32_t)(src)\
15405 #define RADIO130NM_RXTXBB2_CH1__SPARE__READ(src) \
15406 (((u_int32_t)(src)\
15408 #define RADIO130NM_RXTXBB2_CH1__SPARE__WRITE(src) \
15409 (((u_int32_t)(src)\
15411 #define RADIO130NM_RXTXBB2_CH1__SPARE__MODIFY(dst, src) \
15413 ~0x00600000U) | (((u_int32_t)(src) <<\
15415 #define RADIO130NM_RXTXBB2_CH1__SPARE__VERIFY(src) \
15416 (!((((u_int32_t)(src)\
15423 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__READ(src) \
15424 (((u_int32_t)(src)\
15426 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__WRITE(src) \
15427 (((u_int32_t)(src)\
15429 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__MODIFY(dst, src) \
15431 ~0x03800000U) | (((u_int32_t)(src) <<\
15433 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSI2V_CTRL__VERIFY(src) \
15434 (!((((u_int32_t)(src)\
15441 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__READ(src) \
15442 (((u_int32_t)(src)\
15444 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__WRITE(src) \
15445 (((u_int32_t)(src)\
15447 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__MODIFY(dst, src) \
15449 ~0x1c000000U) | (((u_int32_t)(src) <<\
15451 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSLO_CTRL__VERIFY(src) \
15452 (!((((u_int32_t)(src)\
15459 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__READ(src) \
15460 (((u_int32_t)(src)\
15462 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__WRITE(src) \
15463 (((u_int32_t)(src)\
15465 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__MODIFY(dst, src) \
15467 ~0xe0000000U) | (((u_int32_t)(src) <<\
15469 #define RADIO130NM_RXTXBB2_CH1__IBN_37P5_OSHI_CTRL__VERIFY(src) \
15470 (!((((u_int32_t)(src)\
15490 #define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__READ(src) \
15491 (u_int32_t)(src)\
15493 #define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__WRITE(src) \
15494 ((u_int32_t)(src)\
15496 #define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__MODIFY(dst, src) \
15498 ~0x00000007U) | ((u_int32_t)(src) &\
15500 #define RADIO130NM_RXTXBB3_CH1__IBN_100U_TEST_CTRL__VERIFY(src) \
15501 (!(((u_int32_t)(src)\
15508 #define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__READ(src) \
15509 (((u_int32_t)(src)\
15511 #define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__WRITE(src) \
15512 (((u_int32_t)(src)\
15514 #define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__MODIFY(dst, src) \
15516 ~0x00000038U) | (((u_int32_t)(src) <<\
15518 #define RADIO130NM_RXTXBB3_CH1__IBRN_12P5_CM_CTRL__VERIFY(src) \
15519 (!((((u_int32_t)(src)\
15526 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__READ(src) \
15527 (((u_int32_t)(src)\
15529 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__WRITE(src) \
15530 (((u_int32_t)(src)\
15532 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__MODIFY(dst, src) \
15534 ~0x000001c0U) | (((u_int32_t)(src) <<\
15536 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO2_CTRL__VERIFY(src) \
15537 (!((((u_int32_t)(src)\
15544 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__READ(src) \
15545 (((u_int32_t)(src)\
15547 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__WRITE(src) \
15548 (((u_int32_t)(src)\
15550 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__MODIFY(dst, src) \
15552 ~0x00000e00U) | (((u_int32_t)(src) <<\
15554 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_LO1_CTRL__VERIFY(src) \
15555 (!((((u_int32_t)(src)\
15562 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__READ(src) \
15563 (((u_int32_t)(src)\
15565 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__WRITE(src) \
15566 (((u_int32_t)(src)\
15568 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__MODIFY(dst, src) \
15570 ~0x00007000U) | (((u_int32_t)(src) <<\
15572 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI2_CTRL__VERIFY(src) \
15573 (!((((u_int32_t)(src)\
15580 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__READ(src) \
15581 (((u_int32_t)(src)\
15583 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__WRITE(src) \
15584 (((u_int32_t)(src)\
15586 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__MODIFY(dst, src) \
15588 ~0x00038000U) | (((u_int32_t)(src) <<\
15590 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_HI1_CTRL__VERIFY(src) \
15591 (!((((u_int32_t)(src)\
15598 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__READ(src) \
15599 (((u_int32_t)(src)\
15601 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__WRITE(src) \
15602 (((u_int32_t)(src)\
15604 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__MODIFY(dst, src) \
15606 ~0x001c0000U) | (((u_int32_t)(src) <<\
15608 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_I2V_CTRL__VERIFY(src) \
15609 (!((((u_int32_t)(src)\
15616 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__READ(src) \
15617 (((u_int32_t)(src)\
15619 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__WRITE(src) \
15620 (((u_int32_t)(src)\
15622 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__MODIFY(dst, src) \
15624 ~0x00e00000U) | (((u_int32_t)(src) <<\
15626 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_BKV2I_CTRL__VERIFY(src) \
15627 (!((((u_int32_t)(src)\
15634 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__READ(src) \
15635 (((u_int32_t)(src)\
15637 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__WRITE(src) \
15638 (((u_int32_t)(src)\
15640 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__MODIFY(dst, src) \
15642 ~0x07000000U) | (((u_int32_t)(src) <<\
15644 #define RADIO130NM_RXTXBB3_CH1__IBN_25U_CM_BUFAMP_CTRL__VERIFY(src) \
15645 (!((((u_int32_t)(src)\
15652 #define RADIO130NM_RXTXBB3_CH1__SPARE__READ(src) \
15653 (((u_int32_t)(src)\
15655 #define RADIO130NM_RXTXBB3_CH1__SPARE__WRITE(src) \
15656 (((u_int32_t)(src)\
15658 #define RADIO130NM_RXTXBB3_CH1__SPARE__MODIFY(dst, src) \
15660 ~0xf8000000U) | (((u_int32_t)(src) <<\
15662 #define RADIO130NM_RXTXBB3_CH1__SPARE__VERIFY(src) \
15663 (!((((u_int32_t)(src)\
15683 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__READ(src) \
15684 (u_int32_t)(src)\
15686 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__WRITE(src) \
15687 ((u_int32_t)(src)\
15689 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__MODIFY(dst, src) \
15691 ~0x0000001fU) | ((u_int32_t)(src) &\
15693 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VQ__VERIFY(src) \
15694 (!(((u_int32_t)(src)\
15701 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__READ(src) \
15702 (((u_int32_t)(src)\
15704 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__WRITE(src) \
15705 (((u_int32_t)(src)\
15707 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__MODIFY(dst, src) \
15709 ~0x000003e0U) | (((u_int32_t)(src) <<\
15711 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRI2VI__VERIFY(src) \
15712 (!((((u_int32_t)(src)\
15719 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__READ(src) \
15720 (((u_int32_t)(src)\
15722 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__WRITE(src) \
15723 (((u_int32_t)(src)\
15725 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__MODIFY(dst, src) \
15727 ~0x00007c00U) | (((u_int32_t)(src) <<\
15729 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOQ__VERIFY(src) \
15730 (!((((u_int32_t)(src)\
15737 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__READ(src) \
15738 (((u_int32_t)(src)\
15740 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__WRITE(src) \
15741 (((u_int32_t)(src)\
15743 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__MODIFY(dst, src) \
15745 ~0x000f8000U) | (((u_int32_t)(src) <<\
15747 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRLOI__VERIFY(src) \
15748 (!((((u_int32_t)(src)\
15755 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__READ(src) \
15756 (((u_int32_t)(src)\
15758 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__WRITE(src) \
15759 (((u_int32_t)(src)\
15761 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__MODIFY(dst, src) \
15763 ~0x01f00000U) | (((u_int32_t)(src) <<\
15765 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRHIQ__VERIFY(src) \
15766 (!((((u_int32_t)(src)\
15773 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__READ(src) \
15774 (((u_int32_t)(src)\
15776 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__WRITE(src) \
15777 (((u_int32_t)(src)\
15779 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__MODIFY(dst, src) \
15781 ~0x3e000000U) | (((u_int32_t)(src) <<\
15783 #define RADIO130NM_RXTXBB4_CH1__OFSTCORRHII__VERIFY(src) \
15784 (!((((u_int32_t)(src)\
15791 #define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__READ(src) \
15792 (((u_int32_t)(src)\
15794 #define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__WRITE(src) \
15795 (((u_int32_t)(src)\
15797 #define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__MODIFY(dst, src) \
15799 ~0x40000000U) | (((u_int32_t)(src) <<\
15801 #define RADIO130NM_RXTXBB4_CH1__LOCALOFFSET__VERIFY(src) \
15802 (!((((u_int32_t)(src)\
15815 #define RADIO130NM_RXTXBB4_CH1__SPARE__READ(src) \
15816 (((u_int32_t)(src)\
15818 #define RADIO130NM_RXTXBB4_CH1__SPARE__WRITE(src) \
15819 (((u_int32_t)(src)\
15821 #define RADIO130NM_RXTXBB4_CH1__SPARE__MODIFY(dst, src) \
15823 ~0x80000000U) | (((u_int32_t)(src) <<\
15825 #define RADIO130NM_RXTXBB4_CH1__SPARE__VERIFY(src) \
15826 (!((((u_int32_t)(src)\
15852 #define RADIO130NM_RF2G1_CH1__SPARES__READ(src) (u_int32_t)(src) & 0x0000003fU
15853 #define RADIO130NM_RF2G1_CH1__SPARES__WRITE(src) \
15854 ((u_int32_t)(src)\
15856 #define RADIO130NM_RF2G1_CH1__SPARES__MODIFY(dst, src) \
15858 ~0x0000003fU) | ((u_int32_t)(src) &\
15860 #define RADIO130NM_RF2G1_CH1__SPARES__VERIFY(src) \
15861 (!(((u_int32_t)(src)\
15868 #define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__READ(src) \
15869 (((u_int32_t)(src)\
15871 #define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__WRITE(src) \
15872 (((u_int32_t)(src)\
15874 #define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__MODIFY(dst, src) \
15876 ~0x00000040U) | (((u_int32_t)(src) <<\
15878 #define RADIO130NM_RF2G1_CH1__REGLO_BYPASS__VERIFY(src) \
15879 (!((((u_int32_t)(src)\
15892 #define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__READ(src) \
15893 (((u_int32_t)(src)\
15895 #define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__WRITE(src) \
15896 (((u_int32_t)(src)\
15898 #define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__MODIFY(dst, src) \
15900 ~0x00000080U) | (((u_int32_t)(src) <<\
15902 #define RADIO130NM_RF2G1_CH1__REGLNA_BYPASS__VERIFY(src) \
15903 (!((((u_int32_t)(src)\
15916 #define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__READ(src) \
15917 (((u_int32_t)(src)\
15919 #define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__WRITE(src) \
15920 (((u_int32_t)(src)\
15922 #define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__MODIFY(dst, src) \
15924 ~0x00000700U) | (((u_int32_t)(src) <<\
15926 #define RADIO130NM_RF2G1_CH1__PDIC25U_VGM__VERIFY(src) \
15927 (!((((u_int32_t)(src)\
15934 #define RADIO130NM_RF2G1_CH1__PACA_SEL__READ(src) \
15935 (((u_int32_t)(src)\
15937 #define RADIO130NM_RF2G1_CH1__PACA_SEL__WRITE(src) \
15938 (((u_int32_t)(src)\
15940 #define RADIO130NM_RF2G1_CH1__PACA_SEL__MODIFY(dst, src) \
15942 ~0x00001800U) | (((u_int32_t)(src) <<\
15944 #define RADIO130NM_RF2G1_CH1__PACA_SEL__VERIFY(src) \
15945 (!((((u_int32_t)(src)\
15952 #define RADIO130NM_RF2G1_CH1__LOCONTROL__READ(src) \
15953 (((u_int32_t)(src)\
15955 #define RADIO130NM_RF2G1_CH1__LOCONTROL__WRITE(src) \
15956 (((u_int32_t)(src)\
15958 #define RADIO130NM_RF2G1_CH1__LOCONTROL__MODIFY(dst, src) \
15960 ~0x00002000U) | (((u_int32_t)(src) <<\
15962 #define RADIO130NM_RF2G1_CH1__LOCONTROL__VERIFY(src) \
15963 (!((((u_int32_t)(src)\
15976 #define RADIO130NM_RF2G1_CH1__TXATB_SEL__READ(src) \
15977 (((u_int32_t)(src)\
15979 #define RADIO130NM_RF2G1_CH1__TXATB_SEL__WRITE(src) \
15980 (((u_int32_t)(src)\
15982 #define RADIO130NM_RF2G1_CH1__TXATB_SEL__MODIFY(dst, src) \
15984 ~0x0001c000U) | (((u_int32_t)(src) <<\
15986 #define RADIO130NM_RF2G1_CH1__TXATB_SEL__VERIFY(src) \
15987 (!((((u_int32_t)(src)\
15994 #define RADIO130NM_RF2G1_CH1__RXATB_SEL__READ(src) \
15995 (((u_int32_t)(src)\
15997 #define RADIO130NM_RF2G1_CH1__RXATB_SEL__WRITE(src) \
15998 (((u_int32_t)(src)\
16000 #define RADIO130NM_RF2G1_CH1__RXATB_SEL__MODIFY(dst, src) \
16002 ~0x000e0000U) | (((u_int32_t)(src) <<\
16004 #define RADIO130NM_RF2G1_CH1__RXATB_SEL__VERIFY(src) \
16005 (!((((u_int32_t)(src)\
16012 #define RADIO130NM_RF2G1_CH1__LOATB_SEL__READ(src) \
16013 (((u_int32_t)(src)\
16015 #define RADIO130NM_RF2G1_CH1__LOATB_SEL__WRITE(src) \
16016 (((u_int32_t)(src)\
16018 #define RADIO130NM_RF2G1_CH1__LOATB_SEL__MODIFY(dst, src) \
16020 ~0x00700000U) | (((u_int32_t)(src) <<\
16022 #define RADIO130NM_RF2G1_CH1__LOATB_SEL__VERIFY(src) \
16023 (!((((u_int32_t)(src)\
16030 #define RADIO130NM_RF2G1_CH1__OB__READ(src) \
16031 (((u_int32_t)(src)\
16033 #define RADIO130NM_RF2G1_CH1__OB__WRITE(src) \
16034 (((u_int32_t)(src)\
16036 #define RADIO130NM_RF2G1_CH1__OB__MODIFY(dst, src) \
16038 ~0x03800000U) | (((u_int32_t)(src) <<\
16040 #define RADIO130NM_RF2G1_CH1__OB__VERIFY(src) \
16041 (!((((u_int32_t)(src)\
16048 #define RADIO130NM_RF2G1_CH1__DB__READ(src) \
16049 (((u_int32_t)(src)\
16051 #define RADIO130NM_RF2G1_CH1__DB__WRITE(src) \
16052 (((u_int32_t)(src)\
16054 #define RADIO130NM_RF2G1_CH1__DB__MODIFY(dst, src) \
16056 ~0x1c000000U) | (((u_int32_t)(src) <<\
16058 #define RADIO130NM_RF2G1_CH1__DB__VERIFY(src) \
16059 (!((((u_int32_t)(src)\
16066 #define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__READ(src) \
16067 (((u_int32_t)(src)\
16069 #define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__WRITE(src) \
16070 (((u_int32_t)(src)\
16072 #define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__MODIFY(dst, src) \
16074 ~0xe0000000U) | (((u_int32_t)(src) <<\
16076 #define RADIO130NM_RF2G1_CH1__PDIC25U_LNA__VERIFY(src) \
16077 (!((((u_int32_t)(src)\
16097 #define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__READ(src) \
16098 (u_int32_t)(src)\
16100 #define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__WRITE(src) \
16101 ((u_int32_t)(src)\
16103 #define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__MODIFY(dst, src) \
16105 ~0x00000007U) | ((u_int32_t)(src) &\
16107 #define RADIO130NM_RF2G2_CH1__PDIR25U_VREGLO__VERIFY(src) \
16108 (!(((u_int32_t)(src)\
16115 #define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__READ(src) \
16116 (((u_int32_t)(src)\
16118 #define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__WRITE(src) \
16119 (((u_int32_t)(src)\
16121 #define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__MODIFY(dst, src) \
16123 ~0x00000038U) | (((u_int32_t)(src) <<\
16125 #define RADIO130NM_RF2G2_CH1__PDIC25U_VREGLO__VERIFY(src) \
16126 (!((((u_int32_t)(src)\
16133 #define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__READ(src) \
16134 (((u_int32_t)(src)\
16136 #define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__WRITE(src) \
16137 (((u_int32_t)(src)\
16139 #define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__MODIFY(dst, src) \
16141 ~0x000001c0U) | (((u_int32_t)(src) <<\
16143 #define RADIO130NM_RF2G2_CH1__PDIC50U_DIV__VERIFY(src) \
16144 (!((((u_int32_t)(src)\
16151 #define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__READ(src) \
16152 (((u_int32_t)(src)\
16154 #define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__WRITE(src) \
16155 (((u_int32_t)(src)\
16157 #define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__MODIFY(dst, src) \
16159 ~0x00000e00U) | (((u_int32_t)(src) <<\
16161 #define RADIO130NM_RF2G2_CH1__PDIC25U_RXRF__VERIFY(src) \
16162 (!((((u_int32_t)(src)\
16169 #define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__READ(src) \
16170 (((u_int32_t)(src)\
16172 #define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__WRITE(src) \
16173 (((u_int32_t)(src)\
16175 #define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__MODIFY(dst, src) \
16177 ~0x00007000U) | (((u_int32_t)(src) <<\
16179 #define RADIO130NM_RF2G2_CH1__PDIC25U_TXRF__VERIFY(src) \
16180 (!((((u_int32_t)(src)\
16187 #define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__READ(src) \
16188 (((u_int32_t)(src)\
16190 #define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__WRITE(src) \
16191 (((u_int32_t)(src)\
16193 #define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__MODIFY(dst, src) \
16195 ~0x00038000U) | (((u_int32_t)(src) <<\
16197 #define RADIO130NM_RF2G2_CH1__PDIC25U_TXPA__VERIFY(src) \
16198 (!((((u_int32_t)(src)\
16205 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__READ(src) \
16206 (((u_int32_t)(src)\
16208 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__WRITE(src) \
16209 (((u_int32_t)(src)\
16211 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__MODIFY(dst, src) \
16213 ~0x00040000U) | (((u_int32_t)(src) <<\
16215 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXPA__VERIFY(src) \
16216 (!((((u_int32_t)(src)\
16229 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__READ(src) \
16230 (((u_int32_t)(src)\
16232 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__WRITE(src) \
16233 (((u_int32_t)(src)\
16235 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__MODIFY(dst, src) \
16237 ~0x00380000U) | (((u_int32_t)(src) <<\
16239 #define RADIO130NM_RF2G2_CH1__PDIR25U_TXMIX__VERIFY(src) \
16240 (!((((u_int32_t)(src)\
16247 #define RADIO130NM_RF2G2_CH1__PDTXMIX__READ(src) \
16248 (((u_int32_t)(src)\
16250 #define RADIO130NM_RF2G2_CH1__PDTXMIX__WRITE(src) \
16251 (((u_int32_t)(src)\
16253 #define RADIO130NM_RF2G2_CH1__PDTXMIX__MODIFY(dst, src) \
16255 ~0x00400000U) | (((u_int32_t)(src) <<\
16257 #define RADIO130NM_RF2G2_CH1__PDTXMIX__VERIFY(src) \
16258 (!((((u_int32_t)(src)\
16271 #define RADIO130NM_RF2G2_CH1__PDTXLO__READ(src) \
16272 (((u_int32_t)(src)\
16274 #define RADIO130NM_RF2G2_CH1__PDTXLO__WRITE(src) \
16275 (((u_int32_t)(src)\
16277 #define RADIO130NM_RF2G2_CH1__PDTXLO__MODIFY(dst, src) \
16279 ~0x00800000U) | (((u_int32_t)(src) <<\
16281 #define RADIO130NM_RF2G2_CH1__PDTXLO__VERIFY(src) \
16282 (!((((u_int32_t)(src)\
16295 #define RADIO130NM_RF2G2_CH1__PDRXLO__READ(src) \
16296 (((u_int32_t)(src)\
16298 #define RADIO130NM_RF2G2_CH1__PDRXLO__WRITE(src) \
16299 (((u_int32_t)(src)\
16301 #define RADIO130NM_RF2G2_CH1__PDRXLO__MODIFY(dst, src) \
16303 ~0x01000000U) | (((u_int32_t)(src) <<\
16305 #define RADIO130NM_RF2G2_CH1__PDRXLO__VERIFY(src) \
16306 (!((((u_int32_t)(src)\
16319 #define RADIO130NM_RF2G2_CH1__PDVGM__READ(src) \
16320 (((u_int32_t)(src)\
16322 #define RADIO130NM_RF2G2_CH1__PDVGM__WRITE(src) \
16323 (((u_int32_t)(src)\
16325 #define RADIO130NM_RF2G2_CH1__PDVGM__MODIFY(dst, src) \
16327 ~0x02000000U) | (((u_int32_t)(src) <<\
16329 #define RADIO130NM_RF2G2_CH1__PDVGM__VERIFY(src) \
16330 (!((((u_int32_t)(src)\
16343 #define RADIO130NM_RF2G2_CH1__PDREGLO__READ(src) \
16344 (((u_int32_t)(src)\
16346 #define RADIO130NM_RF2G2_CH1__PDREGLO__WRITE(src) \
16347 (((u_int32_t)(src)\
16349 #define RADIO130NM_RF2G2_CH1__PDREGLO__MODIFY(dst, src) \
16351 ~0x04000000U) | (((u_int32_t)(src) <<\
16353 #define RADIO130NM_RF2G2_CH1__PDREGLO__VERIFY(src) \
16354 (!((((u_int32_t)(src)\
16367 #define RADIO130NM_RF2G2_CH1__PDREGLNA__READ(src) \
16368 (((u_int32_t)(src)\
16370 #define RADIO130NM_RF2G2_CH1__PDREGLNA__WRITE(src) \
16371 (((u_int32_t)(src)\
16373 #define RADIO130NM_RF2G2_CH1__PDREGLNA__MODIFY(dst, src) \
16375 ~0x08000000U) | (((u_int32_t)(src) <<\
16377 #define RADIO130NM_RF2G2_CH1__PDREGLNA__VERIFY(src) \
16378 (!((((u_int32_t)(src)\
16391 #define RADIO130NM_RF2G2_CH1__PDPAOUT__READ(src) \
16392 (((u_int32_t)(src)\
16394 #define RADIO130NM_RF2G2_CH1__PDPAOUT__WRITE(src) \
16395 (((u_int32_t)(src)\
16397 #define RADIO130NM_RF2G2_CH1__PDPAOUT__MODIFY(dst, src) \
16399 ~0x10000000U) | (((u_int32_t)(src) <<\
16401 #define RADIO130NM_RF2G2_CH1__PDPAOUT__VERIFY(src) \
16402 (!((((u_int32_t)(src)\
16415 #define RADIO130NM_RF2G2_CH1__PDPADRV__READ(src) \
16416 (((u_int32_t)(src)\
16418 #define RADIO130NM_RF2G2_CH1__PDPADRV__WRITE(src) \
16419 (((u_int32_t)(src)\
16421 #define RADIO130NM_RF2G2_CH1__PDPADRV__MODIFY(dst, src) \
16423 ~0x20000000U) | (((u_int32_t)(src) <<\
16425 #define RADIO130NM_RF2G2_CH1__PDPADRV__VERIFY(src) \
16426 (!((((u_int32_t)(src)\
16439 #define RADIO130NM_RF2G2_CH1__PDDIV__READ(src) \
16440 (((u_int32_t)(src)\
16442 #define RADIO130NM_RF2G2_CH1__PDDIV__WRITE(src) \
16443 (((u_int32_t)(src)\
16445 #define RADIO130NM_RF2G2_CH1__PDDIV__MODIFY(dst, src) \
16447 ~0x40000000U) | (((u_int32_t)(src) <<\
16449 #define RADIO130NM_RF2G2_CH1__PDDIV__VERIFY(src) \
16450 (!((((u_int32_t)(src)\
16463 #define RADIO130NM_RF2G2_CH1__PDLNA__READ(src) \
16464 (((u_int32_t)(src)\
16466 #define RADIO130NM_RF2G2_CH1__PDLNA__WRITE(src) \
16467 (((u_int32_t)(src)\
16469 #define RADIO130NM_RF2G2_CH1__PDLNA__MODIFY(dst, src) \
16471 ~0x80000000U) | (((u_int32_t)(src) <<\
16473 #define RADIO130NM_RF2G2_CH1__PDLNA__VERIFY(src) \
16474 (!((((u_int32_t)(src)\
16500 #define RADIO130NM_RF5G1_CH1__SPARE__READ(src) (u_int32_t)(src) & 0x000003ffU
16501 #define RADIO130NM_RF5G1_CH1__SPARE__WRITE(src) \
16502 ((u_int32_t)(src)\
16504 #define RADIO130NM_RF5G1_CH1__SPARE__MODIFY(dst, src) \
16506 ~0x000003ffU) | ((u_int32_t)(src) &\
16508 #define RADIO130NM_RF5G1_CH1__SPARE__VERIFY(src) \
16509 (!(((u_int32_t)(src)\
16516 #define RADIO130NM_RF5G1_CH1__PDREGLO5__READ(src) \
16517 (((u_int32_t)(src)\
16519 #define RADIO130NM_RF5G1_CH1__PDREGLO5__WRITE(src) \
16520 (((u_int32_t)(src)\
16522 #define RADIO130NM_RF5G1_CH1__PDREGLO5__MODIFY(dst, src) \
16524 ~0x00000400U) | (((u_int32_t)(src) <<\
16526 #define RADIO130NM_RF5G1_CH1__PDREGLO5__VERIFY(src) \
16527 (!((((u_int32_t)(src)\
16540 #define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__READ(src) \
16541 (((u_int32_t)(src)\
16543 #define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__WRITE(src) \
16544 (((u_int32_t)(src)\
16546 #define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__MODIFY(dst, src) \
16548 ~0x00000800U) | (((u_int32_t)(src) <<\
16550 #define RADIO130NM_RF5G1_CH1__REGLO_BYPASS5__VERIFY(src) \
16551 (!((((u_int32_t)(src)\
16564 #define RADIO130NM_RF5G1_CH1__LO5CONTROL__READ(src) \
16565 (((u_int32_t)(src)\
16567 #define RADIO130NM_RF5G1_CH1__LO5CONTROL__WRITE(src) \
16568 (((u_int32_t)(src)\
16570 #define RADIO130NM_RF5G1_CH1__LO5CONTROL__MODIFY(dst, src) \
16572 ~0x00001000U) | (((u_int32_t)(src) <<\
16574 #define RADIO130NM_RF5G1_CH1__LO5CONTROL__VERIFY(src) \
16575 (!((((u_int32_t)(src)\
16588 #define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__READ(src) \
16589 (((u_int32_t)(src)\
16591 #define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__WRITE(src) \
16592 (((u_int32_t)(src)\
16594 #define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__MODIFY(dst, src) \
16596 ~0x0000e000U) | (((u_int32_t)(src) <<\
16598 #define RADIO130NM_RF5G1_CH1__TX5_ATB_SEL__VERIFY(src) \
16599 (!((((u_int32_t)(src)\
16606 #define RADIO130NM_RF5G1_CH1__OB5__READ(src) \
16607 (((u_int32_t)(src)\
16609 #define RADIO130NM_RF5G1_CH1__OB5__WRITE(src) \
16610 (((u_int32_t)(src)\
16612 #define RADIO130NM_RF5G1_CH1__OB5__MODIFY(dst, src) \
16614 ~0x00070000U) | (((u_int32_t)(src) <<\
16616 #define RADIO130NM_RF5G1_CH1__OB5__VERIFY(src) \
16617 (!((((u_int32_t)(src)\
16624 #define RADIO130NM_RF5G1_CH1__DB5__READ(src) \
16625 (((u_int32_t)(src)\
16627 #define RADIO130NM_RF5G1_CH1__DB5__WRITE(src) \
16628 (((u_int32_t)(src)\
16630 #define RADIO130NM_RF5G1_CH1__DB5__MODIFY(dst, src) \
16632 ~0x00380000U) | (((u_int32_t)(src) <<\
16634 #define RADIO130NM_RF5G1_CH1__DB5__VERIFY(src) \
16635 (!((((u_int32_t)(src)\
16642 #define RADIO130NM_RF5G1_CH1__PWDTXPKD__READ(src) \
16643 (((u_int32_t)(src)\
16645 #define RADIO130NM_RF5G1_CH1__PWDTXPKD__WRITE(src) \
16646 (((u_int32_t)(src)\
16648 #define RADIO130NM_RF5G1_CH1__PWDTXPKD__MODIFY(dst, src) \
16650 ~0x01c00000U) | (((u_int32_t)(src) <<\
16652 #define RADIO130NM_RF5G1_CH1__PWDTXPKD__VERIFY(src) \
16653 (!((((u_int32_t)(src)\
16660 #define RADIO130NM_RF5G1_CH1__PACASCBIAS__READ(src) \
16661 (((u_int32_t)(src)\
16663 #define RADIO130NM_RF5G1_CH1__PACASCBIAS__WRITE(src) \
16664 (((u_int32_t)(src)\
16666 #define RADIO130NM_RF5G1_CH1__PACASCBIAS__MODIFY(dst, src) \
16668 ~0x06000000U) | (((u_int32_t)(src) <<\
16670 #define RADIO130NM_RF5G1_CH1__PACASCBIAS__VERIFY(src) \
16671 (!((((u_int32_t)(src)\
16678 #define RADIO130NM_RF5G1_CH1__PDPAOUT5__READ(src) \
16679 (((u_int32_t)(src)\
16681 #define RADIO130NM_RF5G1_CH1__PDPAOUT5__WRITE(src) \
16682 (((u_int32_t)(src)\
16684 #define RADIO130NM_RF5G1_CH1__PDPAOUT5__MODIFY(dst, src) \
16686 ~0x08000000U) | (((u_int32_t)(src) <<\
16688 #define RADIO130NM_RF5G1_CH1__PDPAOUT5__VERIFY(src) \
16689 (!((((u_int32_t)(src)\
16702 #define RADIO130NM_RF5G1_CH1__PDPADRV5__READ(src) \
16703 (((u_int32_t)(src)\
16705 #define RADIO130NM_RF5G1_CH1__PDPADRV5__WRITE(src) \
16706 (((u_int32_t)(src)\
16708 #define RADIO130NM_RF5G1_CH1__PDPADRV5__MODIFY(dst, src) \
16710 ~0x10000000U) | (((u_int32_t)(src) <<\
16712 #define RADIO130NM_RF5G1_CH1__PDPADRV5__VERIFY(src) \
16713 (!((((u_int32_t)(src)\
16726 #define RADIO130NM_RF5G1_CH1__PDTXBUF5__READ(src) \
16727 (((u_int32_t)(src)\
16729 #define RADIO130NM_RF5G1_CH1__PDTXBUF5__WRITE(src) \
16730 (((u_int32_t)(src)\
16732 #define RADIO130NM_RF5G1_CH1__PDTXBUF5__MODIFY(dst, src) \
16734 ~0x20000000U) | (((u_int32_t)(src) <<\
16736 #define RADIO130NM_RF5G1_CH1__PDTXBUF5__VERIFY(src) \
16737 (!((((u_int32_t)(src)\
16750 #define RADIO130NM_RF5G1_CH1__PDTXMIX5__READ(src) \
16751 (((u_int32_t)(src)\
16753 #define RADIO130NM_RF5G1_CH1__PDTXMIX5__WRITE(src) \
16754 (((u_int32_t)(src)\
16756 #define RADIO130NM_RF5G1_CH1__PDTXMIX5__MODIFY(dst, src) \
16758 ~0x40000000U) | (((u_int32_t)(src) <<\
16760 #define RADIO130NM_RF5G1_CH1__PDTXMIX5__VERIFY(src) \
16761 (!((((u_int32_t)(src)\
16774 #define RADIO130NM_RF5G1_CH1__PDTXLO5__READ(src) \
16775 (((u_int32_t)(src)\
16777 #define RADIO130NM_RF5G1_CH1__PDTXLO5__WRITE(src) \
16778 (((u_int32_t)(src)\
16780 #define RADIO130NM_RF5G1_CH1__PDTXLO5__MODIFY(dst, src) \
16782 ~0x80000000U) | (((u_int32_t)(src) <<\
16784 #define RADIO130NM_RF5G1_CH1__PDTXLO5__VERIFY(src) \
16785 (!((((u_int32_t)(src)\
16811 #define RADIO130NM_RF5G2_CH1__SPARE__READ(src) (u_int32_t)(src) & 0x000007ffU
16812 #define RADIO130NM_RF5G2_CH1__SPARE__WRITE(src) \
16813 ((u_int32_t)(src)\
16815 #define RADIO130NM_RF5G2_CH1__SPARE__MODIFY(dst, src) \
16817 ~0x000007ffU) | ((u_int32_t)(src) &\
16819 #define RADIO130NM_RF5G2_CH1__SPARE__VERIFY(src) \
16820 (!(((u_int32_t)(src)\
16827 #define RADIO130NM_RF5G2_CH1__PDBIR2__READ(src) \
16828 (((u_int32_t)(src)\
16830 #define RADIO130NM_RF5G2_CH1__PDBIR2__WRITE(src) \
16831 (((u_int32_t)(src)\
16833 #define RADIO130NM_RF5G2_CH1__PDBIR2__MODIFY(dst, src) \
16835 ~0x00003800U) | (((u_int32_t)(src) <<\
16837 #define RADIO130NM_RF5G2_CH1__PDBIR2__VERIFY(src) \
16838 (!((((u_int32_t)(src)\
16845 #define RADIO130NM_RF5G2_CH1__PDBIR1__READ(src) \
16846 (((u_int32_t)(src)\
16848 #define RADIO130NM_RF5G2_CH1__PDBIR1__WRITE(src) \
16849 (((u_int32_t)(src)\
16851 #define RADIO130NM_RF5G2_CH1__PDBIR1__MODIFY(dst, src) \
16853 ~0x0001c000U) | (((u_int32_t)(src) <<\
16855 #define RADIO130NM_RF5G2_CH1__PDBIR1__VERIFY(src) \
16856 (!((((u_int32_t)(src)\
16863 #define RADIO130NM_RF5G2_CH1__PDBIRTXPA__READ(src) \
16864 (((u_int32_t)(src)\
16866 #define RADIO130NM_RF5G2_CH1__PDBIRTXPA__WRITE(src) \
16867 (((u_int32_t)(src)\
16869 #define RADIO130NM_RF5G2_CH1__PDBIRTXPA__MODIFY(dst, src) \
16871 ~0x000e0000U) | (((u_int32_t)(src) <<\
16873 #define RADIO130NM_RF5G2_CH1__PDBIRTXPA__VERIFY(src) \
16874 (!((((u_int32_t)(src)\
16881 #define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__READ(src) \
16882 (((u_int32_t)(src)\
16884 #define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__WRITE(src) \
16885 (((u_int32_t)(src)\
16887 #define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__MODIFY(dst, src) \
16889 ~0x00700000U) | (((u_int32_t)(src) <<\
16891 #define RADIO130NM_RF5G2_CH1__PDBIRTXMIX__VERIFY(src) \
16892 (!((((u_int32_t)(src)\
16899 #define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__READ(src) \
16900 (((u_int32_t)(src)\
16902 #define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__WRITE(src) \
16903 (((u_int32_t)(src)\
16905 #define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__MODIFY(dst, src) \
16907 ~0x03800000U) | (((u_int32_t)(src) <<\
16909 #define RADIO130NM_RF5G2_CH1__RX5_ATB_SEL__VERIFY(src) \
16910 (!((((u_int32_t)(src)\
16917 #define RADIO130NM_RF5G2_CH1__PDRFVGA5__READ(src) \
16918 (((u_int32_t)(src)\
16920 #define RADIO130NM_RF5G2_CH1__PDRFVGA5__WRITE(src) \
16921 (((u_int32_t)(src)\
16923 #define RADIO130NM_RF5G2_CH1__PDRFVGA5__MODIFY(dst, src) \
16925 ~0x04000000U) | (((u_int32_t)(src) <<\
16927 #define RADIO130NM_RF5G2_CH1__PDRFVGA5__VERIFY(src) \
16928 (!((((u_int32_t)(src)\
16941 #define RADIO130NM_RF5G2_CH1__PDCSLNA5__READ(src) \
16942 (((u_int32_t)(src)\
16944 #define RADIO130NM_RF5G2_CH1__PDCSLNA5__WRITE(src) \
16945 (((u_int32_t)(src)\
16947 #define RADIO130NM_RF5G2_CH1__PDCSLNA5__MODIFY(dst, src) \
16949 ~0x08000000U) | (((u_int32_t)(src) <<\
16951 #define RADIO130NM_RF5G2_CH1__PDCSLNA5__VERIFY(src) \
16952 (!((((u_int32_t)(src)\
16965 #define RADIO130NM_RF5G2_CH1__PDVGM5__READ(src) \
16966 (((u_int32_t)(src)\
16968 #define RADIO130NM_RF5G2_CH1__PDVGM5__WRITE(src) \
16969 (((u_int32_t)(src)\
16971 #define RADIO130NM_RF5G2_CH1__PDVGM5__MODIFY(dst, src) \
16973 ~0x10000000U) | (((u_int32_t)(src) <<\
16975 #define RADIO130NM_RF5G2_CH1__PDVGM5__VERIFY(src) \
16976 (!((((u_int32_t)(src)\
16989 #define RADIO130NM_RF5G2_CH1__PDRXLO5__READ(src) \
16990 (((u_int32_t)(src)\
16992 #define RADIO130NM_RF5G2_CH1__PDRXLO5__WRITE(src) \
16993 (((u_int32_t)(src)\
16995 #define RADIO130NM_RF5G2_CH1__PDRXLO5__MODIFY(dst, src) \
16997 ~0x20000000U) | (((u_int32_t)(src) <<\
16999 #define RADIO130NM_RF5G2_CH1__PDRXLO5__VERIFY(src) \
17000 (!((((u_int32_t)(src)\
17013 #define RADIO130NM_RF5G2_CH1__PDREGFE5__READ(src) \
17014 (((u_int32_t)(src)\
17016 #define RADIO130NM_RF5G2_CH1__PDREGFE5__WRITE(src) \
17017 (((u_int32_t)(src)\
17019 #define RADIO130NM_RF5G2_CH1__PDREGFE5__MODIFY(dst, src) \
17021 ~0x40000000U) | (((u_int32_t)(src) <<\
17023 #define RADIO130NM_RF5G2_CH1__PDREGFE5__VERIFY(src) \
17024 (!((((u_int32_t)(src)\
17037 #define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__READ(src) \
17038 (((u_int32_t)(src)\
17040 #define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__WRITE(src) \
17041 (((u_int32_t)(src)\
17043 #define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__MODIFY(dst, src) \
17045 ~0x80000000U) | (((u_int32_t)(src) <<\
17047 #define RADIO130NM_RF5G2_CH1__REGFE_BYPASS5__VERIFY(src) \
17048 (!((((u_int32_t)(src)\
17074 #define RADIO130NM_RF5G3_CH1__SPARE__READ(src) (u_int32_t)(src) & 0x0000001fU
17075 #define RADIO130NM_RF5G3_CH1__SPARE__WRITE(src) \
17076 ((u_int32_t)(src)\
17078 #define RADIO130NM_RF5G3_CH1__SPARE__MODIFY(dst, src) \
17080 ~0x0000001fU) | ((u_int32_t)(src) &\
17082 #define RADIO130NM_RF5G3_CH1__SPARE__VERIFY(src) \
17083 (!(((u_int32_t)(src)\
17090 #define RADIO130NM_RF5G3_CH1__PDBIBCVGM__READ(src) \
17091 (((u_int32_t)(src)\
17093 #define RADIO130NM_RF5G3_CH1__PDBIBCVGM__WRITE(src) \
17094 (((u_int32_t)(src)\
17096 #define RADIO130NM_RF5G3_CH1__PDBIBCVGM__MODIFY(dst, src) \
17098 ~0x000000e0U) | (((u_int32_t)(src) <<\
17100 #define RADIO130NM_RF5G3_CH1__PDBIBCVGM__VERIFY(src) \
17101 (!((((u_int32_t)(src)\
17108 #define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__READ(src) \
17109 (((u_int32_t)(src)\
17111 #define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__WRITE(src) \
17112 (((u_int32_t)(src)\
17114 #define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__MODIFY(dst, src) \
17116 ~0x00000700U) | (((u_int32_t)(src) <<\
17118 #define RADIO130NM_RF5G3_CH1__PDBIBCRFVGA__VERIFY(src) \
17119 (!((((u_int32_t)(src)\
17126 #define RADIO130NM_RF5G3_CH1__PDBIBCLNA__READ(src) \
17127 (((u_int32_t)(src)\
17129 #define RADIO130NM_RF5G3_CH1__PDBIBCLNA__WRITE(src) \
17130 (((u_int32_t)(src)\
17132 #define RADIO130NM_RF5G3_CH1__PDBIBCLNA__MODIFY(dst, src) \
17134 ~0x00003800U) | (((u_int32_t)(src) <<\
17136 #define RADIO130NM_RF5G3_CH1__PDBIBCLNA__VERIFY(src) \
17137 (!((((u_int32_t)(src)\
17144 #define RADIO130NM_RF5G3_CH1__PDBIC3__READ(src) \
17145 (((u_int32_t)(src)\
17147 #define RADIO130NM_RF5G3_CH1__PDBIC3__WRITE(src) \
17148 (((u_int32_t)(src)\
17150 #define RADIO130NM_RF5G3_CH1__PDBIC3__MODIFY(dst, src) \
17152 ~0x0001c000U) | (((u_int32_t)(src) <<\
17154 #define RADIO130NM_RF5G3_CH1__PDBIC3__VERIFY(src) \
17155 (!((((u_int32_t)(src)\
17162 #define RADIO130NM_RF5G3_CH1__PDBIC2__READ(src) \
17163 (((u_int32_t)(src)\
17165 #define RADIO130NM_RF5G3_CH1__PDBIC2__WRITE(src) \
17166 (((u_int32_t)(src)\
17168 #define RADIO130NM_RF5G3_CH1__PDBIC2__MODIFY(dst, src) \
17170 ~0x000e0000U) | (((u_int32_t)(src) <<\
17172 #define RADIO130NM_RF5G3_CH1__PDBIC2__VERIFY(src) \
17173 (!((((u_int32_t)(src)\
17180 #define RADIO130NM_RF5G3_CH1__PDBIC1__READ(src) \
17181 (((u_int32_t)(src)\
17183 #define RADIO130NM_RF5G3_CH1__PDBIC1__WRITE(src) \
17184 (((u_int32_t)(src)\
17186 #define RADIO130NM_RF5G3_CH1__PDBIC1__MODIFY(dst, src) \
17188 ~0x00700000U) | (((u_int32_t)(src) <<\
17190 #define RADIO130NM_RF5G3_CH1__PDBIC1__VERIFY(src) \
17191 (!((((u_int32_t)(src)\
17198 #define RADIO130NM_RF5G3_CH1__PDBICTXMIX__READ(src) \
17199 (((u_int32_t)(src)\
17201 #define RADIO130NM_RF5G3_CH1__PDBICTXMIX__WRITE(src) \
17202 (((u_int32_t)(src)\
17204 #define RADIO130NM_RF5G3_CH1__PDBICTXMIX__MODIFY(dst, src) \
17206 ~0x03800000U) | (((u_int32_t)(src) <<\
17208 #define RADIO130NM_RF5G3_CH1__PDBICTXMIX__VERIFY(src) \
17209 (!((((u_int32_t)(src)\
17216 #define RADIO130NM_RF5G3_CH1__PDBICTXPA__READ(src) \
17217 (((u_int32_t)(src)\
17219 #define RADIO130NM_RF5G3_CH1__PDBICTXPA__WRITE(src) \
17220 (((u_int32_t)(src)\
17222 #define RADIO130NM_RF5G3_CH1__PDBICTXPA__MODIFY(dst, src) \
17224 ~0x1c000000U) | (((u_int32_t)(src) <<\
17226 #define RADIO130NM_RF5G3_CH1__PDBICTXPA__VERIFY(src) \
17227 (!((((u_int32_t)(src)\
17234 #define RADIO130NM_RF5G3_CH1__PDBICTXBUF__READ(src) \
17235 (((u_int32_t)(src)\
17237 #define RADIO130NM_RF5G3_CH1__PDBICTXBUF__WRITE(src) \
17238 (((u_int32_t)(src)\
17240 #define RADIO130NM_RF5G3_CH1__PDBICTXBUF__MODIFY(dst, src) \
17242 ~0xe0000000U) | (((u_int32_t)(src) <<\
17244 #define RADIO130NM_RF5G3_CH1__PDBICTXBUF__VERIFY(src) \
17245 (!((((u_int32_t)(src)\
17265 #define RADIO130NM_RXTXBB1_CH0__PDHIQ__READ(src) (u_int32_t)(src) & 0x00000001U
17266 #define RADIO130NM_RXTXBB1_CH0__PDHIQ__WRITE(src) \
17267 ((u_int32_t)(src)\
17269 #define RADIO130NM_RXTXBB1_CH0__PDHIQ__MODIFY(dst, src) \
17271 ~0x00000001U) | ((u_int32_t)(src) &\
17273 #define RADIO130NM_RXTXBB1_CH0__PDHIQ__VERIFY(src) \
17274 (!(((u_int32_t)(src)\
17287 #define RADIO130NM_RXTXBB1_CH0__PDLOQ__READ(src) \
17288 (((u_int32_t)(src)\
17290 #define RADIO130NM_RXTXBB1_CH0__PDLOQ__WRITE(src) \
17291 (((u_int32_t)(src)\
17293 #define RADIO130NM_RXTXBB1_CH0__PDLOQ__MODIFY(dst, src) \
17295 ~0x00000002U) | (((u_int32_t)(src) <<\
17297 #define RADIO130NM_RXTXBB1_CH0__PDLOQ__VERIFY(src) \
17298 (!((((u_int32_t)(src)\
17311 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__READ(src) \
17312 (((u_int32_t)(src)\
17314 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__WRITE(src) \
17315 (((u_int32_t)(src)\
17317 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__MODIFY(dst, src) \
17319 ~0x00000004U) | (((u_int32_t)(src) <<\
17321 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETI2V__VERIFY(src) \
17322 (!((((u_int32_t)(src)\
17335 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__READ(src) \
17336 (((u_int32_t)(src)\
17338 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__WRITE(src) \
17339 (((u_int32_t)(src)\
17341 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__MODIFY(dst, src) \
17343 ~0x00000008U) | (((u_int32_t)(src) <<\
17345 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETHIQ__VERIFY(src) \
17346 (!((((u_int32_t)(src)\
17359 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__READ(src) \
17360 (((u_int32_t)(src)\
17362 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__WRITE(src) \
17363 (((u_int32_t)(src)\
17365 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__MODIFY(dst, src) \
17367 ~0x00000010U) | (((u_int32_t)(src) <<\
17369 #define RADIO130NM_RXTXBB1_CH0__PDOFFSETLOQ__VERIFY(src) \
17370 (!((((u_int32_t)(src)\
17383 #define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__READ(src) \
17384 (((u_int32_t)(src)\
17386 #define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__WRITE(src) \
17387 (((u_int32_t)(src)\
17389 #define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__MODIFY(dst, src) \
17391 ~0x00000020U) | (((u_int32_t)(src) <<\
17393 #define RADIO130NM_RXTXBB1_CH0__PDRXTXBB__VERIFY(src) \
17394 (!((((u_int32_t)(src)\
17407 #define RADIO130NM_RXTXBB1_CH0__PDI2V__READ(src) \
17408 (((u_int32_t)(src)\
17410 #define RADIO130NM_RXTXBB1_CH0__PDI2V__WRITE(src) \
17411 (((u_int32_t)(src)\
17413 #define RADIO130NM_RXTXBB1_CH0__PDI2V__MODIFY(dst, src) \
17415 ~0x00000040U) | (((u_int32_t)(src) <<\
17417 #define RADIO130NM_RXTXBB1_CH0__PDI2V__VERIFY(src) \
17418 (!((((u_int32_t)(src)\
17431 #define RADIO130NM_RXTXBB1_CH0__PDV2I__READ(src) \
17432 (((u_int32_t)(src)\
17434 #define RADIO130NM_RXTXBB1_CH0__PDV2I__WRITE(src) \
17435 (((u_int32_t)(src)\
17437 #define RADIO130NM_RXTXBB1_CH0__PDV2I__MODIFY(dst, src) \
17439 ~0x00000080U) | (((u_int32_t)(src) <<\
17441 #define RADIO130NM_RXTXBB1_CH0__PDV2I__VERIFY(src) \
17442 (!((((u_int32_t)(src)\
17455 #define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__READ(src) \
17456 (((u_int32_t)(src)\
17458 #define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__WRITE(src) \
17459 (((u_int32_t)(src)\
17461 #define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__MODIFY(dst, src) \
17463 ~0x00000100U) | (((u_int32_t)(src) <<\
17465 #define RADIO130NM_RXTXBB1_CH0__PDDACINTERFACE__VERIFY(src) \
17466 (!((((u_int32_t)(src)\
17479 #define RADIO130NM_RXTXBB1_CH0__SEL_ATB__READ(src) \
17480 (((u_int32_t)(src)\
17482 #define RADIO130NM_RXTXBB1_CH0__SEL_ATB__WRITE(src) \
17483 (((u_int32_t)(src)\
17485 #define RADIO130NM_RXTXBB1_CH0__SEL_ATB__MODIFY(dst, src) \
17487 ~0x0001fe00U) | (((u_int32_t)(src) <<\
17489 #define RADIO130NM_RXTXBB1_CH0__SEL_ATB__VERIFY(src) \
17490 (!((((u_int32_t)(src)\
17497 #define RADIO130NM_RXTXBB1_CH0__FNOTCH__READ(src) \
17498 (((u_int32_t)(src)\
17500 #define RADIO130NM_RXTXBB1_CH0__FNOTCH__WRITE(src) \
17501 (((u_int32_t)(src)\
17503 #define RADIO130NM_RXTXBB1_CH0__FNOTCH__MODIFY(dst, src) \
17505 ~0x00060000U) | (((u_int32_t)(src) <<\
17507 #define RADIO130NM_RXTXBB1_CH0__FNOTCH__VERIFY(src) \
17508 (!((((u_int32_t)(src)\
17515 #define RADIO130NM_RXTXBB1_CH0__SPARE__READ(src) \
17516 (((u_int32_t)(src)\
17518 #define RADIO130NM_RXTXBB1_CH0__SPARE__WRITE(src) \
17519 (((u_int32_t)(src)\
17521 #define RADIO130NM_RXTXBB1_CH0__SPARE__MODIFY(dst, src) \
17523 ~0xfff80000U) | (((u_int32_t)(src) <<\
17525 #define RADIO130NM_RXTXBB1_CH0__SPARE__VERIFY(src) \
17526 (!((((u_int32_t)(src)\
17546 #define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__READ(src) \
17547 (u_int32_t)(src)\
17549 #define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__WRITE(src) \
17550 ((u_int32_t)(src)\
17552 #define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__MODIFY(dst, src) \
17554 ~0x00000001U) | ((u_int32_t)(src) &\
17556 #define RADIO130NM_RXTXBB2_CH0__PATH_OVERRIDE__VERIFY(src) \
17557 (!(((u_int32_t)(src)\
17570 #define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__READ(src) \
17571 (((u_int32_t)(src)\
17573 #define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__WRITE(src) \
17574 (((u_int32_t)(src)\
17576 #define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__MODIFY(dst, src) \
17578 ~0x00000002U) | (((u_int32_t)(src) <<\
17580 #define RADIO130NM_RXTXBB2_CH0__PATH1LOQ_EN__VERIFY(src) \
17581 (!((((u_int32_t)(src)\
17594 #define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__READ(src) \
17595 (((u_int32_t)(src)\
17597 #define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__WRITE(src) \
17598 (((u_int32_t)(src)\
17600 #define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__MODIFY(dst, src) \
17602 ~0x00000004U) | (((u_int32_t)(src) <<\
17604 #define RADIO130NM_RXTXBB2_CH0__PATH2LOQ_EN__VERIFY(src) \
17605 (!((((u_int32_t)(src)\
17618 #define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__READ(src) \
17619 (((u_int32_t)(src)\
17621 #define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__WRITE(src) \
17622 (((u_int32_t)(src)\
17624 #define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__MODIFY(dst, src) \
17626 ~0x00000008U) | (((u_int32_t)(src) <<\
17628 #define RADIO130NM_RXTXBB2_CH0__PATH3LOQ_EN__VERIFY(src) \
17629 (!((((u_int32_t)(src)\
17642 #define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__READ(src) \
17643 (((u_int32_t)(src)\
17645 #define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__WRITE(src) \
17646 (((u_int32_t)(src)\
17648 #define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__MODIFY(dst, src) \
17650 ~0x00000010U) | (((u_int32_t)(src) <<\
17652 #define RADIO130NM_RXTXBB2_CH0__PATH1HIQ_EN__VERIFY(src) \
17653 (!((((u_int32_t)(src)\
17666 #define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__READ(src) \
17667 (((u_int32_t)(src)\
17669 #define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__WRITE(src) \
17670 (((u_int32_t)(src)\
17672 #define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__MODIFY(dst, src) \
17674 ~0x00000020U) | (((u_int32_t)(src) <<\
17676 #define RADIO130NM_RXTXBB2_CH0__PATH2HIQ_EN__VERIFY(src) \
17677 (!((((u_int32_t)(src)\
17690 #define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__READ(src) \
17691 (((u_int32_t)(src)\
17693 #define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__WRITE(src) \
17694 (((u_int32_t)(src)\
17696 #define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__MODIFY(dst, src) \
17698 ~0x00000040U) | (((u_int32_t)(src) <<\
17700 #define RADIO130NM_RXTXBB2_CH0__FILTERDOUBLEBW__VERIFY(src) \
17701 (!((((u_int32_t)(src)\
17714 #define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__READ(src) \
17715 (((u_int32_t)(src)\
17717 #define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__WRITE(src) \
17718 (((u_int32_t)(src)\
17720 #define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__MODIFY(dst, src) \
17722 ~0x00000080U) | (((u_int32_t)(src) <<\
17724 #define RADIO130NM_RXTXBB2_CH0__LOCALFILTERTUNING__VERIFY(src) \
17725 (!((((u_int32_t)(src)\
17738 #define RADIO130NM_RXTXBB2_CH0__FILTERFC__READ(src) \
17739 (((u_int32_t)(src)\
17741 #define RADIO130NM_RXTXBB2_CH0__FILTERFC__WRITE(src) \
17742 (((u_int32_t)(src)\
17744 #define RADIO130NM_RXTXBB2_CH0__FILTERFC__MODIFY(dst, src) \
17746 ~0x00001f00U) | (((u_int32_t)(src) <<\
17748 #define RADIO130NM_RXTXBB2_CH0__FILTERFC__VERIFY(src) \
17749 (!((((u_int32_t)(src)\
17756 #define RADIO130NM_RXTXBB2_CH0__CMSEL__READ(src) \
17757 (((u_int32_t)(src)\
17759 #define RADIO130NM_RXTXBB2_CH0__CMSEL__WRITE(src) \
17760 (((u_int32_t)(src)\
17762 #define RADIO130NM_RXTXBB2_CH0__CMSEL__MODIFY(dst, src) \
17764 ~0x00006000U) | (((u_int32_t)(src) <<\
17766 #define RADIO130NM_RXTXBB2_CH0__CMSEL__VERIFY(src) \
17767 (!((((u_int32_t)(src)\
17774 #define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__READ(src) \
17775 (((u_int32_t)(src)\
17777 #define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__WRITE(src) \
17778 (((u_int32_t)(src)\
17780 #define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__MODIFY(dst, src) \
17782 ~0x00008000U) | (((u_int32_t)(src) <<\
17784 #define RADIO130NM_RXTXBB2_CH0__SEL_I2V_TEST__VERIFY(src) \
17785 (!((((u_int32_t)(src)\
17798 #define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__READ(src) \
17799 (((u_int32_t)(src)\
17801 #define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__WRITE(src) \
17802 (((u_int32_t)(src)\
17804 #define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__MODIFY(dst, src) \
17806 ~0x00010000U) | (((u_int32_t)(src) <<\
17808 #define RADIO130NM_RXTXBB2_CH0__SEL_HIQ_TEST__VERIFY(src) \
17809 (!((((u_int32_t)(src)\
17822 #define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__READ(src) \
17823 (((u_int32_t)(src)\
17825 #define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__WRITE(src) \
17826 (((u_int32_t)(src)\
17828 #define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__MODIFY(dst, src) \
17830 ~0x00020000U) | (((u_int32_t)(src) <<\
17832 #define RADIO130NM_RXTXBB2_CH0__SEL_LOQ_TEST__VERIFY(src) \
17833 (!((((u_int32_t)(src)\
17846 #define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__READ(src) \
17847 (((u_int32_t)(src)\
17849 #define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__WRITE(src) \
17850 (((u_int32_t)(src)\
17852 #define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__MODIFY(dst, src) \
17854 ~0x00040000U) | (((u_int32_t)(src) <<\
17856 #define RADIO130NM_RXTXBB2_CH0__SEL_DAC_TEST__VERIFY(src) \
17857 (!((((u_int32_t)(src)\
17870 #define RADIO130NM_RXTXBB2_CH0__SELBUFFER__READ(src) \
17871 (((u_int32_t)(src)\
17873 #define RADIO130NM_RXTXBB2_CH0__SELBUFFER__WRITE(src) \
17874 (((u_int32_t)(src)\
17876 #define RADIO130NM_RXTXBB2_CH0__SELBUFFER__MODIFY(dst, src) \
17878 ~0x00080000U) | (((u_int32_t)(src) <<\
17880 #define RADIO130NM_RXTXBB2_CH0__SELBUFFER__VERIFY(src) \
17881 (!((((u_int32_t)(src)\
17894 #define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__READ(src) \
17895 (((u_int32_t)(src)\
17897 #define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__WRITE(src) \
17898 (((u_int32_t)(src)\
17900 #define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__MODIFY(dst, src) \
17902 ~0x00100000U) | (((u_int32_t)(src) <<\
17904 #define RADIO130NM_RXTXBB2_CH0__SHORTBUFFER__VERIFY(src) \
17905 (!((((u_int32_t)(src)\
17918 #define RADIO130NM_RXTXBB2_CH0__SPARE__READ(src) \
17919 (((u_int32_t)(src)\
17921 #define RADIO130NM_RXTXBB2_CH0__SPARE__WRITE(src) \
17922 (((u_int32_t)(src)\
17924 #define RADIO130NM_RXTXBB2_CH0__SPARE__MODIFY(dst, src) \
17926 ~0x00600000U) | (((u_int32_t)(src) <<\
17928 #define RADIO130NM_RXTXBB2_CH0__SPARE__VERIFY(src) \
17929 (!((((u_int32_t)(src)\
17936 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__READ(src) \
17937 (((u_int32_t)(src)\
17939 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__WRITE(src) \
17940 (((u_int32_t)(src)\
17942 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__MODIFY(dst, src) \
17944 ~0x03800000U) | (((u_int32_t)(src) <<\
17946 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSI2V_CTRL__VERIFY(src) \
17947 (!((((u_int32_t)(src)\
17954 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__READ(src) \
17955 (((u_int32_t)(src)\
17957 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__WRITE(src) \
17958 (((u_int32_t)(src)\
17960 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__MODIFY(dst, src) \
17962 ~0x1c000000U) | (((u_int32_t)(src) <<\
17964 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSLO_CTRL__VERIFY(src) \
17965 (!((((u_int32_t)(src)\
17972 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__READ(src) \
17973 (((u_int32_t)(src)\
17975 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__WRITE(src) \
17976 (((u_int32_t)(src)\
17978 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__MODIFY(dst, src) \
17980 ~0xe0000000U) | (((u_int32_t)(src) <<\
17982 #define RADIO130NM_RXTXBB2_CH0__IBN_37P5_OSHI_CTRL__VERIFY(src) \
17983 (!((((u_int32_t)(src)\
18003 #define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__READ(src) \
18004 (u_int32_t)(src)\
18006 #define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__WRITE(src) \
18007 ((u_int32_t)(src)\
18009 #define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__MODIFY(dst, src) \
18011 ~0x00000007U) | ((u_int32_t)(src) &\
18013 #define RADIO130NM_RXTXBB3_CH0__IBN_100U_TEST_CTRL__VERIFY(src) \
18014 (!(((u_int32_t)(src)\
18021 #define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__READ(src) \
18022 (((u_int32_t)(src)\
18024 #define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__WRITE(src) \
18025 (((u_int32_t)(src)\
18027 #define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__MODIFY(dst, src) \
18029 ~0x00000038U) | (((u_int32_t)(src) <<\
18031 #define RADIO130NM_RXTXBB3_CH0__IBRN_12P5_CM_CTRL__VERIFY(src) \
18032 (!((((u_int32_t)(src)\
18039 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__READ(src) \
18040 (((u_int32_t)(src)\
18042 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__WRITE(src) \
18043 (((u_int32_t)(src)\
18045 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__MODIFY(dst, src) \
18047 ~0x000001c0U) | (((u_int32_t)(src) <<\
18049 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO2_CTRL__VERIFY(src) \
18050 (!((((u_int32_t)(src)\
18057 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__READ(src) \
18058 (((u_int32_t)(src)\
18060 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__WRITE(src) \
18061 (((u_int32_t)(src)\
18063 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__MODIFY(dst, src) \
18065 ~0x00000e00U) | (((u_int32_t)(src) <<\
18067 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_LO1_CTRL__VERIFY(src) \
18068 (!((((u_int32_t)(src)\
18075 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__READ(src) \
18076 (((u_int32_t)(src)\
18078 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__WRITE(src) \
18079 (((u_int32_t)(src)\
18081 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__MODIFY(dst, src) \
18083 ~0x00007000U) | (((u_int32_t)(src) <<\
18085 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI2_CTRL__VERIFY(src) \
18086 (!((((u_int32_t)(src)\
18093 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__READ(src) \
18094 (((u_int32_t)(src)\
18096 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__WRITE(src) \
18097 (((u_int32_t)(src)\
18099 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__MODIFY(dst, src) \
18101 ~0x00038000U) | (((u_int32_t)(src) <<\
18103 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_HI1_CTRL__VERIFY(src) \
18104 (!((((u_int32_t)(src)\
18111 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__READ(src) \
18112 (((u_int32_t)(src)\
18114 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__WRITE(src) \
18115 (((u_int32_t)(src)\
18117 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__MODIFY(dst, src) \
18119 ~0x001c0000U) | (((u_int32_t)(src) <<\
18121 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_I2V_CTRL__VERIFY(src) \
18122 (!((((u_int32_t)(src)\
18129 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__READ(src) \
18130 (((u_int32_t)(src)\
18132 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__WRITE(src) \
18133 (((u_int32_t)(src)\
18135 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__MODIFY(dst, src) \
18137 ~0x00e00000U) | (((u_int32_t)(src) <<\
18139 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_BKV2I_CTRL__VERIFY(src) \
18140 (!((((u_int32_t)(src)\
18147 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__READ(src) \
18148 (((u_int32_t)(src)\
18150 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__WRITE(src) \
18151 (((u_int32_t)(src)\
18153 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__MODIFY(dst, src) \
18155 ~0x07000000U) | (((u_int32_t)(src) <<\
18157 #define RADIO130NM_RXTXBB3_CH0__IBN_25U_CM_BUFAMP_CTRL__VERIFY(src) \
18158 (!((((u_int32_t)(src)\
18165 #define RADIO130NM_RXTXBB3_CH0__SPARE__READ(src) \
18166 (((u_int32_t)(src)\
18168 #define RADIO130NM_RXTXBB3_CH0__SPARE__WRITE(src) \
18169 (((u_int32_t)(src)\
18171 #define RADIO130NM_RXTXBB3_CH0__SPARE__MODIFY(dst, src) \
18173 ~0xf8000000U) | (((u_int32_t)(src) <<\
18175 #define RADIO130NM_RXTXBB3_CH0__SPARE__VERIFY(src) \
18176 (!((((u_int32_t)(src)\
18196 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__READ(src) \
18197 (u_int32_t)(src)\
18199 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__WRITE(src) \
18200 ((u_int32_t)(src)\
18202 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__MODIFY(dst, src) \
18204 ~0x0000001fU) | ((u_int32_t)(src) &\
18206 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VQ__VERIFY(src) \
18207 (!(((u_int32_t)(src)\
18214 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__READ(src) \
18215 (((u_int32_t)(src)\
18217 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__WRITE(src) \
18218 (((u_int32_t)(src)\
18220 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__MODIFY(dst, src) \
18222 ~0x000003e0U) | (((u_int32_t)(src) <<\
18224 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRI2VI__VERIFY(src) \
18225 (!((((u_int32_t)(src)\
18232 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__READ(src) \
18233 (((u_int32_t)(src)\
18235 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__WRITE(src) \
18236 (((u_int32_t)(src)\
18238 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__MODIFY(dst, src) \
18240 ~0x00007c00U) | (((u_int32_t)(src) <<\
18242 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOQ__VERIFY(src) \
18243 (!((((u_int32_t)(src)\
18250 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__READ(src) \
18251 (((u_int32_t)(src)\
18253 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__WRITE(src) \
18254 (((u_int32_t)(src)\
18256 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__MODIFY(dst, src) \
18258 ~0x000f8000U) | (((u_int32_t)(src) <<\
18260 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRLOI__VERIFY(src) \
18261 (!((((u_int32_t)(src)\
18268 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__READ(src) \
18269 (((u_int32_t)(src)\
18271 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__WRITE(src) \
18272 (((u_int32_t)(src)\
18274 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__MODIFY(dst, src) \
18276 ~0x01f00000U) | (((u_int32_t)(src) <<\
18278 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRHIQ__VERIFY(src) \
18279 (!((((u_int32_t)(src)\
18286 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__READ(src) \
18287 (((u_int32_t)(src)\
18289 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__WRITE(src) \
18290 (((u_int32_t)(src)\
18292 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__MODIFY(dst, src) \
18294 ~0x3e000000U) | (((u_int32_t)(src) <<\
18296 #define RADIO130NM_RXTXBB4_CH0__OFSTCORRHII__VERIFY(src) \
18297 (!((((u_int32_t)(src)\
18304 #define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__READ(src) \
18305 (((u_int32_t)(src)\
18307 #define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__WRITE(src) \
18308 (((u_int32_t)(src)\
18310 #define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__MODIFY(dst, src) \
18312 ~0x40000000U) | (((u_int32_t)(src) <<\
18314 #define RADIO130NM_RXTXBB4_CH0__LOCALOFFSET__VERIFY(src) \
18315 (!((((u_int32_t)(src)\
18328 #define RADIO130NM_RXTXBB4_CH0__SPARE__READ(src) \
18329 (((u_int32_t)(src)\
18331 #define RADIO130NM_RXTXBB4_CH0__SPARE__WRITE(src) \
18332 (((u_int32_t)(src)\
18334 #define RADIO130NM_RXTXBB4_CH0__SPARE__MODIFY(dst, src) \
18336 ~0x80000000U) | (((u_int32_t)(src) <<\
18338 #define RADIO130NM_RXTXBB4_CH0__SPARE__VERIFY(src) \
18339 (!((((u_int32_t)(src)\
18365 #define RADIO130NM_RF5G1_CH0__SPARE__READ(src) (u_int32_t)(src) & 0x000003ffU
18366 #define RADIO130NM_RF5G1_CH0__SPARE__WRITE(src) \
18367 ((u_int32_t)(src)\
18369 #define RADIO130NM_RF5G1_CH0__SPARE__MODIFY(dst, src) \
18371 ~0x000003ffU) | ((u_int32_t)(src) &\
18373 #define RADIO130NM_RF5G1_CH0__SPARE__VERIFY(src) \
18374 (!(((u_int32_t)(src)\
18381 #define RADIO130NM_RF5G1_CH0__PDREGLO5__READ(src) \
18382 (((u_int32_t)(src)\
18384 #define RADIO130NM_RF5G1_CH0__PDREGLO5__WRITE(src) \
18385 (((u_int32_t)(src)\
18387 #define RADIO130NM_RF5G1_CH0__PDREGLO5__MODIFY(dst, src) \
18389 ~0x00000400U) | (((u_int32_t)(src) <<\
18391 #define RADIO130NM_RF5G1_CH0__PDREGLO5__VERIFY(src) \
18392 (!((((u_int32_t)(src)\
18405 #define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__READ(src) \
18406 (((u_int32_t)(src)\
18408 #define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__WRITE(src) \
18409 (((u_int32_t)(src)\
18411 #define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__MODIFY(dst, src) \
18413 ~0x00000800U) | (((u_int32_t)(src) <<\
18415 #define RADIO130NM_RF5G1_CH0__REGLO_BYPASS5__VERIFY(src) \
18416 (!((((u_int32_t)(src)\
18429 #define RADIO130NM_RF5G1_CH0__LO5CONTROL__READ(src) \
18430 (((u_int32_t)(src)\
18432 #define RADIO130NM_RF5G1_CH0__LO5CONTROL__WRITE(src) \
18433 (((u_int32_t)(src)\
18435 #define RADIO130NM_RF5G1_CH0__LO5CONTROL__MODIFY(dst, src) \
18437 ~0x00001000U) | (((u_int32_t)(src) <<\
18439 #define RADIO130NM_RF5G1_CH0__LO5CONTROL__VERIFY(src) \
18440 (!((((u_int32_t)(src)\
18453 #define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__READ(src) \
18454 (((u_int32_t)(src)\
18456 #define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__WRITE(src) \
18457 (((u_int32_t)(src)\
18459 #define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__MODIFY(dst, src) \
18461 ~0x0000e000U) | (((u_int32_t)(src) <<\
18463 #define RADIO130NM_RF5G1_CH0__TX5_ATB_SEL__VERIFY(src) \
18464 (!((((u_int32_t)(src)\
18471 #define RADIO130NM_RF5G1_CH0__OB5__READ(src) \
18472 (((u_int32_t)(src)\
18474 #define RADIO130NM_RF5G1_CH0__OB5__WRITE(src) \
18475 (((u_int32_t)(src)\
18477 #define RADIO130NM_RF5G1_CH0__OB5__MODIFY(dst, src) \
18479 ~0x00070000U) | (((u_int32_t)(src) <<\
18481 #define RADIO130NM_RF5G1_CH0__OB5__VERIFY(src) \
18482 (!((((u_int32_t)(src)\
18489 #define RADIO130NM_RF5G1_CH0__DB5__READ(src) \
18490 (((u_int32_t)(src)\
18492 #define RADIO130NM_RF5G1_CH0__DB5__WRITE(src) \
18493 (((u_int32_t)(src)\
18495 #define RADIO130NM_RF5G1_CH0__DB5__MODIFY(dst, src) \
18497 ~0x00380000U) | (((u_int32_t)(src) <<\
18499 #define RADIO130NM_RF5G1_CH0__DB5__VERIFY(src) \
18500 (!((((u_int32_t)(src)\
18507 #define RADIO130NM_RF5G1_CH0__PWDTXPKD__READ(src) \
18508 (((u_int32_t)(src)\
18510 #define RADIO130NM_RF5G1_CH0__PWDTXPKD__WRITE(src) \
18511 (((u_int32_t)(src)\
18513 #define RADIO130NM_RF5G1_CH0__PWDTXPKD__MODIFY(dst, src) \
18515 ~0x01c00000U) | (((u_int32_t)(src) <<\
18517 #define RADIO130NM_RF5G1_CH0__PWDTXPKD__VERIFY(src) \
18518 (!((((u_int32_t)(src)\
18525 #define RADIO130NM_RF5G1_CH0__PACASCBIAS__READ(src) \
18526 (((u_int32_t)(src)\
18528 #define RADIO130NM_RF5G1_CH0__PACASCBIAS__WRITE(src) \
18529 (((u_int32_t)(src)\
18531 #define RADIO130NM_RF5G1_CH0__PACASCBIAS__MODIFY(dst, src) \
18533 ~0x06000000U) | (((u_int32_t)(src) <<\
18535 #define RADIO130NM_RF5G1_CH0__PACASCBIAS__VERIFY(src) \
18536 (!((((u_int32_t)(src)\
18543 #define RADIO130NM_RF5G1_CH0__PDPAOUT5__READ(src) \
18544 (((u_int32_t)(src)\
18546 #define RADIO130NM_RF5G1_CH0__PDPAOUT5__WRITE(src) \
18547 (((u_int32_t)(src)\
18549 #define RADIO130NM_RF5G1_CH0__PDPAOUT5__MODIFY(dst, src) \
18551 ~0x08000000U) | (((u_int32_t)(src) <<\
18553 #define RADIO130NM_RF5G1_CH0__PDPAOUT5__VERIFY(src) \
18554 (!((((u_int32_t)(src)\
18567 #define RADIO130NM_RF5G1_CH0__PDPADRV5__READ(src) \
18568 (((u_int32_t)(src)\
18570 #define RADIO130NM_RF5G1_CH0__PDPADRV5__WRITE(src) \
18571 (((u_int32_t)(src)\
18573 #define RADIO130NM_RF5G1_CH0__PDPADRV5__MODIFY(dst, src) \
18575 ~0x10000000U) | (((u_int32_t)(src) <<\
18577 #define RADIO130NM_RF5G1_CH0__PDPADRV5__VERIFY(src) \
18578 (!((((u_int32_t)(src)\
18591 #define RADIO130NM_RF5G1_CH0__PDTXBUF5__READ(src) \
18592 (((u_int32_t)(src)\
18594 #define RADIO130NM_RF5G1_CH0__PDTXBUF5__WRITE(src) \
18595 (((u_int32_t)(src)\
18597 #define RADIO130NM_RF5G1_CH0__PDTXBUF5__MODIFY(dst, src) \
18599 ~0x20000000U) | (((u_int32_t)(src) <<\
18601 #define RADIO130NM_RF5G1_CH0__PDTXBUF5__VERIFY(src) \
18602 (!((((u_int32_t)(src)\
18615 #define RADIO130NM_RF5G1_CH0__PDTXMIX5__READ(src) \
18616 (((u_int32_t)(src)\
18618 #define RADIO130NM_RF5G1_CH0__PDTXMIX5__WRITE(src) \
18619 (((u_int32_t)(src)\
18621 #define RADIO130NM_RF5G1_CH0__PDTXMIX5__MODIFY(dst, src) \
18623 ~0x40000000U) | (((u_int32_t)(src) <<\
18625 #define RADIO130NM_RF5G1_CH0__PDTXMIX5__VERIFY(src) \
18626 (!((((u_int32_t)(src)\
18639 #define RADIO130NM_RF5G1_CH0__PDTXLO5__READ(src) \
18640 (((u_int32_t)(src)\
18642 #define RADIO130NM_RF5G1_CH0__PDTXLO5__WRITE(src) \
18643 (((u_int32_t)(src)\
18645 #define RADIO130NM_RF5G1_CH0__PDTXLO5__MODIFY(dst, src) \
18647 ~0x80000000U) | (((u_int32_t)(src) <<\
18649 #define RADIO130NM_RF5G1_CH0__PDTXLO5__VERIFY(src) \
18650 (!((((u_int32_t)(src)\
18676 #define RADIO130NM_RF5G2_CH0__SPARE__READ(src) (u_int32_t)(src) & 0x000007ffU
18677 #define RADIO130NM_RF5G2_CH0__SPARE__WRITE(src) \
18678 ((u_int32_t)(src)\
18680 #define RADIO130NM_RF5G2_CH0__SPARE__MODIFY(dst, src) \
18682 ~0x000007ffU) | ((u_int32_t)(src) &\
18684 #define RADIO130NM_RF5G2_CH0__SPARE__VERIFY(src) \
18685 (!(((u_int32_t)(src)\
18692 #define RADIO130NM_RF5G2_CH0__PDBIR2__READ(src) \
18693 (((u_int32_t)(src)\
18695 #define RADIO130NM_RF5G2_CH0__PDBIR2__WRITE(src) \
18696 (((u_int32_t)(src)\
18698 #define RADIO130NM_RF5G2_CH0__PDBIR2__MODIFY(dst, src) \
18700 ~0x00003800U) | (((u_int32_t)(src) <<\
18702 #define RADIO130NM_RF5G2_CH0__PDBIR2__VERIFY(src) \
18703 (!((((u_int32_t)(src)\
18710 #define RADIO130NM_RF5G2_CH0__PDBIR1__READ(src) \
18711 (((u_int32_t)(src)\
18713 #define RADIO130NM_RF5G2_CH0__PDBIR1__WRITE(src) \
18714 (((u_int32_t)(src)\
18716 #define RADIO130NM_RF5G2_CH0__PDBIR1__MODIFY(dst, src) \
18718 ~0x0001c000U) | (((u_int32_t)(src) <<\
18720 #define RADIO130NM_RF5G2_CH0__PDBIR1__VERIFY(src) \
18721 (!((((u_int32_t)(src)\
18728 #define RADIO130NM_RF5G2_CH0__PDBIRTXPA__READ(src) \
18729 (((u_int32_t)(src)\
18731 #define RADIO130NM_RF5G2_CH0__PDBIRTXPA__WRITE(src) \
18732 (((u_int32_t)(src)\
18734 #define RADIO130NM_RF5G2_CH0__PDBIRTXPA__MODIFY(dst, src) \
18736 ~0x000e0000U) | (((u_int32_t)(src) <<\
18738 #define RADIO130NM_RF5G2_CH0__PDBIRTXPA__VERIFY(src) \
18739 (!((((u_int32_t)(src)\
18746 #define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__READ(src) \
18747 (((u_int32_t)(src)\
18749 #define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__WRITE(src) \
18750 (((u_int32_t)(src)\
18752 #define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__MODIFY(dst, src) \
18754 ~0x00700000U) | (((u_int32_t)(src) <<\
18756 #define RADIO130NM_RF5G2_CH0__PDBIRTXMIX__VERIFY(src) \
18757 (!((((u_int32_t)(src)\
18764 #define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__READ(src) \
18765 (((u_int32_t)(src)\
18767 #define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__WRITE(src) \
18768 (((u_int32_t)(src)\
18770 #define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__MODIFY(dst, src) \
18772 ~0x03800000U) | (((u_int32_t)(src) <<\
18774 #define RADIO130NM_RF5G2_CH0__RX5_ATB_SEL__VERIFY(src) \
18775 (!((((u_int32_t)(src)\
18782 #define RADIO130NM_RF5G2_CH0__PDRFVGA5__READ(src) \
18783 (((u_int32_t)(src)\
18785 #define RADIO130NM_RF5G2_CH0__PDRFVGA5__WRITE(src) \
18786 (((u_int32_t)(src)\
18788 #define RADIO130NM_RF5G2_CH0__PDRFVGA5__MODIFY(dst, src) \
18790 ~0x04000000U) | (((u_int32_t)(src) <<\
18792 #define RADIO130NM_RF5G2_CH0__PDRFVGA5__VERIFY(src) \
18793 (!((((u_int32_t)(src)\
18806 #define RADIO130NM_RF5G2_CH0__PDCSLNA5__READ(src) \
18807 (((u_int32_t)(src)\
18809 #define RADIO130NM_RF5G2_CH0__PDCSLNA5__WRITE(src) \
18810 (((u_int32_t)(src)\
18812 #define RADIO130NM_RF5G2_CH0__PDCSLNA5__MODIFY(dst, src) \
18814 ~0x08000000U) | (((u_int32_t)(src) <<\
18816 #define RADIO130NM_RF5G2_CH0__PDCSLNA5__VERIFY(src) \
18817 (!((((u_int32_t)(src)\
18830 #define RADIO130NM_RF5G2_CH0__PDVGM5__READ(src) \
18831 (((u_int32_t)(src)\
18833 #define RADIO130NM_RF5G2_CH0__PDVGM5__WRITE(src) \
18834 (((u_int32_t)(src)\
18836 #define RADIO130NM_RF5G2_CH0__PDVGM5__MODIFY(dst, src) \
18838 ~0x10000000U) | (((u_int32_t)(src) <<\
18840 #define RADIO130NM_RF5G2_CH0__PDVGM5__VERIFY(src) \
18841 (!((((u_int32_t)(src)\
18854 #define RADIO130NM_RF5G2_CH0__PDRXLO5__READ(src) \
18855 (((u_int32_t)(src)\
18857 #define RADIO130NM_RF5G2_CH0__PDRXLO5__WRITE(src) \
18858 (((u_int32_t)(src)\
18860 #define RADIO130NM_RF5G2_CH0__PDRXLO5__MODIFY(dst, src) \
18862 ~0x20000000U) | (((u_int32_t)(src) <<\
18864 #define RADIO130NM_RF5G2_CH0__PDRXLO5__VERIFY(src) \
18865 (!((((u_int32_t)(src)\
18878 #define RADIO130NM_RF5G2_CH0__PDREGFE5__READ(src) \
18879 (((u_int32_t)(src)\
18881 #define RADIO130NM_RF5G2_CH0__PDREGFE5__WRITE(src) \
18882 (((u_int32_t)(src)\
18884 #define RADIO130NM_RF5G2_CH0__PDREGFE5__MODIFY(dst, src) \
18886 ~0x40000000U) | (((u_int32_t)(src) <<\
18888 #define RADIO130NM_RF5G2_CH0__PDREGFE5__VERIFY(src) \
18889 (!((((u_int32_t)(src)\
18902 #define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__READ(src) \
18903 (((u_int32_t)(src)\
18905 #define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__WRITE(src) \
18906 (((u_int32_t)(src)\
18908 #define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__MODIFY(dst, src) \
18910 ~0x80000000U) | (((u_int32_t)(src) <<\
18912 #define RADIO130NM_RF5G2_CH0__REGFE_BYPASS5__VERIFY(src) \
18913 (!((((u_int32_t)(src)\
18939 #define RADIO130NM_RF5G3_CH0__SPARE__READ(src) (u_int32_t)(src) & 0x0000001fU
18940 #define RADIO130NM_RF5G3_CH0__SPARE__WRITE(src) \
18941 ((u_int32_t)(src)\
18943 #define RADIO130NM_RF5G3_CH0__SPARE__MODIFY(dst, src) \
18945 ~0x0000001fU) | ((u_int32_t)(src) &\
18947 #define RADIO130NM_RF5G3_CH0__SPARE__VERIFY(src) \
18948 (!(((u_int32_t)(src)\
18955 #define RADIO130NM_RF5G3_CH0__PDBIBCVGM__READ(src) \
18956 (((u_int32_t)(src)\
18958 #define RADIO130NM_RF5G3_CH0__PDBIBCVGM__WRITE(src) \
18959 (((u_int32_t)(src)\
18961 #define RADIO130NM_RF5G3_CH0__PDBIBCVGM__MODIFY(dst, src) \
18963 ~0x000000e0U) | (((u_int32_t)(src) <<\
18965 #define RADIO130NM_RF5G3_CH0__PDBIBCVGM__VERIFY(src) \
18966 (!((((u_int32_t)(src)\
18973 #define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__READ(src) \
18974 (((u_int32_t)(src)\
18976 #define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__WRITE(src) \
18977 (((u_int32_t)(src)\
18979 #define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__MODIFY(dst, src) \
18981 ~0x00000700U) | (((u_int32_t)(src) <<\
18983 #define RADIO130NM_RF5G3_CH0__PDBIBCRFVGA__VERIFY(src) \
18984 (!((((u_int32_t)(src)\
18991 #define RADIO130NM_RF5G3_CH0__PDBIBCLNA__READ(src) \
18992 (((u_int32_t)(src)\
18994 #define RADIO130NM_RF5G3_CH0__PDBIBCLNA__WRITE(src) \
18995 (((u_int32_t)(src)\
18997 #define RADIO130NM_RF5G3_CH0__PDBIBCLNA__MODIFY(dst, src) \
18999 ~0x00003800U) | (((u_int32_t)(src) <<\
19001 #define RADIO130NM_RF5G3_CH0__PDBIBCLNA__VERIFY(src) \
19002 (!((((u_int32_t)(src)\
19009 #define RADIO130NM_RF5G3_CH0__PDBIC3__READ(src) \
19010 (((u_int32_t)(src)\
19012 #define RADIO130NM_RF5G3_CH0__PDBIC3__WRITE(src) \
19013 (((u_int32_t)(src)\
19015 #define RADIO130NM_RF5G3_CH0__PDBIC3__MODIFY(dst, src) \
19017 ~0x0001c000U) | (((u_int32_t)(src) <<\
19019 #define RADIO130NM_RF5G3_CH0__PDBIC3__VERIFY(src) \
19020 (!((((u_int32_t)(src)\
19027 #define RADIO130NM_RF5G3_CH0__PDBIC2__READ(src) \
19028 (((u_int32_t)(src)\
19030 #define RADIO130NM_RF5G3_CH0__PDBIC2__WRITE(src) \
19031 (((u_int32_t)(src)\
19033 #define RADIO130NM_RF5G3_CH0__PDBIC2__MODIFY(dst, src) \
19035 ~0x000e0000U) | (((u_int32_t)(src) <<\
19037 #define RADIO130NM_RF5G3_CH0__PDBIC2__VERIFY(src) \
19038 (!((((u_int32_t)(src)\
19045 #define RADIO130NM_RF5G3_CH0__PDBIC1__READ(src) \
19046 (((u_int32_t)(src)\
19048 #define RADIO130NM_RF5G3_CH0__PDBIC1__WRITE(src) \
19049 (((u_int32_t)(src)\
19051 #define RADIO130NM_RF5G3_CH0__PDBIC1__MODIFY(dst, src) \
19053 ~0x00700000U) | (((u_int32_t)(src) <<\
19055 #define RADIO130NM_RF5G3_CH0__PDBIC1__VERIFY(src) \
19056 (!((((u_int32_t)(src)\
19063 #define RADIO130NM_RF5G3_CH0__PDBICTXMIX__READ(src) \
19064 (((u_int32_t)(src)\
19066 #define RADIO130NM_RF5G3_CH0__PDBICTXMIX__WRITE(src) \
19067 (((u_int32_t)(src)\
19069 #define RADIO130NM_RF5G3_CH0__PDBICTXMIX__MODIFY(dst, src) \
19071 ~0x03800000U) | (((u_int32_t)(src) <<\
19073 #define RADIO130NM_RF5G3_CH0__PDBICTXMIX__VERIFY(src) \
19074 (!((((u_int32_t)(src)\
19081 #define RADIO130NM_RF5G3_CH0__PDBICTXPA__READ(src) \
19082 (((u_int32_t)(src)\
19084 #define RADIO130NM_RF5G3_CH0__PDBICTXPA__WRITE(src) \
19085 (((u_int32_t)(src)\
19087 #define RADIO130NM_RF5G3_CH0__PDBICTXPA__MODIFY(dst, src) \
19089 ~0x1c000000U) | (((u_int32_t)(src) <<\
19091 #define RADIO130NM_RF5G3_CH0__PDBICTXPA__VERIFY(src) \
19092 (!((((u_int32_t)(src)\
19099 #define RADIO130NM_RF5G3_CH0__PDBICTXBUF__READ(src) \
19100 (((u_int32_t)(src)\
19102 #define RADIO130NM_RF5G3_CH0__PDBICTXBUF__WRITE(src) \
19103 (((u_int32_t)(src)\
19105 #define RADIO130NM_RF5G3_CH0__PDBICTXBUF__MODIFY(dst, src) \
19107 ~0xe0000000U) | (((u_int32_t)(src) <<\
19109 #define RADIO130NM_RF5G3_CH0__PDBICTXBUF__VERIFY(src) \
19110 (!((((u_int32_t)(src)\
19130 #define RADIO130NM_RF2G1_CH0__SPARES__READ(src) (u_int32_t)(src) & 0x0000003fU
19131 #define RADIO130NM_RF2G1_CH0__SPARES__WRITE(src) \
19132 ((u_int32_t)(src)\
19134 #define RADIO130NM_RF2G1_CH0__SPARES__MODIFY(dst, src) \
19136 ~0x0000003fU) | ((u_int32_t)(src) &\
19138 #define RADIO130NM_RF2G1_CH0__SPARES__VERIFY(src) \
19139 (!(((u_int32_t)(src)\
19146 #define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__READ(src) \
19147 (((u_int32_t)(src)\
19149 #define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__WRITE(src) \
19150 (((u_int32_t)(src)\
19152 #define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__MODIFY(dst, src) \
19154 ~0x00000040U) | (((u_int32_t)(src) <<\
19156 #define RADIO130NM_RF2G1_CH0__REGLO_BYPASS__VERIFY(src) \
19157 (!((((u_int32_t)(src)\
19170 #define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__READ(src) \
19171 (((u_int32_t)(src)\
19173 #define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__WRITE(src) \
19174 (((u_int32_t)(src)\
19176 #define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__MODIFY(dst, src) \
19178 ~0x00000080U) | (((u_int32_t)(src) <<\
19180 #define RADIO130NM_RF2G1_CH0__REGLNA_BYPASS__VERIFY(src) \
19181 (!((((u_int32_t)(src)\
19194 #define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__READ(src) \
19195 (((u_int32_t)(src)\
19197 #define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__WRITE(src) \
19198 (((u_int32_t)(src)\
19200 #define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__MODIFY(dst, src) \
19202 ~0x00000700U) | (((u_int32_t)(src) <<\
19204 #define RADIO130NM_RF2G1_CH0__PDIC25U_VGM__VERIFY(src) \
19205 (!((((u_int32_t)(src)\
19212 #define RADIO130NM_RF2G1_CH0__PACA_SEL__READ(src) \
19213 (((u_int32_t)(src)\
19215 #define RADIO130NM_RF2G1_CH0__PACA_SEL__WRITE(src) \
19216 (((u_int32_t)(src)\
19218 #define RADIO130NM_RF2G1_CH0__PACA_SEL__MODIFY(dst, src) \
19220 ~0x00001800U) | (((u_int32_t)(src) <<\
19222 #define RADIO130NM_RF2G1_CH0__PACA_SEL__VERIFY(src) \
19223 (!((((u_int32_t)(src)\
19230 #define RADIO130NM_RF2G1_CH0__LOCONTROL__READ(src) \
19231 (((u_int32_t)(src)\
19233 #define RADIO130NM_RF2G1_CH0__LOCONTROL__WRITE(src) \
19234 (((u_int32_t)(src)\
19236 #define RADIO130NM_RF2G1_CH0__LOCONTROL__MODIFY(dst, src) \
19238 ~0x00002000U) | (((u_int32_t)(src) <<\
19240 #define RADIO130NM_RF2G1_CH0__LOCONTROL__VERIFY(src) \
19241 (!((((u_int32_t)(src)\
19254 #define RADIO130NM_RF2G1_CH0__TXATB_SEL__READ(src) \
19255 (((u_int32_t)(src)\
19257 #define RADIO130NM_RF2G1_CH0__TXATB_SEL__WRITE(src) \
19258 (((u_int32_t)(src)\
19260 #define RADIO130NM_RF2G1_CH0__TXATB_SEL__MODIFY(dst, src) \
19262 ~0x0001c000U) | (((u_int32_t)(src) <<\
19264 #define RADIO130NM_RF2G1_CH0__TXATB_SEL__VERIFY(src) \
19265 (!((((u_int32_t)(src)\
19272 #define RADIO130NM_RF2G1_CH0__RXATB_SEL__READ(src) \
19273 (((u_int32_t)(src)\
19275 #define RADIO130NM_RF2G1_CH0__RXATB_SEL__WRITE(src) \
19276 (((u_int32_t)(src)\
19278 #define RADIO130NM_RF2G1_CH0__RXATB_SEL__MODIFY(dst, src) \
19280 ~0x000e0000U) | (((u_int32_t)(src) <<\
19282 #define RADIO130NM_RF2G1_CH0__RXATB_SEL__VERIFY(src) \
19283 (!((((u_int32_t)(src)\
19290 #define RADIO130NM_RF2G1_CH0__LOATB_SEL__READ(src) \
19291 (((u_int32_t)(src)\
19293 #define RADIO130NM_RF2G1_CH0__LOATB_SEL__WRITE(src) \
19294 (((u_int32_t)(src)\
19296 #define RADIO130NM_RF2G1_CH0__LOATB_SEL__MODIFY(dst, src) \
19298 ~0x00700000U) | (((u_int32_t)(src) <<\
19300 #define RADIO130NM_RF2G1_CH0__LOATB_SEL__VERIFY(src) \
19301 (!((((u_int32_t)(src)\
19308 #define RADIO130NM_RF2G1_CH0__OB__READ(src) \
19309 (((u_int32_t)(src)\
19311 #define RADIO130NM_RF2G1_CH0__OB__WRITE(src) \
19312 (((u_int32_t)(src)\
19314 #define RADIO130NM_RF2G1_CH0__OB__MODIFY(dst, src) \
19316 ~0x03800000U) | (((u_int32_t)(src) <<\
19318 #define RADIO130NM_RF2G1_CH0__OB__VERIFY(src) \
19319 (!((((u_int32_t)(src)\
19326 #define RADIO130NM_RF2G1_CH0__DB__READ(src) \
19327 (((u_int32_t)(src)\
19329 #define RADIO130NM_RF2G1_CH0__DB__WRITE(src) \
19330 (((u_int32_t)(src)\
19332 #define RADIO130NM_RF2G1_CH0__DB__MODIFY(dst, src) \
19334 ~0x1c000000U) | (((u_int32_t)(src) <<\
19336 #define RADIO130NM_RF2G1_CH0__DB__VERIFY(src) \
19337 (!((((u_int32_t)(src)\
19344 #define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__READ(src) \
19345 (((u_int32_t)(src)\
19347 #define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__WRITE(src) \
19348 (((u_int32_t)(src)\
19350 #define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__MODIFY(dst, src) \
19352 ~0xe0000000U) | (((u_int32_t)(src) <<\
19354 #define RADIO130NM_RF2G1_CH0__PDIC25U_LNA__VERIFY(src) \
19355 (!((((u_int32_t)(src)\
19375 #define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__READ(src) \
19376 (u_int32_t)(src)\
19378 #define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__WRITE(src) \
19379 ((u_int32_t)(src)\
19381 #define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__MODIFY(dst, src) \
19383 ~0x00000007U) | ((u_int32_t)(src) &\
19385 #define RADIO130NM_RF2G2_CH0__PDIR25U_VREGLO__VERIFY(src) \
19386 (!(((u_int32_t)(src)\
19393 #define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__READ(src) \
19394 (((u_int32_t)(src)\
19396 #define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__WRITE(src) \
19397 (((u_int32_t)(src)\
19399 #define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__MODIFY(dst, src) \
19401 ~0x00000038U) | (((u_int32_t)(src) <<\
19403 #define RADIO130NM_RF2G2_CH0__PDIC25U_VREGLO__VERIFY(src) \
19404 (!((((u_int32_t)(src)\
19411 #define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__READ(src) \
19412 (((u_int32_t)(src)\
19414 #define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__WRITE(src) \
19415 (((u_int32_t)(src)\
19417 #define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__MODIFY(dst, src) \
19419 ~0x000001c0U) | (((u_int32_t)(src) <<\
19421 #define RADIO130NM_RF2G2_CH0__PDIC50U_DIV__VERIFY(src) \
19422 (!((((u_int32_t)(src)\
19429 #define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__READ(src) \
19430 (((u_int32_t)(src)\
19432 #define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__WRITE(src) \
19433 (((u_int32_t)(src)\
19435 #define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__MODIFY(dst, src) \
19437 ~0x00000e00U) | (((u_int32_t)(src) <<\
19439 #define RADIO130NM_RF2G2_CH0__PDIC25U_RXRF__VERIFY(src) \
19440 (!((((u_int32_t)(src)\
19447 #define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__READ(src) \
19448 (((u_int32_t)(src)\
19450 #define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__WRITE(src) \
19451 (((u_int32_t)(src)\
19453 #define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__MODIFY(dst, src) \
19455 ~0x00007000U) | (((u_int32_t)(src) <<\
19457 #define RADIO130NM_RF2G2_CH0__PDIC25U_TXRF__VERIFY(src) \
19458 (!((((u_int32_t)(src)\
19465 #define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__READ(src) \
19466 (((u_int32_t)(src)\
19468 #define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__WRITE(src) \
19469 (((u_int32_t)(src)\
19471 #define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__MODIFY(dst, src) \
19473 ~0x00038000U) | (((u_int32_t)(src) <<\
19475 #define RADIO130NM_RF2G2_CH0__PDIC25U_TXPA__VERIFY(src) \
19476 (!((((u_int32_t)(src)\
19483 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__READ(src) \
19484 (((u_int32_t)(src)\
19486 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__WRITE(src) \
19487 (((u_int32_t)(src)\
19489 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__MODIFY(dst, src) \
19491 ~0x00040000U) | (((u_int32_t)(src) <<\
19493 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXPA__VERIFY(src) \
19494 (!((((u_int32_t)(src)\
19507 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__READ(src) \
19508 (((u_int32_t)(src)\
19510 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__WRITE(src) \
19511 (((u_int32_t)(src)\
19513 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__MODIFY(dst, src) \
19515 ~0x00380000U) | (((u_int32_t)(src) <<\
19517 #define RADIO130NM_RF2G2_CH0__PDIR25U_TXMIX__VERIFY(src) \
19518 (!((((u_int32_t)(src)\
19525 #define RADIO130NM_RF2G2_CH0__PDTXMIX__READ(src) \
19526 (((u_int32_t)(src)\
19528 #define RADIO130NM_RF2G2_CH0__PDTXMIX__WRITE(src) \
19529 (((u_int32_t)(src)\
19531 #define RADIO130NM_RF2G2_CH0__PDTXMIX__MODIFY(dst, src) \
19533 ~0x00400000U) | (((u_int32_t)(src) <<\
19535 #define RADIO130NM_RF2G2_CH0__PDTXMIX__VERIFY(src) \
19536 (!((((u_int32_t)(src)\
19549 #define RADIO130NM_RF2G2_CH0__PDTXLO__READ(src) \
19550 (((u_int32_t)(src)\
19552 #define RADIO130NM_RF2G2_CH0__PDTXLO__WRITE(src) \
19553 (((u_int32_t)(src)\
19555 #define RADIO130NM_RF2G2_CH0__PDTXLO__MODIFY(dst, src) \
19557 ~0x00800000U) | (((u_int32_t)(src) <<\
19559 #define RADIO130NM_RF2G2_CH0__PDTXLO__VERIFY(src) \
19560 (!((((u_int32_t)(src)\
19573 #define RADIO130NM_RF2G2_CH0__PDRXLO__READ(src) \
19574 (((u_int32_t)(src)\
19576 #define RADIO130NM_RF2G2_CH0__PDRXLO__WRITE(src) \
19577 (((u_int32_t)(src)\
19579 #define RADIO130NM_RF2G2_CH0__PDRXLO__MODIFY(dst, src) \
19581 ~0x01000000U) | (((u_int32_t)(src) <<\
19583 #define RADIO130NM_RF2G2_CH0__PDRXLO__VERIFY(src) \
19584 (!((((u_int32_t)(src)\
19597 #define RADIO130NM_RF2G2_CH0__PDVGM__READ(src) \
19598 (((u_int32_t)(src)\
19600 #define RADIO130NM_RF2G2_CH0__PDVGM__WRITE(src) \
19601 (((u_int32_t)(src)\
19603 #define RADIO130NM_RF2G2_CH0__PDVGM__MODIFY(dst, src) \
19605 ~0x02000000U) | (((u_int32_t)(src) <<\
19607 #define RADIO130NM_RF2G2_CH0__PDVGM__VERIFY(src) \
19608 (!((((u_int32_t)(src)\
19621 #define RADIO130NM_RF2G2_CH0__PDREGLO__READ(src) \
19622 (((u_int32_t)(src)\
19624 #define RADIO130NM_RF2G2_CH0__PDREGLO__WRITE(src) \
19625 (((u_int32_t)(src)\
19627 #define RADIO130NM_RF2G2_CH0__PDREGLO__MODIFY(dst, src) \
19629 ~0x04000000U) | (((u_int32_t)(src) <<\
19631 #define RADIO130NM_RF2G2_CH0__PDREGLO__VERIFY(src) \
19632 (!((((u_int32_t)(src)\
19645 #define RADIO130NM_RF2G2_CH0__PDREGLNA__READ(src) \
19646 (((u_int32_t)(src)\
19648 #define RADIO130NM_RF2G2_CH0__PDREGLNA__WRITE(src) \
19649 (((u_int32_t)(src)\
19651 #define RADIO130NM_RF2G2_CH0__PDREGLNA__MODIFY(dst, src) \
19653 ~0x08000000U) | (((u_int32_t)(src) <<\
19655 #define RADIO130NM_RF2G2_CH0__PDREGLNA__VERIFY(src) \
19656 (!((((u_int32_t)(src)\
19669 #define RADIO130NM_RF2G2_CH0__PDPAOUT__READ(src) \
19670 (((u_int32_t)(src)\
19672 #define RADIO130NM_RF2G2_CH0__PDPAOUT__WRITE(src) \
19673 (((u_int32_t)(src)\
19675 #define RADIO130NM_RF2G2_CH0__PDPAOUT__MODIFY(dst, src) \
19677 ~0x10000000U) | (((u_int32_t)(src) <<\
19679 #define RADIO130NM_RF2G2_CH0__PDPAOUT__VERIFY(src) \
19680 (!((((u_int32_t)(src)\
19693 #define RADIO130NM_RF2G2_CH0__PDPADRV__READ(src) \
19694 (((u_int32_t)(src)\
19696 #define RADIO130NM_RF2G2_CH0__PDPADRV__WRITE(src) \
19697 (((u_int32_t)(src)\
19699 #define RADIO130NM_RF2G2_CH0__PDPADRV__MODIFY(dst, src) \
19701 ~0x20000000U) | (((u_int32_t)(src) <<\
19703 #define RADIO130NM_RF2G2_CH0__PDPADRV__VERIFY(src) \
19704 (!((((u_int32_t)(src)\
19717 #define RADIO130NM_RF2G2_CH0__PDDIV__READ(src) \
19718 (((u_int32_t)(src)\
19720 #define RADIO130NM_RF2G2_CH0__PDDIV__WRITE(src) \
19721 (((u_int32_t)(src)\
19723 #define RADIO130NM_RF2G2_CH0__PDDIV__MODIFY(dst, src) \
19725 ~0x40000000U) | (((u_int32_t)(src) <<\
19727 #define RADIO130NM_RF2G2_CH0__PDDIV__VERIFY(src) \
19728 (!((((u_int32_t)(src)\
19741 #define RADIO130NM_RF2G2_CH0__PDLNA__READ(src) \
19742 (((u_int32_t)(src)\
19744 #define RADIO130NM_RF2G2_CH0__PDLNA__WRITE(src) \
19745 (((u_int32_t)(src)\
19747 #define RADIO130NM_RF2G2_CH0__PDLNA__MODIFY(dst, src) \
19749 ~0x80000000U) | (((u_int32_t)(src) <<\
19751 #define RADIO130NM_RF2G2_CH0__PDLNA__VERIFY(src) \
19752 (!((((u_int32_t)(src)\
19778 #define RADIO130NM_SYNTH1__SEL_VCMONABUS__READ(src) \
19779 (u_int32_t)(src)\
19781 #define RADIO130NM_SYNTH1__SEL_VCMONABUS__WRITE(src) \
19782 ((u_int32_t)(src)\
19784 #define RADIO130NM_SYNTH1__SEL_VCMONABUS__MODIFY(dst, src) \
19786 ~0x00000007U) | ((u_int32_t)(src) &\
19788 #define RADIO130NM_SYNTH1__SEL_VCMONABUS__VERIFY(src) \
19789 (!(((u_int32_t)(src)\
19796 #define RADIO130NM_SYNTH1__CON_IVCOBUF__READ(src) \
19797 (((u_int32_t)(src)\
19799 #define RADIO130NM_SYNTH1__CON_IVCOBUF__WRITE(src) \
19800 (((u_int32_t)(src)\
19802 #define RADIO130NM_SYNTH1__CON_IVCOBUF__MODIFY(dst, src) \
19804 ~0x00000008U) | (((u_int32_t)(src) <<\
19806 #define RADIO130NM_SYNTH1__CON_IVCOBUF__VERIFY(src) \
19807 (!((((u_int32_t)(src)\
19820 #define RADIO130NM_SYNTH1__CON_IVCOREG__READ(src) \
19821 (((u_int32_t)(src)\
19823 #define RADIO130NM_SYNTH1__CON_IVCOREG__WRITE(src) \
19824 (((u_int32_t)(src)\
19826 #define RADIO130NM_SYNTH1__CON_IVCOREG__MODIFY(dst, src) \
19828 ~0x00000010U) | (((u_int32_t)(src) <<\
19830 #define RADIO130NM_SYNTH1__CON_IVCOREG__VERIFY(src) \
19831 (!((((u_int32_t)(src)\
19844 #define RADIO130NM_SYNTH1__CON_VDDVCOREG__READ(src) \
19845 (((u_int32_t)(src)\
19847 #define RADIO130NM_SYNTH1__CON_VDDVCOREG__WRITE(src) \
19848 (((u_int32_t)(src)\
19850 #define RADIO130NM_SYNTH1__CON_VDDVCOREG__MODIFY(dst, src) \
19852 ~0x00000020U) | (((u_int32_t)(src) <<\
19854 #define RADIO130NM_SYNTH1__CON_VDDVCOREG__VERIFY(src) \
19855 (!((((u_int32_t)(src)\
19868 #define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__READ(src) \
19869 (((u_int32_t)(src)\
19871 #define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__WRITE(src) \
19872 (((u_int32_t)(src)\
19874 #define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__MODIFY(dst, src) \
19876 ~0x00000040U) | (((u_int32_t)(src) <<\
19878 #define RADIO130NM_SYNTH1__MONITOR_SYNTHLOCKVCOK__VERIFY(src) \
19879 (!((((u_int32_t)(src)\
19892 #define RADIO130NM_SYNTH1__MONITOR_VC2LOW__READ(src) \
19893 (((u_int32_t)(src)\
19895 #define RADIO130NM_SYNTH1__MONITOR_VC2LOW__WRITE(src) \
19896 (((u_int32_t)(src)\
19898 #define RADIO130NM_SYNTH1__MONITOR_VC2LOW__MODIFY(dst, src) \
19900 ~0x00000080U) | (((u_int32_t)(src) <<\
19902 #define RADIO130NM_SYNTH1__MONITOR_VC2LOW__VERIFY(src) \
19903 (!((((u_int32_t)(src)\
19916 #define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__READ(src) \
19917 (((u_int32_t)(src)\
19919 #define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__WRITE(src) \
19920 (((u_int32_t)(src)\
19922 #define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__MODIFY(dst, src) \
19924 ~0x00000100U) | (((u_int32_t)(src) <<\
19926 #define RADIO130NM_SYNTH1__MONITOR_VC2HIGH__VERIFY(src) \
19927 (!((((u_int32_t)(src)\
19940 #define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__READ(src) \
19941 (((u_int32_t)(src)\
19943 #define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__WRITE(src) \
19944 (((u_int32_t)(src)\
19946 #define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__MODIFY(dst, src) \
19948 ~0x00000200U) | (((u_int32_t)(src) <<\
19950 #define RADIO130NM_SYNTH1__MONITOR_FB_DIV2__VERIFY(src) \
19951 (!((((u_int32_t)(src)\
19964 #define RADIO130NM_SYNTH1__MONITOR_REF__READ(src) \
19965 (((u_int32_t)(src)\
19967 #define RADIO130NM_SYNTH1__MONITOR_REF__WRITE(src) \
19968 (((u_int32_t)(src)\
19970 #define RADIO130NM_SYNTH1__MONITOR_REF__MODIFY(dst, src) \
19972 ~0x00000400U) | (((u_int32_t)(src) <<\
19974 #define RADIO130NM_SYNTH1__MONITOR_REF__VERIFY(src) \
19975 (!((((u_int32_t)(src)\
19988 #define RADIO130NM_SYNTH1__MONITOR_FB__READ(src) \
19989 (((u_int32_t)(src)\
19991 #define RADIO130NM_SYNTH1__MONITOR_FB__WRITE(src) \
19992 (((u_int32_t)(src)\
19994 #define RADIO130NM_SYNTH1__MONITOR_FB__MODIFY(dst, src) \
19996 ~0x00000800U) | (((u_int32_t)(src) <<\
19998 #define RADIO130NM_SYNTH1__MONITOR_FB__VERIFY(src) \
19999 (!((((u_int32_t)(src)\
20012 #define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__READ(src) \
20013 (((u_int32_t)(src)\
20015 #define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__WRITE(src) \
20016 (((u_int32_t)(src)\
20018 #define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__MODIFY(dst, src) \
20020 ~0x00001000U) | (((u_int32_t)(src) <<\
20022 #define RADIO130NM_SYNTH1__PWUP_LOMIX_PD__VERIFY(src) \
20023 (!((((u_int32_t)(src)\
20036 #define RADIO130NM_SYNTH1__PWUP_LODIV_PD__READ(src) \
20037 (((u_int32_t)(src)\
20039 #define RADIO130NM_SYNTH1__PWUP_LODIV_PD__WRITE(src) \
20040 (((u_int32_t)(src)\
20042 #define RADIO130NM_SYNTH1__PWUP_LODIV_PD__MODIFY(dst, src) \
20044 ~0x00002000U) | (((u_int32_t)(src) <<\
20046 #define RADIO130NM_SYNTH1__PWUP_LODIV_PD__VERIFY(src) \
20047 (!((((u_int32_t)(src)\
20060 #define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__READ(src) \
20061 (((u_int32_t)(src)\
20063 #define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__WRITE(src) \
20064 (((u_int32_t)(src)\
20066 #define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__MODIFY(dst, src) \
20068 ~0x00004000U) | (((u_int32_t)(src) <<\
20070 #define RADIO130NM_SYNTH1__PWUP_LOBUF5G_PD__VERIFY(src) \
20071 (!((((u_int32_t)(src)\
20084 #define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__READ(src) \
20085 (((u_int32_t)(src)\
20087 #define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__WRITE(src) \
20088 (((u_int32_t)(src)\
20090 #define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__MODIFY(dst, src) \
20092 ~0x00008000U) | (((u_int32_t)(src) <<\
20094 #define RADIO130NM_SYNTH1__PWUP_LOBUF2G_PD__VERIFY(src) \
20095 (!((((u_int32_t)(src)\
20108 #define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__READ(src) \
20109 (((u_int32_t)(src)\
20111 #define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__WRITE(src) \
20112 (((u_int32_t)(src)\
20114 #define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__MODIFY(dst, src) \
20116 ~0x00010000U) | (((u_int32_t)(src) <<\
20118 #define RADIO130NM_SYNTH1__PWUP_VCOBUF_PD__VERIFY(src) \
20119 (!((((u_int32_t)(src)\
20132 #define RADIO130NM_SYNTH1__VCOBUFBIAS__READ(src) \
20133 (((u_int32_t)(src)\
20135 #define RADIO130NM_SYNTH1__VCOBUFBIAS__WRITE(src) \
20136 (((u_int32_t)(src)\
20138 #define RADIO130NM_SYNTH1__VCOBUFBIAS__MODIFY(dst, src) \
20140 ~0x00060000U) | (((u_int32_t)(src) <<\
20142 #define RADIO130NM_SYNTH1__VCOBUFBIAS__VERIFY(src) \
20143 (!((((u_int32_t)(src)\
20150 #define RADIO130NM_SYNTH1__VCOREGLEVEL__READ(src) \
20151 (((u_int32_t)(src)\
20153 #define RADIO130NM_SYNTH1__VCOREGLEVEL__WRITE(src) \
20154 (((u_int32_t)(src)\
20156 #define RADIO130NM_SYNTH1__VCOREGLEVEL__MODIFY(dst, src) \
20158 ~0x00180000U) | (((u_int32_t)(src) <<\
20160 #define RADIO130NM_SYNTH1__VCOREGLEVEL__VERIFY(src) \
20161 (!((((u_int32_t)(src)\
20168 #define RADIO130NM_SYNTH1__VCOREGBYPASS__READ(src) \
20169 (((u_int32_t)(src)\
20171 #define RADIO130NM_SYNTH1__VCOREGBYPASS__WRITE(src) \
20172 (((u_int32_t)(src)\
20174 #define RADIO130NM_SYNTH1__VCOREGBYPASS__MODIFY(dst, src) \
20176 ~0x00200000U) | (((u_int32_t)(src) <<\
20178 #define RADIO130NM_SYNTH1__VCOREGBYPASS__VERIFY(src) \
20179 (!((((u_int32_t)(src)\
20192 #define RADIO130NM_SYNTH1__PWUP_LOREF__READ(src) \
20193 (((u_int32_t)(src)\
20195 #define RADIO130NM_SYNTH1__PWUP_LOREF__WRITE(src) \
20196 (((u_int32_t)(src)\
20198 #define RADIO130NM_SYNTH1__PWUP_LOREF__MODIFY(dst, src) \
20200 ~0x00400000U) | (((u_int32_t)(src) <<\
20202 #define RADIO130NM_SYNTH1__PWUP_LOREF__VERIFY(src) \
20203 (!((((u_int32_t)(src)\
20216 #define RADIO130NM_SYNTH1__PWD_LOMIX__READ(src) \
20217 (((u_int32_t)(src)\
20219 #define RADIO130NM_SYNTH1__PWD_LOMIX__WRITE(src) \
20220 (((u_int32_t)(src)\
20222 #define RADIO130NM_SYNTH1__PWD_LOMIX__MODIFY(dst, src) \
20224 ~0x00800000U) | (((u_int32_t)(src) <<\
20226 #define RADIO130NM_SYNTH1__PWD_LOMIX__VERIFY(src) \
20227 (!((((u_int32_t)(src)\
20240 #define RADIO130NM_SYNTH1__PWD_LODIV__READ(src) \
20241 (((u_int32_t)(src)\
20243 #define RADIO130NM_SYNTH1__PWD_LODIV__WRITE(src) \
20244 (((u_int32_t)(src)\
20246 #define RADIO130NM_SYNTH1__PWD_LODIV__MODIFY(dst, src) \
20248 ~0x01000000U) | (((u_int32_t)(src) <<\
20250 #define RADIO130NM_SYNTH1__PWD_LODIV__VERIFY(src) \
20251 (!((((u_int32_t)(src)\
20264 #define RADIO130NM_SYNTH1__PWD_LOBUF5G__READ(src) \
20265 (((u_int32_t)(src)\
20267 #define RADIO130NM_SYNTH1__PWD_LOBUF5G__WRITE(src) \
20268 (((u_int32_t)(src)\
20270 #define RADIO130NM_SYNTH1__PWD_LOBUF5G__MODIFY(dst, src) \
20272 ~0x02000000U) | (((u_int32_t)(src) <<\
20274 #define RADIO130NM_SYNTH1__PWD_LOBUF5G__VERIFY(src) \
20275 (!((((u_int32_t)(src)\
20288 #define RADIO130NM_SYNTH1__PWD_LOBUF2G__READ(src) \
20289 (((u_int32_t)(src)\
20291 #define RADIO130NM_SYNTH1__PWD_LOBUF2G__WRITE(src) \
20292 (((u_int32_t)(src)\
20294 #define RADIO130NM_SYNTH1__PWD_LOBUF2G__MODIFY(dst, src) \
20296 ~0x04000000U) | (((u_int32_t)(src) <<\
20298 #define RADIO130NM_SYNTH1__PWD_LOBUF2G__VERIFY(src) \
20299 (!((((u_int32_t)(src)\
20312 #define RADIO130NM_SYNTH1__PWD_PRESC__READ(src) \
20313 (((u_int32_t)(src)\
20315 #define RADIO130NM_SYNTH1__PWD_PRESC__WRITE(src) \
20316 (((u_int32_t)(src)\
20318 #define RADIO130NM_SYNTH1__PWD_PRESC__MODIFY(dst, src) \
20320 ~0x08000000U) | (((u_int32_t)(src) <<\
20322 #define RADIO130NM_SYNTH1__PWD_PRESC__VERIFY(src) \
20323 (!((((u_int32_t)(src)\
20336 #define RADIO130NM_SYNTH1__PWD_VCO__READ(src) \
20337 (((u_int32_t)(src)\
20339 #define RADIO130NM_SYNTH1__PWD_VCO__WRITE(src) \
20340 (((u_int32_t)(src)\
20342 #define RADIO130NM_SYNTH1__PWD_VCO__MODIFY(dst, src) \
20344 ~0x10000000U) | (((u_int32_t)(src) <<\
20346 #define RADIO130NM_SYNTH1__PWD_VCO__VERIFY(src) \
20347 (!((((u_int32_t)(src)\
20360 #define RADIO130NM_SYNTH1__PWD_VCMON__READ(src) \
20361 (((u_int32_t)(src)\
20363 #define RADIO130NM_SYNTH1__PWD_VCMON__WRITE(src) \
20364 (((u_int32_t)(src)\
20366 #define RADIO130NM_SYNTH1__PWD_VCMON__MODIFY(dst, src) \
20368 ~0x20000000U) | (((u_int32_t)(src) <<\
20370 #define RADIO130NM_SYNTH1__PWD_VCMON__VERIFY(src) \
20371 (!((((u_int32_t)(src)\
20384 #define RADIO130NM_SYNTH1__PWD_CP__READ(src) \
20385 (((u_int32_t)(src)\
20387 #define RADIO130NM_SYNTH1__PWD_CP__WRITE(src) \
20388 (((u_int32_t)(src)\
20390 #define RADIO130NM_SYNTH1__PWD_CP__MODIFY(dst, src) \
20392 ~0x40000000U) | (((u_int32_t)(src) <<\
20394 #define RADIO130NM_SYNTH1__PWD_CP__VERIFY(src) \
20395 (!((((u_int32_t)(src)\
20408 #define RADIO130NM_SYNTH1__PWD_BIAS__READ(src) \
20409 (((u_int32_t)(src)\
20411 #define RADIO130NM_SYNTH1__PWD_BIAS__WRITE(src) \
20412 (((u_int32_t)(src)\
20414 #define RADIO130NM_SYNTH1__PWD_BIAS__MODIFY(dst, src) \
20416 ~0x80000000U) | (((u_int32_t)(src) <<\
20418 #define RADIO130NM_SYNTH1__PWD_BIAS__VERIFY(src) \
20419 (!((((u_int32_t)(src)\
20445 #define RADIO130NM_SYNTH2__CAPRANGE3__READ(src) (u_int32_t)(src) & 0x0000000fU
20446 #define RADIO130NM_SYNTH2__CAPRANGE3__WRITE(src) \
20447 ((u_int32_t)(src)\
20449 #define RADIO130NM_SYNTH2__CAPRANGE3__MODIFY(dst, src) \
20451 ~0x0000000fU) | ((u_int32_t)(src) &\
20453 #define RADIO130NM_SYNTH2__CAPRANGE3__VERIFY(src) \
20454 (!(((u_int32_t)(src)\
20461 #define RADIO130NM_SYNTH2__CAPRANGE2__READ(src) \
20462 (((u_int32_t)(src)\
20464 #define RADIO130NM_SYNTH2__CAPRANGE2__WRITE(src) \
20465 (((u_int32_t)(src)\
20467 #define RADIO130NM_SYNTH2__CAPRANGE2__MODIFY(dst, src) \
20469 ~0x000000f0U) | (((u_int32_t)(src) <<\
20471 #define RADIO130NM_SYNTH2__CAPRANGE2__VERIFY(src) \
20472 (!((((u_int32_t)(src)\
20479 #define RADIO130NM_SYNTH2__CAPRANGE1__READ(src) \
20480 (((u_int32_t)(src)\
20482 #define RADIO130NM_SYNTH2__CAPRANGE1__WRITE(src) \
20483 (((u_int32_t)(src)\
20485 #define RADIO130NM_SYNTH2__CAPRANGE1__MODIFY(dst, src) \
20487 ~0x00000f00U) | (((u_int32_t)(src) <<\
20489 #define RADIO130NM_SYNTH2__CAPRANGE1__VERIFY(src) \
20490 (!((((u_int32_t)(src)\
20497 #define RADIO130NM_SYNTH2__LOOPLEAKCUR__READ(src) \
20498 (((u_int32_t)(src)\
20500 #define RADIO130NM_SYNTH2__LOOPLEAKCUR__WRITE(src) \
20501 (((u_int32_t)(src)\
20503 #define RADIO130NM_SYNTH2__LOOPLEAKCUR__MODIFY(dst, src) \
20505 ~0x0000f000U) | (((u_int32_t)(src) <<\
20507 #define RADIO130NM_SYNTH2__LOOPLEAKCUR__VERIFY(src) \
20508 (!((((u_int32_t)(src)\
20515 #define RADIO130NM_SYNTH2__CPLOWLK__READ(src) \
20516 (((u_int32_t)(src)\
20518 #define RADIO130NM_SYNTH2__CPLOWLK__WRITE(src) \
20519 (((u_int32_t)(src)\
20521 #define RADIO130NM_SYNTH2__CPLOWLK__MODIFY(dst, src) \
20523 ~0x00010000U) | (((u_int32_t)(src) <<\
20525 #define RADIO130NM_SYNTH2__CPLOWLK__VERIFY(src) \
20526 (!((((u_int32_t)(src)\
20539 #define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__READ(src) \
20540 (((u_int32_t)(src)\
20542 #define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__WRITE(src) \
20543 (((u_int32_t)(src)\
20545 #define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__MODIFY(dst, src) \
20547 ~0x00020000U) | (((u_int32_t)(src) <<\
20549 #define RADIO130NM_SYNTH2__CPSTEERING_EN_INTN__VERIFY(src) \
20550 (!((((u_int32_t)(src)\
20563 #define RADIO130NM_SYNTH2__CPBIAS__READ(src) \
20564 (((u_int32_t)(src)\
20566 #define RADIO130NM_SYNTH2__CPBIAS__WRITE(src) \
20567 (((u_int32_t)(src)\
20569 #define RADIO130NM_SYNTH2__CPBIAS__MODIFY(dst, src) \
20571 ~0x000c0000U) | (((u_int32_t)(src) <<\
20573 #define RADIO130NM_SYNTH2__CPBIAS__VERIFY(src) \
20574 (!((((u_int32_t)(src)\
20581 #define RADIO130NM_SYNTH2__VC_LOW_REF__READ(src) \
20582 (((u_int32_t)(src)\
20584 #define RADIO130NM_SYNTH2__VC_LOW_REF__WRITE(src) \
20585 (((u_int32_t)(src)\
20587 #define RADIO130NM_SYNTH2__VC_LOW_REF__MODIFY(dst, src) \
20589 ~0x00700000U) | (((u_int32_t)(src) <<\
20591 #define RADIO130NM_SYNTH2__VC_LOW_REF__VERIFY(src) \
20592 (!((((u_int32_t)(src)\
20599 #define RADIO130NM_SYNTH2__VC_MID_REF__READ(src) \
20600 (((u_int32_t)(src)\
20602 #define RADIO130NM_SYNTH2__VC_MID_REF__WRITE(src) \
20603 (((u_int32_t)(src)\
20605 #define RADIO130NM_SYNTH2__VC_MID_REF__MODIFY(dst, src) \
20607 ~0x03800000U) | (((u_int32_t)(src) <<\
20609 #define RADIO130NM_SYNTH2__VC_MID_REF__VERIFY(src) \
20610 (!((((u_int32_t)(src)\
20617 #define RADIO130NM_SYNTH2__VC_HI_REF__READ(src) \
20618 (((u_int32_t)(src)\
20620 #define RADIO130NM_SYNTH2__VC_HI_REF__WRITE(src) \
20621 (((u_int32_t)(src)\
20623 #define RADIO130NM_SYNTH2__VC_HI_REF__MODIFY(dst, src) \
20625 ~0x1c000000U) | (((u_int32_t)(src) <<\
20627 #define RADIO130NM_SYNTH2__VC_HI_REF__VERIFY(src) \
20628 (!((((u_int32_t)(src)\
20635 #define RADIO130NM_SYNTH2__VC_CAL_REF__READ(src) \
20636 (((u_int32_t)(src)\
20638 #define RADIO130NM_SYNTH2__VC_CAL_REF__WRITE(src) \
20639 (((u_int32_t)(src)\
20641 #define RADIO130NM_SYNTH2__VC_CAL_REF__MODIFY(dst, src) \
20643 ~0xe0000000U) | (((u_int32_t)(src) <<\
20645 #define RADIO130NM_SYNTH2__VC_CAL_REF__VERIFY(src) \
20646 (!((((u_int32_t)(src)\
20666 #define RADIO130NM_SYNTH3__WAIT_VC_CHECK__READ(src) \
20667 (u_int32_t)(src)\
20669 #define RADIO130NM_SYNTH3__WAIT_VC_CHECK__WRITE(src) \
20670 ((u_int32_t)(src)\
20672 #define RADIO130NM_SYNTH3__WAIT_VC_CHECK__MODIFY(dst, src) \
20674 ~0x0000003fU) | ((u_int32_t)(src) &\
20676 #define RADIO130NM_SYNTH3__WAIT_VC_CHECK__VERIFY(src) \
20677 (!(((u_int32_t)(src)\
20684 #define RADIO130NM_SYNTH3__WAIT_CAL_LIN__READ(src) \
20685 (((u_int32_t)(src)\
20687 #define RADIO130NM_SYNTH3__WAIT_CAL_LIN__WRITE(src) \
20688 (((u_int32_t)(src)\
20690 #define RADIO130NM_SYNTH3__WAIT_CAL_LIN__MODIFY(dst, src) \
20692 ~0x00000fc0U) | (((u_int32_t)(src) <<\
20694 #define RADIO130NM_SYNTH3__WAIT_CAL_LIN__VERIFY(src) \
20695 (!((((u_int32_t)(src)\
20702 #define RADIO130NM_SYNTH3__WAIT_CAL_BIN__READ(src) \
20703 (((u_int32_t)(src)\
20705 #define RADIO130NM_SYNTH3__WAIT_CAL_BIN__WRITE(src) \
20706 (((u_int32_t)(src)\
20708 #define RADIO130NM_SYNTH3__WAIT_CAL_BIN__MODIFY(dst, src) \
20710 ~0x0003f000U) | (((u_int32_t)(src) <<\
20712 #define RADIO130NM_SYNTH3__WAIT_CAL_BIN__VERIFY(src) \
20713 (!((((u_int32_t)(src)\
20720 #define RADIO130NM_SYNTH3__WAIT_PWRUP__READ(src) \
20721 (((u_int32_t)(src)\
20723 #define RADIO130NM_SYNTH3__WAIT_PWRUP__WRITE(src) \
20724 (((u_int32_t)(src)\
20726 #define RADIO130NM_SYNTH3__WAIT_PWRUP__MODIFY(dst, src) \
20728 ~0x00fc0000U) | (((u_int32_t)(src) <<\
20730 #define RADIO130NM_SYNTH3__WAIT_PWRUP__VERIFY(src) \
20731 (!((((u_int32_t)(src)\
20738 #define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__READ(src) \
20739 (((u_int32_t)(src)\
20741 #define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__WRITE(src) \
20742 (((u_int32_t)(src)\
20744 #define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__MODIFY(dst, src) \
20746 ~0x3f000000U) | (((u_int32_t)(src) <<\
20748 #define RADIO130NM_SYNTH3__WAIT_SHORTR_PWRUP__VERIFY(src) \
20749 (!((((u_int32_t)(src)\
20756 #define RADIO130NM_SYNTH3__SEL_CLK_DIV2__READ(src) \
20757 (((u_int32_t)(src)\
20759 #define RADIO130NM_SYNTH3__SEL_CLK_DIV2__WRITE(src) \
20760 (((u_int32_t)(src)\
20762 #define RADIO130NM_SYNTH3__SEL_CLK_DIV2__MODIFY(dst, src) \
20764 ~0x40000000U) | (((u_int32_t)(src) <<\
20766 #define RADIO130NM_SYNTH3__SEL_CLK_DIV2__VERIFY(src) \
20767 (!((((u_int32_t)(src)\
20780 #define RADIO130NM_SYNTH3__DIS_CLK_XTAL__READ(src) \
20781 (((u_int32_t)(src)\
20783 #define RADIO130NM_SYNTH3__DIS_CLK_XTAL__WRITE(src) \
20784 (((u_int32_t)(src)\
20786 #define RADIO130NM_SYNTH3__DIS_CLK_XTAL__MODIFY(dst, src) \
20788 ~0x80000000U) | (((u_int32_t)(src) <<\
20790 #define RADIO130NM_SYNTH3__DIS_CLK_XTAL__VERIFY(src) \
20791 (!((((u_int32_t)(src)\
20817 #define RADIO130NM_SYNTH4__FORCE_SHIFTREG__READ(src) \
20818 (u_int32_t)(src)\
20820 #define RADIO130NM_SYNTH4__FORCE_SHIFTREG__WRITE(src) \
20821 ((u_int32_t)(src)\
20823 #define RADIO130NM_SYNTH4__FORCE_SHIFTREG__MODIFY(dst, src) \
20825 ~0x00000001U) | ((u_int32_t)(src) &\
20827 #define RADIO130NM_SYNTH4__FORCE_SHIFTREG__VERIFY(src) \
20828 (!(((u_int32_t)(src)\
20841 #define RADIO130NM_SYNTH4__LONGSHIFTSEL__READ(src) \
20842 (((u_int32_t)(src)\
20844 #define RADIO130NM_SYNTH4__LONGSHIFTSEL__WRITE(src) \
20845 (((u_int32_t)(src)\
20847 #define RADIO130NM_SYNTH4__LONGSHIFTSEL__MODIFY(dst, src) \
20849 ~0x00000002U) | (((u_int32_t)(src) <<\
20851 #define RADIO130NM_SYNTH4__LONGSHIFTSEL__VERIFY(src) \
20852 (!((((u_int32_t)(src)\
20865 #define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__READ(src) \
20866 (((u_int32_t)(src)\
20868 #define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__WRITE(src) \
20869 (((u_int32_t)(src)\
20871 #define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__MODIFY(dst, src) \
20873 ~0x0000000cU) | (((u_int32_t)(src) <<\
20875 #define RADIO130NM_SYNTH4__LOBUF5GTUNE_OVR__VERIFY(src) \
20876 (!((((u_int32_t)(src)\
20883 #define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__READ(src) \
20884 (((u_int32_t)(src)\
20886 #define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__WRITE(src) \
20887 (((u_int32_t)(src)\
20889 #define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__MODIFY(dst, src) \
20891 ~0x00000010U) | (((u_int32_t)(src) <<\
20893 #define RADIO130NM_SYNTH4__FORCE_LOBUF5GTUNE__VERIFY(src) \
20894 (!((((u_int32_t)(src)\
20907 #define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__READ(src) \
20908 (((u_int32_t)(src)\
20910 #define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__WRITE(src) \
20911 (((u_int32_t)(src)\
20913 #define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__MODIFY(dst, src) \
20915 ~0x00000020U) | (((u_int32_t)(src) <<\
20917 #define RADIO130NM_SYNTH4__PSCOUNT_FBSEL__VERIFY(src) \
20918 (!((((u_int32_t)(src)\
20931 #define RADIO130NM_SYNTH4__SDM_DITHER__READ(src) \
20932 (((u_int32_t)(src)\
20934 #define RADIO130NM_SYNTH4__SDM_DITHER__WRITE(src) \
20935 (((u_int32_t)(src)\
20937 #define RADIO130NM_SYNTH4__SDM_DITHER__MODIFY(dst, src) \
20939 ~0x000000c0U) | (((u_int32_t)(src) <<\
20941 #define RADIO130NM_SYNTH4__SDM_DITHER__VERIFY(src) \
20942 (!((((u_int32_t)(src)\
20949 #define RADIO130NM_SYNTH4__SDM_MODE__READ(src) \
20950 (((u_int32_t)(src)\
20952 #define RADIO130NM_SYNTH4__SDM_MODE__WRITE(src) \
20953 (((u_int32_t)(src)\
20955 #define RADIO130NM_SYNTH4__SDM_MODE__MODIFY(dst, src) \
20957 ~0x00000100U) | (((u_int32_t)(src) <<\
20959 #define RADIO130NM_SYNTH4__SDM_MODE__VERIFY(src) \
20960 (!((((u_int32_t)(src)\
20973 #define RADIO130NM_SYNTH4__SDM_DISABLE__READ(src) \
20974 (((u_int32_t)(src)\
20976 #define RADIO130NM_SYNTH4__SDM_DISABLE__WRITE(src) \
20977 (((u_int32_t)(src)\
20979 #define RADIO130NM_SYNTH4__SDM_DISABLE__MODIFY(dst, src) \
20981 ~0x00000200U) | (((u_int32_t)(src) <<\
20983 #define RADIO130NM_SYNTH4__SDM_DISABLE__VERIFY(src) \
20984 (!((((u_int32_t)(src)\
20997 #define RADIO130NM_SYNTH4__RESET_PRESC__READ(src) \
20998 (((u_int32_t)(src)\
21000 #define RADIO130NM_SYNTH4__RESET_PRESC__WRITE(src) \
21001 (((u_int32_t)(src)\
21003 #define RADIO130NM_SYNTH4__RESET_PRESC__MODIFY(dst, src) \
21005 ~0x00000400U) | (((u_int32_t)(src) <<\
21007 #define RADIO130NM_SYNTH4__RESET_PRESC__VERIFY(src) \
21008 (!((((u_int32_t)(src)\
21021 #define RADIO130NM_SYNTH4__PRESCSEL__READ(src) \
21022 (((u_int32_t)(src)\
21024 #define RADIO130NM_SYNTH4__PRESCSEL__WRITE(src) \
21025 (((u_int32_t)(src)\
21027 #define RADIO130NM_SYNTH4__PRESCSEL__MODIFY(dst, src) \
21029 ~0x00001800U) | (((u_int32_t)(src) <<\
21031 #define RADIO130NM_SYNTH4__PRESCSEL__VERIFY(src) \
21032 (!((((u_int32_t)(src)\
21039 #define RADIO130NM_SYNTH4__PFD_DISABLE__READ(src) \
21040 (((u_int32_t)(src)\
21042 #define RADIO130NM_SYNTH4__PFD_DISABLE__WRITE(src) \
21043 (((u_int32_t)(src)\
21045 #define RADIO130NM_SYNTH4__PFD_DISABLE__MODIFY(dst, src) \
21047 ~0x00002000U) | (((u_int32_t)(src) <<\
21049 #define RADIO130NM_SYNTH4__PFD_DISABLE__VERIFY(src) \
21050 (!((((u_int32_t)(src)\
21063 #define RADIO130NM_SYNTH4__PFDDELAY_FRACN__READ(src) \
21064 (((u_int32_t)(src)\
21066 #define RADIO130NM_SYNTH4__PFDDELAY_FRACN__WRITE(src) \
21067 (((u_int32_t)(src)\
21069 #define RADIO130NM_SYNTH4__PFDDELAY_FRACN__MODIFY(dst, src) \
21071 ~0x00004000U) | (((u_int32_t)(src) <<\
21073 #define RADIO130NM_SYNTH4__PFDDELAY_FRACN__VERIFY(src) \
21074 (!((((u_int32_t)(src)\
21087 #define RADIO130NM_SYNTH4__FORCE_LO_ON__READ(src) \
21088 (((u_int32_t)(src)\
21090 #define RADIO130NM_SYNTH4__FORCE_LO_ON__WRITE(src) \
21091 (((u_int32_t)(src)\
21093 #define RADIO130NM_SYNTH4__FORCE_LO_ON__MODIFY(dst, src) \
21095 ~0x00008000U) | (((u_int32_t)(src) <<\
21097 #define RADIO130NM_SYNTH4__FORCE_LO_ON__VERIFY(src) \
21098 (!((((u_int32_t)(src)\
21111 #define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__READ(src) \
21112 (((u_int32_t)(src)\
21114 #define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__WRITE(src) \
21115 (((u_int32_t)(src)\
21117 #define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__MODIFY(dst, src) \
21119 ~0x00010000U) | (((u_int32_t)(src) <<\
21121 #define RADIO130NM_SYNTH4__CLKXTAL_EDGE_SEL__VERIFY(src) \
21122 (!((((u_int32_t)(src)\
21135 #define RADIO130NM_SYNTH4__VCOCAPPULLUP__READ(src) \
21136 (((u_int32_t)(src)\
21138 #define RADIO130NM_SYNTH4__VCOCAPPULLUP__WRITE(src) \
21139 (((u_int32_t)(src)\
21141 #define RADIO130NM_SYNTH4__VCOCAPPULLUP__MODIFY(dst, src) \
21143 ~0x00020000U) | (((u_int32_t)(src) <<\
21145 #define RADIO130NM_SYNTH4__VCOCAPPULLUP__VERIFY(src) \
21146 (!((((u_int32_t)(src)\
21159 #define RADIO130NM_SYNTH4__VCOCAP_OVR__READ(src) \
21160 (((u_int32_t)(src)\
21162 #define RADIO130NM_SYNTH4__VCOCAP_OVR__WRITE(src) \
21163 (((u_int32_t)(src)\
21165 #define RADIO130NM_SYNTH4__VCOCAP_OVR__MODIFY(dst, src) \
21167 ~0x03fc0000U) | (((u_int32_t)(src) <<\
21169 #define RADIO130NM_SYNTH4__VCOCAP_OVR__VERIFY(src) \
21170 (!((((u_int32_t)(src)\
21177 #define RADIO130NM_SYNTH4__FORCE_VCOCAP__READ(src) \
21178 (((u_int32_t)(src)\
21180 #define RADIO130NM_SYNTH4__FORCE_VCOCAP__WRITE(src) \
21181 (((u_int32_t)(src)\
21183 #define RADIO130NM_SYNTH4__FORCE_VCOCAP__MODIFY(dst, src) \
21185 ~0x04000000U) | (((u_int32_t)(src) <<\
21187 #define RADIO130NM_SYNTH4__FORCE_VCOCAP__VERIFY(src) \
21188 (!((((u_int32_t)(src)\
21201 #define RADIO130NM_SYNTH4__FORCE_PINVC__READ(src) \
21202 (((u_int32_t)(src)\
21204 #define RADIO130NM_SYNTH4__FORCE_PINVC__WRITE(src) \
21205 (((u_int32_t)(src)\
21207 #define RADIO130NM_SYNTH4__FORCE_PINVC__MODIFY(dst, src) \
21209 ~0x08000000U) | (((u_int32_t)(src) <<\
21211 #define RADIO130NM_SYNTH4__FORCE_PINVC__VERIFY(src) \
21212 (!((((u_int32_t)(src)\
21225 #define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__READ(src) \
21226 (((u_int32_t)(src)\
21228 #define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__WRITE(src) \
21229 (((u_int32_t)(src)\
21231 #define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__MODIFY(dst, src) \
21233 ~0x10000000U) | (((u_int32_t)(src) <<\
21235 #define RADIO130NM_SYNTH4__SHORTR_UNTIL_LOCKED__VERIFY(src) \
21236 (!((((u_int32_t)(src)\
21249 #define RADIO130NM_SYNTH4__ALWAYS_SHORTR__READ(src) \
21250 (((u_int32_t)(src)\
21252 #define RADIO130NM_SYNTH4__ALWAYS_SHORTR__WRITE(src) \
21253 (((u_int32_t)(src)\
21255 #define RADIO130NM_SYNTH4__ALWAYS_SHORTR__MODIFY(dst, src) \
21257 ~0x20000000U) | (((u_int32_t)(src) <<\
21259 #define RADIO130NM_SYNTH4__ALWAYS_SHORTR__VERIFY(src) \
21260 (!((((u_int32_t)(src)\
21273 #define RADIO130NM_SYNTH4__DIS_LOSTVC__READ(src) \
21274 (((u_int32_t)(src)\
21276 #define RADIO130NM_SYNTH4__DIS_LOSTVC__WRITE(src) \
21277 (((u_int32_t)(src)\
21279 #define RADIO130NM_SYNTH4__DIS_LOSTVC__MODIFY(dst, src) \
21281 ~0x40000000U) | (((u_int32_t)(src) <<\
21283 #define RADIO130NM_SYNTH4__DIS_LOSTVC__VERIFY(src) \
21284 (!((((u_int32_t)(src)\
21297 #define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__READ(src) \
21298 (((u_int32_t)(src)\
21300 #define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__WRITE(src) \
21301 (((u_int32_t)(src)\
21303 #define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__MODIFY(dst, src) \
21305 ~0x80000000U) | (((u_int32_t)(src) <<\
21307 #define RADIO130NM_SYNTH4__DIS_LIN_CAPSEARCH__VERIFY(src) \
21308 (!((((u_int32_t)(src)\
21334 #define RADIO130NM_SYNTH5__ICPKCOMP__READ(src) (u_int32_t)(src) & 0x00000003U
21335 #define RADIO130NM_SYNTH5__ICPKCOMP__WRITE(src) \
21336 ((u_int32_t)(src)\
21338 #define RADIO130NM_SYNTH5__ICPKCOMP__MODIFY(dst, src) \
21340 ~0x00000003U) | ((u_int32_t)(src) &\
21342 #define RADIO130NM_SYNTH5__ICPKCOMP__VERIFY(src) \
21343 (!(((u_int32_t)(src)\
21350 #define RADIO130NM_SYNTH5__ICLOBUF5G__READ(src) \
21351 (((u_int32_t)(src)\
21353 #define RADIO130NM_SYNTH5__ICLOBUF5G__WRITE(src) \
21354 (((u_int32_t)(src)\
21356 #define RADIO130NM_SYNTH5__ICLOBUF5G__MODIFY(dst, src) \
21358 ~0x0000001cU) | (((u_int32_t)(src) <<\
21360 #define RADIO130NM_SYNTH5__ICLOBUF5G__VERIFY(src) \
21361 (!((((u_int32_t)(src)\
21368 #define RADIO130NM_SYNTH5__ICLOBUF2G__READ(src) \
21369 (((u_int32_t)(src)\
21371 #define RADIO130NM_SYNTH5__ICLOBUF2G__WRITE(src) \
21372 (((u_int32_t)(src)\
21374 #define RADIO130NM_SYNTH5__ICLOBUF2G__MODIFY(dst, src) \
21376 ~0x000000e0U) | (((u_int32_t)(src) <<\
21378 #define RADIO130NM_SYNTH5__ICLOBUF2G__VERIFY(src) \
21379 (!((((u_int32_t)(src)\
21386 #define RADIO130NM_SYNTH5__ICVCO__READ(src) \
21387 (((u_int32_t)(src)\
21389 #define RADIO130NM_SYNTH5__ICVCO__WRITE(src) \
21390 (((u_int32_t)(src)\
21392 #define RADIO130NM_SYNTH5__ICVCO__MODIFY(dst, src) \
21394 ~0x00000700U) | (((u_int32_t)(src) <<\
21396 #define RADIO130NM_SYNTH5__ICVCO__VERIFY(src) \
21397 (!((((u_int32_t)(src)\
21404 #define RADIO130NM_SYNTH5__ICVCOREG__READ(src) \
21405 (((u_int32_t)(src)\
21407 #define RADIO130NM_SYNTH5__ICVCOREG__WRITE(src) \
21408 (((u_int32_t)(src)\
21410 #define RADIO130NM_SYNTH5__ICVCOREG__MODIFY(dst, src) \
21412 ~0x00003800U) | (((u_int32_t)(src) <<\
21414 #define RADIO130NM_SYNTH5__ICVCOREG__VERIFY(src) \
21415 (!((((u_int32_t)(src)\
21422 #define RADIO130NM_SYNTH5__ICLOMIX__READ(src) \
21423 (((u_int32_t)(src)\
21425 #define RADIO130NM_SYNTH5__ICLOMIX__WRITE(src) \
21426 (((u_int32_t)(src)\
21428 #define RADIO130NM_SYNTH5__ICLOMIX__MODIFY(dst, src) \
21430 ~0x0001c000U) | (((u_int32_t)(src) <<\
21432 #define RADIO130NM_SYNTH5__ICLOMIX__VERIFY(src) \
21433 (!((((u_int32_t)(src)\
21440 #define RADIO130NM_SYNTH5__ICLODIV__READ(src) \
21441 (((u_int32_t)(src)\
21443 #define RADIO130NM_SYNTH5__ICLODIV__WRITE(src) \
21444 (((u_int32_t)(src)\
21446 #define RADIO130NM_SYNTH5__ICLODIV__MODIFY(dst, src) \
21448 ~0x000e0000U) | (((u_int32_t)(src) <<\
21450 #define RADIO130NM_SYNTH5__ICLODIV__VERIFY(src) \
21451 (!((((u_int32_t)(src)\
21458 #define RADIO130NM_SYNTH5__ICPRESC__READ(src) \
21459 (((u_int32_t)(src)\
21461 #define RADIO130NM_SYNTH5__ICPRESC__WRITE(src) \
21462 (((u_int32_t)(src)\
21464 #define RADIO130NM_SYNTH5__ICPRESC__MODIFY(dst, src) \
21466 ~0x00700000U) | (((u_int32_t)(src) <<\
21468 #define RADIO130NM_SYNTH5__ICPRESC__VERIFY(src) \
21469 (!((((u_int32_t)(src)\
21476 #define RADIO130NM_SYNTH5__IRLOPKDET__READ(src) \
21477 (((u_int32_t)(src)\
21479 #define RADIO130NM_SYNTH5__IRLOPKDET__WRITE(src) \
21480 (((u_int32_t)(src)\
21482 #define RADIO130NM_SYNTH5__IRLOPKDET__MODIFY(dst, src) \
21484 ~0x03800000U) | (((u_int32_t)(src) <<\
21486 #define RADIO130NM_SYNTH5__IRLOPKDET__VERIFY(src) \
21487 (!((((u_int32_t)(src)\
21494 #define RADIO130NM_SYNTH5__IRVCMON__READ(src) \
21495 (((u_int32_t)(src)\
21497 #define RADIO130NM_SYNTH5__IRVCMON__WRITE(src) \
21498 (((u_int32_t)(src)\
21500 #define RADIO130NM_SYNTH5__IRVCMON__MODIFY(dst, src) \
21502 ~0x1c000000U) | (((u_int32_t)(src) <<\
21504 #define RADIO130NM_SYNTH5__IRVCMON__VERIFY(src) \
21505 (!((((u_int32_t)(src)\
21512 #define RADIO130NM_SYNTH5__IRCP__READ(src) \
21513 (((u_int32_t)(src)\
21515 #define RADIO130NM_SYNTH5__IRCP__WRITE(src) \
21516 (((u_int32_t)(src)\
21518 #define RADIO130NM_SYNTH5__IRCP__MODIFY(dst, src) \
21520 ~0xe0000000U) | (((u_int32_t)(src) <<\
21522 #define RADIO130NM_SYNTH5__IRCP__VERIFY(src) \
21523 (!((((u_int32_t)(src)\
21543 #define RADIO130NM_SYNTH6__LOBUF5GTUNE__READ(src) \
21544 (u_int32_t)(src)\
21551 #define RADIO130NM_SYNTH6__LOOP_IP__READ(src) \
21552 (((u_int32_t)(src)\
21559 #define RADIO130NM_SYNTH6__VC2LOW__READ(src) \
21560 (((u_int32_t)(src)\
21573 #define RADIO130NM_SYNTH6__VC2HIGH__READ(src) \
21574 (((u_int32_t)(src)\
21587 #define RADIO130NM_SYNTH6__RESET_SDM_B__READ(src) \
21588 (((u_int32_t)(src)\
21601 #define RADIO130NM_SYNTH6__RESET_PSCOUNTERS__READ(src) \
21602 (((u_int32_t)(src)\
21615 #define RADIO130NM_SYNTH6__RESET_PFD__READ(src) \
21616 (((u_int32_t)(src)\
21629 #define RADIO130NM_SYNTH6__RESET_RFD__READ(src) \
21630 (((u_int32_t)(src)\
21643 #define RADIO130NM_SYNTH6__SHORT_R__READ(src) \
21644 (((u_int32_t)(src)\
21657 #define RADIO130NM_SYNTH6__VCO_CAP_ST__READ(src) \
21658 (((u_int32_t)(src)\
21665 #define RADIO130NM_SYNTH6__PIN_VC__READ(src) \
21666 (((u_int32_t)(src)\
21679 #define RADIO130NM_SYNTH6__SYNTH_LOCK_VC_OK__READ(src) \
21680 (((u_int32_t)(src)\
21693 #define RADIO130NM_SYNTH6__CAP_SEARCH__READ(src) \
21694 (((u_int32_t)(src)\
21707 #define RADIO130NM_SYNTH6__SYNTH_SM_STATE__READ(src) \
21708 (((u_int32_t)(src)\
21715 #define RADIO130NM_SYNTH6__SYNTH_ON__READ(src) \
21716 (((u_int32_t)(src)\
21741 #define RADIO130NM_SYNTH7__OVRCHANDECODER__READ(src) \
21742 (u_int32_t)(src)\
21744 #define RADIO130NM_SYNTH7__OVRCHANDECODER__WRITE(src) \
21745 ((u_int32_t)(src)\
21747 #define RADIO130NM_SYNTH7__OVRCHANDECODER__MODIFY(dst, src) \
21749 ~0x00000001U) | ((u_int32_t)(src) &\
21751 #define RADIO130NM_SYNTH7__OVRCHANDECODER__VERIFY(src) \
21752 (!(((u_int32_t)(src)\
21765 #define RADIO130NM_SYNTH7__FORCE_FRACLSB__READ(src) \
21766 (((u_int32_t)(src)\
21768 #define RADIO130NM_SYNTH7__FORCE_FRACLSB__WRITE(src) \
21769 (((u_int32_t)(src)\
21771 #define RADIO130NM_SYNTH7__FORCE_FRACLSB__MODIFY(dst, src) \
21773 ~0x00000002U) | (((u_int32_t)(src) <<\
21775 #define RADIO130NM_SYNTH7__FORCE_FRACLSB__VERIFY(src) \
21776 (!((((u_int32_t)(src)\
21789 #define RADIO130NM_SYNTH7__CHANFRAC__READ(src) \
21790 (((u_int32_t)(src)\
21792 #define RADIO130NM_SYNTH7__CHANFRAC__WRITE(src) \
21793 (((u_int32_t)(src)\
21795 #define RADIO130NM_SYNTH7__CHANFRAC__MODIFY(dst, src) \
21797 ~0x0007fffcU) | (((u_int32_t)(src) <<\
21799 #define RADIO130NM_SYNTH7__CHANFRAC__VERIFY(src) \
21800 (!((((u_int32_t)(src)\
21807 #define RADIO130NM_SYNTH7__CHANSEL__READ(src) \
21808 (((u_int32_t)(src)\
21810 #define RADIO130NM_SYNTH7__CHANSEL__WRITE(src) \
21811 (((u_int32_t)(src)\
21813 #define RADIO130NM_SYNTH7__CHANSEL__MODIFY(dst, src) \
21815 ~0x0ff80000U) | (((u_int32_t)(src) <<\
21817 #define RADIO130NM_SYNTH7__CHANSEL__VERIFY(src) \
21818 (!((((u_int32_t)(src)\
21825 #define RADIO130NM_SYNTH7__AMODEREFSEL__READ(src) \
21826 (((u_int32_t)(src)\
21828 #define RADIO130NM_SYNTH7__AMODEREFSEL__WRITE(src) \
21829 (((u_int32_t)(src)\
21831 #define RADIO130NM_SYNTH7__AMODEREFSEL__MODIFY(dst, src) \
21833 ~0x30000000U) | (((u_int32_t)(src) <<\
21835 #define RADIO130NM_SYNTH7__AMODEREFSEL__VERIFY(src) \
21836 (!((((u_int32_t)(src)\
21843 #define RADIO130NM_SYNTH7__FRACMODE__READ(src) \
21844 (((u_int32_t)(src)\
21846 #define RADIO130NM_SYNTH7__FRACMODE__WRITE(src) \
21847 (((u_int32_t)(src)\
21849 #define RADIO130NM_SYNTH7__FRACMODE__MODIFY(dst, src) \
21851 ~0x40000000U) | (((u_int32_t)(src) <<\
21853 #define RADIO130NM_SYNTH7__FRACMODE__VERIFY(src) \
21854 (!((((u_int32_t)(src)\
21867 #define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__READ(src) \
21868 (((u_int32_t)(src)\
21870 #define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__WRITE(src) \
21871 (((u_int32_t)(src)\
21873 #define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__MODIFY(dst, src) \
21875 ~0x80000000U) | (((u_int32_t)(src) <<\
21877 #define RADIO130NM_SYNTH7__LOADSYNTHCHANNEL__VERIFY(src) \
21878 (!((((u_int32_t)(src)\
21904 #define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__READ(src) \
21905 (u_int32_t)(src)\
21907 #define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__WRITE(src) \
21908 ((u_int32_t)(src)\
21910 #define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__MODIFY(dst, src) \
21912 ~0x00000001U) | ((u_int32_t)(src) &\
21914 #define RADIO130NM_SYNTH8__CPSTEERING_EN_FRACN__VERIFY(src) \
21915 (!(((u_int32_t)(src)\
21928 #define RADIO130NM_SYNTH8__LOOP_ICPB__READ(src) \
21929 (((u_int32_t)(src)\
21931 #define RADIO130NM_SYNTH8__LOOP_ICPB__WRITE(src) \
21932 (((u_int32_t)(src)\
21934 #define RADIO130NM_SYNTH8__LOOP_ICPB__MODIFY(dst, src) \
21936 ~0x000000feU) | (((u_int32_t)(src) <<\
21938 #define RADIO130NM_SYNTH8__LOOP_ICPB__VERIFY(src) \
21939 (!((((u_int32_t)(src)\
21946 #define RADIO130NM_SYNTH8__LOOP_CSB__READ(src) \
21947 (((u_int32_t)(src)\
21949 #define RADIO130NM_SYNTH8__LOOP_CSB__WRITE(src) \
21950 (((u_int32_t)(src)\
21952 #define RADIO130NM_SYNTH8__LOOP_CSB__MODIFY(dst, src) \
21954 ~0x00000f00U) | (((u_int32_t)(src) <<\
21956 #define RADIO130NM_SYNTH8__LOOP_CSB__VERIFY(src) \
21957 (!((((u_int32_t)(src)\
21964 #define RADIO130NM_SYNTH8__LOOP_RSB__READ(src) \
21965 (((u_int32_t)(src)\
21967 #define RADIO130NM_SYNTH8__LOOP_RSB__WRITE(src) \
21968 (((u_int32_t)(src)\
21970 #define RADIO130NM_SYNTH8__LOOP_RSB__MODIFY(dst, src) \
21972 ~0x0001f000U) | (((u_int32_t)(src) <<\
21974 #define RADIO130NM_SYNTH8__LOOP_RSB__VERIFY(src) \
21975 (!((((u_int32_t)(src)\
21982 #define RADIO130NM_SYNTH8__LOOP_CPB__READ(src) \
21983 (((u_int32_t)(src)\
21985 #define RADIO130NM_SYNTH8__LOOP_CPB__WRITE(src) \
21986 (((u_int32_t)(src)\
21988 #define RADIO130NM_SYNTH8__LOOP_CPB__MODIFY(dst, src) \
21990 ~0x003e0000U) | (((u_int32_t)(src) <<\
21992 #define RADIO130NM_SYNTH8__LOOP_CPB__VERIFY(src) \
21993 (!((((u_int32_t)(src)\
22000 #define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__READ(src) \
22001 (((u_int32_t)(src)\
22003 #define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__WRITE(src) \
22004 (((u_int32_t)(src)\
22006 #define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__MODIFY(dst, src) \
22008 ~0x07c00000U) | (((u_int32_t)(src) <<\
22010 #define RADIO130NM_SYNTH8__LOOP_3RD_ORDER_RB__VERIFY(src) \
22011 (!((((u_int32_t)(src)\
22018 #define RADIO130NM_SYNTH8__REFDIVB__READ(src) \
22019 (((u_int32_t)(src)\
22021 #define RADIO130NM_SYNTH8__REFDIVB__WRITE(src) \
22022 (((u_int32_t)(src)\
22024 #define RADIO130NM_SYNTH8__REFDIVB__MODIFY(dst, src) \
22026 ~0xf8000000U) | (((u_int32_t)(src) <<\
22028 #define RADIO130NM_SYNTH8__REFDIVB__VERIFY(src) \
22029 (!((((u_int32_t)(src)\
22049 #define RADIO130NM_SYNTH9__PFDDELAY_INTN__READ(src) \
22050 (u_int32_t)(src)\
22052 #define RADIO130NM_SYNTH9__PFDDELAY_INTN__WRITE(src) \
22053 ((u_int32_t)(src)\
22055 #define RADIO130NM_SYNTH9__PFDDELAY_INTN__MODIFY(dst, src) \
22057 ~0x00000001U) | ((u_int32_t)(src) &\
22059 #define RADIO130NM_SYNTH9__PFDDELAY_INTN__VERIFY(src) \
22060 (!(((u_int32_t)(src)\
22073 #define RADIO130NM_SYNTH9__SLOPE_ICPA0__READ(src) \
22074 (((u_int32_t)(src)\
22076 #define RADIO130NM_SYNTH9__SLOPE_ICPA0__WRITE(src) \
22077 (((u_int32_t)(src)\
22079 #define RADIO130NM_SYNTH9__SLOPE_ICPA0__MODIFY(dst, src) \
22081 ~0x0000000eU) | (((u_int32_t)(src) <<\
22083 #define RADIO130NM_SYNTH9__SLOPE_ICPA0__VERIFY(src) \
22084 (!((((u_int32_t)(src)\
22091 #define RADIO130NM_SYNTH9__LOOP_ICPA0__READ(src) \
22092 (((u_int32_t)(src)\
22094 #define RADIO130NM_SYNTH9__LOOP_ICPA0__WRITE(src) \
22095 (((u_int32_t)(src)\
22097 #define RADIO130NM_SYNTH9__LOOP_ICPA0__MODIFY(dst, src) \
22099 ~0x000000f0U) | (((u_int32_t)(src) <<\
22101 #define RADIO130NM_SYNTH9__LOOP_ICPA0__VERIFY(src) \
22102 (!((((u_int32_t)(src)\
22109 #define RADIO130NM_SYNTH9__LOOP_CSA0__READ(src) \
22110 (((u_int32_t)(src)\
22112 #define RADIO130NM_SYNTH9__LOOP_CSA0__WRITE(src) \
22113 (((u_int32_t)(src)\
22115 #define RADIO130NM_SYNTH9__LOOP_CSA0__MODIFY(dst, src) \
22117 ~0x00000f00U) | (((u_int32_t)(src) <<\
22119 #define RADIO130NM_SYNTH9__LOOP_CSA0__VERIFY(src) \
22120 (!((((u_int32_t)(src)\
22127 #define RADIO130NM_SYNTH9__LOOP_RSA0__READ(src) \
22128 (((u_int32_t)(src)\
22130 #define RADIO130NM_SYNTH9__LOOP_RSA0__WRITE(src) \
22131 (((u_int32_t)(src)\
22133 #define RADIO130NM_SYNTH9__LOOP_RSA0__MODIFY(dst, src) \
22135 ~0x0001f000U) | (((u_int32_t)(src) <<\
22137 #define RADIO130NM_SYNTH9__LOOP_RSA0__VERIFY(src) \
22138 (!((((u_int32_t)(src)\
22145 #define RADIO130NM_SYNTH9__LOOP_CPA0__READ(src) \
22146 (((u_int32_t)(src)\
22148 #define RADIO130NM_SYNTH9__LOOP_CPA0__WRITE(src) \
22149 (((u_int32_t)(src)\
22151 #define RADIO130NM_SYNTH9__LOOP_CPA0__MODIFY(dst, src) \
22153 ~0x003e0000U) | (((u_int32_t)(src) <<\
22155 #define RADIO130NM_SYNTH9__LOOP_CPA0__VERIFY(src) \
22156 (!((((u_int32_t)(src)\
22163 #define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__READ(src) \
22164 (((u_int32_t)(src)\
22166 #define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__WRITE(src) \
22167 (((u_int32_t)(src)\
22169 #define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__MODIFY(dst, src) \
22171 ~0x07c00000U) | (((u_int32_t)(src) <<\
22173 #define RADIO130NM_SYNTH9__LOOP_3RD_ORDER_RA__VERIFY(src) \
22174 (!((((u_int32_t)(src)\
22181 #define RADIO130NM_SYNTH9__REFDIVA__READ(src) \
22182 (((u_int32_t)(src)\
22184 #define RADIO130NM_SYNTH9__REFDIVA__WRITE(src) \
22185 (((u_int32_t)(src)\
22187 #define RADIO130NM_SYNTH9__REFDIVA__MODIFY(dst, src) \
22189 ~0xf8000000U) | (((u_int32_t)(src) <<\
22191 #define RADIO130NM_SYNTH9__REFDIVA__VERIFY(src) \
22192 (!((((u_int32_t)(src)\
22212 #define RADIO130NM_SYNTH10__SPARE__READ(src) (u_int32_t)(src) & 0x000007ffU
22213 #define RADIO130NM_SYNTH10__SPARE__WRITE(src) ((u_int32_t)(src) & 0x000007ffU)
22214 #define RADIO130NM_SYNTH10__SPARE__MODIFY(dst, src) \
22216 ~0x000007ffU) | ((u_int32_t)(src) &\
22218 #define RADIO130NM_SYNTH10__SPARE__VERIFY(src) \
22219 (!(((u_int32_t)(src)\
22226 #define RADIO130NM_SYNTH10__SLOPE_ICPA1__READ(src) \
22227 (((u_int32_t)(src)\
22229 #define RADIO130NM_SYNTH10__SLOPE_ICPA1__WRITE(src) \
22230 (((u_int32_t)(src)\
22232 #define RADIO130NM_SYNTH10__SLOPE_ICPA1__MODIFY(dst, src) \
22234 ~0x00003800U) | (((u_int32_t)(src) <<\
22236 #define RADIO130NM_SYNTH10__SLOPE_ICPA1__VERIFY(src) \
22237 (!((((u_int32_t)(src)\
22244 #define RADIO130NM_SYNTH10__LOOP_ICPA1__READ(src) \
22245 (((u_int32_t)(src)\
22247 #define RADIO130NM_SYNTH10__LOOP_ICPA1__WRITE(src) \
22248 (((u_int32_t)(src)\
22250 #define RADIO130NM_SYNTH10__LOOP_ICPA1__MODIFY(dst, src) \
22252 ~0x0003c000U) | (((u_int32_t)(src) <<\
22254 #define RADIO130NM_SYNTH10__LOOP_ICPA1__VERIFY(src) \
22255 (!((((u_int32_t)(src)\
22262 #define RADIO130NM_SYNTH10__LOOP_CSA1__READ(src) \
22263 (((u_int32_t)(src)\
22265 #define RADIO130NM_SYNTH10__LOOP_CSA1__WRITE(src) \
22266 (((u_int32_t)(src)\
22268 #define RADIO130NM_SYNTH10__LOOP_CSA1__MODIFY(dst, src) \
22270 ~0x003c0000U) | (((u_int32_t)(src) <<\
22272 #define RADIO130NM_SYNTH10__LOOP_CSA1__VERIFY(src) \
22273 (!((((u_int32_t)(src)\
22280 #define RADIO130NM_SYNTH10__LOOP_RSA1__READ(src) \
22281 (((u_int32_t)(src)\
22283 #define RADIO130NM_SYNTH10__LOOP_RSA1__WRITE(src) \
22284 (((u_int32_t)(src)\
22286 #define RADIO130NM_SYNTH10__LOOP_RSA1__MODIFY(dst, src) \
22288 ~0x07c00000U) | (((u_int32_t)(src) <<\
22290 #define RADIO130NM_SYNTH10__LOOP_RSA1__VERIFY(src) \
22291 (!((((u_int32_t)(src)\
22298 #define RADIO130NM_SYNTH10__LOOP_CPA1__READ(src) \
22299 (((u_int32_t)(src)\
22301 #define RADIO130NM_SYNTH10__LOOP_CPA1__WRITE(src) \
22302 (((u_int32_t)(src)\
22304 #define RADIO130NM_SYNTH10__LOOP_CPA1__MODIFY(dst, src) \
22306 ~0xf8000000U) | (((u_int32_t)(src) <<\
22308 #define RADIO130NM_SYNTH10__LOOP_CPA1__VERIFY(src) \
22309 (!((((u_int32_t)(src)\
22329 #define RADIO130NM_SYNTH11__SPARE__READ(src) (u_int32_t)(src) & 0x0000001fU
22330 #define RADIO130NM_SYNTH11__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000001fU)
22331 #define RADIO130NM_SYNTH11__SPARE__MODIFY(dst, src) \
22333 ~0x0000001fU) | ((u_int32_t)(src) &\
22335 #define RADIO130NM_SYNTH11__SPARE__VERIFY(src) \
22336 (!(((u_int32_t)(src)\
22343 #define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__READ(src) \
22344 (((u_int32_t)(src)\
22346 #define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__WRITE(src) \
22347 (((u_int32_t)(src)\
22349 #define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__MODIFY(dst, src) \
22351 ~0x00000020U) | (((u_int32_t)(src) <<\
22353 #define RADIO130NM_SYNTH11__FORCE_LOBUF5G_ON__VERIFY(src) \
22354 (!((((u_int32_t)(src)\
22367 #define RADIO130NM_SYNTH11__LOREFSEL__READ(src) \
22368 (((u_int32_t)(src)\
22370 #define RADIO130NM_SYNTH11__LOREFSEL__WRITE(src) \
22371 (((u_int32_t)(src)\
22373 #define RADIO130NM_SYNTH11__LOREFSEL__MODIFY(dst, src) \
22375 ~0x000000c0U) | (((u_int32_t)(src) <<\
22377 #define RADIO130NM_SYNTH11__LOREFSEL__VERIFY(src) \
22378 (!((((u_int32_t)(src)\
22385 #define RADIO130NM_SYNTH11__LO2GSEL__READ(src) \
22386 (((u_int32_t)(src)\
22388 #define RADIO130NM_SYNTH11__LO2GSEL__WRITE(src) \
22389 (((u_int32_t)(src)\
22391 #define RADIO130NM_SYNTH11__LO2GSEL__MODIFY(dst, src) \
22393 ~0x00000300U) | (((u_int32_t)(src) <<\
22395 #define RADIO130NM_SYNTH11__LO2GSEL__VERIFY(src) \
22396 (!((((u_int32_t)(src)\
22403 #define RADIO130NM_SYNTH11__CPSTEERING_MODE__READ(src) \
22404 (((u_int32_t)(src)\
22406 #define RADIO130NM_SYNTH11__CPSTEERING_MODE__WRITE(src) \
22407 (((u_int32_t)(src)\
22409 #define RADIO130NM_SYNTH11__CPSTEERING_MODE__MODIFY(dst, src) \
22411 ~0x00000400U) | (((u_int32_t)(src) <<\
22413 #define RADIO130NM_SYNTH11__CPSTEERING_MODE__VERIFY(src) \
22414 (!((((u_int32_t)(src)\
22427 #define RADIO130NM_SYNTH11__SLOPE_ICPA2__READ(src) \
22428 (((u_int32_t)(src)\
22430 #define RADIO130NM_SYNTH11__SLOPE_ICPA2__WRITE(src) \
22431 (((u_int32_t)(src)\
22433 #define RADIO130NM_SYNTH11__SLOPE_ICPA2__MODIFY(dst, src) \
22435 ~0x00003800U) | (((u_int32_t)(src) <<\
22437 #define RADIO130NM_SYNTH11__SLOPE_ICPA2__VERIFY(src) \
22438 (!((((u_int32_t)(src)\
22445 #define RADIO130NM_SYNTH11__LOOP_ICPA2__READ(src) \
22446 (((u_int32_t)(src)\
22448 #define RADIO130NM_SYNTH11__LOOP_ICPA2__WRITE(src) \
22449 (((u_int32_t)(src)\
22451 #define RADIO130NM_SYNTH11__LOOP_ICPA2__MODIFY(dst, src) \
22453 ~0x0003c000U) | (((u_int32_t)(src) <<\
22455 #define RADIO130NM_SYNTH11__LOOP_ICPA2__VERIFY(src) \
22456 (!((((u_int32_t)(src)\
22463 #define RADIO130NM_SYNTH11__LOOP_CSA2__READ(src) \
22464 (((u_int32_t)(src)\
22466 #define RADIO130NM_SYNTH11__LOOP_CSA2__WRITE(src) \
22467 (((u_int32_t)(src)\
22469 #define RADIO130NM_SYNTH11__LOOP_CSA2__MODIFY(dst, src) \
22471 ~0x003c0000U) | (((u_int32_t)(src) <<\
22473 #define RADIO130NM_SYNTH11__LOOP_CSA2__VERIFY(src) \
22474 (!((((u_int32_t)(src)\
22481 #define RADIO130NM_SYNTH11__LOOP_RSA2__READ(src) \
22482 (((u_int32_t)(src)\
22484 #define RADIO130NM_SYNTH11__LOOP_RSA2__WRITE(src) \
22485 (((u_int32_t)(src)\
22487 #define RADIO130NM_SYNTH11__LOOP_RSA2__MODIFY(dst, src) \
22489 ~0x07c00000U) | (((u_int32_t)(src) <<\
22491 #define RADIO130NM_SYNTH11__LOOP_RSA2__VERIFY(src) \
22492 (!((((u_int32_t)(src)\
22499 #define RADIO130NM_SYNTH11__LOOP_CPA2__READ(src) \
22500 (((u_int32_t)(src)\
22502 #define RADIO130NM_SYNTH11__LOOP_CPA2__WRITE(src) \
22503 (((u_int32_t)(src)\
22505 #define RADIO130NM_SYNTH11__LOOP_CPA2__MODIFY(dst, src) \
22507 ~0xf8000000U) | (((u_int32_t)(src) <<\
22509 #define RADIO130NM_SYNTH11__LOOP_CPA2__VERIFY(src) \
22510 (!((((u_int32_t)(src)\
22530 #define RADIO130NM_BIAS1__PWD_IRPCIE50__READ(src) \
22531 (u_int32_t)(src)\
22533 #define RADIO130NM_BIAS1__PWD_IRPCIE50__WRITE(src) \
22534 ((u_int32_t)(src)\
22536 #define RADIO130NM_BIAS1__PWD_IRPCIE50__MODIFY(dst, src) \
22538 ~0x00000001U) | ((u_int32_t)(src) &\
22540 #define RADIO130NM_BIAS1__PWD_IRPCIE50__VERIFY(src) \
22541 (!(((u_int32_t)(src)\
22554 #define RADIO130NM_BIAS1__PWD_ICPCIE50__READ(src) \
22555 (((u_int32_t)(src)\
22557 #define RADIO130NM_BIAS1__PWD_ICPCIE50__WRITE(src) \
22558 (((u_int32_t)(src)\
22560 #define RADIO130NM_BIAS1__PWD_ICPCIE50__MODIFY(dst, src) \
22562 ~0x00000002U) | (((u_int32_t)(src) <<\
22564 #define RADIO130NM_BIAS1__PWD_ICPCIE50__VERIFY(src) \
22565 (!((((u_int32_t)(src)\
22578 #define RADIO130NM_BIAS1__PWD_IRPLL25__READ(src) \
22579 (((u_int32_t)(src)\
22581 #define RADIO130NM_BIAS1__PWD_IRPLL25__WRITE(src) \
22582 (((u_int32_t)(src)\
22584 #define RADIO130NM_BIAS1__PWD_IRPLL25__MODIFY(dst, src) \
22586 ~0x00000004U) | (((u_int32_t)(src) <<\
22588 #define RADIO130NM_BIAS1__PWD_IRPLL25__VERIFY(src) \
22589 (!((((u_int32_t)(src)\
22602 #define RADIO130NM_BIAS1__PWD_ICPLL25__READ(src) \
22603 (((u_int32_t)(src)\
22605 #define RADIO130NM_BIAS1__PWD_ICPLL25__WRITE(src) \
22606 (((u_int32_t)(src)\
22608 #define RADIO130NM_BIAS1__PWD_ICPLL25__MODIFY(dst, src) \
22610 ~0x00000008U) | (((u_int32_t)(src) <<\
22612 #define RADIO130NM_BIAS1__PWD_ICPLL25__VERIFY(src) \
22613 (!((((u_int32_t)(src)\
22626 #define RADIO130NM_BIAS1__PWD_IRRXLDO25__READ(src) \
22627 (((u_int32_t)(src)\
22629 #define RADIO130NM_BIAS1__PWD_IRRXLDO25__WRITE(src) \
22630 (((u_int32_t)(src)\
22632 #define RADIO130NM_BIAS1__PWD_IRRXLDO25__MODIFY(dst, src) \
22634 ~0x00000070U) | (((u_int32_t)(src) <<\
22636 #define RADIO130NM_BIAS1__PWD_IRRXLDO25__VERIFY(src) \
22637 (!((((u_int32_t)(src)\
22644 #define RADIO130NM_BIAS1__PWD_ICRXLDO25__READ(src) \
22645 (((u_int32_t)(src)\
22647 #define RADIO130NM_BIAS1__PWD_ICRXLDO25__WRITE(src) \
22648 (((u_int32_t)(src)\
22650 #define RADIO130NM_BIAS1__PWD_ICRXLDO25__MODIFY(dst, src) \
22652 ~0x00000380U) | (((u_int32_t)(src) <<\
22654 #define RADIO130NM_BIAS1__PWD_ICRXLDO25__VERIFY(src) \
22655 (!((((u_int32_t)(src)\
22662 #define RADIO130NM_BIAS1__PWD_IRXPALDO25__READ(src) \
22663 (((u_int32_t)(src)\
22665 #define RADIO130NM_BIAS1__PWD_IRXPALDO25__WRITE(src) \
22666 (((u_int32_t)(src)\
22668 #define RADIO130NM_BIAS1__PWD_IRXPALDO25__MODIFY(dst, src) \
22670 ~0x00001c00U) | (((u_int32_t)(src) <<\
22672 #define RADIO130NM_BIAS1__PWD_IRXPALDO25__VERIFY(src) \
22673 (!((((u_int32_t)(src)\
22680 #define RADIO130NM_BIAS1__PWD_ICXPALDO25__READ(src) \
22681 (((u_int32_t)(src)\
22683 #define RADIO130NM_BIAS1__PWD_ICXPALDO25__WRITE(src) \
22684 (((u_int32_t)(src)\
22686 #define RADIO130NM_BIAS1__PWD_ICXPALDO25__MODIFY(dst, src) \
22688 ~0x0000e000U) | (((u_int32_t)(src) <<\
22690 #define RADIO130NM_BIAS1__PWD_ICXPALDO25__VERIFY(src) \
22691 (!((((u_int32_t)(src)\
22698 #define RADIO130NM_BIAS1__PWD_IRXTAL25__READ(src) \
22699 (((u_int32_t)(src)\
22701 #define RADIO130NM_BIAS1__PWD_IRXTAL25__WRITE(src) \
22702 (((u_int32_t)(src)\
22704 #define RADIO130NM_BIAS1__PWD_IRXTAL25__MODIFY(dst, src) \
22706 ~0x00070000U) | (((u_int32_t)(src) <<\
22708 #define RADIO130NM_BIAS1__PWD_IRXTAL25__VERIFY(src) \
22709 (!((((u_int32_t)(src)\
22716 #define RADIO130NM_BIAS1__PWD_ICXTAL25__READ(src) \
22717 (((u_int32_t)(src)\
22719 #define RADIO130NM_BIAS1__PWD_ICXTAL25__WRITE(src) \
22720 (((u_int32_t)(src)\
22722 #define RADIO130NM_BIAS1__PWD_ICXTAL25__MODIFY(dst, src) \
22724 ~0x00380000U) | (((u_int32_t)(src) <<\
22726 #define RADIO130NM_BIAS1__PWD_ICXTAL25__VERIFY(src) \
22727 (!((((u_int32_t)(src)\
22734 #define RADIO130NM_BIAS1__BIAS1_SPARE__READ(src) \
22735 (((u_int32_t)(src)\
22737 #define RADIO130NM_BIAS1__BIAS1_SPARE__WRITE(src) \
22738 (((u_int32_t)(src)\
22740 #define RADIO130NM_BIAS1__BIAS1_SPARE__MODIFY(dst, src) \
22742 ~0x01c00000U) | (((u_int32_t)(src) <<\
22744 #define RADIO130NM_BIAS1__BIAS1_SPARE__VERIFY(src) \
22745 (!((((u_int32_t)(src)\
22752 #define RADIO130NM_BIAS1__SEL_BIAS__READ(src) \
22753 (((u_int32_t)(src)\
22755 #define RADIO130NM_BIAS1__SEL_BIAS__WRITE(src) \
22756 (((u_int32_t)(src)\
22758 #define RADIO130NM_BIAS1__SEL_BIAS__MODIFY(dst, src) \
22760 ~0x7e000000U) | (((u_int32_t)(src) <<\
22762 #define RADIO130NM_BIAS1__SEL_BIAS__VERIFY(src) \
22763 (!((((u_int32_t)(src)\
22770 #define RADIO130NM_BIAS1__PADON__READ(src) \
22771 (((u_int32_t)(src)\
22773 #define RADIO130NM_BIAS1__PADON__WRITE(src) \
22774 (((u_int32_t)(src)\
22776 #define RADIO130NM_BIAS1__PADON__MODIFY(dst, src) \
22778 ~0x80000000U) | (((u_int32_t)(src) <<\
22780 #define RADIO130NM_BIAS1__PADON__VERIFY(src) \
22781 (!((((u_int32_t)(src)\
22807 #define RADIO130NM_BIAS2__PWD_ICDAC50__READ(src) (u_int32_t)(src) & 0x00000007U
22808 #define RADIO130NM_BIAS2__PWD_ICDAC50__WRITE(src) \
22809 ((u_int32_t)(src)\
22811 #define RADIO130NM_BIAS2__PWD_ICDAC50__MODIFY(dst, src) \
22813 ~0x00000007U) | ((u_int32_t)(src) &\
22815 #define RADIO130NM_BIAS2__PWD_ICDAC50__VERIFY(src) \
22816 (!(((u_int32_t)(src)\
22823 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__READ(src) \
22824 (((u_int32_t)(src)\
22826 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__WRITE(src) \
22827 (((u_int32_t)(src)\
22829 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__MODIFY(dst, src) \
22831 ~0x00000008U) | (((u_int32_t)(src) <<\
22833 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRQ12P5__VERIFY(src) \
22834 (!((((u_int32_t)(src)\
22847 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__READ(src) \
22848 (((u_int32_t)(src)\
22850 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__WRITE(src) \
22851 (((u_int32_t)(src)\
22853 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__MODIFY(dst, src) \
22855 ~0x00000010U) | (((u_int32_t)(src) <<\
22857 #define RADIO130NM_BIAS2__PWD_IRADCREFMSTRI12P5__VERIFY(src) \
22858 (!((((u_int32_t)(src)\
22871 #define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__READ(src) \
22872 (((u_int32_t)(src)\
22874 #define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__WRITE(src) \
22875 (((u_int32_t)(src)\
22877 #define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__MODIFY(dst, src) \
22879 ~0x000000e0U) | (((u_int32_t)(src) <<\
22881 #define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPQ25__VERIFY(src) \
22882 (!((((u_int32_t)(src)\
22889 #define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__READ(src) \
22890 (((u_int32_t)(src)\
22892 #define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__WRITE(src) \
22893 (((u_int32_t)(src)\
22895 #define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__MODIFY(dst, src) \
22897 ~0x00000700U) | (((u_int32_t)(src) <<\
22899 #define RADIO130NM_BIAS2__PWD_ICADCREFOPAMPI25__VERIFY(src) \
22900 (!((((u_int32_t)(src)\
22907 #define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__READ(src) \
22908 (((u_int32_t)(src)\
22910 #define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__WRITE(src) \
22911 (((u_int32_t)(src)\
22913 #define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__MODIFY(dst, src) \
22915 ~0x00003800U) | (((u_int32_t)(src) <<\
22917 #define RADIO130NM_BIAS2__PWD_ICADCREFBUFQ12P5__VERIFY(src) \
22918 (!((((u_int32_t)(src)\
22925 #define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__READ(src) \
22926 (((u_int32_t)(src)\
22928 #define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__WRITE(src) \
22929 (((u_int32_t)(src)\
22931 #define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__MODIFY(dst, src) \
22933 ~0x0001c000U) | (((u_int32_t)(src) <<\
22935 #define RADIO130NM_BIAS2__PWD_ICADCREFBUFI12P5__VERIFY(src) \
22936 (!((((u_int32_t)(src)\
22943 #define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__READ(src) \
22944 (((u_int32_t)(src)\
22946 #define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__WRITE(src) \
22947 (((u_int32_t)(src)\
22949 #define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__MODIFY(dst, src) \
22951 ~0x000e0000U) | (((u_int32_t)(src) <<\
22953 #define RADIO130NM_BIAS2__PWD_ICADCCOMPQ25__VERIFY(src) \
22954 (!((((u_int32_t)(src)\
22961 #define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__READ(src) \
22962 (((u_int32_t)(src)\
22964 #define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__WRITE(src) \
22965 (((u_int32_t)(src)\
22967 #define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__MODIFY(dst, src) \
22969 ~0x00700000U) | (((u_int32_t)(src) <<\
22971 #define RADIO130NM_BIAS2__PWD_ICADCCOMPI25__VERIFY(src) \
22972 (!((((u_int32_t)(src)\
22979 #define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__READ(src) \
22980 (((u_int32_t)(src)\
22982 #define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__WRITE(src) \
22983 (((u_int32_t)(src)\
22985 #define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__MODIFY(dst, src) \
22987 ~0x00800000U) | (((u_int32_t)(src) <<\
22989 #define RADIO130NM_BIAS2__PWD_ICDACINTFACE25__VERIFY(src) \
22990 (!((((u_int32_t)(src)\
23003 #define RADIO130NM_BIAS2__PWD_IRBB50__READ(src) \
23004 (((u_int32_t)(src)\
23006 #define RADIO130NM_BIAS2__PWD_IRBB50__WRITE(src) \
23007 (((u_int32_t)(src)\
23009 #define RADIO130NM_BIAS2__PWD_IRBB50__MODIFY(dst, src) \
23011 ~0x01000000U) | (((u_int32_t)(src) <<\
23013 #define RADIO130NM_BIAS2__PWD_IRBB50__VERIFY(src) \
23014 (!((((u_int32_t)(src)\
23027 #define RADIO130NM_BIAS2__PWD_ICBB50__READ(src) \
23028 (((u_int32_t)(src)\
23030 #define RADIO130NM_BIAS2__PWD_ICBB50__WRITE(src) \
23031 (((u_int32_t)(src)\
23033 #define RADIO130NM_BIAS2__PWD_ICBB50__MODIFY(dst, src) \
23035 ~0x02000000U) | (((u_int32_t)(src) <<\
23037 #define RADIO130NM_BIAS2__PWD_ICBB50__VERIFY(src) \
23038 (!((((u_int32_t)(src)\
23051 #define RADIO130NM_BIAS2__PWD_IRRF2G50__READ(src) \
23052 (((u_int32_t)(src)\
23054 #define RADIO130NM_BIAS2__PWD_IRRF2G50__WRITE(src) \
23055 (((u_int32_t)(src)\
23057 #define RADIO130NM_BIAS2__PWD_IRRF2G50__MODIFY(dst, src) \
23059 ~0x04000000U) | (((u_int32_t)(src) <<\
23061 #define RADIO130NM_BIAS2__PWD_IRRF2G50__VERIFY(src) \
23062 (!((((u_int32_t)(src)\
23075 #define RADIO130NM_BIAS2__PWD_IRRF5G50__READ(src) \
23076 (((u_int32_t)(src)\
23078 #define RADIO130NM_BIAS2__PWD_IRRF5G50__WRITE(src) \
23079 (((u_int32_t)(src)\
23081 #define RADIO130NM_BIAS2__PWD_IRRF5G50__MODIFY(dst, src) \
23083 ~0x08000000U) | (((u_int32_t)(src) <<\
23085 #define RADIO130NM_BIAS2__PWD_IRRF5G50__VERIFY(src) \
23086 (!((((u_int32_t)(src)\
23099 #define RADIO130NM_BIAS2__PWD_ICRF2G50__READ(src) \
23100 (((u_int32_t)(src)\
23102 #define RADIO130NM_BIAS2__PWD_ICRF2G50__WRITE(src) \
23103 (((u_int32_t)(src)\
23105 #define RADIO130NM_BIAS2__PWD_ICRF2G50__MODIFY(dst, src) \
23107 ~0x10000000U) | (((u_int32_t)(src) <<\
23109 #define RADIO130NM_BIAS2__PWD_ICRF2G50__VERIFY(src) \
23110 (!((((u_int32_t)(src)\
23123 #define RADIO130NM_BIAS2__PWD_ICRF5G50__READ(src) \
23124 (((u_int32_t)(src)\
23126 #define RADIO130NM_BIAS2__PWD_ICRF5G50__WRITE(src) \
23127 (((u_int32_t)(src)\
23129 #define RADIO130NM_BIAS2__PWD_ICRF5G50__MODIFY(dst, src) \
23131 ~0x20000000U) | (((u_int32_t)(src) <<\
23133 #define RADIO130NM_BIAS2__PWD_ICRF5G50__VERIFY(src) \
23134 (!((((u_int32_t)(src)\
23147 #define RADIO130NM_BIAS2__PWD_IRSYNTH50__READ(src) \
23148 (((u_int32_t)(src)\
23150 #define RADIO130NM_BIAS2__PWD_IRSYNTH50__WRITE(src) \
23151 (((u_int32_t)(src)\
23153 #define RADIO130NM_BIAS2__PWD_IRSYNTH50__MODIFY(dst, src) \
23155 ~0x40000000U) | (((u_int32_t)(src) <<\
23157 #define RADIO130NM_BIAS2__PWD_IRSYNTH50__VERIFY(src) \
23158 (!((((u_int32_t)(src)\
23171 #define RADIO130NM_BIAS2__PWD_ICSYNTH50__READ(src) \
23172 (((u_int32_t)(src)\
23174 #define RADIO130NM_BIAS2__PWD_ICSYNTH50__WRITE(src) \
23175 (((u_int32_t)(src)\
23177 #define RADIO130NM_BIAS2__PWD_ICSYNTH50__MODIFY(dst, src) \
23179 ~0x80000000U) | (((u_int32_t)(src) <<\
23181 #define RADIO130NM_BIAS2__PWD_ICSYNTH50__VERIFY(src) \
23182 (!((((u_int32_t)(src)\
23208 #define RADIO130NM_BIAS3__BIAS3_SPARE__READ(src) (u_int32_t)(src) & 0x00000001U
23209 #define RADIO130NM_BIAS3__BIAS3_SPARE__WRITE(src) \
23210 ((u_int32_t)(src)\
23212 #define RADIO130NM_BIAS3__BIAS3_SPARE__MODIFY(dst, src) \
23214 ~0x00000001U) | ((u_int32_t)(src) &\
23216 #define RADIO130NM_BIAS3__BIAS3_SPARE__VERIFY(src) \
23217 (!(((u_int32_t)(src)\
23230 #define RADIO130NM_BIAS3__PWD_ICLOLDO25__READ(src) \
23231 (((u_int32_t)(src)\
23233 #define RADIO130NM_BIAS3__PWD_ICLOLDO25__WRITE(src) \
23234 (((u_int32_t)(src)\
23236 #define RADIO130NM_BIAS3__PWD_ICLOLDO25__MODIFY(dst, src) \
23238 ~0x0000000eU) | (((u_int32_t)(src) <<\
23240 #define RADIO130NM_BIAS3__PWD_ICLOLDO25__VERIFY(src) \
23241 (!((((u_int32_t)(src)\
23248 #define RADIO130NM_BIAS3__PWD_IR25SPARE4__READ(src) \
23249 (((u_int32_t)(src)\
23251 #define RADIO130NM_BIAS3__PWD_IR25SPARE4__WRITE(src) \
23252 (((u_int32_t)(src)\
23254 #define RADIO130NM_BIAS3__PWD_IR25SPARE4__MODIFY(dst, src) \
23256 ~0x00000070U) | (((u_int32_t)(src) <<\
23258 #define RADIO130NM_BIAS3__PWD_IR25SPARE4__VERIFY(src) \
23259 (!((((u_int32_t)(src)\
23266 #define RADIO130NM_BIAS3__PWD_IR25SPARE3__READ(src) \
23267 (((u_int32_t)(src)\
23269 #define RADIO130NM_BIAS3__PWD_IR25SPARE3__WRITE(src) \
23270 (((u_int32_t)(src)\
23272 #define RADIO130NM_BIAS3__PWD_IR25SPARE3__MODIFY(dst, src) \
23274 ~0x00000380U) | (((u_int32_t)(src) <<\
23276 #define RADIO130NM_BIAS3__PWD_IR25SPARE3__VERIFY(src) \
23277 (!((((u_int32_t)(src)\
23284 #define RADIO130NM_BIAS3__PWD_IR25SPARE2__READ(src) \
23285 (((u_int32_t)(src)\
23287 #define RADIO130NM_BIAS3__PWD_IR25SPARE2__WRITE(src) \
23288 (((u_int32_t)(src)\
23290 #define RADIO130NM_BIAS3__PWD_IR25SPARE2__MODIFY(dst, src) \
23292 ~0x00001c00U) | (((u_int32_t)(src) <<\
23294 #define RADIO130NM_BIAS3__PWD_IR25SPARE2__VERIFY(src) \
23295 (!((((u_int32_t)(src)\
23302 #define RADIO130NM_BIAS3__PWD_IR25SPARE1__READ(src) \
23303 (((u_int32_t)(src)\
23305 #define RADIO130NM_BIAS3__PWD_IR25SPARE1__WRITE(src) \
23306 (((u_int32_t)(src)\
23308 #define RADIO130NM_BIAS3__PWD_IR25SPARE1__MODIFY(dst, src) \
23310 ~0x0000e000U) | (((u_int32_t)(src) <<\
23312 #define RADIO130NM_BIAS3__PWD_IR25SPARE1__VERIFY(src) \
23313 (!((((u_int32_t)(src)\
23320 #define RADIO130NM_BIAS3__PWD_IC25SPARE4__READ(src) \
23321 (((u_int32_t)(src)\
23323 #define RADIO130NM_BIAS3__PWD_IC25SPARE4__WRITE(src) \
23324 (((u_int32_t)(src)\
23326 #define RADIO130NM_BIAS3__PWD_IC25SPARE4__MODIFY(dst, src) \
23328 ~0x00070000U) | (((u_int32_t)(src) <<\
23330 #define RADIO130NM_BIAS3__PWD_IC25SPARE4__VERIFY(src) \
23331 (!((((u_int32_t)(src)\
23338 #define RADIO130NM_BIAS3__PWD_IC25SPARE3__READ(src) \
23339 (((u_int32_t)(src)\
23341 #define RADIO130NM_BIAS3__PWD_IC25SPARE3__WRITE(src) \
23342 (((u_int32_t)(src)\
23344 #define RADIO130NM_BIAS3__PWD_IC25SPARE3__MODIFY(dst, src) \
23346 ~0x00380000U) | (((u_int32_t)(src) <<\
23348 #define RADIO130NM_BIAS3__PWD_IC25SPARE3__VERIFY(src) \
23349 (!((((u_int32_t)(src)\
23356 #define RADIO130NM_BIAS3__PWD_IC25SPARE2__READ(src) \
23357 (((u_int32_t)(src)\
23359 #define RADIO130NM_BIAS3__PWD_IC25SPARE2__WRITE(src) \
23360 (((u_int32_t)(src)\
23362 #define RADIO130NM_BIAS3__PWD_IC25SPARE2__MODIFY(dst, src) \
23364 ~0x01c00000U) | (((u_int32_t)(src) <<\
23366 #define RADIO130NM_BIAS3__PWD_IC25SPARE2__VERIFY(src) \
23367 (!((((u_int32_t)(src)\
23374 #define RADIO130NM_BIAS3__PWD_IC25SPARE1__READ(src) \
23375 (((u_int32_t)(src)\
23377 #define RADIO130NM_BIAS3__PWD_IC25SPARE1__WRITE(src) \
23378 (((u_int32_t)(src)\
23380 #define RADIO130NM_BIAS3__PWD_IC25SPARE1__MODIFY(dst, src) \
23382 ~0x0e000000U) | (((u_int32_t)(src) <<\
23384 #define RADIO130NM_BIAS3__PWD_IC25SPARE1__VERIFY(src) \
23385 (!((((u_int32_t)(src)\
23392 #define RADIO130NM_BIAS3__PWD_IRTSENS25__READ(src) \
23393 (((u_int32_t)(src)\
23395 #define RADIO130NM_BIAS3__PWD_IRTSENS25__WRITE(src) \
23396 (((u_int32_t)(src)\
23398 #define RADIO130NM_BIAS3__PWD_IRTSENS25__MODIFY(dst, src) \
23400 ~0x10000000U) | (((u_int32_t)(src) <<\
23402 #define RADIO130NM_BIAS3__PWD_IRTSENS25__VERIFY(src) \
23403 (!((((u_int32_t)(src)\
23416 #define RADIO130NM_BIAS3__PWD_ICTSENS25__READ(src) \
23417 (((u_int32_t)(src)\
23419 #define RADIO130NM_BIAS3__PWD_ICTSENS25__WRITE(src) \
23420 (((u_int32_t)(src)\
23422 #define RADIO130NM_BIAS3__PWD_ICTSENS25__MODIFY(dst, src) \
23424 ~0x20000000U) | (((u_int32_t)(src) <<\
23426 #define RADIO130NM_BIAS3__PWD_ICTSENS25__VERIFY(src) \
23427 (!((((u_int32_t)(src)\
23440 #define RADIO130NM_BIAS3__PWD_IRTXPC25__READ(src) \
23441 (((u_int32_t)(src)\
23443 #define RADIO130NM_BIAS3__PWD_IRTXPC25__WRITE(src) \
23444 (((u_int32_t)(src)\
23446 #define RADIO130NM_BIAS3__PWD_IRTXPC25__MODIFY(dst, src) \
23448 ~0x40000000U) | (((u_int32_t)(src) <<\
23450 #define RADIO130NM_BIAS3__PWD_IRTXPC25__VERIFY(src) \
23451 (!((((u_int32_t)(src)\
23464 #define RADIO130NM_BIAS3__PWD_ICTXPC25__READ(src) \
23465 (((u_int32_t)(src)\
23467 #define RADIO130NM_BIAS3__PWD_ICTXPC25__WRITE(src) \
23468 (((u_int32_t)(src)\
23470 #define RADIO130NM_BIAS3__PWD_ICTXPC25__MODIFY(dst, src) \
23472 ~0x80000000U) | (((u_int32_t)(src) <<\
23474 #define RADIO130NM_BIAS3__PWD_ICTXPC25__VERIFY(src) \
23475 (!((((u_int32_t)(src)\
23501 #define RADIO130NM_BIAS4__BIAS4_SPARE__READ(src) (u_int32_t)(src) & 0x00007fffU
23502 #define RADIO130NM_BIAS4__BIAS4_SPARE__WRITE(src) \
23503 ((u_int32_t)(src)\
23505 #define RADIO130NM_BIAS4__BIAS4_SPARE__MODIFY(dst, src) \
23507 ~0x00007fffU) | ((u_int32_t)(src) &\
23509 #define RADIO130NM_BIAS4__BIAS4_SPARE__VERIFY(src) \
23510 (!(((u_int32_t)(src)\
23517 #define RADIO130NM_BIAS4__PWD_IRLOLDO25__READ(src) \
23518 (((u_int32_t)(src)\
23520 #define RADIO130NM_BIAS4__PWD_IRLOLDO25__WRITE(src) \
23521 (((u_int32_t)(src)\
23523 #define RADIO130NM_BIAS4__PWD_IRLOLDO25__MODIFY(dst, src) \
23525 ~0x00038000U) | (((u_int32_t)(src) <<\
23527 #define RADIO130NM_BIAS4__PWD_IRLOLDO25__VERIFY(src) \
23528 (!((((u_int32_t)(src)\
23535 #define RADIO130NM_BIAS4__PWD_ICXLNA5G50__READ(src) \
23536 (((u_int32_t)(src)\
23538 #define RADIO130NM_BIAS4__PWD_ICXLNA5G50__WRITE(src) \
23539 (((u_int32_t)(src)\
23541 #define RADIO130NM_BIAS4__PWD_ICXLNA5G50__MODIFY(dst, src) \
23543 ~0x001c0000U) | (((u_int32_t)(src) <<\
23545 #define RADIO130NM_BIAS4__PWD_ICXLNA5G50__VERIFY(src) \
23546 (!((((u_int32_t)(src)\
23553 #define RADIO130NM_BIAS4__PWD_ICXLNA2G50__READ(src) \
23554 (((u_int32_t)(src)\
23556 #define RADIO130NM_BIAS4__PWD_ICXLNA2G50__WRITE(src) \
23557 (((u_int32_t)(src)\
23559 #define RADIO130NM_BIAS4__PWD_ICXLNA2G50__MODIFY(dst, src) \
23561 ~0x00e00000U) | (((u_int32_t)(src) <<\
23563 #define RADIO130NM_BIAS4__PWD_ICXLNA2G50__VERIFY(src) \
23564 (!((((u_int32_t)(src)\
23571 #define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__READ(src) \
23572 (((u_int32_t)(src)\
23574 #define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__WRITE(src) \
23575 (((u_int32_t)(src)\
23577 #define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__MODIFY(dst, src) \
23579 ~0xff000000U) | (((u_int32_t)(src) <<\
23581 #define RADIO130NM_BIAS4__BIAS4_SEL_SPARE__VERIFY(src) \
23582 (!((((u_int32_t)(src)\
23602 #define RADIO130NM_GAIN0__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U
23603 #define RADIO130NM_GAIN0__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
23604 #define RADIO130NM_GAIN0__SPARE__MODIFY(dst, src) \
23606 ~0x00000001U) | ((u_int32_t)(src) &\
23608 #define RADIO130NM_GAIN0__SPARE__VERIFY(src) \
23609 (!(((u_int32_t)(src)\
23622 #define RADIO130NM_GAIN0__RX6DBHIQGAIN__READ(src) \
23623 (((u_int32_t)(src)\
23625 #define RADIO130NM_GAIN0__RX6DBHIQGAIN__WRITE(src) \
23626 (((u_int32_t)(src)\
23628 #define RADIO130NM_GAIN0__RX6DBHIQGAIN__MODIFY(dst, src) \
23630 ~0x00000006U) | (((u_int32_t)(src) <<\
23632 #define RADIO130NM_GAIN0__RX6DBHIQGAIN__VERIFY(src) \
23633 (!((((u_int32_t)(src)\
23640 #define RADIO130NM_GAIN0__RX1DBLOQGAIN__READ(src) \
23641 (((u_int32_t)(src)\
23643 #define RADIO130NM_GAIN0__RX1DBLOQGAIN__WRITE(src) \
23644 (((u_int32_t)(src)\
23646 #define RADIO130NM_GAIN0__RX1DBLOQGAIN__MODIFY(dst, src) \
23648 ~0x00000038U) | (((u_int32_t)(src) <<\
23650 #define RADIO130NM_GAIN0__RX1DBLOQGAIN__VERIFY(src) \
23651 (!((((u_int32_t)(src)\
23658 #define RADIO130NM_GAIN0__RX6DBLOQGAIN__READ(src) \
23659 (((u_int32_t)(src)\
23661 #define RADIO130NM_GAIN0__RX6DBLOQGAIN__WRITE(src) \
23662 (((u_int32_t)(src)\
23664 #define RADIO130NM_GAIN0__RX6DBLOQGAIN__MODIFY(dst, src) \
23666 ~0x000000c0U) | (((u_int32_t)(src) <<\
23668 #define RADIO130NM_GAIN0__RX6DBLOQGAIN__VERIFY(src) \
23669 (!((((u_int32_t)(src)\
23676 #define RADIO130NM_GAIN0__RFGMGN__READ(src) \
23677 (((u_int32_t)(src)\
23679 #define RADIO130NM_GAIN0__RFGMGN__WRITE(src) \
23680 (((u_int32_t)(src)\
23682 #define RADIO130NM_GAIN0__RFGMGN__MODIFY(dst, src) \
23684 ~0x00000700U) | (((u_int32_t)(src) <<\
23686 #define RADIO130NM_GAIN0__RFGMGN__VERIFY(src) \
23687 (!((((u_int32_t)(src)\
23694 #define RADIO130NM_GAIN0__RFVGA5GAIN__READ(src) \
23695 (((u_int32_t)(src)\
23697 #define RADIO130NM_GAIN0__RFVGA5GAIN__WRITE(src) \
23698 (((u_int32_t)(src)\
23700 #define RADIO130NM_GAIN0__RFVGA5GAIN__MODIFY(dst, src) \
23702 ~0x00001800U) | (((u_int32_t)(src) <<\
23704 #define RADIO130NM_GAIN0__RFVGA5GAIN__VERIFY(src) \
23705 (!((((u_int32_t)(src)\
23712 #define RADIO130NM_GAIN0__LNAGAIN__READ(src) \
23713 (((u_int32_t)(src)\
23715 #define RADIO130NM_GAIN0__LNAGAIN__WRITE(src) \
23716 (((u_int32_t)(src)\
23718 #define RADIO130NM_GAIN0__LNAGAIN__MODIFY(dst, src) \
23720 ~0x0001e000U) | (((u_int32_t)(src) <<\
23722 #define RADIO130NM_GAIN0__LNAGAIN__VERIFY(src) \
23723 (!((((u_int32_t)(src)\
23730 #define RADIO130NM_GAIN0__LNAON__READ(src) \
23731 (((u_int32_t)(src)\
23733 #define RADIO130NM_GAIN0__LNAON__WRITE(src) \
23734 (((u_int32_t)(src)\
23736 #define RADIO130NM_GAIN0__LNAON__MODIFY(dst, src) \
23738 ~0x00020000U) | (((u_int32_t)(src) <<\
23740 #define RADIO130NM_GAIN0__LNAON__VERIFY(src) \
23741 (!((((u_int32_t)(src)\
23754 #define RADIO130NM_GAIN0__PAOUT2GN__READ(src) \
23755 (((u_int32_t)(src)\
23757 #define RADIO130NM_GAIN0__PAOUT2GN__WRITE(src) \
23758 (((u_int32_t)(src)\
23760 #define RADIO130NM_GAIN0__PAOUT2GN__MODIFY(dst, src) \
23762 ~0x001c0000U) | (((u_int32_t)(src) <<\
23764 #define RADIO130NM_GAIN0__PAOUT2GN__VERIFY(src) \
23765 (!((((u_int32_t)(src)\
23772 #define RADIO130NM_GAIN0__PADRVGN__READ(src) \
23773 (((u_int32_t)(src)\
23775 #define RADIO130NM_GAIN0__PADRVGN__WRITE(src) \
23776 (((u_int32_t)(src)\
23778 #define RADIO130NM_GAIN0__PADRVGN__MODIFY(dst, src) \
23780 ~0x00e00000U) | (((u_int32_t)(src) <<\
23782 #define RADIO130NM_GAIN0__PADRVGN__VERIFY(src) \
23783 (!((((u_int32_t)(src)\
23790 #define RADIO130NM_GAIN0__PABUF5GN__READ(src) \
23791 (((u_int32_t)(src)\
23793 #define RADIO130NM_GAIN0__PABUF5GN__WRITE(src) \
23794 (((u_int32_t)(src)\
23796 #define RADIO130NM_GAIN0__PABUF5GN__MODIFY(dst, src) \
23798 ~0x01000000U) | (((u_int32_t)(src) <<\
23800 #define RADIO130NM_GAIN0__PABUF5GN__VERIFY(src) \
23801 (!((((u_int32_t)(src)\
23814 #define RADIO130NM_GAIN0__TXV2IGAIN__READ(src) \
23815 (((u_int32_t)(src)\
23817 #define RADIO130NM_GAIN0__TXV2IGAIN__WRITE(src) \
23818 (((u_int32_t)(src)\
23820 #define RADIO130NM_GAIN0__TXV2IGAIN__MODIFY(dst, src) \
23822 ~0x06000000U) | (((u_int32_t)(src) <<\
23824 #define RADIO130NM_GAIN0__TXV2IGAIN__VERIFY(src) \
23825 (!((((u_int32_t)(src)\
23832 #define RADIO130NM_GAIN0__TX1DBLOQGAIN__READ(src) \
23833 (((u_int32_t)(src)\
23835 #define RADIO130NM_GAIN0__TX1DBLOQGAIN__WRITE(src) \
23836 (((u_int32_t)(src)\
23838 #define RADIO130NM_GAIN0__TX1DBLOQGAIN__MODIFY(dst, src) \
23840 ~0x38000000U) | (((u_int32_t)(src) <<\
23842 #define RADIO130NM_GAIN0__TX1DBLOQGAIN__VERIFY(src) \
23843 (!((((u_int32_t)(src)\
23850 #define RADIO130NM_GAIN0__TX6DBLOQGAIN__READ(src) \
23851 (((u_int32_t)(src)\
23853 #define RADIO130NM_GAIN0__TX6DBLOQGAIN__WRITE(src) \
23854 (((u_int32_t)(src)\
23856 #define RADIO130NM_GAIN0__TX6DBLOQGAIN__MODIFY(dst, src) \
23858 ~0xc0000000U) | (((u_int32_t)(src) <<\
23860 #define RADIO130NM_GAIN0__TX6DBLOQGAIN__VERIFY(src) \
23861 (!((((u_int32_t)(src)\
23881 #define RADIO130NM_GAIN1__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U
23882 #define RADIO130NM_GAIN1__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
23883 #define RADIO130NM_GAIN1__SPARE__MODIFY(dst, src) \
23885 ~0x00000001U) | ((u_int32_t)(src) &\
23887 #define RADIO130NM_GAIN1__SPARE__VERIFY(src) \
23888 (!(((u_int32_t)(src)\
23901 #define RADIO130NM_GAIN1__RX6DBHIQGAIN__READ(src) \
23902 (((u_int32_t)(src)\
23904 #define RADIO130NM_GAIN1__RX6DBHIQGAIN__WRITE(src) \
23905 (((u_int32_t)(src)\
23907 #define RADIO130NM_GAIN1__RX6DBHIQGAIN__MODIFY(dst, src) \
23909 ~0x00000006U) | (((u_int32_t)(src) <<\
23911 #define RADIO130NM_GAIN1__RX6DBHIQGAIN__VERIFY(src) \
23912 (!((((u_int32_t)(src)\
23919 #define RADIO130NM_GAIN1__RX1DBLOQGAIN__READ(src) \
23920 (((u_int32_t)(src)\
23922 #define RADIO130NM_GAIN1__RX1DBLOQGAIN__WRITE(src) \
23923 (((u_int32_t)(src)\
23925 #define RADIO130NM_GAIN1__RX1DBLOQGAIN__MODIFY(dst, src) \
23927 ~0x00000038U) | (((u_int32_t)(src) <<\
23929 #define RADIO130NM_GAIN1__RX1DBLOQGAIN__VERIFY(src) \
23930 (!((((u_int32_t)(src)\
23937 #define RADIO130NM_GAIN1__RX6DBLOQGAIN__READ(src) \
23938 (((u_int32_t)(src)\
23940 #define RADIO130NM_GAIN1__RX6DBLOQGAIN__WRITE(src) \
23941 (((u_int32_t)(src)\
23943 #define RADIO130NM_GAIN1__RX6DBLOQGAIN__MODIFY(dst, src) \
23945 ~0x000000c0U) | (((u_int32_t)(src) <<\
23947 #define RADIO130NM_GAIN1__RX6DBLOQGAIN__VERIFY(src) \
23948 (!((((u_int32_t)(src)\
23955 #define RADIO130NM_GAIN1__RFGMGN__READ(src) \
23956 (((u_int32_t)(src)\
23958 #define RADIO130NM_GAIN1__RFGMGN__WRITE(src) \
23959 (((u_int32_t)(src)\
23961 #define RADIO130NM_GAIN1__RFGMGN__MODIFY(dst, src) \
23963 ~0x00000700U) | (((u_int32_t)(src) <<\
23965 #define RADIO130NM_GAIN1__RFGMGN__VERIFY(src) \
23966 (!((((u_int32_t)(src)\
23973 #define RADIO130NM_GAIN1__RFVGA5GAIN__READ(src) \
23974 (((u_int32_t)(src)\
23976 #define RADIO130NM_GAIN1__RFVGA5GAIN__WRITE(src) \
23977 (((u_int32_t)(src)\
23979 #define RADIO130NM_GAIN1__RFVGA5GAIN__MODIFY(dst, src) \
23981 ~0x00001800U) | (((u_int32_t)(src) <<\
23983 #define RADIO130NM_GAIN1__RFVGA5GAIN__VERIFY(src) \
23984 (!((((u_int32_t)(src)\
23991 #define RADIO130NM_GAIN1__LNAGAIN__READ(src) \
23992 (((u_int32_t)(src)\
23994 #define RADIO130NM_GAIN1__LNAGAIN__WRITE(src) \
23995 (((u_int32_t)(src)\
23997 #define RADIO130NM_GAIN1__LNAGAIN__MODIFY(dst, src) \
23999 ~0x0001e000U) | (((u_int32_t)(src) <<\
24001 #define RADIO130NM_GAIN1__LNAGAIN__VERIFY(src) \
24002 (!((((u_int32_t)(src)\
24009 #define RADIO130NM_GAIN1__LNAON__READ(src) \
24010 (((u_int32_t)(src)\
24012 #define RADIO130NM_GAIN1__LNAON__WRITE(src) \
24013 (((u_int32_t)(src)\
24015 #define RADIO130NM_GAIN1__LNAON__MODIFY(dst, src) \
24017 ~0x00020000U) | (((u_int32_t)(src) <<\
24019 #define RADIO130NM_GAIN1__LNAON__VERIFY(src) \
24020 (!((((u_int32_t)(src)\
24033 #define RADIO130NM_GAIN1__PAOUT2GN__READ(src) \
24034 (((u_int32_t)(src)\
24036 #define RADIO130NM_GAIN1__PAOUT2GN__WRITE(src) \
24037 (((u_int32_t)(src)\
24039 #define RADIO130NM_GAIN1__PAOUT2GN__MODIFY(dst, src) \
24041 ~0x001c0000U) | (((u_int32_t)(src) <<\
24043 #define RADIO130NM_GAIN1__PAOUT2GN__VERIFY(src) \
24044 (!((((u_int32_t)(src)\
24051 #define RADIO130NM_GAIN1__PADRVGN__READ(src) \
24052 (((u_int32_t)(src)\
24054 #define RADIO130NM_GAIN1__PADRVGN__WRITE(src) \
24055 (((u_int32_t)(src)\
24057 #define RADIO130NM_GAIN1__PADRVGN__MODIFY(dst, src) \
24059 ~0x00e00000U) | (((u_int32_t)(src) <<\
24061 #define RADIO130NM_GAIN1__PADRVGN__VERIFY(src) \
24062 (!((((u_int32_t)(src)\
24069 #define RADIO130NM_GAIN1__PABUF5GN__READ(src) \
24070 (((u_int32_t)(src)\
24072 #define RADIO130NM_GAIN1__PABUF5GN__WRITE(src) \
24073 (((u_int32_t)(src)\
24075 #define RADIO130NM_GAIN1__PABUF5GN__MODIFY(dst, src) \
24077 ~0x01000000U) | (((u_int32_t)(src) <<\
24079 #define RADIO130NM_GAIN1__PABUF5GN__VERIFY(src) \
24080 (!((((u_int32_t)(src)\
24093 #define RADIO130NM_GAIN1__TXV2IGAIN__READ(src) \
24094 (((u_int32_t)(src)\
24096 #define RADIO130NM_GAIN1__TXV2IGAIN__WRITE(src) \
24097 (((u_int32_t)(src)\
24099 #define RADIO130NM_GAIN1__TXV2IGAIN__MODIFY(dst, src) \
24101 ~0x06000000U) | (((u_int32_t)(src) <<\
24103 #define RADIO130NM_GAIN1__TXV2IGAIN__VERIFY(src) \
24104 (!((((u_int32_t)(src)\
24111 #define RADIO130NM_GAIN1__TX1DBLOQGAIN__READ(src) \
24112 (((u_int32_t)(src)\
24114 #define RADIO130NM_GAIN1__TX1DBLOQGAIN__WRITE(src) \
24115 (((u_int32_t)(src)\
24117 #define RADIO130NM_GAIN1__TX1DBLOQGAIN__MODIFY(dst, src) \
24119 ~0x38000000U) | (((u_int32_t)(src) <<\
24121 #define RADIO130NM_GAIN1__TX1DBLOQGAIN__VERIFY(src) \
24122 (!((((u_int32_t)(src)\
24129 #define RADIO130NM_GAIN1__TX6DBLOQGAIN__READ(src) \
24130 (((u_int32_t)(src)\
24132 #define RADIO130NM_GAIN1__TX6DBLOQGAIN__WRITE(src) \
24133 (((u_int32_t)(src)\
24135 #define RADIO130NM_GAIN1__TX6DBLOQGAIN__MODIFY(dst, src) \
24137 ~0xc0000000U) | (((u_int32_t)(src) <<\
24139 #define RADIO130NM_GAIN1__TX6DBLOQGAIN__VERIFY(src) \
24140 (!((((u_int32_t)(src)\
24160 #define RADIO130NM_TOP0__FORCEMSBLOW__READ(src) (u_int32_t)(src) & 0x00000001U
24161 #define RADIO130NM_TOP0__FORCEMSBLOW__WRITE(src) \
24162 ((u_int32_t)(src)\
24164 #define RADIO130NM_TOP0__FORCEMSBLOW__MODIFY(dst, src) \
24166 ~0x00000001U) | ((u_int32_t)(src) &\
24168 #define RADIO130NM_TOP0__FORCEMSBLOW__VERIFY(src) \
24169 (!(((u_int32_t)(src)\
24182 #define RADIO130NM_TOP0__PWDBIAS__READ(src) \
24183 (((u_int32_t)(src)\
24185 #define RADIO130NM_TOP0__PWDBIAS__WRITE(src) \
24186 (((u_int32_t)(src)\
24188 #define RADIO130NM_TOP0__PWDBIAS__MODIFY(dst, src) \
24190 ~0x00000002U) | (((u_int32_t)(src) <<\
24192 #define RADIO130NM_TOP0__PWDBIAS__VERIFY(src) \
24193 (!((((u_int32_t)(src)\
24206 #define RADIO130NM_TOP0__SYNTHON_FORCE__READ(src) \
24207 (((u_int32_t)(src)\
24209 #define RADIO130NM_TOP0__SYNTHON_FORCE__WRITE(src) \
24210 (((u_int32_t)(src)\
24212 #define RADIO130NM_TOP0__SYNTHON_FORCE__MODIFY(dst, src) \
24214 ~0x00000004U) | (((u_int32_t)(src) <<\
24216 #define RADIO130NM_TOP0__SYNTHON_FORCE__VERIFY(src) \
24217 (!((((u_int32_t)(src)\
24230 #define RADIO130NM_TOP0__SCLKEN_FORCE__READ(src) \
24231 (((u_int32_t)(src)\
24233 #define RADIO130NM_TOP0__SCLKEN_FORCE__WRITE(src) \
24234 (((u_int32_t)(src)\
24236 #define RADIO130NM_TOP0__SCLKEN_FORCE__MODIFY(dst, src) \
24238 ~0x00000008U) | (((u_int32_t)(src) <<\
24240 #define RADIO130NM_TOP0__SCLKEN_FORCE__VERIFY(src) \
24241 (!((((u_int32_t)(src)\
24254 #define RADIO130NM_TOP0__OSCON__READ(src) \
24255 (((u_int32_t)(src)\
24257 #define RADIO130NM_TOP0__OSCON__WRITE(src) \
24258 (((u_int32_t)(src)\
24260 #define RADIO130NM_TOP0__OSCON__MODIFY(dst, src) \
24262 ~0x00000010U) | (((u_int32_t)(src) <<\
24264 #define RADIO130NM_TOP0__OSCON__VERIFY(src) \
24265 (!((((u_int32_t)(src)\
24278 #define RADIO130NM_TOP0__PWDCLKIN__READ(src) \
24279 (((u_int32_t)(src)\
24281 #define RADIO130NM_TOP0__PWDCLKIN__WRITE(src) \
24282 (((u_int32_t)(src)\
24284 #define RADIO130NM_TOP0__PWDCLKIN__MODIFY(dst, src) \
24286 ~0x00000020U) | (((u_int32_t)(src) <<\
24288 #define RADIO130NM_TOP0__PWDCLKIN__VERIFY(src) \
24289 (!((((u_int32_t)(src)\
24302 #define RADIO130NM_TOP0__LOCALXTAL__READ(src) \
24303 (((u_int32_t)(src)\
24305 #define RADIO130NM_TOP0__LOCALXTAL__WRITE(src) \
24306 (((u_int32_t)(src)\
24308 #define RADIO130NM_TOP0__LOCALXTAL__MODIFY(dst, src) \
24310 ~0x00000040U) | (((u_int32_t)(src) <<\
24312 #define RADIO130NM_TOP0__LOCALXTAL__VERIFY(src) \
24313 (!((((u_int32_t)(src)\
24326 #define RADIO130NM_TOP0__XPAON__READ(src) \
24327 (((u_int32_t)(src)\
24329 #define RADIO130NM_TOP0__XPAON__WRITE(src) \
24330 (((u_int32_t)(src)\
24332 #define RADIO130NM_TOP0__XPAON__MODIFY(dst, src) \
24334 ~0x00000080U) | (((u_int32_t)(src) <<\
24336 #define RADIO130NM_TOP0__XPAON__VERIFY(src) \
24337 (!((((u_int32_t)(src)\
24350 #define RADIO130NM_TOP0__XLNAON__READ(src) \
24351 (((u_int32_t)(src)\
24353 #define RADIO130NM_TOP0__XLNAON__WRITE(src) \
24354 (((u_int32_t)(src)\
24356 #define RADIO130NM_TOP0__XLNAON__MODIFY(dst, src) \
24358 ~0x00000300U) | (((u_int32_t)(src) <<\
24360 #define RADIO130NM_TOP0__XLNAON__VERIFY(src) \
24361 (!((((u_int32_t)(src)\
24368 #define RADIO130NM_TOP0__PAON__READ(src) \
24369 (((u_int32_t)(src)\
24371 #define RADIO130NM_TOP0__PAON__WRITE(src) \
24372 (((u_int32_t)(src)\
24374 #define RADIO130NM_TOP0__PAON__MODIFY(dst, src) \
24376 ~0x00000c00U) | (((u_int32_t)(src) <<\
24378 #define RADIO130NM_TOP0__PAON__VERIFY(src) \
24379 (!((((u_int32_t)(src)\
24386 #define RADIO130NM_TOP0__TXON__READ(src) \
24387 (((u_int32_t)(src)\
24389 #define RADIO130NM_TOP0__TXON__WRITE(src) \
24390 (((u_int32_t)(src)\
24392 #define RADIO130NM_TOP0__TXON__MODIFY(dst, src) \
24394 ~0x00003000U) | (((u_int32_t)(src) <<\
24396 #define RADIO130NM_TOP0__TXON__VERIFY(src) \
24397 (!((((u_int32_t)(src)\
24404 #define RADIO130NM_TOP0__RXON__READ(src) \
24405 (((u_int32_t)(src)\
24407 #define RADIO130NM_TOP0__RXON__WRITE(src) \
24408 (((u_int32_t)(src)\
24410 #define RADIO130NM_TOP0__RXON__MODIFY(dst, src) \
24412 ~0x0000c000U) | (((u_int32_t)(src) <<\
24414 #define RADIO130NM_TOP0__RXON__VERIFY(src) \
24415 (!((((u_int32_t)(src)\
24422 #define RADIO130NM_TOP0__SYNTHON__READ(src) \
24423 (((u_int32_t)(src)\
24425 #define RADIO130NM_TOP0__SYNTHON__WRITE(src) \
24426 (((u_int32_t)(src)\
24428 #define RADIO130NM_TOP0__SYNTHON__MODIFY(dst, src) \
24430 ~0x00010000U) | (((u_int32_t)(src) <<\
24432 #define RADIO130NM_TOP0__SYNTHON__VERIFY(src) \
24433 (!((((u_int32_t)(src)\
24446 #define RADIO130NM_TOP0__TURBOMODE__READ(src) \
24447 (((u_int32_t)(src)\
24449 #define RADIO130NM_TOP0__TURBOMODE__WRITE(src) \
24450 (((u_int32_t)(src)\
24452 #define RADIO130NM_TOP0__TURBOMODE__MODIFY(dst, src) \
24454 ~0x00020000U) | (((u_int32_t)(src) <<\
24456 #define RADIO130NM_TOP0__TURBOMODE__VERIFY(src) \
24457 (!((((u_int32_t)(src)\
24470 #define RADIO130NM_TOP0__BMODERXTX__READ(src) \
24471 (((u_int32_t)(src)\
24473 #define RADIO130NM_TOP0__BMODERXTX__WRITE(src) \
24474 (((u_int32_t)(src)\
24476 #define RADIO130NM_TOP0__BMODERXTX__MODIFY(dst, src) \
24478 ~0x000c0000U) | (((u_int32_t)(src) <<\
24480 #define RADIO130NM_TOP0__BMODERXTX__VERIFY(src) \
24481 (!((((u_int32_t)(src)\
24488 #define RADIO130NM_TOP0__BMODE__READ(src) \
24489 (((u_int32_t)(src)\
24491 #define RADIO130NM_TOP0__BMODE__WRITE(src) \
24492 (((u_int32_t)(src)\
24494 #define RADIO130NM_TOP0__BMODE__MODIFY(dst, src) \
24496 ~0x00100000U) | (((u_int32_t)(src) <<\
24498 #define RADIO130NM_TOP0__BMODE__VERIFY(src) \
24499 (!((((u_int32_t)(src)\
24512 #define RADIO130NM_TOP0__CALTX__READ(src) \
24513 (((u_int32_t)(src)\
24515 #define RADIO130NM_TOP0__CALTX__WRITE(src) \
24516 (((u_int32_t)(src)\
24518 #define RADIO130NM_TOP0__CALTX__MODIFY(dst, src) \
24520 ~0x00600000U) | (((u_int32_t)(src) <<\
24522 #define RADIO130NM_TOP0__CALTX__VERIFY(src) \
24523 (!((((u_int32_t)(src)\
24530 #define RADIO130NM_TOP0__CAL_RESIDUE__READ(src) \
24531 (((u_int32_t)(src)\
24533 #define RADIO130NM_TOP0__CAL_RESIDUE__WRITE(src) \
24534 (((u_int32_t)(src)\
24536 #define RADIO130NM_TOP0__CAL_RESIDUE__MODIFY(dst, src) \
24538 ~0x01800000U) | (((u_int32_t)(src) <<\
24540 #define RADIO130NM_TOP0__CAL_RESIDUE__VERIFY(src) \
24541 (!((((u_int32_t)(src)\
24548 #define RADIO130NM_TOP0__CALDC__READ(src) \
24549 (((u_int32_t)(src)\
24551 #define RADIO130NM_TOP0__CALDC__WRITE(src) \
24552 (((u_int32_t)(src)\
24554 #define RADIO130NM_TOP0__CALDC__MODIFY(dst, src) \
24556 ~0x06000000U) | (((u_int32_t)(src) <<\
24558 #define RADIO130NM_TOP0__CALDC__VERIFY(src) \
24559 (!((((u_int32_t)(src)\
24566 #define RADIO130NM_TOP0__CALFC__READ(src) \
24567 (((u_int32_t)(src)\
24569 #define RADIO130NM_TOP0__CALFC__WRITE(src) \
24570 (((u_int32_t)(src)\
24572 #define RADIO130NM_TOP0__CALFC__MODIFY(dst, src) \
24574 ~0x18000000U) | (((u_int32_t)(src) <<\
24576 #define RADIO130NM_TOP0__CALFC__VERIFY(src) \
24577 (!((((u_int32_t)(src)\
24584 #define RADIO130NM_TOP0__LOCALMODE__READ(src) \
24585 (((u_int32_t)(src)\
24587 #define RADIO130NM_TOP0__LOCALMODE__WRITE(src) \
24588 (((u_int32_t)(src)\
24590 #define RADIO130NM_TOP0__LOCALMODE__MODIFY(dst, src) \
24592 ~0x20000000U) | (((u_int32_t)(src) <<\
24594 #define RADIO130NM_TOP0__LOCALMODE__VERIFY(src) \
24595 (!((((u_int32_t)(src)\
24608 #define RADIO130NM_TOP0__LOCALRXGAIN__READ(src) \
24609 (((u_int32_t)(src)\
24611 #define RADIO130NM_TOP0__LOCALRXGAIN__WRITE(src) \
24612 (((u_int32_t)(src)\
24614 #define RADIO130NM_TOP0__LOCALRXGAIN__MODIFY(dst, src) \
24616 ~0x40000000U) | (((u_int32_t)(src) <<\
24618 #define RADIO130NM_TOP0__LOCALRXGAIN__VERIFY(src) \
24619 (!((((u_int32_t)(src)\
24632 #define RADIO130NM_TOP0__LOCALTXGAIN__READ(src) \
24633 (((u_int32_t)(src)\
24635 #define RADIO130NM_TOP0__LOCALTXGAIN__WRITE(src) \
24636 (((u_int32_t)(src)\
24638 #define RADIO130NM_TOP0__LOCALTXGAIN__MODIFY(dst, src) \
24640 ~0x80000000U) | (((u_int32_t)(src) <<\
24642 #define RADIO130NM_TOP0__LOCALTXGAIN__VERIFY(src) \
24643 (!((((u_int32_t)(src)\
24669 #define RADIO130NM_TOP1__PLL_SVREG__READ(src) (u_int32_t)(src) & 0x00000001U
24670 #define RADIO130NM_TOP1__PLL_SVREG__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
24671 #define RADIO130NM_TOP1__PLL_SVREG__MODIFY(dst, src) \
24673 ~0x00000001U) | ((u_int32_t)(src) &\
24675 #define RADIO130NM_TOP1__PLL_SVREG__VERIFY(src) \
24676 (!(((u_int32_t)(src)\
24689 #define RADIO130NM_TOP1__PLL_SCLAMP__READ(src) \
24690 (((u_int32_t)(src)\
24692 #define RADIO130NM_TOP1__PLL_SCLAMP__WRITE(src) \
24693 (((u_int32_t)(src)\
24695 #define RADIO130NM_TOP1__PLL_SCLAMP__MODIFY(dst, src) \
24697 ~0x0000000eU) | (((u_int32_t)(src) <<\
24699 #define RADIO130NM_TOP1__PLL_SCLAMP__VERIFY(src) \
24700 (!((((u_int32_t)(src)\
24707 #define RADIO130NM_TOP1__PLL_ICP__READ(src) \
24708 (((u_int32_t)(src)\
24710 #define RADIO130NM_TOP1__PLL_ICP__WRITE(src) \
24711 (((u_int32_t)(src)\
24713 #define RADIO130NM_TOP1__PLL_ICP__MODIFY(dst, src) \
24715 ~0x00000070U) | (((u_int32_t)(src) <<\
24717 #define RADIO130NM_TOP1__PLL_ICP__VERIFY(src) \
24718 (!((((u_int32_t)(src)\
24725 #define RADIO130NM_TOP1__PLL_FILTER__READ(src) \
24726 (((u_int32_t)(src)\
24728 #define RADIO130NM_TOP1__PLL_FILTER__WRITE(src) \
24729 (((u_int32_t)(src)\
24731 #define RADIO130NM_TOP1__PLL_FILTER__MODIFY(dst, src) \
24733 ~0x00007f80U) | (((u_int32_t)(src) <<\
24735 #define RADIO130NM_TOP1__PLL_FILTER__VERIFY(src) \
24736 (!((((u_int32_t)(src)\
24743 #define RADIO130NM_TOP1__PLL_ATB__READ(src) \
24744 (((u_int32_t)(src)\
24746 #define RADIO130NM_TOP1__PLL_ATB__WRITE(src) \
24747 (((u_int32_t)(src)\
24749 #define RADIO130NM_TOP1__PLL_ATB__MODIFY(dst, src) \
24751 ~0x00018000U) | (((u_int32_t)(src) <<\
24753 #define RADIO130NM_TOP1__PLL_ATB__VERIFY(src) \
24754 (!((((u_int32_t)(src)\
24761 #define RADIO130NM_TOP1__INV_CLK160_ADC__READ(src) \
24762 (((u_int32_t)(src)\
24764 #define RADIO130NM_TOP1__INV_CLK160_ADC__WRITE(src) \
24765 (((u_int32_t)(src)\
24767 #define RADIO130NM_TOP1__INV_CLK160_ADC__MODIFY(dst, src) \
24769 ~0x00020000U) | (((u_int32_t)(src) <<\
24771 #define RADIO130NM_TOP1__INV_CLK160_ADC__VERIFY(src) \
24772 (!((((u_int32_t)(src)\
24785 #define RADIO130NM_TOP1__DACLPMODE__READ(src) \
24786 (((u_int32_t)(src)\
24788 #define RADIO130NM_TOP1__DACLPMODE__WRITE(src) \
24789 (((u_int32_t)(src)\
24791 #define RADIO130NM_TOP1__DACLPMODE__MODIFY(dst, src) \
24793 ~0x00040000U) | (((u_int32_t)(src) <<\
24795 #define RADIO130NM_TOP1__DACLPMODE__VERIFY(src) \
24796 (!((((u_int32_t)(src)\
24809 #define RADIO130NM_TOP1__PWDDAC__READ(src) \
24810 (((u_int32_t)(src)\
24812 #define RADIO130NM_TOP1__PWDDAC__WRITE(src) \
24813 (((u_int32_t)(src)\
24815 #define RADIO130NM_TOP1__PWDDAC__MODIFY(dst, src) \
24817 ~0x00180000U) | (((u_int32_t)(src) <<\
24819 #define RADIO130NM_TOP1__PWDDAC__VERIFY(src) \
24820 (!((((u_int32_t)(src)\
24827 #define RADIO130NM_TOP1__PWDADC__READ(src) \
24828 (((u_int32_t)(src)\
24830 #define RADIO130NM_TOP1__PWDADC__WRITE(src) \
24831 (((u_int32_t)(src)\
24833 #define RADIO130NM_TOP1__PWDADC__MODIFY(dst, src) \
24835 ~0x00600000U) | (((u_int32_t)(src) <<\
24837 #define RADIO130NM_TOP1__PWDADC__VERIFY(src) \
24838 (!((((u_int32_t)(src)\
24845 #define RADIO130NM_TOP1__PWDPLL__READ(src) \
24846 (((u_int32_t)(src)\
24848 #define RADIO130NM_TOP1__PWDPLL__WRITE(src) \
24849 (((u_int32_t)(src)\
24851 #define RADIO130NM_TOP1__PWDPLL__MODIFY(dst, src) \
24853 ~0x00800000U) | (((u_int32_t)(src) <<\
24855 #define RADIO130NM_TOP1__PWDPLL__VERIFY(src) \
24856 (!((((u_int32_t)(src)\
24869 #define RADIO130NM_TOP1__LOCALADDAC__READ(src) \
24870 (((u_int32_t)(src)\
24872 #define RADIO130NM_TOP1__LOCALADDAC__WRITE(src) \
24873 (((u_int32_t)(src)\
24875 #define RADIO130NM_TOP1__LOCALADDAC__MODIFY(dst, src) \
24877 ~0x01000000U) | (((u_int32_t)(src) <<\
24879 #define RADIO130NM_TOP1__LOCALADDAC__VERIFY(src) \
24880 (!((((u_int32_t)(src)\
24893 #define RADIO130NM_TOP1__INT2GND__READ(src) \
24894 (((u_int32_t)(src)\
24896 #define RADIO130NM_TOP1__INT2GND__WRITE(src) \
24897 (((u_int32_t)(src)\
24899 #define RADIO130NM_TOP1__INT2GND__MODIFY(dst, src) \
24901 ~0x02000000U) | (((u_int32_t)(src) <<\
24903 #define RADIO130NM_TOP1__INT2GND__VERIFY(src) \
24904 (!((((u_int32_t)(src)\
24917 #define RADIO130NM_TOP1__PAD2GND__READ(src) \
24918 (((u_int32_t)(src)\
24920 #define RADIO130NM_TOP1__PAD2GND__WRITE(src) \
24921 (((u_int32_t)(src)\
24923 #define RADIO130NM_TOP1__PAD2GND__MODIFY(dst, src) \
24925 ~0x04000000U) | (((u_int32_t)(src) <<\
24927 #define RADIO130NM_TOP1__PAD2GND__VERIFY(src) \
24928 (!((((u_int32_t)(src)\
24941 #define RADIO130NM_TOP1__INTH2PAD__READ(src) \
24942 (((u_int32_t)(src)\
24944 #define RADIO130NM_TOP1__INTH2PAD__WRITE(src) \
24945 (((u_int32_t)(src)\
24947 #define RADIO130NM_TOP1__INTH2PAD__MODIFY(dst, src) \
24949 ~0x08000000U) | (((u_int32_t)(src) <<\
24951 #define RADIO130NM_TOP1__INTH2PAD__VERIFY(src) \
24952 (!((((u_int32_t)(src)\
24965 #define RADIO130NM_TOP1__INT2PAD__READ(src) \
24966 (((u_int32_t)(src)\
24968 #define RADIO130NM_TOP1__INT2PAD__WRITE(src) \
24969 (((u_int32_t)(src)\
24971 #define RADIO130NM_TOP1__INT2PAD__MODIFY(dst, src) \
24973 ~0x10000000U) | (((u_int32_t)(src) <<\
24975 #define RADIO130NM_TOP1__INT2PAD__VERIFY(src) \
24976 (!((((u_int32_t)(src)\
24989 #define RADIO130NM_TOP1__REVID__READ(src) \
24990 (((u_int32_t)(src)\
25010 #define RADIO130NM_TOP2__BYPASSVREGLO__READ(src) (u_int32_t)(src) & 0x00000001U
25011 #define RADIO130NM_TOP2__BYPASSVREGLO__WRITE(src) \
25012 ((u_int32_t)(src)\
25014 #define RADIO130NM_TOP2__BYPASSVREGLO__MODIFY(dst, src) \
25016 ~0x00000001U) | ((u_int32_t)(src) &\
25018 #define RADIO130NM_TOP2__BYPASSVREGLO__VERIFY(src) \
25019 (!(((u_int32_t)(src)\
25032 #define RADIO130NM_TOP2__DATAOUTSEL__READ(src) \
25033 (((u_int32_t)(src)\
25035 #define RADIO130NM_TOP2__DATAOUTSEL__WRITE(src) \
25036 (((u_int32_t)(src)\
25038 #define RADIO130NM_TOP2__DATAOUTSEL__MODIFY(dst, src) \
25040 ~0x00000006U) | (((u_int32_t)(src) <<\
25042 #define RADIO130NM_TOP2__DATAOUTSEL__VERIFY(src) \
25043 (!((((u_int32_t)(src)\
25050 #define RADIO130NM_TOP2__TXPC_CLKDELAY__READ(src) \
25051 (((u_int32_t)(src)\
25053 #define RADIO130NM_TOP2__TXPC_CLKDELAY__WRITE(src) \
25054 (((u_int32_t)(src)\
25056 #define RADIO130NM_TOP2__TXPC_CLKDELAY__MODIFY(dst, src) \
25058 ~0x00000008U) | (((u_int32_t)(src) <<\
25060 #define RADIO130NM_TOP2__TXPC_CLKDELAY__VERIFY(src) \
25061 (!((((u_int32_t)(src)\
25074 #define RADIO130NM_TOP2__TXPC_XPDBS__READ(src) \
25075 (((u_int32_t)(src)\
25077 #define RADIO130NM_TOP2__TXPC_XPDBS__WRITE(src) \
25078 (((u_int32_t)(src)\
25080 #define RADIO130NM_TOP2__TXPC_XPDBS__MODIFY(dst, src) \
25082 ~0x00000070U) | (((u_int32_t)(src) <<\
25084 #define RADIO130NM_TOP2__TXPC_XPDBS__VERIFY(src) \
25085 (!((((u_int32_t)(src)\
25092 #define RADIO130NM_TOP2__TXPC_TESTPWD__READ(src) \
25093 (((u_int32_t)(src)\
25095 #define RADIO130NM_TOP2__TXPC_TESTPWD__WRITE(src) \
25096 (((u_int32_t)(src)\
25098 #define RADIO130NM_TOP2__TXPC_TESTPWD__MODIFY(dst, src) \
25100 ~0x00000080U) | (((u_int32_t)(src) <<\
25102 #define RADIO130NM_TOP2__TXPC_TESTPWD__VERIFY(src) \
25103 (!((((u_int32_t)(src)\
25116 #define RADIO130NM_TOP2__TXPC_TESTGAIN__READ(src) \
25117 (((u_int32_t)(src)\
25119 #define RADIO130NM_TOP2__TXPC_TESTGAIN__WRITE(src) \
25120 (((u_int32_t)(src)\
25122 #define RADIO130NM_TOP2__TXPC_TESTGAIN__MODIFY(dst, src) \
25124 ~0x00000300U) | (((u_int32_t)(src) <<\
25126 #define RADIO130NM_TOP2__TXPC_TESTGAIN__VERIFY(src) \
25127 (!((((u_int32_t)(src)\
25134 #define RADIO130NM_TOP2__TXPC_TESTDAC__READ(src) \
25135 (((u_int32_t)(src)\
25137 #define RADIO130NM_TOP2__TXPC_TESTDAC__WRITE(src) \
25138 (((u_int32_t)(src)\
25140 #define RADIO130NM_TOP2__TXPC_TESTDAC__MODIFY(dst, src) \
25142 ~0x0000fc00U) | (((u_int32_t)(src) <<\
25144 #define RADIO130NM_TOP2__TXPC_TESTDAC__VERIFY(src) \
25145 (!((((u_int32_t)(src)\
25152 #define RADIO130NM_TOP2__TXPC_TEST__READ(src) \
25153 (((u_int32_t)(src)\
25155 #define RADIO130NM_TOP2__TXPC_TEST__WRITE(src) \
25156 (((u_int32_t)(src)\
25158 #define RADIO130NM_TOP2__TXPC_TEST__MODIFY(dst, src) \
25160 ~0x00010000U) | (((u_int32_t)(src) <<\
25162 #define RADIO130NM_TOP2__TXPC_TEST__VERIFY(src) \
25163 (!((((u_int32_t)(src)\
25176 #define RADIO130NM_TOP2__TXPC_NEGOUT__READ(src) \
25177 (((u_int32_t)(src)\
25179 #define RADIO130NM_TOP2__TXPC_NEGOUT__WRITE(src) \
25180 (((u_int32_t)(src)\
25182 #define RADIO130NM_TOP2__TXPC_NEGOUT__MODIFY(dst, src) \
25184 ~0x00020000U) | (((u_int32_t)(src) <<\
25186 #define RADIO130NM_TOP2__TXPC_NEGOUT__VERIFY(src) \
25187 (!((((u_int32_t)(src)\
25200 #define RADIO130NM_TOP2__XTALDIV__READ(src) \
25201 (((u_int32_t)(src)\
25203 #define RADIO130NM_TOP2__XTALDIV__WRITE(src) \
25204 (((u_int32_t)(src)\
25206 #define RADIO130NM_TOP2__XTALDIV__MODIFY(dst, src) \
25208 ~0x000c0000U) | (((u_int32_t)(src) <<\
25210 #define RADIO130NM_TOP2__XTALDIV__VERIFY(src) \
25211 (!((((u_int32_t)(src)\
25218 #define RADIO130NM_TOP2__LOCALBIAS2X__READ(src) \
25219 (((u_int32_t)(src)\
25221 #define RADIO130NM_TOP2__LOCALBIAS2X__WRITE(src) \
25222 (((u_int32_t)(src)\
25224 #define RADIO130NM_TOP2__LOCALBIAS2X__MODIFY(dst, src) \
25226 ~0x00100000U) | (((u_int32_t)(src) <<\
25228 #define RADIO130NM_TOP2__LOCALBIAS2X__VERIFY(src) \
25229 (!((((u_int32_t)(src)\
25242 #define RADIO130NM_TOP2__LOCALBIAS__READ(src) \
25243 (((u_int32_t)(src)\
25245 #define RADIO130NM_TOP2__LOCALBIAS__WRITE(src) \
25246 (((u_int32_t)(src)\
25248 #define RADIO130NM_TOP2__LOCALBIAS__MODIFY(dst, src) \
25250 ~0x00200000U) | (((u_int32_t)(src) <<\
25252 #define RADIO130NM_TOP2__LOCALBIAS__VERIFY(src) \
25253 (!((((u_int32_t)(src)\
25266 #define RADIO130NM_TOP2__PWDCLKIND__READ(src) \
25267 (((u_int32_t)(src)\
25269 #define RADIO130NM_TOP2__PWDCLKIND__WRITE(src) \
25270 (((u_int32_t)(src)\
25272 #define RADIO130NM_TOP2__PWDCLKIND__MODIFY(dst, src) \
25274 ~0x00400000U) | (((u_int32_t)(src) <<\
25276 #define RADIO130NM_TOP2__PWDCLKIND__VERIFY(src) \
25277 (!((((u_int32_t)(src)\
25290 #define RADIO130NM_TOP2__PWDXINPAD__READ(src) \
25291 (((u_int32_t)(src)\
25293 #define RADIO130NM_TOP2__PWDXINPAD__WRITE(src) \
25294 (((u_int32_t)(src)\
25296 #define RADIO130NM_TOP2__PWDXINPAD__MODIFY(dst, src) \
25298 ~0x00800000U) | (((u_int32_t)(src) <<\
25300 #define RADIO130NM_TOP2__PWDXINPAD__VERIFY(src) \
25301 (!((((u_int32_t)(src)\
25314 #define RADIO130NM_TOP2__NOTCXODET__READ(src) \
25315 (((u_int32_t)(src)\
25317 #define RADIO130NM_TOP2__NOTCXODET__WRITE(src) \
25318 (((u_int32_t)(src)\
25320 #define RADIO130NM_TOP2__NOTCXODET__MODIFY(dst, src) \
25322 ~0x01000000U) | (((u_int32_t)(src) <<\
25324 #define RADIO130NM_TOP2__NOTCXODET__VERIFY(src) \
25325 (!((((u_int32_t)(src)\
25338 #define RADIO130NM_TOP2__XLNABUFIN__READ(src) \
25339 (((u_int32_t)(src)\
25341 #define RADIO130NM_TOP2__XLNABUFIN__WRITE(src) \
25342 (((u_int32_t)(src)\
25344 #define RADIO130NM_TOP2__XLNABUFIN__MODIFY(dst, src) \
25346 ~0x02000000U) | (((u_int32_t)(src) <<\
25348 #define RADIO130NM_TOP2__XLNABUFIN__VERIFY(src) \
25349 (!((((u_int32_t)(src)\
25362 #define RADIO130NM_TOP2__XLNAISEL__READ(src) \
25363 (((u_int32_t)(src)\
25365 #define RADIO130NM_TOP2__XLNAISEL__WRITE(src) \
25366 (((u_int32_t)(src)\
25368 #define RADIO130NM_TOP2__XLNAISEL__MODIFY(dst, src) \
25370 ~0x0c000000U) | (((u_int32_t)(src) <<\
25372 #define RADIO130NM_TOP2__XLNAISEL__VERIFY(src) \
25373 (!((((u_int32_t)(src)\
25380 #define RADIO130NM_TOP2__XLNABUFMODE__READ(src) \
25381 (((u_int32_t)(src)\
25383 #define RADIO130NM_TOP2__XLNABUFMODE__WRITE(src) \
25384 (((u_int32_t)(src)\
25386 #define RADIO130NM_TOP2__XLNABUFMODE__MODIFY(dst, src) \
25388 ~0x10000000U) | (((u_int32_t)(src) <<\
25390 #define RADIO130NM_TOP2__XLNABUFMODE__VERIFY(src) \
25391 (!((((u_int32_t)(src)\
25404 #define RADIO130NM_TOP2__FORCE_XLDO_ON__READ(src) \
25405 (((u_int32_t)(src)\
25407 #define RADIO130NM_TOP2__FORCE_XLDO_ON__WRITE(src) \
25408 (((u_int32_t)(src)\
25410 #define RADIO130NM_TOP2__FORCE_XLDO_ON__MODIFY(dst, src) \
25412 ~0x20000000U) | (((u_int32_t)(src) <<\
25414 #define RADIO130NM_TOP2__FORCE_XLDO_ON__VERIFY(src) \
25415 (!((((u_int32_t)(src)\
25428 #define RADIO130NM_TOP2__XPABIAS_LVL__READ(src) \
25429 (((u_int32_t)(src)\
25431 #define RADIO130NM_TOP2__XPABIAS_LVL__WRITE(src) \
25432 (((u_int32_t)(src)\
25434 #define RADIO130NM_TOP2__XPABIAS_LVL__MODIFY(dst, src) \
25436 ~0xc0000000U) | (((u_int32_t)(src) <<\
25438 #define RADIO130NM_TOP2__XPABIAS_LVL__VERIFY(src) \
25439 (!((((u_int32_t)(src)\
25459 #define RADIO130NM_TOP3__VREGLO_ATBSEL__READ(src) \
25460 (u_int32_t)(src)\
25462 #define RADIO130NM_TOP3__VREGLO_ATBSEL__WRITE(src) \
25463 ((u_int32_t)(src)\
25465 #define RADIO130NM_TOP3__VREGLO_ATBSEL__MODIFY(dst, src) \
25467 ~0x00000007U) | ((u_int32_t)(src) &\
25469 #define RADIO130NM_TOP3__VREGLO_ATBSEL__VERIFY(src) \
25470 (!(((u_int32_t)(src)\
25477 #define RADIO130NM_TOP3__PLLFBDIVB__READ(src) \
25478 (((u_int32_t)(src)\
25480 #define RADIO130NM_TOP3__PLLFBDIVB__WRITE(src) \
25481 (((u_int32_t)(src)\
25483 #define RADIO130NM_TOP3__PLLFBDIVB__MODIFY(dst, src) \
25485 ~0x00001ff8U) | (((u_int32_t)(src) <<\
25487 #define RADIO130NM_TOP3__PLLFBDIVB__VERIFY(src) \
25488 (!((((u_int32_t)(src)\
25495 #define RADIO130NM_TOP3__PLLFBDIVA__READ(src) \
25496 (((u_int32_t)(src)\
25498 #define RADIO130NM_TOP3__PLLFBDIVA__WRITE(src) \
25499 (((u_int32_t)(src)\
25501 #define RADIO130NM_TOP3__PLLFBDIVA__MODIFY(dst, src) \
25503 ~0x007fe000U) | (((u_int32_t)(src) <<\
25505 #define RADIO130NM_TOP3__PLLFBDIVA__VERIFY(src) \
25506 (!((((u_int32_t)(src)\
25513 #define RADIO130NM_TOP3__PLLREFDIVB__READ(src) \
25514 (((u_int32_t)(src)\
25516 #define RADIO130NM_TOP3__PLLREFDIVB__WRITE(src) \
25517 (((u_int32_t)(src)\
25519 #define RADIO130NM_TOP3__PLLREFDIVB__MODIFY(dst, src) \
25521 ~0x07800000U) | (((u_int32_t)(src) <<\
25523 #define RADIO130NM_TOP3__PLLREFDIVB__VERIFY(src) \
25524 (!((((u_int32_t)(src)\
25531 #define RADIO130NM_TOP3__PLLREFDIVA__READ(src) \
25532 (((u_int32_t)(src)\
25534 #define RADIO130NM_TOP3__PLLREFDIVA__WRITE(src) \
25535 (((u_int32_t)(src)\
25537 #define RADIO130NM_TOP3__PLLREFDIVA__MODIFY(dst, src) \
25539 ~0x78000000U) | (((u_int32_t)(src) <<\
25541 #define RADIO130NM_TOP3__PLLREFDIVA__VERIFY(src) \
25542 (!((((u_int32_t)(src)\
25549 #define RADIO130NM_TOP3__LOCALPLLDIV__READ(src) \
25550 (((u_int32_t)(src)\
25552 #define RADIO130NM_TOP3__LOCALPLLDIV__WRITE(src) \
25553 (((u_int32_t)(src)\
25555 #define RADIO130NM_TOP3__LOCALPLLDIV__MODIFY(dst, src) \
25557 ~0x80000000U) | (((u_int32_t)(src) <<\
25559 #define RADIO130NM_TOP3__LOCALPLLDIV__VERIFY(src) \
25560 (!((((u_int32_t)(src)\
25586 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__READ(src) \
25587 (u_int32_t)(src)\
25589 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__WRITE(src) \
25590 ((u_int32_t)(src)\
25592 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__MODIFY(dst, src) \
25594 ~0x00000001U) | ((u_int32_t)(src) &\
25596 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__ENABLE__VERIFY(src) \
25597 (!(((u_int32_t)(src)\
25610 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__READ(src) \
25611 (((u_int32_t)(src)\
25613 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__WRITE(src) \
25614 (((u_int32_t)(src)\
25616 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__MODIFY(dst, src) \
25618 ~0x00000002U) | (((u_int32_t)(src) <<\
25620 #define ANALOG_INTF_REG_CSR__SW_OVERRIDE__SUPDATE_DELAY__VERIFY(src) \
25621 (!((((u_int32_t)(src)\
25647 #define ANALOG_INTF_REG_CSR__SIN_VAL__SIN__READ(src) \
25648 (u_int32_t)(src)\
25673 #define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__READ(src) \
25674 (u_int32_t)(src)\
25676 #define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__WRITE(src) \
25677 ((u_int32_t)(src)\
25679 #define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__MODIFY(dst, src) \
25681 ~0x00000001U) | ((u_int32_t)(src) &\
25683 #define ANALOG_INTF_REG_CSR__SW_SCLK__SW_SCLK__VERIFY(src) \
25684 (!(((u_int32_t)(src)\
25710 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__READ(src) \
25711 (u_int32_t)(src)\
25713 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__WRITE(src) \
25714 ((u_int32_t)(src)\
25716 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__MODIFY(dst, src) \
25718 ~0x00000001U) | ((u_int32_t)(src) &\
25720 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SOUT__VERIFY(src) \
25721 (!(((u_int32_t)(src)\
25734 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__READ(src) \
25735 (((u_int32_t)(src)\
25737 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__WRITE(src) \
25738 (((u_int32_t)(src)\
25740 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__MODIFY(dst, src) \
25742 ~0x00000002U) | (((u_int32_t)(src) <<\
25744 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SUPDATE__VERIFY(src) \
25745 (!((((u_int32_t)(src)\
25758 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__READ(src) \
25759 (((u_int32_t)(src)\
25761 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__WRITE(src) \
25762 (((u_int32_t)(src)\
25764 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__MODIFY(dst, src) \
25766 ~0x00000004U) | (((u_int32_t)(src) <<\
25768 #define ANALOG_INTF_REG_CSR__SW_CNTL__SW_SCAPTURE__VERIFY(src) \
25769 (!((((u_int32_t)(src)\
25795 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__READ(src) \
25796 (u_int32_t)(src)\
25798 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__WRITE(src) \
25799 ((u_int32_t)(src)\
25801 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__MODIFY(dst, src) \
25803 ~0xffffffffU) | ((u_int32_t)(src) &\
25805 #define MAC_PCU_STA_ADDR_L32__ADDR_31_0__VERIFY(src) \
25806 (!(((u_int32_t)(src)\
25826 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__READ(src) \
25827 (u_int32_t)(src)\
25829 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__WRITE(src) \
25830 ((u_int32_t)(src)\
25832 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__MODIFY(dst, src) \
25834 ~0x0000ffffU) | ((u_int32_t)(src) &\
25836 #define MAC_PCU_STA_ADDR_U16__ADDR_47_32__VERIFY(src) \
25837 (!(((u_int32_t)(src)\
25844 #define MAC_PCU_STA_ADDR_U16__STA_AP__READ(src) \
25845 (((u_int32_t)(src)\
25847 #define MAC_PCU_STA_ADDR_U16__STA_AP__WRITE(src) \
25848 (((u_int32_t)(src)\
25850 #define MAC_PCU_STA_ADDR_U16__STA_AP__MODIFY(dst, src) \
25852 ~0x00010000U) | (((u_int32_t)(src) <<\
25854 #define MAC_PCU_STA_ADDR_U16__STA_AP__VERIFY(src) \
25855 (!((((u_int32_t)(src)\
25868 #define MAC_PCU_STA_ADDR_U16__ADHOC__READ(src) \
25869 (((u_int32_t)(src)\
25871 #define MAC_PCU_STA_ADDR_U16__ADHOC__WRITE(src) \
25872 (((u_int32_t)(src)\
25874 #define MAC_PCU_STA_ADDR_U16__ADHOC__MODIFY(dst, src) \
25876 ~0x00020000U) | (((u_int32_t)(src) <<\
25878 #define MAC_PCU_STA_ADDR_U16__ADHOC__VERIFY(src) \
25879 (!((((u_int32_t)(src)\
25892 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__READ(src) \
25893 (((u_int32_t)(src)\
25895 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__WRITE(src) \
25896 (((u_int32_t)(src)\
25898 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__MODIFY(dst, src) \
25900 ~0x00040000U) | (((u_int32_t)(src) <<\
25902 #define MAC_PCU_STA_ADDR_U16__PW_SAVE__VERIFY(src) \
25903 (!((((u_int32_t)(src)\
25916 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__READ(src) \
25917 (((u_int32_t)(src)\
25919 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__WRITE(src) \
25920 (((u_int32_t)(src)\
25922 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__MODIFY(dst, src) \
25924 ~0x00080000U) | (((u_int32_t)(src) <<\
25926 #define MAC_PCU_STA_ADDR_U16__KEYSRCH_DIS__VERIFY(src) \
25927 (!((((u_int32_t)(src)\
25940 #define MAC_PCU_STA_ADDR_U16__PCF__READ(src) \
25941 (((u_int32_t)(src)\
25943 #define MAC_PCU_STA_ADDR_U16__PCF__WRITE(src) \
25944 (((u_int32_t)(src)\
25946 #define MAC_PCU_STA_ADDR_U16__PCF__MODIFY(dst, src) \
25948 ~0x00100000U) | (((u_int32_t)(src) <<\
25950 #define MAC_PCU_STA_ADDR_U16__PCF__VERIFY(src) \
25951 (!((((u_int32_t)(src)\
25964 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__READ(src) \
25965 (((u_int32_t)(src)\
25967 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__WRITE(src) \
25968 (((u_int32_t)(src)\
25970 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__MODIFY(dst, src) \
25972 ~0x00200000U) | (((u_int32_t)(src) <<\
25974 #define MAC_PCU_STA_ADDR_U16__USE_DEFANT__VERIFY(src) \
25975 (!((((u_int32_t)(src)\
25988 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__READ(src) \
25989 (((u_int32_t)(src)\
25991 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__WRITE(src) \
25992 (((u_int32_t)(src)\
25994 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__MODIFY(dst, src) \
25996 ~0x00400000U) | (((u_int32_t)(src) <<\
25998 #define MAC_PCU_STA_ADDR_U16__DEFANT_UPDATE__VERIFY(src) \
25999 (!((((u_int32_t)(src)\
26012 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__READ(src) \
26013 (((u_int32_t)(src)\
26015 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__WRITE(src) \
26016 (((u_int32_t)(src)\
26018 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__MODIFY(dst, src) \
26020 ~0x00800000U) | (((u_int32_t)(src) <<\
26022 #define MAC_PCU_STA_ADDR_U16__RTS_USE_DEF__VERIFY(src) \
26023 (!((((u_int32_t)(src)\
26036 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__READ(src) \
26037 (((u_int32_t)(src)\
26039 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__WRITE(src) \
26040 (((u_int32_t)(src)\
26042 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__MODIFY(dst, src) \
26044 ~0x01000000U) | (((u_int32_t)(src) <<\
26046 #define MAC_PCU_STA_ADDR_U16__ACKCTS_6MB__VERIFY(src) \
26047 (!((((u_int32_t)(src)\
26060 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__READ(src) \
26061 (((u_int32_t)(src)\
26063 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__WRITE(src) \
26064 (((u_int32_t)(src)\
26066 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__MODIFY(dst, src) \
26068 ~0x02000000U) | (((u_int32_t)(src) <<\
26070 #define MAC_PCU_STA_ADDR_U16__BASE_RATE_11B__VERIFY(src) \
26071 (!((((u_int32_t)(src)\
26084 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__READ(src) \
26085 (((u_int32_t)(src)\
26087 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__WRITE(src) \
26088 (((u_int32_t)(src)\
26090 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__MODIFY(dst, src) \
26092 ~0x04000000U) | (((u_int32_t)(src) <<\
26094 #define MAC_PCU_STA_ADDR_U16__SECTOR_SELF_GEN__VERIFY(src) \
26095 (!((((u_int32_t)(src)\
26108 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__READ(src) \
26109 (((u_int32_t)(src)\
26111 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__WRITE(src) \
26112 (((u_int32_t)(src)\
26114 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__MODIFY(dst, src) \
26116 ~0x08000000U) | (((u_int32_t)(src) <<\
26118 #define MAC_PCU_STA_ADDR_U16__CRPT_MIC_ENABLE__VERIFY(src) \
26119 (!((((u_int32_t)(src)\
26132 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__READ(src) \
26133 (((u_int32_t)(src)\
26135 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__WRITE(src) \
26136 (((u_int32_t)(src)\
26138 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__MODIFY(dst, src) \
26140 ~0x10000000U) | (((u_int32_t)(src) <<\
26142 #define MAC_PCU_STA_ADDR_U16__KSRCH_MODE__VERIFY(src) \
26143 (!((((u_int32_t)(src)\
26156 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__READ(src) \
26157 (((u_int32_t)(src)\
26159 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__WRITE(src) \
26160 (((u_int32_t)(src)\
26162 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__MODIFY(dst, src) \
26164 ~0x20000000U) | (((u_int32_t)(src) <<\
26166 #define MAC_PCU_STA_ADDR_U16__PRESERVE_SEQNUM__VERIFY(src) \
26167 (!((((u_int32_t)(src)\
26180 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__READ(src) \
26181 (((u_int32_t)(src)\
26183 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__WRITE(src) \
26184 (((u_int32_t)(src)\
26186 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__MODIFY(dst, src) \
26188 ~0x40000000U) | (((u_int32_t)(src) <<\
26190 #define MAC_PCU_STA_ADDR_U16__CBCIV_ENDIAN__VERIFY(src) \
26191 (!((((u_int32_t)(src)\
26204 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__READ(src) \
26205 (((u_int32_t)(src)\
26207 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__WRITE(src) \
26208 (((u_int32_t)(src)\
26210 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__MODIFY(dst, src) \
26212 ~0x80000000U) | (((u_int32_t)(src) <<\
26214 #define MAC_PCU_STA_ADDR_U16__ADHOC_MCAST_SEARCH__VERIFY(src) \
26215 (!((((u_int32_t)(src)\
26241 #define MAC_PCU_BSSID_L32__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU
26242 #define MAC_PCU_BSSID_L32__ADDR__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
26243 #define MAC_PCU_BSSID_L32__ADDR__MODIFY(dst, src) \
26245 ~0xffffffffU) | ((u_int32_t)(src) &\
26247 #define MAC_PCU_BSSID_L32__ADDR__VERIFY(src) \
26248 (!(((u_int32_t)(src)\
26268 #define MAC_PCU_BSSID_U16__ADDR__READ(src) (u_int32_t)(src) & 0x0000ffffU
26269 #define MAC_PCU_BSSID_U16__ADDR__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
26270 #define MAC_PCU_BSSID_U16__ADDR__MODIFY(dst, src) \
26272 ~0x0000ffffU) | ((u_int32_t)(src) &\
26274 #define MAC_PCU_BSSID_U16__ADDR__VERIFY(src) \
26275 (!(((u_int32_t)(src)\
26282 #define MAC_PCU_BSSID_U16__AID__READ(src) \
26283 (((u_int32_t)(src)\
26285 #define MAC_PCU_BSSID_U16__AID__WRITE(src) \
26286 (((u_int32_t)(src)\
26288 #define MAC_PCU_BSSID_U16__AID__MODIFY(dst, src) \
26290 ~0x07ff0000U) | (((u_int32_t)(src) <<\
26292 #define MAC_PCU_BSSID_U16__AID__VERIFY(src) \
26293 (!((((u_int32_t)(src)\
26313 #define MAC_PCU_BCN_RSSI_AVE__AVE_VALUE__READ(src) \
26314 (u_int32_t)(src)\
26333 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__READ(src) \
26334 (u_int32_t)(src)\
26336 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__WRITE(src) \
26337 ((u_int32_t)(src)\
26339 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__MODIFY(dst, src) \
26341 ~0x00003fffU) | ((u_int32_t)(src) &\
26343 #define MAC_PCU_ACK_CTS_TIMEOUT__ACK_TIMEOUT__VERIFY(src) \
26344 (!(((u_int32_t)(src)\
26351 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__READ(src) \
26352 (((u_int32_t)(src)\
26354 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__WRITE(src) \
26355 (((u_int32_t)(src)\
26357 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__MODIFY(dst, src) \
26359 ~0x3fff0000U) | (((u_int32_t)(src) <<\
26361 #define MAC_PCU_ACK_CTS_TIMEOUT__CTS_TIMEOUT__VERIFY(src) \
26362 (!((((u_int32_t)(src)\
26382 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__READ(src) \
26383 (u_int32_t)(src)\
26385 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__WRITE(src) \
26386 ((u_int32_t)(src)\
26388 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__MODIFY(dst, src) \
26390 ~0x000000ffU) | ((u_int32_t)(src) &\
26392 #define MAC_PCU_BCN_RSSI_CTL__RSSI_THRESH__VERIFY(src) \
26393 (!(((u_int32_t)(src)\
26400 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__READ(src) \
26401 (((u_int32_t)(src)\
26403 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__WRITE(src) \
26404 (((u_int32_t)(src)\
26406 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__MODIFY(dst, src) \
26408 ~0x0000ff00U) | (((u_int32_t)(src) <<\
26410 #define MAC_PCU_BCN_RSSI_CTL__MISS_THRESH__VERIFY(src) \
26411 (!((((u_int32_t)(src)\
26418 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__READ(src) \
26419 (((u_int32_t)(src)\
26421 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__WRITE(src) \
26422 (((u_int32_t)(src)\
26424 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__MODIFY(dst, src) \
26426 ~0x1f000000U) | (((u_int32_t)(src) <<\
26428 #define MAC_PCU_BCN_RSSI_CTL__WEIGHT__VERIFY(src) \
26429 (!((((u_int32_t)(src)\
26436 #define MAC_PCU_BCN_RSSI_CTL__RESET__READ(src) \
26437 (((u_int32_t)(src)\
26439 #define MAC_PCU_BCN_RSSI_CTL__RESET__WRITE(src) \
26440 (((u_int32_t)(src)\
26442 #define MAC_PCU_BCN_RSSI_CTL__RESET__MODIFY(dst, src) \
26444 ~0x20000000U) | (((u_int32_t)(src) <<\
26446 #define MAC_PCU_BCN_RSSI_CTL__RESET__VERIFY(src) \
26447 (!((((u_int32_t)(src)\
26473 #define MAC_PCU_USEC_LATENCY__USEC__READ(src) (u_int32_t)(src) & 0x000000ffU
26474 #define MAC_PCU_USEC_LATENCY__USEC__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
26475 #define MAC_PCU_USEC_LATENCY__USEC__MODIFY(dst, src) \
26477 ~0x000000ffU) | ((u_int32_t)(src) &\
26479 #define MAC_PCU_USEC_LATENCY__USEC__VERIFY(src) \
26480 (!(((u_int32_t)(src)\
26487 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__READ(src) \
26488 (((u_int32_t)(src)\
26490 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__WRITE(src) \
26491 (((u_int32_t)(src)\
26493 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__MODIFY(dst, src) \
26495 ~0x007fc000U) | (((u_int32_t)(src) <<\
26497 #define MAC_PCU_USEC_LATENCY__TX_LATENCY__VERIFY(src) \
26498 (!((((u_int32_t)(src)\
26505 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__READ(src) \
26506 (((u_int32_t)(src)\
26508 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__WRITE(src) \
26509 (((u_int32_t)(src)\
26511 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__MODIFY(dst, src) \
26513 ~0x1f800000U) | (((u_int32_t)(src) <<\
26515 #define MAC_PCU_USEC_LATENCY__RX_LATENCY__VERIFY(src) \
26516 (!((((u_int32_t)(src)\
26536 #define MAC_PCU_RESET_TSF__ONE_SHOT__READ(src) \
26537 (((u_int32_t)(src)\
26539 #define MAC_PCU_RESET_TSF__ONE_SHOT__WRITE(src) \
26540 (((u_int32_t)(src)\
26542 #define MAC_PCU_RESET_TSF__ONE_SHOT__MODIFY(dst, src) \
26544 ~0x01000000U) | (((u_int32_t)(src) <<\
26546 #define MAC_PCU_RESET_TSF__ONE_SHOT__VERIFY(src) \
26547 (!((((u_int32_t)(src)\
26560 #define MAC_PCU_RESET_TSF__ONE_SHOT2__READ(src) \
26561 (((u_int32_t)(src)\
26563 #define MAC_PCU_RESET_TSF__ONE_SHOT2__WRITE(src) \
26564 (((u_int32_t)(src)\
26566 #define MAC_PCU_RESET_TSF__ONE_SHOT2__MODIFY(dst, src) \
26568 ~0x02000000U) | (((u_int32_t)(src) <<\
26570 #define MAC_PCU_RESET_TSF__ONE_SHOT2__VERIFY(src) \
26571 (!((((u_int32_t)(src)\
26597 #define MAC_PCU_MAX_CFP_DUR__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU
26598 #define MAC_PCU_MAX_CFP_DUR__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
26599 #define MAC_PCU_MAX_CFP_DUR__VALUE__MODIFY(dst, src) \
26601 ~0x0000ffffU) | ((u_int32_t)(src) &\
26603 #define MAC_PCU_MAX_CFP_DUR__VALUE__VERIFY(src) \
26604 (!(((u_int32_t)(src)\
26611 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__READ(src) \
26612 (((u_int32_t)(src)\
26614 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__WRITE(src) \
26615 (((u_int32_t)(src)\
26617 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__MODIFY(dst, src) \
26619 ~0x000f0000U) | (((u_int32_t)(src) <<\
26621 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_NUMERATOR__VERIFY(src) \
26622 (!((((u_int32_t)(src)\
26629 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__READ(src) \
26630 (((u_int32_t)(src)\
26632 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__WRITE(src) \
26633 (((u_int32_t)(src)\
26635 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__MODIFY(dst, src) \
26637 ~0x0f000000U) | (((u_int32_t)(src) <<\
26639 #define MAC_PCU_MAX_CFP_DUR__USEC_FRAC_DENOMINATOR__VERIFY(src) \
26640 (!((((u_int32_t)(src)\
26660 #define MAC_PCU_RX_FILTER__UNICAST__READ(src) (u_int32_t)(src) & 0x00000001U
26661 #define MAC_PCU_RX_FILTER__UNICAST__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
26662 #define MAC_PCU_RX_FILTER__UNICAST__MODIFY(dst, src) \
26664 ~0x00000001U) | ((u_int32_t)(src) &\
26666 #define MAC_PCU_RX_FILTER__UNICAST__VERIFY(src) \
26667 (!(((u_int32_t)(src)\
26680 #define MAC_PCU_RX_FILTER__MULTICAST__READ(src) \
26681 (((u_int32_t)(src)\
26683 #define MAC_PCU_RX_FILTER__MULTICAST__WRITE(src) \
26684 (((u_int32_t)(src)\
26686 #define MAC_PCU_RX_FILTER__MULTICAST__MODIFY(dst, src) \
26688 ~0x00000002U) | (((u_int32_t)(src) <<\
26690 #define MAC_PCU_RX_FILTER__MULTICAST__VERIFY(src) \
26691 (!((((u_int32_t)(src)\
26704 #define MAC_PCU_RX_FILTER__BROADCAST__READ(src) \
26705 (((u_int32_t)(src)\
26707 #define MAC_PCU_RX_FILTER__BROADCAST__WRITE(src) \
26708 (((u_int32_t)(src)\
26710 #define MAC_PCU_RX_FILTER__BROADCAST__MODIFY(dst, src) \
26712 ~0x00000004U) | (((u_int32_t)(src) <<\
26714 #define MAC_PCU_RX_FILTER__BROADCAST__VERIFY(src) \
26715 (!((((u_int32_t)(src)\
26728 #define MAC_PCU_RX_FILTER__CONTROL__READ(src) \
26729 (((u_int32_t)(src)\
26731 #define MAC_PCU_RX_FILTER__CONTROL__WRITE(src) \
26732 (((u_int32_t)(src)\
26734 #define MAC_PCU_RX_FILTER__CONTROL__MODIFY(dst, src) \
26736 ~0x00000008U) | (((u_int32_t)(src) <<\
26738 #define MAC_PCU_RX_FILTER__CONTROL__VERIFY(src) \
26739 (!((((u_int32_t)(src)\
26752 #define MAC_PCU_RX_FILTER__BEACON__READ(src) \
26753 (((u_int32_t)(src)\
26755 #define MAC_PCU_RX_FILTER__BEACON__WRITE(src) \
26756 (((u_int32_t)(src)\
26758 #define MAC_PCU_RX_FILTER__BEACON__MODIFY(dst, src) \
26760 ~0x00000010U) | (((u_int32_t)(src) <<\
26762 #define MAC_PCU_RX_FILTER__BEACON__VERIFY(src) \
26763 (!((((u_int32_t)(src)\
26776 #define MAC_PCU_RX_FILTER__PROMISCUOUS__READ(src) \
26777 (((u_int32_t)(src)\
26779 #define MAC_PCU_RX_FILTER__PROMISCUOUS__WRITE(src) \
26780 (((u_int32_t)(src)\
26782 #define MAC_PCU_RX_FILTER__PROMISCUOUS__MODIFY(dst, src) \
26784 ~0x00000020U) | (((u_int32_t)(src) <<\
26786 #define MAC_PCU_RX_FILTER__PROMISCUOUS__VERIFY(src) \
26787 (!((((u_int32_t)(src)\
26800 #define MAC_PCU_RX_FILTER__XR_POLL__READ(src) \
26801 (((u_int32_t)(src)\
26803 #define MAC_PCU_RX_FILTER__XR_POLL__WRITE(src) \
26804 (((u_int32_t)(src)\
26806 #define MAC_PCU_RX_FILTER__XR_POLL__MODIFY(dst, src) \
26808 ~0x00000040U) | (((u_int32_t)(src) <<\
26810 #define MAC_PCU_RX_FILTER__XR_POLL__VERIFY(src) \
26811 (!((((u_int32_t)(src)\
26824 #define MAC_PCU_RX_FILTER__PROBE_REQ__READ(src) \
26825 (((u_int32_t)(src)\
26827 #define MAC_PCU_RX_FILTER__PROBE_REQ__WRITE(src) \
26828 (((u_int32_t)(src)\
26830 #define MAC_PCU_RX_FILTER__PROBE_REQ__MODIFY(dst, src) \
26832 ~0x00000080U) | (((u_int32_t)(src) <<\
26834 #define MAC_PCU_RX_FILTER__PROBE_REQ__VERIFY(src) \
26835 (!((((u_int32_t)(src)\
26848 #define MAC_PCU_RX_FILTER__SYNC_FRAME__READ(src) \
26849 (((u_int32_t)(src)\
26851 #define MAC_PCU_RX_FILTER__SYNC_FRAME__WRITE(src) \
26852 (((u_int32_t)(src)\
26854 #define MAC_PCU_RX_FILTER__SYNC_FRAME__MODIFY(dst, src) \
26856 ~0x00000100U) | (((u_int32_t)(src) <<\
26858 #define MAC_PCU_RX_FILTER__SYNC_FRAME__VERIFY(src) \
26859 (!((((u_int32_t)(src)\
26872 #define MAC_PCU_RX_FILTER__MY_BEACON__READ(src) \
26873 (((u_int32_t)(src)\
26875 #define MAC_PCU_RX_FILTER__MY_BEACON__WRITE(src) \
26876 (((u_int32_t)(src)\
26878 #define MAC_PCU_RX_FILTER__MY_BEACON__MODIFY(dst, src) \
26880 ~0x00000200U) | (((u_int32_t)(src) <<\
26882 #define MAC_PCU_RX_FILTER__MY_BEACON__VERIFY(src) \
26883 (!((((u_int32_t)(src)\
26896 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__READ(src) \
26897 (((u_int32_t)(src)\
26899 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__WRITE(src) \
26900 (((u_int32_t)(src)\
26902 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__MODIFY(dst, src) \
26904 ~0x00000400U) | (((u_int32_t)(src) <<\
26906 #define MAC_PCU_RX_FILTER__COMPRESSED_BAR__VERIFY(src) \
26907 (!((((u_int32_t)(src)\
26920 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__READ(src) \
26921 (((u_int32_t)(src)\
26923 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__WRITE(src) \
26924 (((u_int32_t)(src)\
26926 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__MODIFY(dst, src) \
26928 ~0x00000800U) | (((u_int32_t)(src) <<\
26930 #define MAC_PCU_RX_FILTER__COMPRESSED_BA__VERIFY(src) \
26931 (!((((u_int32_t)(src)\
26944 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__READ(src) \
26945 (((u_int32_t)(src)\
26947 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__WRITE(src) \
26948 (((u_int32_t)(src)\
26950 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__MODIFY(dst, src) \
26952 ~0x00001000U) | (((u_int32_t)(src) <<\
26954 #define MAC_PCU_RX_FILTER__UNCOMPRESSED_BA_BAR__VERIFY(src) \
26955 (!((((u_int32_t)(src)\
26968 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__READ(src) \
26969 (((u_int32_t)(src)\
26971 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__WRITE(src) \
26972 (((u_int32_t)(src)\
26974 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__MODIFY(dst, src) \
26976 ~0x00002000U) | (((u_int32_t)(src) <<\
26978 #define MAC_PCU_RX_FILTER__ASSUME_RADAR__VERIFY(src) \
26979 (!((((u_int32_t)(src)\
26992 #define MAC_PCU_RX_FILTER__PS_POLL__READ(src) \
26993 (((u_int32_t)(src)\
26995 #define MAC_PCU_RX_FILTER__PS_POLL__WRITE(src) \
26996 (((u_int32_t)(src)\
26998 #define MAC_PCU_RX_FILTER__PS_POLL__MODIFY(dst, src) \
27000 ~0x00004000U) | (((u_int32_t)(src) <<\
27002 #define MAC_PCU_RX_FILTER__PS_POLL__VERIFY(src) \
27003 (!((((u_int32_t)(src)\
27016 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__READ(src) \
27017 (((u_int32_t)(src)\
27019 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__WRITE(src) \
27020 (((u_int32_t)(src)\
27022 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__MODIFY(dst, src) \
27024 ~0x00008000U) | (((u_int32_t)(src) <<\
27026 #define MAC_PCU_RX_FILTER__MCAST_BCAST_ALL__VERIFY(src) \
27027 (!((((u_int32_t)(src)\
27040 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__READ(src) \
27041 (((u_int32_t)(src)\
27043 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__WRITE(src) \
27044 (((u_int32_t)(src)\
27046 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__MODIFY(dst, src) \
27048 ~0x00010000U) | (((u_int32_t)(src) <<\
27050 #define MAC_PCU_RX_FILTER__RST_DLMTR_CNT_DISABLE__VERIFY(src) \
27051 (!((((u_int32_t)(src)\
27064 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__READ(src) \
27065 (((u_int32_t)(src)\
27067 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__WRITE(src) \
27068 (((u_int32_t)(src)\
27070 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__MODIFY(dst, src) \
27072 ~0x00020000U) | (((u_int32_t)(src) <<\
27074 #define MAC_PCU_RX_FILTER__HW_BCN_PROC_ENABLE__VERIFY(src) \
27075 (!((((u_int32_t)(src)\
27088 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__READ(src) \
27089 (((u_int32_t)(src)\
27091 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__WRITE(src) \
27092 (((u_int32_t)(src)\
27094 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__MODIFY(dst, src) \
27096 ~0x00040000U) | (((u_int32_t)(src) <<\
27098 #define MAC_PCU_RX_FILTER__MGMT_ACTION_MCAST__VERIFY(src) \
27099 (!((((u_int32_t)(src)\
27125 #define MAC_PCU_MCAST_FILTER_L32__VALUE__READ(src) \
27126 (u_int32_t)(src)\
27128 #define MAC_PCU_MCAST_FILTER_L32__VALUE__WRITE(src) \
27129 ((u_int32_t)(src)\
27131 #define MAC_PCU_MCAST_FILTER_L32__VALUE__MODIFY(dst, src) \
27133 ~0xffffffffU) | ((u_int32_t)(src) &\
27135 #define MAC_PCU_MCAST_FILTER_L32__VALUE__VERIFY(src) \
27136 (!(((u_int32_t)(src)\
27156 #define MAC_PCU_MCAST_FILTER_U32__VALUE__READ(src) \
27157 (u_int32_t)(src)\
27159 #define MAC_PCU_MCAST_FILTER_U32__VALUE__WRITE(src) \
27160 ((u_int32_t)(src)\
27162 #define MAC_PCU_MCAST_FILTER_U32__VALUE__MODIFY(dst, src) \
27164 ~0xffffffffU) | ((u_int32_t)(src) &\
27166 #define MAC_PCU_MCAST_FILTER_U32__VALUE__VERIFY(src) \
27167 (!(((u_int32_t)(src)\
27187 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__READ(src) \
27188 (u_int32_t)(src)\
27190 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__WRITE(src) \
27191 ((u_int32_t)(src)\
27193 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__MODIFY(dst, src) \
27195 ~0x00000001U) | ((u_int32_t)(src) &\
27197 #define MAC_PCU_DIAG_SW__INVALID_KEY_NO_ACK__VERIFY(src) \
27198 (!(((u_int32_t)(src)\
27211 #define MAC_PCU_DIAG_SW__NO_ACK__READ(src) \
27212 (((u_int32_t)(src)\
27214 #define MAC_PCU_DIAG_SW__NO_ACK__WRITE(src) \
27215 (((u_int32_t)(src)\
27217 #define MAC_PCU_DIAG_SW__NO_ACK__MODIFY(dst, src) \
27219 ~0x00000002U) | (((u_int32_t)(src) <<\
27221 #define MAC_PCU_DIAG_SW__NO_ACK__VERIFY(src) \
27222 (!((((u_int32_t)(src)\
27235 #define MAC_PCU_DIAG_SW__NO_CTS__READ(src) \
27236 (((u_int32_t)(src)\
27238 #define MAC_PCU_DIAG_SW__NO_CTS__WRITE(src) \
27239 (((u_int32_t)(src)\
27241 #define MAC_PCU_DIAG_SW__NO_CTS__MODIFY(dst, src) \
27243 ~0x00000004U) | (((u_int32_t)(src) <<\
27245 #define MAC_PCU_DIAG_SW__NO_CTS__VERIFY(src) \
27246 (!((((u_int32_t)(src)\
27259 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__READ(src) \
27260 (((u_int32_t)(src)\
27262 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__WRITE(src) \
27263 (((u_int32_t)(src)\
27265 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__MODIFY(dst, src) \
27267 ~0x00000008U) | (((u_int32_t)(src) <<\
27269 #define MAC_PCU_DIAG_SW__NO_ENCRYPT__VERIFY(src) \
27270 (!((((u_int32_t)(src)\
27283 #define MAC_PCU_DIAG_SW__NO_DECRYPT__READ(src) \
27284 (((u_int32_t)(src)\
27286 #define MAC_PCU_DIAG_SW__NO_DECRYPT__WRITE(src) \
27287 (((u_int32_t)(src)\
27289 #define MAC_PCU_DIAG_SW__NO_DECRYPT__MODIFY(dst, src) \
27291 ~0x00000010U) | (((u_int32_t)(src) <<\
27293 #define MAC_PCU_DIAG_SW__NO_DECRYPT__VERIFY(src) \
27294 (!((((u_int32_t)(src)\
27307 #define MAC_PCU_DIAG_SW__HALT_RX__READ(src) \
27308 (((u_int32_t)(src)\
27310 #define MAC_PCU_DIAG_SW__HALT_RX__WRITE(src) \
27311 (((u_int32_t)(src)\
27313 #define MAC_PCU_DIAG_SW__HALT_RX__MODIFY(dst, src) \
27315 ~0x00000020U) | (((u_int32_t)(src) <<\
27317 #define MAC_PCU_DIAG_SW__HALT_RX__VERIFY(src) \
27318 (!((((u_int32_t)(src)\
27331 #define MAC_PCU_DIAG_SW__LOOP_BACK__READ(src) \
27332 (((u_int32_t)(src)\
27334 #define MAC_PCU_DIAG_SW__LOOP_BACK__WRITE(src) \
27335 (((u_int32_t)(src)\
27337 #define MAC_PCU_DIAG_SW__LOOP_BACK__MODIFY(dst, src) \
27339 ~0x00000040U) | (((u_int32_t)(src) <<\
27341 #define MAC_PCU_DIAG_SW__LOOP_BACK__VERIFY(src) \
27342 (!((((u_int32_t)(src)\
27355 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__READ(src) \
27356 (((u_int32_t)(src)\
27358 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__WRITE(src) \
27359 (((u_int32_t)(src)\
27361 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__MODIFY(dst, src) \
27363 ~0x00000080U) | (((u_int32_t)(src) <<\
27365 #define MAC_PCU_DIAG_SW__CORRUPT_FCS__VERIFY(src) \
27366 (!((((u_int32_t)(src)\
27379 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__READ(src) \
27380 (((u_int32_t)(src)\
27382 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__WRITE(src) \
27383 (((u_int32_t)(src)\
27385 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__MODIFY(dst, src) \
27387 ~0x00000100U) | (((u_int32_t)(src) <<\
27389 #define MAC_PCU_DIAG_SW__DUMP_CHAN_INFO__VERIFY(src) \
27390 (!((((u_int32_t)(src)\
27403 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__READ(src) \
27404 (((u_int32_t)(src)\
27406 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__WRITE(src) \
27407 (((u_int32_t)(src)\
27409 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__MODIFY(dst, src) \
27411 ~0x00020000U) | (((u_int32_t)(src) <<\
27413 #define MAC_PCU_DIAG_SW__ACCEPT_NON_V0__VERIFY(src) \
27414 (!((((u_int32_t)(src)\
27427 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__READ(src) \
27428 (((u_int32_t)(src)\
27430 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__WRITE(src) \
27431 (((u_int32_t)(src)\
27433 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__MODIFY(dst, src) \
27435 ~0x000c0000U) | (((u_int32_t)(src) <<\
27437 #define MAC_PCU_DIAG_SW__OBS_SEL_1_0__VERIFY(src) \
27438 (!((((u_int32_t)(src)\
27445 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__READ(src) \
27446 (((u_int32_t)(src)\
27448 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__WRITE(src) \
27449 (((u_int32_t)(src)\
27451 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__MODIFY(dst, src) \
27453 ~0x00100000U) | (((u_int32_t)(src) <<\
27455 #define MAC_PCU_DIAG_SW__RX_CLEAR_HIGH__VERIFY(src) \
27456 (!((((u_int32_t)(src)\
27469 #define MAC_PCU_DIAG_SW__IGNORE_NAV__READ(src) \
27470 (((u_int32_t)(src)\
27472 #define MAC_PCU_DIAG_SW__IGNORE_NAV__WRITE(src) \
27473 (((u_int32_t)(src)\
27475 #define MAC_PCU_DIAG_SW__IGNORE_NAV__MODIFY(dst, src) \
27477 ~0x00200000U) | (((u_int32_t)(src) <<\
27479 #define MAC_PCU_DIAG_SW__IGNORE_NAV__VERIFY(src) \
27480 (!((((u_int32_t)(src)\
27493 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__READ(src) \
27494 (((u_int32_t)(src)\
27496 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__WRITE(src) \
27497 (((u_int32_t)(src)\
27499 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__MODIFY(dst, src) \
27501 ~0x00400000U) | (((u_int32_t)(src) <<\
27503 #define MAC_PCU_DIAG_SW__CHAN_IDLE_HIGH__VERIFY(src) \
27504 (!((((u_int32_t)(src)\
27517 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__READ(src) \
27518 (((u_int32_t)(src)\
27520 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__WRITE(src) \
27521 (((u_int32_t)(src)\
27523 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__MODIFY(dst, src) \
27525 ~0x00800000U) | (((u_int32_t)(src) <<\
27527 #define MAC_PCU_DIAG_SW__PHYERR_ENABLE_EIFS_CTL__VERIFY(src) \
27528 (!((((u_int32_t)(src)\
27541 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__READ(src) \
27542 (((u_int32_t)(src)\
27544 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__WRITE(src) \
27545 (((u_int32_t)(src)\
27547 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__MODIFY(dst, src) \
27549 ~0x01000000U) | (((u_int32_t)(src) <<\
27551 #define MAC_PCU_DIAG_SW__DUAL_CHAIN_CHAN_INFO__VERIFY(src) \
27552 (!((((u_int32_t)(src)\
27565 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__READ(src) \
27566 (((u_int32_t)(src)\
27568 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__WRITE(src) \
27569 (((u_int32_t)(src)\
27571 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__MODIFY(dst, src) \
27573 ~0x02000000U) | (((u_int32_t)(src) <<\
27575 #define MAC_PCU_DIAG_SW__FORCE_RX_ABORT__VERIFY(src) \
27576 (!((((u_int32_t)(src)\
27589 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__READ(src) \
27590 (((u_int32_t)(src)\
27592 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__WRITE(src) \
27593 (((u_int32_t)(src)\
27595 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__MODIFY(dst, src) \
27597 ~0x04000000U) | (((u_int32_t)(src) <<\
27599 #define MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT__VERIFY(src) \
27600 (!((((u_int32_t)(src)\
27613 #define MAC_PCU_DIAG_SW__OBS_SEL_2__READ(src) \
27614 (((u_int32_t)(src)\
27616 #define MAC_PCU_DIAG_SW__OBS_SEL_2__WRITE(src) \
27617 (((u_int32_t)(src)\
27619 #define MAC_PCU_DIAG_SW__OBS_SEL_2__MODIFY(dst, src) \
27621 ~0x08000000U) | (((u_int32_t)(src) <<\
27623 #define MAC_PCU_DIAG_SW__OBS_SEL_2__VERIFY(src) \
27624 (!((((u_int32_t)(src)\
27637 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__READ(src) \
27638 (((u_int32_t)(src)\
27640 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__WRITE(src) \
27641 (((u_int32_t)(src)\
27643 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__MODIFY(dst, src) \
27645 ~0x10000000U) | (((u_int32_t)(src) <<\
27647 #define MAC_PCU_DIAG_SW__RX_CLEAR_CTL_LOW__VERIFY(src) \
27648 (!((((u_int32_t)(src)\
27661 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__READ(src) \
27662 (((u_int32_t)(src)\
27664 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__WRITE(src) \
27665 (((u_int32_t)(src)\
27667 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__MODIFY(dst, src) \
27669 ~0x20000000U) | (((u_int32_t)(src) <<\
27671 #define MAC_PCU_DIAG_SW__RX_CLEAR_EXT_LOW__VERIFY(src) \
27672 (!((((u_int32_t)(src)\
27685 #define MAC_PCU_DIAG_SW__DEBUG_MODE__READ(src) \
27686 (((u_int32_t)(src)\
27688 #define MAC_PCU_DIAG_SW__DEBUG_MODE__WRITE(src) \
27689 (((u_int32_t)(src)\
27691 #define MAC_PCU_DIAG_SW__DEBUG_MODE__MODIFY(dst, src) \
27693 ~0xc0000000U) | (((u_int32_t)(src) <<\
27695 #define MAC_PCU_DIAG_SW__DEBUG_MODE__VERIFY(src) \
27696 (!((((u_int32_t)(src)\
27716 #define MAC_PCU_TSF_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
27717 #define MAC_PCU_TSF_L32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
27718 #define MAC_PCU_TSF_L32__VALUE__MODIFY(dst, src) \
27720 ~0xffffffffU) | ((u_int32_t)(src) &\
27722 #define MAC_PCU_TSF_L32__VALUE__VERIFY(src) \
27723 (!(((u_int32_t)(src)\
27743 #define MAC_PCU_TSF_U32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
27744 #define MAC_PCU_TSF_U32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
27745 #define MAC_PCU_TSF_U32__VALUE__MODIFY(dst, src) \
27747 ~0xffffffffU) | ((u_int32_t)(src) &\
27749 #define MAC_PCU_TSF_U32__VALUE__VERIFY(src) \
27750 (!(((u_int32_t)(src)\
27770 #define MAC_PCU_TST_ADDAC__CONT_TX__READ(src) (u_int32_t)(src) & 0x00000001U
27771 #define MAC_PCU_TST_ADDAC__CONT_TX__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
27772 #define MAC_PCU_TST_ADDAC__CONT_TX__MODIFY(dst, src) \
27774 ~0x00000001U) | ((u_int32_t)(src) &\
27776 #define MAC_PCU_TST_ADDAC__CONT_TX__VERIFY(src) \
27777 (!(((u_int32_t)(src)\
27790 #define MAC_PCU_TST_ADDAC__TESTMODE__READ(src) \
27791 (((u_int32_t)(src)\
27793 #define MAC_PCU_TST_ADDAC__TESTMODE__WRITE(src) \
27794 (((u_int32_t)(src)\
27796 #define MAC_PCU_TST_ADDAC__TESTMODE__MODIFY(dst, src) \
27798 ~0x00000002U) | (((u_int32_t)(src) <<\
27800 #define MAC_PCU_TST_ADDAC__TESTMODE__VERIFY(src) \
27801 (!((((u_int32_t)(src)\
27814 #define MAC_PCU_TST_ADDAC__LOOP__READ(src) \
27815 (((u_int32_t)(src)\
27817 #define MAC_PCU_TST_ADDAC__LOOP__WRITE(src) \
27818 (((u_int32_t)(src)\
27820 #define MAC_PCU_TST_ADDAC__LOOP__MODIFY(dst, src) \
27822 ~0x00000004U) | (((u_int32_t)(src) <<\
27824 #define MAC_PCU_TST_ADDAC__LOOP__VERIFY(src) \
27825 (!((((u_int32_t)(src)\
27838 #define MAC_PCU_TST_ADDAC__LOOP_LEN__READ(src) \
27839 (((u_int32_t)(src)\
27841 #define MAC_PCU_TST_ADDAC__LOOP_LEN__WRITE(src) \
27842 (((u_int32_t)(src)\
27844 #define MAC_PCU_TST_ADDAC__LOOP_LEN__MODIFY(dst, src) \
27846 ~0x00003ff8U) | (((u_int32_t)(src) <<\
27848 #define MAC_PCU_TST_ADDAC__LOOP_LEN__VERIFY(src) \
27849 (!((((u_int32_t)(src)\
27856 #define MAC_PCU_TST_ADDAC__UPPER_8B__READ(src) \
27857 (((u_int32_t)(src)\
27859 #define MAC_PCU_TST_ADDAC__UPPER_8B__WRITE(src) \
27860 (((u_int32_t)(src)\
27862 #define MAC_PCU_TST_ADDAC__UPPER_8B__MODIFY(dst, src) \
27864 ~0x00004000U) | (((u_int32_t)(src) <<\
27866 #define MAC_PCU_TST_ADDAC__UPPER_8B__VERIFY(src) \
27867 (!((((u_int32_t)(src)\
27880 #define MAC_PCU_TST_ADDAC__TRIG_SEL__READ(src) \
27881 (((u_int32_t)(src)\
27883 #define MAC_PCU_TST_ADDAC__TRIG_SEL__WRITE(src) \
27884 (((u_int32_t)(src)\
27886 #define MAC_PCU_TST_ADDAC__TRIG_SEL__MODIFY(dst, src) \
27888 ~0x00010000U) | (((u_int32_t)(src) <<\
27890 #define MAC_PCU_TST_ADDAC__TRIG_SEL__VERIFY(src) \
27891 (!((((u_int32_t)(src)\
27904 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__READ(src) \
27905 (((u_int32_t)(src)\
27907 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__WRITE(src) \
27908 (((u_int32_t)(src)\
27910 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__MODIFY(dst, src) \
27912 ~0x00020000U) | (((u_int32_t)(src) <<\
27914 #define MAC_PCU_TST_ADDAC__TRIG_POLARITY__VERIFY(src) \
27915 (!((((u_int32_t)(src)\
27928 #define MAC_PCU_TST_ADDAC__CONT_TEST__READ(src) \
27929 (((u_int32_t)(src)\
27942 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__READ(src) \
27943 (((u_int32_t)(src)\
27945 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__WRITE(src) \
27946 (((u_int32_t)(src)\
27948 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__MODIFY(dst, src) \
27950 ~0x00080000U) | (((u_int32_t)(src) <<\
27952 #define MAC_PCU_TST_ADDAC__TEST_CAPTURE__VERIFY(src) \
27953 (!((((u_int32_t)(src)\
27966 #define MAC_PCU_TST_ADDAC__TEST_ARM__READ(src) \
27967 (((u_int32_t)(src)\
27969 #define MAC_PCU_TST_ADDAC__TEST_ARM__WRITE(src) \
27970 (((u_int32_t)(src)\
27972 #define MAC_PCU_TST_ADDAC__TEST_ARM__MODIFY(dst, src) \
27974 ~0x00100000U) | (((u_int32_t)(src) <<\
27976 #define MAC_PCU_TST_ADDAC__TEST_ARM__VERIFY(src) \
27977 (!((((u_int32_t)(src)\
28003 #define MAC_PCU_DEF_ANTENNA__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU
28004 #define MAC_PCU_DEF_ANTENNA__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00ffffffU)
28005 #define MAC_PCU_DEF_ANTENNA__VALUE__MODIFY(dst, src) \
28007 ~0x00ffffffU) | ((u_int32_t)(src) &\
28009 #define MAC_PCU_DEF_ANTENNA__VALUE__VERIFY(src) \
28010 (!(((u_int32_t)(src)\
28017 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__READ(src) \
28018 (((u_int32_t)(src)\
28020 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__WRITE(src) \
28021 (((u_int32_t)(src)\
28023 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__MODIFY(dst, src) \
28025 ~0x01000000U) | (((u_int32_t)(src) <<\
28027 #define MAC_PCU_DEF_ANTENNA__TX_DEF_ANT_SEL__VERIFY(src) \
28028 (!((((u_int32_t)(src)\
28041 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__READ(src) \
28042 (((u_int32_t)(src)\
28044 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__WRITE(src) \
28045 (((u_int32_t)(src)\
28047 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__MODIFY(dst, src) \
28049 ~0x02000000U) | (((u_int32_t)(src) <<\
28051 #define MAC_PCU_DEF_ANTENNA__SLOW_TX_ANT_EN__VERIFY(src) \
28052 (!((((u_int32_t)(src)\
28065 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__READ(src) \
28066 (((u_int32_t)(src)\
28068 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__WRITE(src) \
28069 (((u_int32_t)(src)\
28071 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__MODIFY(dst, src) \
28073 ~0x04000000U) | (((u_int32_t)(src) <<\
28075 #define MAC_PCU_DEF_ANTENNA__TX_CUR_ANT__VERIFY(src) \
28076 (!((((u_int32_t)(src)\
28089 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__READ(src) \
28090 (((u_int32_t)(src)\
28092 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__WRITE(src) \
28093 (((u_int32_t)(src)\
28095 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__MODIFY(dst, src) \
28097 ~0x08000000U) | (((u_int32_t)(src) <<\
28099 #define MAC_PCU_DEF_ANTENNA__FAST_DEF_ANT__VERIFY(src) \
28100 (!((((u_int32_t)(src)\
28113 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__READ(src) \
28114 (((u_int32_t)(src)\
28116 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__WRITE(src) \
28117 (((u_int32_t)(src)\
28119 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__MODIFY(dst, src) \
28121 ~0x10000000U) | (((u_int32_t)(src) <<\
28123 #define MAC_PCU_DEF_ANTENNA__RX_LNA_CONFIG_SEL__VERIFY(src) \
28124 (!((((u_int32_t)(src)\
28137 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__READ(src) \
28138 (((u_int32_t)(src)\
28140 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__WRITE(src) \
28141 (((u_int32_t)(src)\
28143 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__MODIFY(dst, src) \
28145 ~0x20000000U) | (((u_int32_t)(src) <<\
28147 #define MAC_PCU_DEF_ANTENNA__FAST_TX_ANT_EN__VERIFY(src) \
28148 (!((((u_int32_t)(src)\
28174 #define MAC_PCU_AES_MUTE_MASK_0__FC__READ(src) (u_int32_t)(src) & 0x0000ffffU
28175 #define MAC_PCU_AES_MUTE_MASK_0__FC__WRITE(src) \
28176 ((u_int32_t)(src)\
28178 #define MAC_PCU_AES_MUTE_MASK_0__FC__MODIFY(dst, src) \
28180 ~0x0000ffffU) | ((u_int32_t)(src) &\
28182 #define MAC_PCU_AES_MUTE_MASK_0__FC__VERIFY(src) \
28183 (!(((u_int32_t)(src)\
28190 #define MAC_PCU_AES_MUTE_MASK_0__QOS__READ(src) \
28191 (((u_int32_t)(src)\
28193 #define MAC_PCU_AES_MUTE_MASK_0__QOS__WRITE(src) \
28194 (((u_int32_t)(src)\
28196 #define MAC_PCU_AES_MUTE_MASK_0__QOS__MODIFY(dst, src) \
28198 ~0xffff0000U) | (((u_int32_t)(src) <<\
28200 #define MAC_PCU_AES_MUTE_MASK_0__QOS__VERIFY(src) \
28201 (!((((u_int32_t)(src)\
28221 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__READ(src) (u_int32_t)(src) & 0x0000ffffU
28222 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__WRITE(src) \
28223 ((u_int32_t)(src)\
28225 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__MODIFY(dst, src) \
28227 ~0x0000ffffU) | ((u_int32_t)(src) &\
28229 #define MAC_PCU_AES_MUTE_MASK_1__SEQ__VERIFY(src) \
28230 (!(((u_int32_t)(src)\
28237 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__READ(src) \
28238 (((u_int32_t)(src)\
28240 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__WRITE(src) \
28241 (((u_int32_t)(src)\
28243 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__MODIFY(dst, src) \
28245 ~0xffff0000U) | (((u_int32_t)(src) <<\
28247 #define MAC_PCU_AES_MUTE_MASK_1__FC_MGMT__VERIFY(src) \
28248 (!((((u_int32_t)(src)\
28268 #define MAC_PCU_GATED_CLKS__GATED_TX__READ(src) \
28269 (((u_int32_t)(src)\
28271 #define MAC_PCU_GATED_CLKS__GATED_TX__WRITE(src) \
28272 (((u_int32_t)(src)\
28274 #define MAC_PCU_GATED_CLKS__GATED_TX__MODIFY(dst, src) \
28276 ~0x00000002U) | (((u_int32_t)(src) <<\
28278 #define MAC_PCU_GATED_CLKS__GATED_TX__VERIFY(src) \
28279 (!((((u_int32_t)(src)\
28292 #define MAC_PCU_GATED_CLKS__GATED_RX__READ(src) \
28293 (((u_int32_t)(src)\
28295 #define MAC_PCU_GATED_CLKS__GATED_RX__WRITE(src) \
28296 (((u_int32_t)(src)\
28298 #define MAC_PCU_GATED_CLKS__GATED_RX__MODIFY(dst, src) \
28300 ~0x00000004U) | (((u_int32_t)(src) <<\
28302 #define MAC_PCU_GATED_CLKS__GATED_RX__VERIFY(src) \
28303 (!((((u_int32_t)(src)\
28316 #define MAC_PCU_GATED_CLKS__GATED_REG__READ(src) \
28317 (((u_int32_t)(src)\
28319 #define MAC_PCU_GATED_CLKS__GATED_REG__WRITE(src) \
28320 (((u_int32_t)(src)\
28322 #define MAC_PCU_GATED_CLKS__GATED_REG__MODIFY(dst, src) \
28324 ~0x00000008U) | (((u_int32_t)(src) <<\
28326 #define MAC_PCU_GATED_CLKS__GATED_REG__VERIFY(src) \
28327 (!((((u_int32_t)(src)\
28353 #define MAC_PCU_OBS_BUS_2__VALUE__READ(src) (u_int32_t)(src) & 0x0003ffffU
28359 #define MAC_PCU_OBS_BUS_2__WCF_STATE__READ(src) \
28360 (((u_int32_t)(src)\
28367 #define MAC_PCU_OBS_BUS_2__WCF0_FULL__READ(src) \
28368 (((u_int32_t)(src)\
28381 #define MAC_PCU_OBS_BUS_2__WCF1_FULL__READ(src) \
28382 (((u_int32_t)(src)\
28395 #define MAC_PCU_OBS_BUS_2__WCF_COUNT__READ(src) \
28396 (((u_int32_t)(src)\
28403 #define MAC_PCU_OBS_BUS_2__MACBB_ALL_AWAKE__READ(src) \
28404 (((u_int32_t)(src)\
28429 #define MAC_PCU_OBS_BUS_1__PCU_DIRECTED__READ(src) \
28430 (u_int32_t)(src)\
28443 #define MAC_PCU_OBS_BUS_1__PCU_RX_END__READ(src) \
28444 (((u_int32_t)(src)\
28457 #define MAC_PCU_OBS_BUS_1__RX_WEP__READ(src) \
28458 (((u_int32_t)(src)\
28471 #define MAC_PCU_OBS_BUS_1__RX_MY_BEACON__READ(src) \
28472 (((u_int32_t)(src)\
28485 #define MAC_PCU_OBS_BUS_1__FILTER_PASS__READ(src) \
28486 (((u_int32_t)(src)\
28499 #define MAC_PCU_OBS_BUS_1__TX_HCF__READ(src) \
28500 (((u_int32_t)(src)\
28513 #define MAC_PCU_OBS_BUS_1__TM_QUIET_TIME__READ(src) \
28514 (((u_int32_t)(src)\
28527 #define MAC_PCU_OBS_BUS_1__PCU_CHANNEL_IDLE__READ(src) \
28528 (((u_int32_t)(src)\
28541 #define MAC_PCU_OBS_BUS_1__TX_HOLD__READ(src) \
28542 (((u_int32_t)(src)\
28555 #define MAC_PCU_OBS_BUS_1__TX_FRAME__READ(src) \
28556 (((u_int32_t)(src)\
28569 #define MAC_PCU_OBS_BUS_1__RX_FRAME__READ(src) \
28570 (((u_int32_t)(src)\
28583 #define MAC_PCU_OBS_BUS_1__RX_CLEAR__READ(src) \
28584 (((u_int32_t)(src)\
28597 #define MAC_PCU_OBS_BUS_1__WEP_STATE__READ(src) \
28598 (((u_int32_t)(src)\
28605 #define MAC_PCU_OBS_BUS_1__RX_STATE__READ(src) \
28606 (((u_int32_t)(src)\
28613 #define MAC_PCU_OBS_BUS_1__TX_STATE__READ(src) \
28614 (((u_int32_t)(src)\
28633 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__READ(src) \
28634 (u_int32_t)(src)\
28636 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__WRITE(src) \
28637 ((u_int32_t)(src)\
28639 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__MODIFY(dst, src) \
28641 ~0x00000001U) | ((u_int32_t)(src) &\
28643 #define MAC_PCU_DYM_MIMO_PWR_SAVE__USE_MAC_CTRL__VERIFY(src) \
28644 (!(((u_int32_t)(src)\
28657 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__READ(src) \
28658 (((u_int32_t)(src)\
28660 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__WRITE(src) \
28661 (((u_int32_t)(src)\
28663 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__MODIFY(dst, src) \
28665 ~0x00000002U) | (((u_int32_t)(src) <<\
28667 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HW_CTRL_EN__VERIFY(src) \
28668 (!((((u_int32_t)(src)\
28681 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__READ(src) \
28682 (((u_int32_t)(src)\
28684 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__WRITE(src) \
28685 (((u_int32_t)(src)\
28687 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__MODIFY(dst, src) \
28689 ~0x00000004U) | (((u_int32_t)(src) <<\
28691 #define MAC_PCU_DYM_MIMO_PWR_SAVE__SW_CHAIN_MASK_SEL__VERIFY(src) \
28692 (!((((u_int32_t)(src)\
28705 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__READ(src) \
28706 (((u_int32_t)(src)\
28708 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__WRITE(src) \
28709 (((u_int32_t)(src)\
28711 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__MODIFY(dst, src) \
28713 ~0x00000070U) | (((u_int32_t)(src) <<\
28715 #define MAC_PCU_DYM_MIMO_PWR_SAVE__LOW_PWR_CHAIN_MASK__VERIFY(src) \
28716 (!((((u_int32_t)(src)\
28723 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__READ(src) \
28724 (((u_int32_t)(src)\
28726 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__WRITE(src) \
28727 (((u_int32_t)(src)\
28729 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__MODIFY(dst, src) \
28731 ~0x00000700U) | (((u_int32_t)(src) <<\
28733 #define MAC_PCU_DYM_MIMO_PWR_SAVE__HI_PWR_CHAIN_MASK__VERIFY(src) \
28734 (!((((u_int32_t)(src)\
28754 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__READ(src) \
28755 (u_int32_t)(src)\
28757 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__WRITE(src) \
28758 ((u_int32_t)(src)\
28760 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__MODIFY(dst, src) \
28762 ~0xffffffffU) | ((u_int32_t)(src) &\
28764 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_LSB__VALUE__VERIFY(src) \
28765 (!(((u_int32_t)(src)\
28786 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__READ(src) \
28787 (u_int32_t)(src)\
28789 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__WRITE(src) \
28790 ((u_int32_t)(src)\
28792 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__MODIFY(dst, src) \
28794 ~0xffffffffU) | ((u_int32_t)(src) &\
28796 #define MAC_PCU_TDMA_TXFRAME_START_TIME_TRIGGER_MSB__VALUE__VERIFY(src) \
28797 (!(((u_int32_t)(src)\
28818 #define MAC_PCU_LAST_BEACON_TSF__VALUE__READ(src) \
28819 (u_int32_t)(src)\
28838 #define MAC_PCU_NAV__VALUE__READ(src) (u_int32_t)(src) & 0x03ffffffU
28839 #define MAC_PCU_NAV__VALUE__WRITE(src) ((u_int32_t)(src) & 0x03ffffffU)
28840 #define MAC_PCU_NAV__VALUE__MODIFY(dst, src) \
28842 ~0x03ffffffU) | ((u_int32_t)(src) &\
28844 #define MAC_PCU_NAV__VALUE__VERIFY(src) (!(((u_int32_t)(src) & ~0x03ffffffU)))
28863 #define MAC_PCU_RTS_SUCCESS_CNT__VALUE__READ(src) \
28864 (u_int32_t)(src)\
28883 #define MAC_PCU_RTS_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU
28901 #define MAC_PCU_ACK_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU
28919 #define MAC_PCU_FCS_FAIL_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU
28937 #define MAC_PCU_BEACON_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU
28955 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__READ(src) \
28956 (u_int32_t)(src)\
28958 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__WRITE(src) \
28959 ((u_int32_t)(src)\
28961 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__MODIFY(dst, src) \
28963 ~0x0000ffffU) | ((u_int32_t)(src) &\
28965 #define MAC_PCU_TDMA_SLOT_ALERT_CNTL__VALUE__VERIFY(src) \
28966 (!(((u_int32_t)(src)\
28986 #define MAC_PCU_BASIC_SET__MCS__READ(src) (u_int32_t)(src) & 0xffffffffU
28987 #define MAC_PCU_BASIC_SET__MCS__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
28988 #define MAC_PCU_BASIC_SET__MCS__MODIFY(dst, src) \
28990 ~0xffffffffU) | ((u_int32_t)(src) &\
28992 #define MAC_PCU_BASIC_SET__MCS__VERIFY(src) \
28993 (!(((u_int32_t)(src)\
29013 #define MAC_PCU_MGMT_SEQ__MIN__READ(src) (u_int32_t)(src) & 0x00000fffU
29014 #define MAC_PCU_MGMT_SEQ__MIN__WRITE(src) ((u_int32_t)(src) & 0x00000fffU)
29015 #define MAC_PCU_MGMT_SEQ__MIN__MODIFY(dst, src) \
29017 ~0x00000fffU) | ((u_int32_t)(src) &\
29019 #define MAC_PCU_MGMT_SEQ__MIN__VERIFY(src) \
29020 (!(((u_int32_t)(src)\
29027 #define MAC_PCU_MGMT_SEQ__MAX__READ(src) \
29028 (((u_int32_t)(src)\
29030 #define MAC_PCU_MGMT_SEQ__MAX__WRITE(src) \
29031 (((u_int32_t)(src)\
29033 #define MAC_PCU_MGMT_SEQ__MAX__MODIFY(dst, src) \
29035 ~0x0fff0000U) | (((u_int32_t)(src) <<\
29037 #define MAC_PCU_MGMT_SEQ__MAX__VERIFY(src) \
29038 (!((((u_int32_t)(src)\
29058 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__READ(src) \
29059 (u_int32_t)(src)\
29061 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__WRITE(src) \
29062 ((u_int32_t)(src)\
29064 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__MODIFY(dst, src) \
29066 ~0x000000ffU) | ((u_int32_t)(src) &\
29068 #define MAC_PCU_BF_RPT1__V_ACTION_VALUE__VERIFY(src) \
29069 (!(((u_int32_t)(src)\
29076 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__READ(src) \
29077 (((u_int32_t)(src)\
29079 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__WRITE(src) \
29080 (((u_int32_t)(src)\
29082 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__MODIFY(dst, src) \
29084 ~0x0000ff00U) | (((u_int32_t)(src) <<\
29086 #define MAC_PCU_BF_RPT1__CV_ACTION_VALUE__VERIFY(src) \
29087 (!((((u_int32_t)(src)\
29094 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__READ(src) \
29095 (((u_int32_t)(src)\
29097 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__WRITE(src) \
29098 (((u_int32_t)(src)\
29100 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__MODIFY(dst, src) \
29102 ~0x00ff0000U) | (((u_int32_t)(src) <<\
29104 #define MAC_PCU_BF_RPT1__CATEGORY_VALUE__VERIFY(src) \
29105 (!((((u_int32_t)(src)\
29112 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__READ(src) \
29113 (((u_int32_t)(src)\
29115 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__WRITE(src) \
29116 (((u_int32_t)(src)\
29118 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \
29120 ~0x0f000000U) | (((u_int32_t)(src) <<\
29122 #define MAC_PCU_BF_RPT1__FRAME_SUBTYPE_VALUE__VERIFY(src) \
29123 (!((((u_int32_t)(src)\
29130 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__READ(src) \
29131 (((u_int32_t)(src)\
29133 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__WRITE(src) \
29134 (((u_int32_t)(src)\
29136 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__MODIFY(dst, src) \
29138 ~0x30000000U) | (((u_int32_t)(src) <<\
29140 #define MAC_PCU_BF_RPT1__FRAME_TYPE_VALUE__VERIFY(src) \
29141 (!((((u_int32_t)(src)\
29161 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__READ(src) \
29162 (u_int32_t)(src)\
29164 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__WRITE(src) \
29165 ((u_int32_t)(src)\
29167 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__MODIFY(dst, src) \
29169 ~0x0000000fU) | ((u_int32_t)(src) &\
29171 #define MAC_PCU_BF_RPT2__FRAME_SUBTYPE_VALUE__VERIFY(src) \
29172 (!(((u_int32_t)(src)\
29192 #define MAC_PCU_TX_ANT_1__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
29193 #define MAC_PCU_TX_ANT_1__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
29194 #define MAC_PCU_TX_ANT_1__VALUE__MODIFY(dst, src) \
29196 ~0xffffffffU) | ((u_int32_t)(src) &\
29198 #define MAC_PCU_TX_ANT_1__VALUE__VERIFY(src) \
29199 (!(((u_int32_t)(src)\
29219 #define MAC_PCU_TX_ANT_2__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
29220 #define MAC_PCU_TX_ANT_2__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
29221 #define MAC_PCU_TX_ANT_2__VALUE__MODIFY(dst, src) \
29223 ~0xffffffffU) | ((u_int32_t)(src) &\
29225 #define MAC_PCU_TX_ANT_2__VALUE__VERIFY(src) \
29226 (!(((u_int32_t)(src)\
29246 #define MAC_PCU_TX_ANT_3__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
29247 #define MAC_PCU_TX_ANT_3__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
29248 #define MAC_PCU_TX_ANT_3__VALUE__MODIFY(dst, src) \
29250 ~0xffffffffU) | ((u_int32_t)(src) &\
29252 #define MAC_PCU_TX_ANT_3__VALUE__VERIFY(src) \
29253 (!(((u_int32_t)(src)\
29273 #define MAC_PCU_TX_ANT_4__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
29274 #define MAC_PCU_TX_ANT_4__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
29275 #define MAC_PCU_TX_ANT_4__VALUE__MODIFY(dst, src) \
29277 ~0xffffffffU) | ((u_int32_t)(src) &\
29279 #define MAC_PCU_TX_ANT_4__VALUE__VERIFY(src) \
29280 (!(((u_int32_t)(src)\
29300 #define MAC_PCU_XRMODE__POLL_TYPE__READ(src) (u_int32_t)(src) & 0x0000003fU
29301 #define MAC_PCU_XRMODE__POLL_TYPE__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
29302 #define MAC_PCU_XRMODE__POLL_TYPE__MODIFY(dst, src) \
29304 ~0x0000003fU) | ((u_int32_t)(src) &\
29306 #define MAC_PCU_XRMODE__POLL_TYPE__VERIFY(src) \
29307 (!(((u_int32_t)(src)\
29314 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__READ(src) \
29315 (((u_int32_t)(src)\
29317 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__WRITE(src) \
29318 (((u_int32_t)(src)\
29320 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__MODIFY(dst, src) \
29322 ~0x00000080U) | (((u_int32_t)(src) <<\
29324 #define MAC_PCU_XRMODE__WAIT_FOR_POLL__VERIFY(src) \
29325 (!((((u_int32_t)(src)\
29338 #define MAC_PCU_XRMODE__FRAME_HOLD__READ(src) \
29339 (((u_int32_t)(src)\
29341 #define MAC_PCU_XRMODE__FRAME_HOLD__WRITE(src) \
29342 (((u_int32_t)(src)\
29344 #define MAC_PCU_XRMODE__FRAME_HOLD__MODIFY(dst, src) \
29346 ~0xfff00000U) | (((u_int32_t)(src) <<\
29348 #define MAC_PCU_XRMODE__FRAME_HOLD__VERIFY(src) \
29349 (!((((u_int32_t)(src)\
29369 #define MAC_PCU_XRDEL__SLOT_DELAY__READ(src) (u_int32_t)(src) & 0x0000ffffU
29370 #define MAC_PCU_XRDEL__SLOT_DELAY__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
29371 #define MAC_PCU_XRDEL__SLOT_DELAY__MODIFY(dst, src) \
29373 ~0x0000ffffU) | ((u_int32_t)(src) &\
29375 #define MAC_PCU_XRDEL__SLOT_DELAY__VERIFY(src) \
29376 (!(((u_int32_t)(src)\
29383 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__READ(src) \
29384 (((u_int32_t)(src)\
29386 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__WRITE(src) \
29387 (((u_int32_t)(src)\
29389 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__MODIFY(dst, src) \
29391 ~0xffff0000U) | (((u_int32_t)(src) <<\
29393 #define MAC_PCU_XRDEL__CHIRP_DATA_DELAY__VERIFY(src) \
29394 (!((((u_int32_t)(src)\
29414 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__READ(src) (u_int32_t)(src) & 0x0000ffffU
29415 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__WRITE(src) \
29416 ((u_int32_t)(src)\
29418 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__MODIFY(dst, src) \
29420 ~0x0000ffffU) | ((u_int32_t)(src) &\
29422 #define MAC_PCU_XRTO__CHIRP_TIMEOUT__VERIFY(src) \
29423 (!(((u_int32_t)(src)\
29430 #define MAC_PCU_XRTO__POLL_TIMEOUT__READ(src) \
29431 (((u_int32_t)(src)\
29433 #define MAC_PCU_XRTO__POLL_TIMEOUT__WRITE(src) \
29434 (((u_int32_t)(src)\
29436 #define MAC_PCU_XRTO__POLL_TIMEOUT__MODIFY(dst, src) \
29438 ~0xffff0000U) | (((u_int32_t)(src) <<\
29440 #define MAC_PCU_XRTO__POLL_TIMEOUT__VERIFY(src) \
29441 (!((((u_int32_t)(src)\
29461 #define MAC_PCU_XRCRP__SEND_CHIRP__READ(src) (u_int32_t)(src) & 0x00000001U
29462 #define MAC_PCU_XRCRP__SEND_CHIRP__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
29463 #define MAC_PCU_XRCRP__SEND_CHIRP__MODIFY(dst, src) \
29465 ~0x00000001U) | ((u_int32_t)(src) &\
29467 #define MAC_PCU_XRCRP__SEND_CHIRP__VERIFY(src) \
29468 (!(((u_int32_t)(src)\
29481 #define MAC_PCU_XRCRP__CHIRP_GAP__READ(src) \
29482 (((u_int32_t)(src)\
29484 #define MAC_PCU_XRCRP__CHIRP_GAP__WRITE(src) \
29485 (((u_int32_t)(src)\
29487 #define MAC_PCU_XRCRP__CHIRP_GAP__MODIFY(dst, src) \
29489 ~0xffff0000U) | (((u_int32_t)(src) <<\
29491 #define MAC_PCU_XRCRP__CHIRP_GAP__VERIFY(src) \
29492 (!((((u_int32_t)(src)\
29512 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__READ(src) (u_int32_t)(src) & 0x00000001U
29513 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__WRITE(src) \
29514 ((u_int32_t)(src)\
29516 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__MODIFY(dst, src) \
29518 ~0x00000001U) | ((u_int32_t)(src) &\
29520 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI__VERIFY(src) \
29521 (!(((u_int32_t)(src)\
29534 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__READ(src) \
29535 (((u_int32_t)(src)\
29537 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__WRITE(src) \
29538 (((u_int32_t)(src)\
29540 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__MODIFY(dst, src) \
29542 ~0x00000002U) | (((u_int32_t)(src) <<\
29544 #define MAC_PCU_XRSTMP__RX_ABORT_BSSID__VERIFY(src) \
29545 (!((((u_int32_t)(src)\
29558 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__READ(src) \
29559 (((u_int32_t)(src)\
29561 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__WRITE(src) \
29562 (((u_int32_t)(src)\
29564 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__MODIFY(dst, src) \
29566 ~0x00000004U) | (((u_int32_t)(src) <<\
29568 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI__VERIFY(src) \
29569 (!((((u_int32_t)(src)\
29582 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__READ(src) \
29583 (((u_int32_t)(src)\
29585 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__WRITE(src) \
29586 (((u_int32_t)(src)\
29588 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__MODIFY(dst, src) \
29590 ~0x00000008U) | (((u_int32_t)(src) <<\
29592 #define MAC_PCU_XRSTMP__TX_STOMP_BSSID__VERIFY(src) \
29593 (!((((u_int32_t)(src)\
29606 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__READ(src) \
29607 (((u_int32_t)(src)\
29609 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__WRITE(src) \
29610 (((u_int32_t)(src)\
29612 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__MODIFY(dst, src) \
29614 ~0x00000010U) | (((u_int32_t)(src) <<\
29616 #define MAC_PCU_XRSTMP__TX_STOMP_DATA__VERIFY(src) \
29617 (!((((u_int32_t)(src)\
29630 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__READ(src) \
29631 (((u_int32_t)(src)\
29633 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__WRITE(src) \
29634 (((u_int32_t)(src)\
29636 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__MODIFY(dst, src) \
29638 ~0x00000020U) | (((u_int32_t)(src) <<\
29640 #define MAC_PCU_XRSTMP__RX_ABORT_DATA__VERIFY(src) \
29641 (!((((u_int32_t)(src)\
29654 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__READ(src) \
29655 (((u_int32_t)(src)\
29657 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__WRITE(src) \
29658 (((u_int32_t)(src)\
29660 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__MODIFY(dst, src) \
29662 ~0x0000ff00U) | (((u_int32_t)(src) <<\
29664 #define MAC_PCU_XRSTMP__TX_STOMP_RSSI_THRESH__VERIFY(src) \
29665 (!((((u_int32_t)(src)\
29672 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__READ(src) \
29673 (((u_int32_t)(src)\
29675 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__WRITE(src) \
29676 (((u_int32_t)(src)\
29678 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__MODIFY(dst, src) \
29680 ~0x00ff0000U) | (((u_int32_t)(src) <<\
29682 #define MAC_PCU_XRSTMP__RX_ABORT_RSSI_THRESH__VERIFY(src) \
29683 (!((((u_int32_t)(src)\
29703 #define MAC_PCU_SLP1__ASSUME_DTIM__READ(src) \
29704 (((u_int32_t)(src)\
29706 #define MAC_PCU_SLP1__ASSUME_DTIM__WRITE(src) \
29707 (((u_int32_t)(src)\
29709 #define MAC_PCU_SLP1__ASSUME_DTIM__MODIFY(dst, src) \
29711 ~0x00080000U) | (((u_int32_t)(src) <<\
29713 #define MAC_PCU_SLP1__ASSUME_DTIM__VERIFY(src) \
29714 (!((((u_int32_t)(src)\
29727 #define MAC_PCU_SLP1__CAB_TIMEOUT__READ(src) \
29728 (((u_int32_t)(src)\
29730 #define MAC_PCU_SLP1__CAB_TIMEOUT__WRITE(src) \
29731 (((u_int32_t)(src)\
29733 #define MAC_PCU_SLP1__CAB_TIMEOUT__MODIFY(dst, src) \
29735 ~0xffe00000U) | (((u_int32_t)(src) <<\
29737 #define MAC_PCU_SLP1__CAB_TIMEOUT__VERIFY(src) \
29738 (!((((u_int32_t)(src)\
29758 #define MAC_PCU_SLP2__BEACON_TIMEOUT__READ(src) \
29759 (((u_int32_t)(src)\
29761 #define MAC_PCU_SLP2__BEACON_TIMEOUT__WRITE(src) \
29762 (((u_int32_t)(src)\
29764 #define MAC_PCU_SLP2__BEACON_TIMEOUT__MODIFY(dst, src) \
29766 ~0xffe00000U) | (((u_int32_t)(src) <<\
29768 #define MAC_PCU_SLP2__BEACON_TIMEOUT__VERIFY(src) \
29769 (!((((u_int32_t)(src)\
29789 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__READ(src) \
29790 (u_int32_t)(src)\
29792 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__WRITE(src) \
29793 ((u_int32_t)(src)\
29795 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__MODIFY(dst, src) \
29797 ~0x00000007U) | ((u_int32_t)(src) &\
29799 #define MAC_PCU_SELF_GEN_DEFAULT__MMSS__VERIFY(src) \
29800 (!(((u_int32_t)(src)\
29807 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__READ(src) \
29808 (((u_int32_t)(src)\
29810 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__WRITE(src) \
29811 (((u_int32_t)(src)\
29813 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__MODIFY(dst, src) \
29815 ~0x00000018U) | (((u_int32_t)(src) <<\
29817 #define MAC_PCU_SELF_GEN_DEFAULT__CEC__VERIFY(src) \
29818 (!((((u_int32_t)(src)\
29825 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__READ(src) \
29826 (((u_int32_t)(src)\
29828 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__WRITE(src) \
29829 (((u_int32_t)(src)\
29831 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__MODIFY(dst, src) \
29833 ~0x00000020U) | (((u_int32_t)(src) <<\
29835 #define MAC_PCU_SELF_GEN_DEFAULT__STAGGER_SOUNDING__VERIFY(src) \
29836 (!((((u_int32_t)(src)\
29862 #define MAC_PCU_ADDR1_MASK_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
29863 #define MAC_PCU_ADDR1_MASK_L32__VALUE__WRITE(src) \
29864 ((u_int32_t)(src)\
29866 #define MAC_PCU_ADDR1_MASK_L32__VALUE__MODIFY(dst, src) \
29868 ~0xffffffffU) | ((u_int32_t)(src) &\
29870 #define MAC_PCU_ADDR1_MASK_L32__VALUE__VERIFY(src) \
29871 (!(((u_int32_t)(src)\
29891 #define MAC_PCU_ADDR1_MASK_U16__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU
29892 #define MAC_PCU_ADDR1_MASK_U16__VALUE__WRITE(src) \
29893 ((u_int32_t)(src)\
29895 #define MAC_PCU_ADDR1_MASK_U16__VALUE__MODIFY(dst, src) \
29897 ~0x0000ffffU) | ((u_int32_t)(src) &\
29899 #define MAC_PCU_ADDR1_MASK_U16__VALUE__VERIFY(src) \
29900 (!(((u_int32_t)(src)\
29920 #define MAC_PCU_TPC__ACK_PWR__READ(src) (u_int32_t)(src) & 0x0000003fU
29921 #define MAC_PCU_TPC__ACK_PWR__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
29922 #define MAC_PCU_TPC__ACK_PWR__MODIFY(dst, src) \
29924 ~0x0000003fU) | ((u_int32_t)(src) &\
29926 #define MAC_PCU_TPC__ACK_PWR__VERIFY(src) \
29927 (!(((u_int32_t)(src)\
29934 #define MAC_PCU_TPC__CTS_PWR__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8)
29935 #define MAC_PCU_TPC__CTS_PWR__WRITE(src) \
29936 (((u_int32_t)(src)\
29938 #define MAC_PCU_TPC__CTS_PWR__MODIFY(dst, src) \
29940 ~0x00003f00U) | (((u_int32_t)(src) <<\
29942 #define MAC_PCU_TPC__CTS_PWR__VERIFY(src) \
29943 (!((((u_int32_t)(src)\
29950 #define MAC_PCU_TPC__CHIRP_PWR__READ(src) \
29951 (((u_int32_t)(src)\
29953 #define MAC_PCU_TPC__CHIRP_PWR__WRITE(src) \
29954 (((u_int32_t)(src)\
29956 #define MAC_PCU_TPC__CHIRP_PWR__MODIFY(dst, src) \
29958 ~0x003f0000U) | (((u_int32_t)(src) <<\
29960 #define MAC_PCU_TPC__CHIRP_PWR__VERIFY(src) \
29961 (!((((u_int32_t)(src)\
29968 #define MAC_PCU_TPC__RPT_PWR__READ(src) \
29969 (((u_int32_t)(src)\
29971 #define MAC_PCU_TPC__RPT_PWR__WRITE(src) \
29972 (((u_int32_t)(src)\
29974 #define MAC_PCU_TPC__RPT_PWR__MODIFY(dst, src) \
29976 ~0x3f000000U) | (((u_int32_t)(src) <<\
29978 #define MAC_PCU_TPC__RPT_PWR__VERIFY(src) \
29979 (!((((u_int32_t)(src)\
29999 #define MAC_PCU_TX_FRAME_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
30000 #define MAC_PCU_TX_FRAME_CNT__VALUE__WRITE(src) \
30001 ((u_int32_t)(src)\
30003 #define MAC_PCU_TX_FRAME_CNT__VALUE__MODIFY(dst, src) \
30005 ~0xffffffffU) | ((u_int32_t)(src) &\
30007 #define MAC_PCU_TX_FRAME_CNT__VALUE__VERIFY(src) \
30008 (!(((u_int32_t)(src)\
30028 #define MAC_PCU_RX_FRAME_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
30029 #define MAC_PCU_RX_FRAME_CNT__VALUE__WRITE(src) \
30030 ((u_int32_t)(src)\
30032 #define MAC_PCU_RX_FRAME_CNT__VALUE__MODIFY(dst, src) \
30034 ~0xffffffffU) | ((u_int32_t)(src) &\
30036 #define MAC_PCU_RX_FRAME_CNT__VALUE__VERIFY(src) \
30037 (!(((u_int32_t)(src)\
30057 #define MAC_PCU_RX_CLEAR_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
30058 #define MAC_PCU_RX_CLEAR_CNT__VALUE__WRITE(src) \
30059 ((u_int32_t)(src)\
30061 #define MAC_PCU_RX_CLEAR_CNT__VALUE__MODIFY(dst, src) \
30063 ~0xffffffffU) | ((u_int32_t)(src) &\
30065 #define MAC_PCU_RX_CLEAR_CNT__VALUE__VERIFY(src) \
30066 (!(((u_int32_t)(src)\
30086 #define MAC_PCU_CYCLE_CNT__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
30087 #define MAC_PCU_CYCLE_CNT__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
30088 #define MAC_PCU_CYCLE_CNT__VALUE__MODIFY(dst, src) \
30090 ~0xffffffffU) | ((u_int32_t)(src) &\
30092 #define MAC_PCU_CYCLE_CNT__VALUE__VERIFY(src) \
30093 (!(((u_int32_t)(src)\
30113 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__READ(src) \
30114 (((u_int32_t)(src)\
30116 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__WRITE(src) \
30117 (((u_int32_t)(src)\
30119 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__MODIFY(dst, src) \
30121 ~0x00020000U) | (((u_int32_t)(src) <<\
30123 #define MAC_PCU_QUIET_TIME_1__ACK_CTS_ENABLE__VERIFY(src) \
30124 (!((((u_int32_t)(src)\
30150 #define MAC_PCU_QUIET_TIME_2__DURATION__READ(src) \
30151 (((u_int32_t)(src)\
30153 #define MAC_PCU_QUIET_TIME_2__DURATION__WRITE(src) \
30154 (((u_int32_t)(src)\
30156 #define MAC_PCU_QUIET_TIME_2__DURATION__MODIFY(dst, src) \
30158 ~0xffff0000U) | (((u_int32_t)(src) <<\
30160 #define MAC_PCU_QUIET_TIME_2__DURATION__VERIFY(src) \
30161 (!((((u_int32_t)(src)\
30181 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__READ(src) \
30182 (u_int32_t)(src)\
30184 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__WRITE(src) \
30185 ((u_int32_t)(src)\
30187 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__MODIFY(dst, src) \
30189 ~0x0000000fU) | ((u_int32_t)(src) &\
30191 #define MAC_PCU_QOS_NO_ACK__TWO_BIT_VALUES__VERIFY(src) \
30192 (!(((u_int32_t)(src)\
30199 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__READ(src) \
30200 (((u_int32_t)(src)\
30202 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__WRITE(src) \
30203 (((u_int32_t)(src)\
30205 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__MODIFY(dst, src) \
30207 ~0x00000070U) | (((u_int32_t)(src) <<\
30209 #define MAC_PCU_QOS_NO_ACK__BIT_OFFSET__VERIFY(src) \
30210 (!((((u_int32_t)(src)\
30217 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__READ(src) \
30218 (((u_int32_t)(src)\
30220 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__WRITE(src) \
30221 (((u_int32_t)(src)\
30223 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__MODIFY(dst, src) \
30225 ~0x00000180U) | (((u_int32_t)(src) <<\
30227 #define MAC_PCU_QOS_NO_ACK__BYTE_OFFSET__VERIFY(src) \
30228 (!((((u_int32_t)(src)\
30248 #define MAC_PCU_PHY_ERROR_MASK__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
30249 #define MAC_PCU_PHY_ERROR_MASK__VALUE__WRITE(src) \
30250 ((u_int32_t)(src)\
30252 #define MAC_PCU_PHY_ERROR_MASK__VALUE__MODIFY(dst, src) \
30254 ~0xffffffffU) | ((u_int32_t)(src) &\
30256 #define MAC_PCU_PHY_ERROR_MASK__VALUE__VERIFY(src) \
30257 (!(((u_int32_t)(src)\
30277 #define MAC_PCU_XRLAT__VALUE__READ(src) (u_int32_t)(src) & 0x00000fffU
30278 #define MAC_PCU_XRLAT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x00000fffU)
30279 #define MAC_PCU_XRLAT__VALUE__MODIFY(dst, src) \
30281 ~0x00000fffU) | ((u_int32_t)(src) &\
30283 #define MAC_PCU_XRLAT__VALUE__VERIFY(src) \
30284 (!(((u_int32_t)(src)\
30304 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__READ(src) \
30305 (u_int32_t)(src)\
30307 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__WRITE(src) \
30308 ((u_int32_t)(src)\
30310 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__MODIFY(dst, src) \
30312 ~0x000007ffU) | ((u_int32_t)(src) &\
30314 #define MAC_PCU_RXBUF__HIGH_PRIORITY_THRSHD__VERIFY(src) \
30315 (!(((u_int32_t)(src)\
30322 #define MAC_PCU_RXBUF__REG_RD_ENABLE__READ(src) \
30323 (((u_int32_t)(src)\
30325 #define MAC_PCU_RXBUF__REG_RD_ENABLE__WRITE(src) \
30326 (((u_int32_t)(src)\
30328 #define MAC_PCU_RXBUF__REG_RD_ENABLE__MODIFY(dst, src) \
30330 ~0x00000800U) | (((u_int32_t)(src) <<\
30332 #define MAC_PCU_RXBUF__REG_RD_ENABLE__VERIFY(src) \
30333 (!((((u_int32_t)(src)\
30359 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__READ(src) \
30360 (u_int32_t)(src)\
30362 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__WRITE(src) \
30363 ((u_int32_t)(src)\
30365 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__MODIFY(dst, src) \
30367 ~0x00000003U) | ((u_int32_t)(src) &\
30369 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_0__VERIFY(src) \
30370 (!(((u_int32_t)(src)\
30377 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__READ(src) \
30378 (((u_int32_t)(src)\
30380 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__WRITE(src) \
30381 (((u_int32_t)(src)\
30383 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__MODIFY(dst, src) \
30385 ~0x0000000cU) | (((u_int32_t)(src) <<\
30387 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_1__VERIFY(src) \
30388 (!((((u_int32_t)(src)\
30395 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__READ(src) \
30396 (((u_int32_t)(src)\
30398 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__WRITE(src) \
30399 (((u_int32_t)(src)\
30401 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__MODIFY(dst, src) \
30403 ~0x00000030U) | (((u_int32_t)(src) <<\
30405 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_2__VERIFY(src) \
30406 (!((((u_int32_t)(src)\
30413 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__READ(src) \
30414 (((u_int32_t)(src)\
30416 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__WRITE(src) \
30417 (((u_int32_t)(src)\
30419 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__MODIFY(dst, src) \
30421 ~0x000000c0U) | (((u_int32_t)(src) <<\
30423 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_3__VERIFY(src) \
30424 (!((((u_int32_t)(src)\
30431 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__READ(src) \
30432 (((u_int32_t)(src)\
30434 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__WRITE(src) \
30435 (((u_int32_t)(src)\
30437 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__MODIFY(dst, src) \
30439 ~0x00000300U) | (((u_int32_t)(src) <<\
30441 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_4__VERIFY(src) \
30442 (!((((u_int32_t)(src)\
30449 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__READ(src) \
30450 (((u_int32_t)(src)\
30452 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__WRITE(src) \
30453 (((u_int32_t)(src)\
30455 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__MODIFY(dst, src) \
30457 ~0x00000c00U) | (((u_int32_t)(src) <<\
30459 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_5__VERIFY(src) \
30460 (!((((u_int32_t)(src)\
30467 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__READ(src) \
30468 (((u_int32_t)(src)\
30470 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__WRITE(src) \
30471 (((u_int32_t)(src)\
30473 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__MODIFY(dst, src) \
30475 ~0x00003000U) | (((u_int32_t)(src) <<\
30477 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_6__VERIFY(src) \
30478 (!((((u_int32_t)(src)\
30485 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__READ(src) \
30486 (((u_int32_t)(src)\
30488 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__WRITE(src) \
30489 (((u_int32_t)(src)\
30491 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__MODIFY(dst, src) \
30493 ~0x0000c000U) | (((u_int32_t)(src) <<\
30495 #define MAC_PCU_MIC_QOS_CONTROL__VALUE_7__VERIFY(src) \
30496 (!((((u_int32_t)(src)\
30503 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__READ(src) \
30504 (((u_int32_t)(src)\
30506 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__WRITE(src) \
30507 (((u_int32_t)(src)\
30509 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__MODIFY(dst, src) \
30511 ~0x00010000U) | (((u_int32_t)(src) <<\
30513 #define MAC_PCU_MIC_QOS_CONTROL__ENABLE__VERIFY(src) \
30514 (!((((u_int32_t)(src)\
30540 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__READ(src) \
30541 (u_int32_t)(src)\
30543 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__WRITE(src) \
30544 ((u_int32_t)(src)\
30546 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__MODIFY(dst, src) \
30548 ~0x0000000fU) | ((u_int32_t)(src) &\
30550 #define MAC_PCU_MIC_QOS_SELECT__VALUE_0__VERIFY(src) \
30551 (!(((u_int32_t)(src)\
30558 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__READ(src) \
30559 (((u_int32_t)(src)\
30561 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__WRITE(src) \
30562 (((u_int32_t)(src)\
30564 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__MODIFY(dst, src) \
30566 ~0x000000f0U) | (((u_int32_t)(src) <<\
30568 #define MAC_PCU_MIC_QOS_SELECT__VALUE_1__VERIFY(src) \
30569 (!((((u_int32_t)(src)\
30576 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__READ(src) \
30577 (((u_int32_t)(src)\
30579 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__WRITE(src) \
30580 (((u_int32_t)(src)\
30582 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__MODIFY(dst, src) \
30584 ~0x00000f00U) | (((u_int32_t)(src) <<\
30586 #define MAC_PCU_MIC_QOS_SELECT__VALUE_2__VERIFY(src) \
30587 (!((((u_int32_t)(src)\
30594 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__READ(src) \
30595 (((u_int32_t)(src)\
30597 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__WRITE(src) \
30598 (((u_int32_t)(src)\
30600 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__MODIFY(dst, src) \
30602 ~0x0000f000U) | (((u_int32_t)(src) <<\
30604 #define MAC_PCU_MIC_QOS_SELECT__VALUE_3__VERIFY(src) \
30605 (!((((u_int32_t)(src)\
30612 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__READ(src) \
30613 (((u_int32_t)(src)\
30615 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__WRITE(src) \
30616 (((u_int32_t)(src)\
30618 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__MODIFY(dst, src) \
30620 ~0x000f0000U) | (((u_int32_t)(src) <<\
30622 #define MAC_PCU_MIC_QOS_SELECT__VALUE_4__VERIFY(src) \
30623 (!((((u_int32_t)(src)\
30630 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__READ(src) \
30631 (((u_int32_t)(src)\
30633 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__WRITE(src) \
30634 (((u_int32_t)(src)\
30636 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__MODIFY(dst, src) \
30638 ~0x00f00000U) | (((u_int32_t)(src) <<\
30640 #define MAC_PCU_MIC_QOS_SELECT__VALUE_5__VERIFY(src) \
30641 (!((((u_int32_t)(src)\
30648 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__READ(src) \
30649 (((u_int32_t)(src)\
30651 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__WRITE(src) \
30652 (((u_int32_t)(src)\
30654 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__MODIFY(dst, src) \
30656 ~0x0f000000U) | (((u_int32_t)(src) <<\
30658 #define MAC_PCU_MIC_QOS_SELECT__VALUE_6__VERIFY(src) \
30659 (!((((u_int32_t)(src)\
30666 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__READ(src) \
30667 (((u_int32_t)(src)\
30669 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__WRITE(src) \
30670 (((u_int32_t)(src)\
30672 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__MODIFY(dst, src) \
30674 ~0xf0000000U) | (((u_int32_t)(src) <<\
30676 #define MAC_PCU_MIC_QOS_SELECT__VALUE_7__VERIFY(src) \
30677 (!((((u_int32_t)(src)\
30697 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__READ(src) \
30698 (u_int32_t)(src)\
30700 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__WRITE(src) \
30701 ((u_int32_t)(src)\
30703 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__MODIFY(dst, src) \
30705 ~0x00000001U) | ((u_int32_t)(src) &\
30707 #define MAC_PCU_MISC_MODE__BSSID_MATCH_FORCE__VERIFY(src) \
30708 (!(((u_int32_t)(src)\
30721 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__READ(src) \
30722 (((u_int32_t)(src)\
30724 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__WRITE(src) \
30725 (((u_int32_t)(src)\
30727 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__MODIFY(dst, src) \
30729 ~0x00000002U) | (((u_int32_t)(src) <<\
30731 #define MAC_PCU_MISC_MODE__DEBUG_MODE_AD__VERIFY(src) \
30732 (!((((u_int32_t)(src)\
30745 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__READ(src) \
30746 (((u_int32_t)(src)\
30748 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__WRITE(src) \
30749 (((u_int32_t)(src)\
30751 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__MODIFY(dst, src) \
30753 ~0x00000004U) | (((u_int32_t)(src) <<\
30755 #define MAC_PCU_MISC_MODE__MIC_NEW_LOCATION_ENABLE__VERIFY(src) \
30756 (!((((u_int32_t)(src)\
30769 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__READ(src) \
30770 (((u_int32_t)(src)\
30772 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__WRITE(src) \
30773 (((u_int32_t)(src)\
30775 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__MODIFY(dst, src) \
30777 ~0x00000008U) | (((u_int32_t)(src) <<\
30779 #define MAC_PCU_MISC_MODE__TX_ADD_TSF__VERIFY(src) \
30780 (!((((u_int32_t)(src)\
30793 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__READ(src) \
30794 (((u_int32_t)(src)\
30796 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__WRITE(src) \
30797 (((u_int32_t)(src)\
30799 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__MODIFY(dst, src) \
30801 ~0x00000010U) | (((u_int32_t)(src) <<\
30803 #define MAC_PCU_MISC_MODE__CCK_SIFS_MODE__VERIFY(src) \
30804 (!((((u_int32_t)(src)\
30817 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__READ(src) \
30818 (((u_int32_t)(src)\
30820 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__WRITE(src) \
30821 (((u_int32_t)(src)\
30823 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__MODIFY(dst, src) \
30825 ~0x00000020U) | (((u_int32_t)(src) <<\
30827 #define MAC_PCU_MISC_MODE__RXSM2SVD_PRE_RST__VERIFY(src) \
30828 (!((((u_int32_t)(src)\
30841 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__READ(src) \
30842 (((u_int32_t)(src)\
30844 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__WRITE(src) \
30845 (((u_int32_t)(src)\
30847 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__MODIFY(dst, src) \
30849 ~0x00000040U) | (((u_int32_t)(src) <<\
30851 #define MAC_PCU_MISC_MODE__RCV_DELAY_SOUNDING_IM_TXBF__VERIFY(src) \
30852 (!((((u_int32_t)(src)\
30865 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__READ(src) \
30866 (((u_int32_t)(src)\
30868 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__WRITE(src) \
30869 (((u_int32_t)(src)\
30871 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__MODIFY(dst, src) \
30873 ~0x00000200U) | (((u_int32_t)(src) <<\
30875 #define MAC_PCU_MISC_MODE__DEBUG_MODE_BA_BITMAP__VERIFY(src) \
30876 (!((((u_int32_t)(src)\
30889 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__READ(src) \
30890 (((u_int32_t)(src)\
30892 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__WRITE(src) \
30893 (((u_int32_t)(src)\
30895 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__MODIFY(dst, src) \
30897 ~0x00000400U) | (((u_int32_t)(src) <<\
30899 #define MAC_PCU_MISC_MODE__DEBUG_MODE_SIFS__VERIFY(src) \
30900 (!((((u_int32_t)(src)\
30913 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__READ(src) \
30914 (((u_int32_t)(src)\
30916 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__WRITE(src) \
30917 (((u_int32_t)(src)\
30919 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__MODIFY(dst, src) \
30921 ~0x00000800U) | (((u_int32_t)(src) <<\
30923 #define MAC_PCU_MISC_MODE__KC_RX_ANT_UPDATE__VERIFY(src) \
30924 (!((((u_int32_t)(src)\
30937 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__READ(src) \
30938 (((u_int32_t)(src)\
30940 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__WRITE(src) \
30941 (((u_int32_t)(src)\
30943 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__MODIFY(dst, src) \
30945 ~0x00001000U) | (((u_int32_t)(src) <<\
30947 #define MAC_PCU_MISC_MODE__TXOP_TBTT_LIMIT_ENABLE__VERIFY(src) \
30948 (!((((u_int32_t)(src)\
30961 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__READ(src) \
30962 (((u_int32_t)(src)\
30964 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__WRITE(src) \
30965 (((u_int32_t)(src)\
30967 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__MODIFY(dst, src) \
30969 ~0x00004000U) | (((u_int32_t)(src) <<\
30971 #define MAC_PCU_MISC_MODE__MISS_BEACON_IN_SLEEP__VERIFY(src) \
30972 (!((((u_int32_t)(src)\
30985 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__READ(src) \
30986 (((u_int32_t)(src)\
30988 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__WRITE(src) \
30989 (((u_int32_t)(src)\
30991 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__MODIFY(dst, src) \
30993 ~0x00040000U) | (((u_int32_t)(src) <<\
30995 #define MAC_PCU_MISC_MODE__FORCE_QUIET_COLLISION__VERIFY(src) \
30996 (!((((u_int32_t)(src)\
31009 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__READ(src) \
31010 (((u_int32_t)(src)\
31012 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__WRITE(src) \
31013 (((u_int32_t)(src)\
31015 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__MODIFY(dst, src) \
31017 ~0x00100000U) | (((u_int32_t)(src) <<\
31019 #define MAC_PCU_MISC_MODE__BT_ANT_PREVENTS_RX__VERIFY(src) \
31020 (!((((u_int32_t)(src)\
31033 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__READ(src) \
31034 (((u_int32_t)(src)\
31036 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__WRITE(src) \
31037 (((u_int32_t)(src)\
31039 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__MODIFY(dst, src) \
31041 ~0x00200000U) | (((u_int32_t)(src) <<\
31043 #define MAC_PCU_MISC_MODE__TBTT_PROTECT__VERIFY(src) \
31044 (!((((u_int32_t)(src)\
31057 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__READ(src) \
31058 (((u_int32_t)(src)\
31060 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__WRITE(src) \
31061 (((u_int32_t)(src)\
31063 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__MODIFY(dst, src) \
31065 ~0x00400000U) | (((u_int32_t)(src) <<\
31067 #define MAC_PCU_MISC_MODE__HCF_POLL_CANCELS_NAV__VERIFY(src) \
31068 (!((((u_int32_t)(src)\
31081 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__READ(src) \
31082 (((u_int32_t)(src)\
31084 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__WRITE(src) \
31085 (((u_int32_t)(src)\
31087 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__MODIFY(dst, src) \
31089 ~0x00800000U) | (((u_int32_t)(src) <<\
31091 #define MAC_PCU_MISC_MODE__RX_HCF_POLL_ENABLE__VERIFY(src) \
31092 (!((((u_int32_t)(src)\
31105 #define MAC_PCU_MISC_MODE__CLEAR_VMF__READ(src) \
31106 (((u_int32_t)(src)\
31108 #define MAC_PCU_MISC_MODE__CLEAR_VMF__WRITE(src) \
31109 (((u_int32_t)(src)\
31111 #define MAC_PCU_MISC_MODE__CLEAR_VMF__MODIFY(dst, src) \
31113 ~0x01000000U) | (((u_int32_t)(src) <<\
31115 #define MAC_PCU_MISC_MODE__CLEAR_VMF__VERIFY(src) \
31116 (!((((u_int32_t)(src)\
31129 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__READ(src) \
31130 (((u_int32_t)(src)\
31132 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__WRITE(src) \
31133 (((u_int32_t)(src)\
31135 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__MODIFY(dst, src) \
31137 ~0x02000000U) | (((u_int32_t)(src) <<\
31139 #define MAC_PCU_MISC_MODE__CLEAR_FIRST_HCF__VERIFY(src) \
31140 (!((((u_int32_t)(src)\
31153 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__READ(src) \
31154 (((u_int32_t)(src)\
31156 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__WRITE(src) \
31157 (((u_int32_t)(src)\
31159 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__MODIFY(dst, src) \
31161 ~0x04000000U) | (((u_int32_t)(src) <<\
31163 #define MAC_PCU_MISC_MODE__CLEAR_BA_VALID__VERIFY(src) \
31164 (!((((u_int32_t)(src)\
31177 #define MAC_PCU_MISC_MODE__SEL_EVM__READ(src) \
31178 (((u_int32_t)(src)\
31180 #define MAC_PCU_MISC_MODE__SEL_EVM__WRITE(src) \
31181 (((u_int32_t)(src)\
31183 #define MAC_PCU_MISC_MODE__SEL_EVM__MODIFY(dst, src) \
31185 ~0x08000000U) | (((u_int32_t)(src) <<\
31187 #define MAC_PCU_MISC_MODE__SEL_EVM__VERIFY(src) \
31188 (!((((u_int32_t)(src)\
31201 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__READ(src) \
31202 (((u_int32_t)(src)\
31204 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__WRITE(src) \
31205 (((u_int32_t)(src)\
31207 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__MODIFY(dst, src) \
31209 ~0x10000000U) | (((u_int32_t)(src) <<\
31211 #define MAC_PCU_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH__VERIFY(src) \
31212 (!((((u_int32_t)(src)\
31225 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__READ(src) \
31226 (((u_int32_t)(src)\
31228 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__WRITE(src) \
31229 (((u_int32_t)(src)\
31231 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__MODIFY(dst, src) \
31233 ~0x20000000U) | (((u_int32_t)(src) <<\
31235 #define MAC_PCU_MISC_MODE__USE_EOP_PTR_FOR_DMA_WR__VERIFY(src) \
31236 (!((((u_int32_t)(src)\
31249 #define MAC_PCU_MISC_MODE__DEBUG_MODE__READ(src) \
31250 (((u_int32_t)(src)\
31252 #define MAC_PCU_MISC_MODE__DEBUG_MODE__WRITE(src) \
31253 (((u_int32_t)(src)\
31255 #define MAC_PCU_MISC_MODE__DEBUG_MODE__MODIFY(dst, src) \
31257 ~0xc0000000U) | (((u_int32_t)(src) <<\
31259 #define MAC_PCU_MISC_MODE__DEBUG_MODE__VERIFY(src) \
31260 (!((((u_int32_t)(src)\
31280 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__READ(src) \
31281 (u_int32_t)(src)\
31283 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__WRITE(src) \
31284 ((u_int32_t)(src)\
31286 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__MODIFY(dst, src) \
31288 ~0x00ffffffU) | ((u_int32_t)(src) &\
31290 #define MAC_PCU_FILTER_OFDM_CNT__VALUE__VERIFY(src) \
31291 (!(((u_int32_t)(src)\
31311 #define MAC_PCU_FILTER_CCK_CNT__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU
31312 #define MAC_PCU_FILTER_CCK_CNT__VALUE__WRITE(src) \
31313 ((u_int32_t)(src)\
31315 #define MAC_PCU_FILTER_CCK_CNT__VALUE__MODIFY(dst, src) \
31317 ~0x00ffffffU) | ((u_int32_t)(src) &\
31319 #define MAC_PCU_FILTER_CCK_CNT__VALUE__VERIFY(src) \
31320 (!(((u_int32_t)(src)\
31340 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU
31341 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__WRITE(src) \
31342 ((u_int32_t)(src)\
31344 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__MODIFY(dst, src) \
31346 ~0x00ffffffU) | ((u_int32_t)(src) &\
31348 #define MAC_PCU_PHY_ERR_CNT_1__VALUE__VERIFY(src) \
31349 (!(((u_int32_t)(src)\
31369 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__READ(src) \
31370 (u_int32_t)(src)\
31372 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__WRITE(src) \
31373 ((u_int32_t)(src)\
31375 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__MODIFY(dst, src) \
31377 ~0xffffffffU) | ((u_int32_t)(src) &\
31379 #define MAC_PCU_PHY_ERR_CNT_1_MASK__VALUE__VERIFY(src) \
31380 (!(((u_int32_t)(src)\
31400 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU
31401 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__WRITE(src) \
31402 ((u_int32_t)(src)\
31404 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__MODIFY(dst, src) \
31406 ~0x00ffffffU) | ((u_int32_t)(src) &\
31408 #define MAC_PCU_PHY_ERR_CNT_2__VALUE__VERIFY(src) \
31409 (!(((u_int32_t)(src)\
31429 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__READ(src) \
31430 (u_int32_t)(src)\
31432 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__WRITE(src) \
31433 ((u_int32_t)(src)\
31435 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__MODIFY(dst, src) \
31437 ~0xffffffffU) | ((u_int32_t)(src) &\
31439 #define MAC_PCU_PHY_ERR_CNT_2_MASK__VALUE__VERIFY(src) \
31440 (!(((u_int32_t)(src)\
31460 #define MAC_PCU_TSF_THRESHOLD__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU
31461 #define MAC_PCU_TSF_THRESHOLD__VALUE__WRITE(src) \
31462 ((u_int32_t)(src)\
31464 #define MAC_PCU_TSF_THRESHOLD__VALUE__MODIFY(dst, src) \
31466 ~0x0000ffffU) | ((u_int32_t)(src) &\
31468 #define MAC_PCU_TSF_THRESHOLD__VALUE__VERIFY(src) \
31469 (!(((u_int32_t)(src)\
31489 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__READ(src) \
31490 (u_int32_t)(src)\
31492 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__WRITE(src) \
31493 ((u_int32_t)(src)\
31495 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__MODIFY(dst, src) \
31497 ~0xffffffffU) | ((u_int32_t)(src) &\
31499 #define MAC_PCU_PHY_ERROR_EIFS_MASK__VALUE__VERIFY(src) \
31500 (!(((u_int32_t)(src)\
31520 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__READ(src) (u_int32_t)(src) & 0x00ffffffU
31521 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__WRITE(src) \
31522 ((u_int32_t)(src)\
31524 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__MODIFY(dst, src) \
31526 ~0x00ffffffU) | ((u_int32_t)(src) &\
31528 #define MAC_PCU_PHY_ERR_CNT_3__VALUE__VERIFY(src) \
31529 (!(((u_int32_t)(src)\
31549 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__READ(src) \
31550 (u_int32_t)(src)\
31552 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__WRITE(src) \
31553 ((u_int32_t)(src)\
31555 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__MODIFY(dst, src) \
31557 ~0xffffffffU) | ((u_int32_t)(src) &\
31559 #define MAC_PCU_PHY_ERR_CNT_3_MASK__VALUE__VERIFY(src) \
31560 (!(((u_int32_t)(src)\
31580 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__READ(src) \
31581 (u_int32_t)(src)\
31583 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__WRITE(src) \
31584 ((u_int32_t)(src)\
31586 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__MODIFY(dst, src) \
31588 ~0x000000ffU) | ((u_int32_t)(src) &\
31590 #define MAC_PCU_BLUETOOTH_MODE__TIME_EXTEND__VERIFY(src) \
31591 (!(((u_int32_t)(src)\
31598 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__READ(src) \
31599 (((u_int32_t)(src)\
31601 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__WRITE(src) \
31602 (((u_int32_t)(src)\
31604 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__MODIFY(dst, src) \
31606 ~0x00000100U) | (((u_int32_t)(src) <<\
31608 #define MAC_PCU_BLUETOOTH_MODE__TX_STATE_EXTEND__VERIFY(src) \
31609 (!((((u_int32_t)(src)\
31622 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__READ(src) \
31623 (((u_int32_t)(src)\
31625 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__WRITE(src) \
31626 (((u_int32_t)(src)\
31628 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__MODIFY(dst, src) \
31630 ~0x00000200U) | (((u_int32_t)(src) <<\
31632 #define MAC_PCU_BLUETOOTH_MODE__TX_FRAME_EXTEND__VERIFY(src) \
31633 (!((((u_int32_t)(src)\
31646 #define MAC_PCU_BLUETOOTH_MODE__MODE__READ(src) \
31647 (((u_int32_t)(src)\
31649 #define MAC_PCU_BLUETOOTH_MODE__MODE__WRITE(src) \
31650 (((u_int32_t)(src)\
31652 #define MAC_PCU_BLUETOOTH_MODE__MODE__MODIFY(dst, src) \
31654 ~0x00000c00U) | (((u_int32_t)(src) <<\
31656 #define MAC_PCU_BLUETOOTH_MODE__MODE__VERIFY(src) \
31657 (!((((u_int32_t)(src)\
31664 #define MAC_PCU_BLUETOOTH_MODE__QUIET__READ(src) \
31665 (((u_int32_t)(src)\
31667 #define MAC_PCU_BLUETOOTH_MODE__QUIET__WRITE(src) \
31668 (((u_int32_t)(src)\
31670 #define MAC_PCU_BLUETOOTH_MODE__QUIET__MODIFY(dst, src) \
31672 ~0x00001000U) | (((u_int32_t)(src) <<\
31674 #define MAC_PCU_BLUETOOTH_MODE__QUIET__VERIFY(src) \
31675 (!((((u_int32_t)(src)\
31688 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__READ(src) \
31689 (((u_int32_t)(src)\
31691 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__WRITE(src) \
31692 (((u_int32_t)(src)\
31694 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__MODIFY(dst, src) \
31696 ~0x0001e000U) | (((u_int32_t)(src) <<\
31698 #define MAC_PCU_BLUETOOTH_MODE__QCU_THRESH__VERIFY(src) \
31699 (!((((u_int32_t)(src)\
31706 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__READ(src) \
31707 (((u_int32_t)(src)\
31709 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__WRITE(src) \
31710 (((u_int32_t)(src)\
31712 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__MODIFY(dst, src) \
31714 ~0x00020000U) | (((u_int32_t)(src) <<\
31716 #define MAC_PCU_BLUETOOTH_MODE__RX_CLEAR_POLARITY__VERIFY(src) \
31717 (!((((u_int32_t)(src)\
31730 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__READ(src) \
31731 (((u_int32_t)(src)\
31733 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__WRITE(src) \
31734 (((u_int32_t)(src)\
31736 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__MODIFY(dst, src) \
31738 ~0x00fc0000U) | (((u_int32_t)(src) <<\
31740 #define MAC_PCU_BLUETOOTH_MODE__PRIORITY_TIME__VERIFY(src) \
31741 (!((((u_int32_t)(src)\
31748 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__READ(src) \
31749 (((u_int32_t)(src)\
31751 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__WRITE(src) \
31752 (((u_int32_t)(src)\
31754 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__MODIFY(dst, src) \
31756 ~0xff000000U) | (((u_int32_t)(src) <<\
31758 #define MAC_PCU_BLUETOOTH_MODE__FIRST_SLOT_TIME__VERIFY(src) \
31759 (!((((u_int32_t)(src)\
31779 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__READ(src) \
31780 (u_int32_t)(src)\
31782 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__WRITE(src) \
31783 ((u_int32_t)(src)\
31785 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__MODIFY(dst, src) \
31787 ~0xffffffffU) | ((u_int32_t)(src) &\
31789 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS0__VALUE__VERIFY(src) \
31790 (!(((u_int32_t)(src)\
31810 #define MAC_PCU_HCF_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000ffffU
31811 #define MAC_PCU_HCF_TIMEOUT__VALUE__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
31812 #define MAC_PCU_HCF_TIMEOUT__VALUE__MODIFY(dst, src) \
31814 ~0x0000ffffU) | ((u_int32_t)(src) &\
31816 #define MAC_PCU_HCF_TIMEOUT__VALUE__VERIFY(src) \
31817 (!(((u_int32_t)(src)\
31837 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__READ(src) \
31838 (u_int32_t)(src)\
31840 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__WRITE(src) \
31841 ((u_int32_t)(src)\
31843 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__MODIFY(dst, src) \
31845 ~0x000000ffU) | ((u_int32_t)(src) &\
31847 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_THRESH__VERIFY(src) \
31848 (!(((u_int32_t)(src)\
31855 #define MAC_PCU_BLUETOOTH_MODE2__BCN_MISS_CNT__READ(src) \
31856 (((u_int32_t)(src)\
31863 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__READ(src) \
31864 (((u_int32_t)(src)\
31866 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__WRITE(src) \
31867 (((u_int32_t)(src)\
31869 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__MODIFY(dst, src) \
31871 ~0x00010000U) | (((u_int32_t)(src) <<\
31873 #define MAC_PCU_BLUETOOTH_MODE2__HOLD_RX_CLEAR__VERIFY(src) \
31874 (!((((u_int32_t)(src)\
31887 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__READ(src) \
31888 (((u_int32_t)(src)\
31890 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__WRITE(src) \
31891 (((u_int32_t)(src)\
31893 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__MODIFY(dst, src) \
31895 ~0x00020000U) | (((u_int32_t)(src) <<\
31897 #define MAC_PCU_BLUETOOTH_MODE2__SLEEP_ALLOW_BT_ACCESS__VERIFY(src) \
31898 (!((((u_int32_t)(src)\
31911 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__READ(src) \
31912 (((u_int32_t)(src)\
31914 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__WRITE(src) \
31915 (((u_int32_t)(src)\
31917 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__MODIFY(dst, src) \
31919 ~0x00080000U) | (((u_int32_t)(src) <<\
31921 #define MAC_PCU_BLUETOOTH_MODE2__PROTECT_BT_AFTER_WAKEUP__VERIFY(src) \
31922 (!((((u_int32_t)(src)\
31935 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__READ(src) \
31936 (((u_int32_t)(src)\
31938 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__WRITE(src) \
31939 (((u_int32_t)(src)\
31941 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__MODIFY(dst, src) \
31943 ~0x00100000U) | (((u_int32_t)(src) <<\
31945 #define MAC_PCU_BLUETOOTH_MODE2__DISABLE_BT_ANT__VERIFY(src) \
31946 (!((((u_int32_t)(src)\
31959 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__READ(src) \
31960 (((u_int32_t)(src)\
31962 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__WRITE(src) \
31963 (((u_int32_t)(src)\
31965 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__MODIFY(dst, src) \
31967 ~0x00200000U) | (((u_int32_t)(src) <<\
31969 #define MAC_PCU_BLUETOOTH_MODE2__QUIET_2_WIRE__VERIFY(src) \
31970 (!((((u_int32_t)(src)\
31983 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__READ(src) \
31984 (((u_int32_t)(src)\
31986 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__WRITE(src) \
31987 (((u_int32_t)(src)\
31989 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__MODIFY(dst, src) \
31991 ~0x00c00000U) | (((u_int32_t)(src) <<\
31993 #define MAC_PCU_BLUETOOTH_MODE2__WL_ACTIVE_MODE__VERIFY(src) \
31994 (!((((u_int32_t)(src)\
32001 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__READ(src) \
32002 (((u_int32_t)(src)\
32004 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__WRITE(src) \
32005 (((u_int32_t)(src)\
32007 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__MODIFY(dst, src) \
32009 ~0x01000000U) | (((u_int32_t)(src) <<\
32011 #define MAC_PCU_BLUETOOTH_MODE2__WL_TXRX_SEPARATE__VERIFY(src) \
32012 (!((((u_int32_t)(src)\
32025 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__READ(src) \
32026 (((u_int32_t)(src)\
32028 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__WRITE(src) \
32029 (((u_int32_t)(src)\
32031 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__MODIFY(dst, src) \
32033 ~0x02000000U) | (((u_int32_t)(src) <<\
32035 #define MAC_PCU_BLUETOOTH_MODE2__RS_DISCARD_EXTEND__VERIFY(src) \
32036 (!((((u_int32_t)(src)\
32049 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__READ(src) \
32050 (((u_int32_t)(src)\
32052 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__WRITE(src) \
32053 (((u_int32_t)(src)\
32055 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__MODIFY(dst, src) \
32057 ~0x0c000000U) | (((u_int32_t)(src) <<\
32059 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_ACTIVE_CTRL__VERIFY(src) \
32060 (!((((u_int32_t)(src)\
32067 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__READ(src) \
32068 (((u_int32_t)(src)\
32070 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__WRITE(src) \
32071 (((u_int32_t)(src)\
32073 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__MODIFY(dst, src) \
32075 ~0x30000000U) | (((u_int32_t)(src) <<\
32077 #define MAC_PCU_BLUETOOTH_MODE2__TSF_BT_PRIORITY_CTRL__VERIFY(src) \
32078 (!((((u_int32_t)(src)\
32085 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__READ(src) \
32086 (((u_int32_t)(src)\
32088 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__WRITE(src) \
32089 (((u_int32_t)(src)\
32091 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__MODIFY(dst, src) \
32093 ~0x40000000U) | (((u_int32_t)(src) <<\
32095 #define MAC_PCU_BLUETOOTH_MODE2__INTERRUPT_ENABLE__VERIFY(src) \
32096 (!((((u_int32_t)(src)\
32109 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__READ(src) \
32110 (((u_int32_t)(src)\
32112 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__WRITE(src) \
32113 (((u_int32_t)(src)\
32115 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__MODIFY(dst, src) \
32117 ~0x80000000U) | (((u_int32_t)(src) <<\
32119 #define MAC_PCU_BLUETOOTH_MODE2__PHY_ERR_BT_COLL_ENABLE__VERIFY(src) \
32120 (!((((u_int32_t)(src)\
32146 #define MAC_PCU_GENERIC_TIMERS2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
32147 #define MAC_PCU_GENERIC_TIMERS2__DATA__WRITE(src) \
32148 ((u_int32_t)(src)\
32150 #define MAC_PCU_GENERIC_TIMERS2__DATA__MODIFY(dst, src) \
32152 ~0xffffffffU) | ((u_int32_t)(src) &\
32154 #define MAC_PCU_GENERIC_TIMERS2__DATA__VERIFY(src) \
32155 (!(((u_int32_t)(src)\
32175 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__READ(src) \
32176 (u_int32_t)(src)\
32178 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__WRITE(src) \
32179 ((u_int32_t)(src)\
32181 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__MODIFY(dst, src) \
32183 ~0x000000ffU) | ((u_int32_t)(src) &\
32185 #define MAC_PCU_GENERIC_TIMERS2_MODE__ENABLE__VERIFY(src) \
32186 (!(((u_int32_t)(src)\
32193 #define MAC_PCU_GENERIC_TIMERS2_MODE__OVERFLOW_INDEX__READ(src) \
32194 (((u_int32_t)(src)\
32214 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__READ(src) \
32215 (u_int32_t)(src)\
32217 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__WRITE(src) \
32218 ((u_int32_t)(src)\
32220 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__MODIFY(dst, src) \
32222 ~0xffffffffU) | ((u_int32_t)(src) &\
32224 #define MAC_PCU_BLUETOOTH_WL_WEIGHTS1__VALUE__VERIFY(src) \
32225 (!(((u_int32_t)(src)\
32245 #define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE__VALUE__READ(src) \
32246 (u_int32_t)(src)\
32265 #define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY__VALUE__READ(src) \
32266 (u_int32_t)(src)\
32285 #define MAC_PCU_TXSIFS__SIFS_TIME__READ(src) (u_int32_t)(src) & 0x000000ffU
32286 #define MAC_PCU_TXSIFS__SIFS_TIME__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
32287 #define MAC_PCU_TXSIFS__SIFS_TIME__MODIFY(dst, src) \
32289 ~0x000000ffU) | ((u_int32_t)(src) &\
32291 #define MAC_PCU_TXSIFS__SIFS_TIME__VERIFY(src) \
32292 (!(((u_int32_t)(src)\
32299 #define MAC_PCU_TXSIFS__TX_LATENCY__READ(src) \
32300 (((u_int32_t)(src)\
32302 #define MAC_PCU_TXSIFS__TX_LATENCY__WRITE(src) \
32303 (((u_int32_t)(src)\
32305 #define MAC_PCU_TXSIFS__TX_LATENCY__MODIFY(dst, src) \
32307 ~0x00000f00U) | (((u_int32_t)(src) <<\
32309 #define MAC_PCU_TXSIFS__TX_LATENCY__VERIFY(src) \
32310 (!((((u_int32_t)(src)\
32317 #define MAC_PCU_TXSIFS__ACK_SHIFT__READ(src) \
32318 (((u_int32_t)(src)\
32320 #define MAC_PCU_TXSIFS__ACK_SHIFT__WRITE(src) \
32321 (((u_int32_t)(src)\
32323 #define MAC_PCU_TXSIFS__ACK_SHIFT__MODIFY(dst, src) \
32325 ~0x00007000U) | (((u_int32_t)(src) <<\
32327 #define MAC_PCU_TXSIFS__ACK_SHIFT__VERIFY(src) \
32328 (!((((u_int32_t)(src)\
32348 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__READ(src) \
32349 (u_int32_t)(src)\
32351 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__WRITE(src) \
32352 ((u_int32_t)(src)\
32354 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__MODIFY(dst, src) \
32356 ~0x000000ffU) | ((u_int32_t)(src) &\
32358 #define MAC_PCU_BLUETOOTH_MODE3__WL_ACTIVE_TIME__VERIFY(src) \
32359 (!(((u_int32_t)(src)\
32366 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__READ(src) \
32367 (((u_int32_t)(src)\
32369 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__WRITE(src) \
32370 (((u_int32_t)(src)\
32372 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__MODIFY(dst, src) \
32374 ~0x0000ff00U) | (((u_int32_t)(src) <<\
32376 #define MAC_PCU_BLUETOOTH_MODE3__WL_QC_TIME__VERIFY(src) \
32377 (!((((u_int32_t)(src)\
32384 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__READ(src) \
32385 (((u_int32_t)(src)\
32387 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__WRITE(src) \
32388 (((u_int32_t)(src)\
32390 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__MODIFY(dst, src) \
32392 ~0x000f0000U) | (((u_int32_t)(src) <<\
32394 #define MAC_PCU_BLUETOOTH_MODE3__ALLOW_CONCURRENT_ACCESS__VERIFY(src) \
32395 (!((((u_int32_t)(src)\
32402 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__READ(src) \
32403 (((u_int32_t)(src)\
32405 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__WRITE(src) \
32406 (((u_int32_t)(src)\
32408 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__MODIFY(dst, src) \
32410 ~0x00100000U) | (((u_int32_t)(src) <<\
32412 #define MAC_PCU_BLUETOOTH_MODE3__AGC_SATURATION_CNT_ENABLE__VERIFY(src) \
32413 (!((((u_int32_t)(src)\
32439 #define MAC_PCU_TXOP_X__VALUE__READ(src) (u_int32_t)(src) & 0x000000ffU
32440 #define MAC_PCU_TXOP_X__VALUE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
32441 #define MAC_PCU_TXOP_X__VALUE__MODIFY(dst, src) \
32443 ~0x000000ffU) | ((u_int32_t)(src) &\
32445 #define MAC_PCU_TXOP_X__VALUE__VERIFY(src) \
32446 (!(((u_int32_t)(src)\
32466 #define MAC_PCU_TXOP_0_3__VALUE_0__READ(src) (u_int32_t)(src) & 0x000000ffU
32467 #define MAC_PCU_TXOP_0_3__VALUE_0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
32468 #define MAC_PCU_TXOP_0_3__VALUE_0__MODIFY(dst, src) \
32470 ~0x000000ffU) | ((u_int32_t)(src) &\
32472 #define MAC_PCU_TXOP_0_3__VALUE_0__VERIFY(src) \
32473 (!(((u_int32_t)(src)\
32480 #define MAC_PCU_TXOP_0_3__VALUE_1__READ(src) \
32481 (((u_int32_t)(src)\
32483 #define MAC_PCU_TXOP_0_3__VALUE_1__WRITE(src) \
32484 (((u_int32_t)(src)\
32486 #define MAC_PCU_TXOP_0_3__VALUE_1__MODIFY(dst, src) \
32488 ~0x0000ff00U) | (((u_int32_t)(src) <<\
32490 #define MAC_PCU_TXOP_0_3__VALUE_1__VERIFY(src) \
32491 (!((((u_int32_t)(src)\
32498 #define MAC_PCU_TXOP_0_3__VALUE_2__READ(src) \
32499 (((u_int32_t)(src)\
32501 #define MAC_PCU_TXOP_0_3__VALUE_2__WRITE(src) \
32502 (((u_int32_t)(src)\
32504 #define MAC_PCU_TXOP_0_3__VALUE_2__MODIFY(dst, src) \
32506 ~0x00ff0000U) | (((u_int32_t)(src) <<\
32508 #define MAC_PCU_TXOP_0_3__VALUE_2__VERIFY(src) \
32509 (!((((u_int32_t)(src)\
32516 #define MAC_PCU_TXOP_0_3__VALUE_3__READ(src) \
32517 (((u_int32_t)(src)\
32519 #define MAC_PCU_TXOP_0_3__VALUE_3__WRITE(src) \
32520 (((u_int32_t)(src)\
32522 #define MAC_PCU_TXOP_0_3__VALUE_3__MODIFY(dst, src) \
32524 ~0xff000000U) | (((u_int32_t)(src) <<\
32526 #define MAC_PCU_TXOP_0_3__VALUE_3__VERIFY(src) \
32527 (!((((u_int32_t)(src)\
32547 #define MAC_PCU_TXOP_4_7__VALUE_4__READ(src) (u_int32_t)(src) & 0x000000ffU
32548 #define MAC_PCU_TXOP_4_7__VALUE_4__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
32549 #define MAC_PCU_TXOP_4_7__VALUE_4__MODIFY(dst, src) \
32551 ~0x000000ffU) | ((u_int32_t)(src) &\
32553 #define MAC_PCU_TXOP_4_7__VALUE_4__VERIFY(src) \
32554 (!(((u_int32_t)(src)\
32561 #define MAC_PCU_TXOP_4_7__VALUE_5__READ(src) \
32562 (((u_int32_t)(src)\
32564 #define MAC_PCU_TXOP_4_7__VALUE_5__WRITE(src) \
32565 (((u_int32_t)(src)\
32567 #define MAC_PCU_TXOP_4_7__VALUE_5__MODIFY(dst, src) \
32569 ~0x0000ff00U) | (((u_int32_t)(src) <<\
32571 #define MAC_PCU_TXOP_4_7__VALUE_5__VERIFY(src) \
32572 (!((((u_int32_t)(src)\
32579 #define MAC_PCU_TXOP_4_7__VALUE_6__READ(src) \
32580 (((u_int32_t)(src)\
32582 #define MAC_PCU_TXOP_4_7__VALUE_6__WRITE(src) \
32583 (((u_int32_t)(src)\
32585 #define MAC_PCU_TXOP_4_7__VALUE_6__MODIFY(dst, src) \
32587 ~0x00ff0000U) | (((u_int32_t)(src) <<\
32589 #define MAC_PCU_TXOP_4_7__VALUE_6__VERIFY(src) \
32590 (!((((u_int32_t)(src)\
32597 #define MAC_PCU_TXOP_4_7__VALUE_7__READ(src) \
32598 (((u_int32_t)(src)\
32600 #define MAC_PCU_TXOP_4_7__VALUE_7__WRITE(src) \
32601 (((u_int32_t)(src)\
32603 #define MAC_PCU_TXOP_4_7__VALUE_7__MODIFY(dst, src) \
32605 ~0xff000000U) | (((u_int32_t)(src) <<\
32607 #define MAC_PCU_TXOP_4_7__VALUE_7__VERIFY(src) \
32608 (!((((u_int32_t)(src)\
32628 #define MAC_PCU_TXOP_8_11__VALUE_8__READ(src) (u_int32_t)(src) & 0x000000ffU
32629 #define MAC_PCU_TXOP_8_11__VALUE_8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
32630 #define MAC_PCU_TXOP_8_11__VALUE_8__MODIFY(dst, src) \
32632 ~0x000000ffU) | ((u_int32_t)(src) &\
32634 #define MAC_PCU_TXOP_8_11__VALUE_8__VERIFY(src) \
32635 (!(((u_int32_t)(src)\
32642 #define MAC_PCU_TXOP_8_11__VALUE_9__READ(src) \
32643 (((u_int32_t)(src)\
32645 #define MAC_PCU_TXOP_8_11__VALUE_9__WRITE(src) \
32646 (((u_int32_t)(src)\
32648 #define MAC_PCU_TXOP_8_11__VALUE_9__MODIFY(dst, src) \
32650 ~0x0000ff00U) | (((u_int32_t)(src) <<\
32652 #define MAC_PCU_TXOP_8_11__VALUE_9__VERIFY(src) \
32653 (!((((u_int32_t)(src)\
32660 #define MAC_PCU_TXOP_8_11__VALUE_10__READ(src) \
32661 (((u_int32_t)(src)\
32663 #define MAC_PCU_TXOP_8_11__VALUE_10__WRITE(src) \
32664 (((u_int32_t)(src)\
32666 #define MAC_PCU_TXOP_8_11__VALUE_10__MODIFY(dst, src) \
32668 ~0x00ff0000U) | (((u_int32_t)(src) <<\
32670 #define MAC_PCU_TXOP_8_11__VALUE_10__VERIFY(src) \
32671 (!((((u_int32_t)(src)\
32678 #define MAC_PCU_TXOP_8_11__VALUE_11__READ(src) \
32679 (((u_int32_t)(src)\
32681 #define MAC_PCU_TXOP_8_11__VALUE_11__WRITE(src) \
32682 (((u_int32_t)(src)\
32684 #define MAC_PCU_TXOP_8_11__VALUE_11__MODIFY(dst, src) \
32686 ~0xff000000U) | (((u_int32_t)(src) <<\
32688 #define MAC_PCU_TXOP_8_11__VALUE_11__VERIFY(src) \
32689 (!((((u_int32_t)(src)\
32709 #define MAC_PCU_TXOP_12_15__VALUE_12__READ(src) (u_int32_t)(src) & 0x000000ffU
32710 #define MAC_PCU_TXOP_12_15__VALUE_12__WRITE(src) \
32711 ((u_int32_t)(src)\
32713 #define MAC_PCU_TXOP_12_15__VALUE_12__MODIFY(dst, src) \
32715 ~0x000000ffU) | ((u_int32_t)(src) &\
32717 #define MAC_PCU_TXOP_12_15__VALUE_12__VERIFY(src) \
32718 (!(((u_int32_t)(src)\
32725 #define MAC_PCU_TXOP_12_15__VALUE_13__READ(src) \
32726 (((u_int32_t)(src)\
32728 #define MAC_PCU_TXOP_12_15__VALUE_13__WRITE(src) \
32729 (((u_int32_t)(src)\
32731 #define MAC_PCU_TXOP_12_15__VALUE_13__MODIFY(dst, src) \
32733 ~0x0000ff00U) | (((u_int32_t)(src) <<\
32735 #define MAC_PCU_TXOP_12_15__VALUE_13__VERIFY(src) \
32736 (!((((u_int32_t)(src)\
32743 #define MAC_PCU_TXOP_12_15__VALUE_14__READ(src) \
32744 (((u_int32_t)(src)\
32746 #define MAC_PCU_TXOP_12_15__VALUE_14__WRITE(src) \
32747 (((u_int32_t)(src)\
32749 #define MAC_PCU_TXOP_12_15__VALUE_14__MODIFY(dst, src) \
32751 ~0x00ff0000U) | (((u_int32_t)(src) <<\
32753 #define MAC_PCU_TXOP_12_15__VALUE_14__VERIFY(src) \
32754 (!((((u_int32_t)(src)\
32761 #define MAC_PCU_TXOP_12_15__VALUE_15__READ(src) \
32762 (((u_int32_t)(src)\
32764 #define MAC_PCU_TXOP_12_15__VALUE_15__WRITE(src) \
32765 (((u_int32_t)(src)\
32767 #define MAC_PCU_TXOP_12_15__VALUE_15__MODIFY(dst, src) \
32769 ~0xff000000U) | (((u_int32_t)(src) <<\
32771 #define MAC_PCU_TXOP_12_15__VALUE_15__VERIFY(src) \
32772 (!((((u_int32_t)(src)\
32792 #define MAC_PCU_GENERIC_TIMERS__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
32793 #define MAC_PCU_GENERIC_TIMERS__DATA__WRITE(src) \
32794 ((u_int32_t)(src)\
32796 #define MAC_PCU_GENERIC_TIMERS__DATA__MODIFY(dst, src) \
32798 ~0xffffffffU) | ((u_int32_t)(src) &\
32800 #define MAC_PCU_GENERIC_TIMERS__DATA__VERIFY(src) \
32801 (!(((u_int32_t)(src)\
32821 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__READ(src) \
32822 (u_int32_t)(src)\
32824 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__WRITE(src) \
32825 ((u_int32_t)(src)\
32827 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__MODIFY(dst, src) \
32829 ~0x000000ffU) | ((u_int32_t)(src) &\
32831 #define MAC_PCU_GENERIC_TIMERS_MODE__ENABLE__VERIFY(src) \
32832 (!(((u_int32_t)(src)\
32839 #define MAC_PCU_GENERIC_TIMERS_MODE__OVERFLOW_INDEX__READ(src) \
32840 (((u_int32_t)(src)\
32847 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__READ(src) \
32848 (((u_int32_t)(src)\
32850 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__WRITE(src) \
32851 (((u_int32_t)(src)\
32853 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__MODIFY(dst, src) \
32855 ~0xfffff000U) | (((u_int32_t)(src) <<\
32857 #define MAC_PCU_GENERIC_TIMERS_MODE__THRESH__VERIFY(src) \
32858 (!((((u_int32_t)(src)\
32878 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__READ(src) \
32879 (u_int32_t)(src)\
32881 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__WRITE(src) \
32882 ((u_int32_t)(src)\
32884 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__MODIFY(dst, src) \
32886 ~0x000fffffU) | ((u_int32_t)(src) &\
32888 #define MAC_PCU_SLP32_MODE__HALF_CLK_LATENCY__VERIFY(src) \
32889 (!(((u_int32_t)(src)\
32896 #define MAC_PCU_SLP32_MODE__ENABLE__READ(src) \
32897 (((u_int32_t)(src)\
32899 #define MAC_PCU_SLP32_MODE__ENABLE__WRITE(src) \
32900 (((u_int32_t)(src)\
32902 #define MAC_PCU_SLP32_MODE__ENABLE__MODIFY(dst, src) \
32904 ~0x00100000U) | (((u_int32_t)(src) <<\
32906 #define MAC_PCU_SLP32_MODE__ENABLE__VERIFY(src) \
32907 (!((((u_int32_t)(src)\
32920 #define MAC_PCU_SLP32_MODE__TSF_WRITE_STATUS__READ(src) \
32921 (((u_int32_t)(src)\
32934 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__READ(src) \
32935 (((u_int32_t)(src)\
32937 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__WRITE(src) \
32938 (((u_int32_t)(src)\
32940 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__MODIFY(dst, src) \
32942 ~0x00400000U) | (((u_int32_t)(src) <<\
32944 #define MAC_PCU_SLP32_MODE__DISABLE_32KHZ__VERIFY(src) \
32945 (!((((u_int32_t)(src)\
32958 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__READ(src) \
32959 (((u_int32_t)(src)\
32961 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__WRITE(src) \
32962 (((u_int32_t)(src)\
32964 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__MODIFY(dst, src) \
32966 ~0x00800000U) | (((u_int32_t)(src) <<\
32968 #define MAC_PCU_SLP32_MODE__FORCE_BIAS_BLOCK_ON__VERIFY(src) \
32969 (!((((u_int32_t)(src)\
32982 #define MAC_PCU_SLP32_MODE__TSF2_WRITE_STATUS__READ(src) \
32983 (((u_int32_t)(src)\
33009 #define MAC_PCU_SLP32_WAKE__XTL_TIME__READ(src) (u_int32_t)(src) & 0x0000ffffU
33010 #define MAC_PCU_SLP32_WAKE__XTL_TIME__WRITE(src) \
33011 ((u_int32_t)(src)\
33013 #define MAC_PCU_SLP32_WAKE__XTL_TIME__MODIFY(dst, src) \
33015 ~0x0000ffffU) | ((u_int32_t)(src) &\
33017 #define MAC_PCU_SLP32_WAKE__XTL_TIME__VERIFY(src) \
33018 (!(((u_int32_t)(src)\
33038 #define MAC_PCU_SLP32_INC__TSF_INC__READ(src) (u_int32_t)(src) & 0x000fffffU
33039 #define MAC_PCU_SLP32_INC__TSF_INC__WRITE(src) ((u_int32_t)(src) & 0x000fffffU)
33040 #define MAC_PCU_SLP32_INC__TSF_INC__MODIFY(dst, src) \
33042 ~0x000fffffU) | ((u_int32_t)(src) &\
33044 #define MAC_PCU_SLP32_INC__TSF_INC__VERIFY(src) \
33045 (!(((u_int32_t)(src)\
33065 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__READ(src) (u_int32_t)(src) & 0xffffffffU
33066 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__WRITE(src) \
33067 ((u_int32_t)(src)\
33069 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__MODIFY(dst, src) \
33071 ~0xffffffffU) | ((u_int32_t)(src) &\
33073 #define MAC_PCU_SLP_MIB1__SLEEP_CNT__VERIFY(src) \
33074 (!(((u_int32_t)(src)\
33094 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__READ(src) (u_int32_t)(src) & 0xffffffffU
33095 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__WRITE(src) \
33096 ((u_int32_t)(src)\
33098 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__MODIFY(dst, src) \
33100 ~0xffffffffU) | ((u_int32_t)(src) &\
33102 #define MAC_PCU_SLP_MIB2__CYCLE_CNT__VERIFY(src) \
33103 (!(((u_int32_t)(src)\
33123 #define MAC_PCU_SLP_MIB3__CLR_CNT__READ(src) (u_int32_t)(src) & 0x00000001U
33124 #define MAC_PCU_SLP_MIB3__CLR_CNT__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
33125 #define MAC_PCU_SLP_MIB3__CLR_CNT__MODIFY(dst, src) \
33127 ~0x00000001U) | ((u_int32_t)(src) &\
33129 #define MAC_PCU_SLP_MIB3__CLR_CNT__VERIFY(src) \
33130 (!(((u_int32_t)(src)\
33143 #define MAC_PCU_SLP_MIB3__PENDING__READ(src) \
33144 (((u_int32_t)(src)\
33170 #define MAC_PCU_WOW1__PATTERN_ENABLE__READ(src) (u_int32_t)(src) & 0x000000ffU
33171 #define MAC_PCU_WOW1__PATTERN_ENABLE__WRITE(src) \
33172 ((u_int32_t)(src)\
33174 #define MAC_PCU_WOW1__PATTERN_ENABLE__MODIFY(dst, src) \
33176 ~0x000000ffU) | ((u_int32_t)(src) &\
33178 #define MAC_PCU_WOW1__PATTERN_ENABLE__VERIFY(src) \
33179 (!(((u_int32_t)(src)\
33186 #define MAC_PCU_WOW1__PATTERN_DETECT__READ(src) \
33187 (((u_int32_t)(src)\
33194 #define MAC_PCU_WOW1__MAGIC_ENABLE__READ(src) \
33195 (((u_int32_t)(src)\
33197 #define MAC_PCU_WOW1__MAGIC_ENABLE__WRITE(src) \
33198 (((u_int32_t)(src)\
33200 #define MAC_PCU_WOW1__MAGIC_ENABLE__MODIFY(dst, src) \
33202 ~0x00010000U) | (((u_int32_t)(src) <<\
33204 #define MAC_PCU_WOW1__MAGIC_ENABLE__VERIFY(src) \
33205 (!((((u_int32_t)(src)\
33218 #define MAC_PCU_WOW1__MAGIC_DETECT__READ(src) \
33219 (((u_int32_t)(src)\
33232 #define MAC_PCU_WOW1__INTR_ENABLE__READ(src) \
33233 (((u_int32_t)(src)\
33235 #define MAC_PCU_WOW1__INTR_ENABLE__WRITE(src) \
33236 (((u_int32_t)(src)\
33238 #define MAC_PCU_WOW1__INTR_ENABLE__MODIFY(dst, src) \
33240 ~0x00040000U) | (((u_int32_t)(src) <<\
33242 #define MAC_PCU_WOW1__INTR_ENABLE__VERIFY(src) \
33243 (!((((u_int32_t)(src)\
33256 #define MAC_PCU_WOW1__INTR_DETECT__READ(src) \
33257 (((u_int32_t)(src)\
33270 #define MAC_PCU_WOW1__KEEP_ALIVE_FAIL__READ(src) \
33271 (((u_int32_t)(src)\
33284 #define MAC_PCU_WOW1__BEACON_FAIL__READ(src) \
33285 (((u_int32_t)(src)\
33298 #define MAC_PCU_WOW1__CW_BITS__READ(src) \
33299 (((u_int32_t)(src)\
33301 #define MAC_PCU_WOW1__CW_BITS__WRITE(src) \
33302 (((u_int32_t)(src)\
33304 #define MAC_PCU_WOW1__CW_BITS__MODIFY(dst, src) \
33306 ~0xf0000000U) | (((u_int32_t)(src) <<\
33308 #define MAC_PCU_WOW1__CW_BITS__VERIFY(src) \
33309 (!((((u_int32_t)(src)\
33329 #define MAC_PCU_WOW2__AIFS__READ(src) (u_int32_t)(src) & 0x000000ffU
33330 #define MAC_PCU_WOW2__AIFS__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
33331 #define MAC_PCU_WOW2__AIFS__MODIFY(dst, src) \
33333 ~0x000000ffU) | ((u_int32_t)(src) &\
33335 #define MAC_PCU_WOW2__AIFS__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
33341 #define MAC_PCU_WOW2__SLOT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
33342 #define MAC_PCU_WOW2__SLOT__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U)
33343 #define MAC_PCU_WOW2__SLOT__MODIFY(dst, src) \
33345 ~0x0000ff00U) | (((u_int32_t)(src) <<\
33347 #define MAC_PCU_WOW2__SLOT__VERIFY(src) \
33348 (!((((u_int32_t)(src)\
33355 #define MAC_PCU_WOW2__TRY_CNT__READ(src) \
33356 (((u_int32_t)(src)\
33358 #define MAC_PCU_WOW2__TRY_CNT__WRITE(src) \
33359 (((u_int32_t)(src)\
33361 #define MAC_PCU_WOW2__TRY_CNT__MODIFY(dst, src) \
33363 ~0x00ff0000U) | (((u_int32_t)(src) <<\
33365 #define MAC_PCU_WOW2__TRY_CNT__VERIFY(src) \
33366 (!((((u_int32_t)(src)\
33386 #define MAC_PCU_LOGIC_ANALYZER__HOLD__READ(src) (u_int32_t)(src) & 0x00000001U
33387 #define MAC_PCU_LOGIC_ANALYZER__HOLD__WRITE(src) \
33388 ((u_int32_t)(src)\
33390 #define MAC_PCU_LOGIC_ANALYZER__HOLD__MODIFY(dst, src) \
33392 ~0x00000001U) | ((u_int32_t)(src) &\
33394 #define MAC_PCU_LOGIC_ANALYZER__HOLD__VERIFY(src) \
33395 (!(((u_int32_t)(src)\
33408 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__READ(src) \
33409 (((u_int32_t)(src)\
33411 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__WRITE(src) \
33412 (((u_int32_t)(src)\
33414 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__MODIFY(dst, src) \
33416 ~0x00000002U) | (((u_int32_t)(src) <<\
33418 #define MAC_PCU_LOGIC_ANALYZER__CLEAR__VERIFY(src) \
33419 (!((((u_int32_t)(src)\
33432 #define MAC_PCU_LOGIC_ANALYZER__STATE__READ(src) \
33433 (((u_int32_t)(src)\
33446 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__READ(src) \
33447 (((u_int32_t)(src)\
33449 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__WRITE(src) \
33450 (((u_int32_t)(src)\
33452 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__MODIFY(dst, src) \
33454 ~0x00000008U) | (((u_int32_t)(src) <<\
33456 #define MAC_PCU_LOGIC_ANALYZER__ENABLE__VERIFY(src) \
33457 (!((((u_int32_t)(src)\
33470 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__READ(src) \
33471 (((u_int32_t)(src)\
33473 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__WRITE(src) \
33474 (((u_int32_t)(src)\
33476 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__MODIFY(dst, src) \
33478 ~0x000000f0U) | (((u_int32_t)(src) <<\
33480 #define MAC_PCU_LOGIC_ANALYZER__QCU_SEL__VERIFY(src) \
33481 (!((((u_int32_t)(src)\
33488 #define MAC_PCU_LOGIC_ANALYZER__INT_ADDR__READ(src) \
33489 (((u_int32_t)(src)\
33496 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__READ(src) \
33497 (((u_int32_t)(src)\
33499 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__WRITE(src) \
33500 (((u_int32_t)(src)\
33502 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__MODIFY(dst, src) \
33504 ~0xfffc0000U) | (((u_int32_t)(src) <<\
33506 #define MAC_PCU_LOGIC_ANALYZER__DIAG_MODE__VERIFY(src) \
33507 (!((((u_int32_t)(src)\
33527 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__READ(src) \
33528 (u_int32_t)(src)\
33530 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__WRITE(src) \
33531 ((u_int32_t)(src)\
33533 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__MODIFY(dst, src) \
33535 ~0xffffffffU) | ((u_int32_t)(src) &\
33537 #define MAC_PCU_LOGIC_ANALYZER_32L__MASK__VERIFY(src) \
33538 (!(((u_int32_t)(src)\
33558 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__READ(src) \
33559 (u_int32_t)(src)\
33561 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__WRITE(src) \
33562 ((u_int32_t)(src)\
33564 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__MODIFY(dst, src) \
33566 ~0x0000ffffU) | ((u_int32_t)(src) &\
33568 #define MAC_PCU_LOGIC_ANALYZER_16U__MASK__VERIFY(src) \
33569 (!(((u_int32_t)(src)\
33589 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__READ(src) \
33590 (u_int32_t)(src)\
33592 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__WRITE(src) \
33593 ((u_int32_t)(src)\
33595 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__MODIFY(dst, src) \
33597 ~0x00000001U) | ((u_int32_t)(src) &\
33599 #define MAC_PCU_WOW3_BEACON_FAIL__ENABLE__VERIFY(src) \
33600 (!(((u_int32_t)(src)\
33626 #define MAC_PCU_WOW3_BEACON__TIMEOUT__READ(src) (u_int32_t)(src) & 0xffffffffU
33627 #define MAC_PCU_WOW3_BEACON__TIMEOUT__WRITE(src) \
33628 ((u_int32_t)(src)\
33630 #define MAC_PCU_WOW3_BEACON__TIMEOUT__MODIFY(dst, src) \
33632 ~0xffffffffU) | ((u_int32_t)(src) &\
33634 #define MAC_PCU_WOW3_BEACON__TIMEOUT__VERIFY(src) \
33635 (!(((u_int32_t)(src)\
33655 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__READ(src) \
33656 (u_int32_t)(src)\
33658 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__WRITE(src) \
33659 ((u_int32_t)(src)\
33661 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__MODIFY(dst, src) \
33663 ~0xffffffffU) | ((u_int32_t)(src) &\
33665 #define MAC_PCU_WOW3_KEEP_ALIVE__TIMEOUT__VERIFY(src) \
33666 (!(((u_int32_t)(src)\
33686 #define MAC_PCU_WOW_KA__AUTO_DISABLE__READ(src) (u_int32_t)(src) & 0x00000001U
33687 #define MAC_PCU_WOW_KA__AUTO_DISABLE__WRITE(src) \
33688 ((u_int32_t)(src)\
33690 #define MAC_PCU_WOW_KA__AUTO_DISABLE__MODIFY(dst, src) \
33692 ~0x00000001U) | ((u_int32_t)(src) &\
33694 #define MAC_PCU_WOW_KA__AUTO_DISABLE__VERIFY(src) \
33695 (!(((u_int32_t)(src)\
33708 #define MAC_PCU_WOW_KA__FAIL_DISABLE__READ(src) \
33709 (((u_int32_t)(src)\
33711 #define MAC_PCU_WOW_KA__FAIL_DISABLE__WRITE(src) \
33712 (((u_int32_t)(src)\
33714 #define MAC_PCU_WOW_KA__FAIL_DISABLE__MODIFY(dst, src) \
33716 ~0x00000002U) | (((u_int32_t)(src) <<\
33718 #define MAC_PCU_WOW_KA__FAIL_DISABLE__VERIFY(src) \
33719 (!((((u_int32_t)(src)\
33732 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__READ(src) \
33733 (((u_int32_t)(src)\
33735 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__WRITE(src) \
33736 (((u_int32_t)(src)\
33738 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__MODIFY(dst, src) \
33740 ~0x00000004U) | (((u_int32_t)(src) <<\
33742 #define MAC_PCU_WOW_KA__BKOFF_CS_ENABLE__VERIFY(src) \
33743 (!((((u_int32_t)(src)\
33769 #define PCU_1US__SCALER__READ(src) (u_int32_t)(src) & 0x0000007fU
33770 #define PCU_1US__SCALER__WRITE(src) ((u_int32_t)(src) & 0x0000007fU)
33771 #define PCU_1US__SCALER__MODIFY(dst, src) \
33773 ~0x0000007fU) | ((u_int32_t)(src) &\
33775 #define PCU_1US__SCALER__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000007fU)))
33794 #define PCU_KA__DEL__READ(src) (u_int32_t)(src) & 0x00000fffU
33795 #define PCU_KA__DEL__WRITE(src) ((u_int32_t)(src) & 0x00000fffU)
33796 #define PCU_KA__DEL__MODIFY(dst, src) \
33798 ~0x00000fffU) | ((u_int32_t)(src) &\
33800 #define PCU_KA__DEL__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000fffU)))
33819 #define WOW_EXACT__LENGTH__READ(src) (u_int32_t)(src) & 0x000000ffU
33820 #define WOW_EXACT__LENGTH__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
33821 #define WOW_EXACT__LENGTH__MODIFY(dst, src) \
33823 ~0x000000ffU) | ((u_int32_t)(src) &\
33825 #define WOW_EXACT__LENGTH__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
33831 #define WOW_EXACT__OFFSET__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
33832 #define WOW_EXACT__OFFSET__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U)
33833 #define WOW_EXACT__OFFSET__MODIFY(dst, src) \
33835 ~0x0000ff00U) | (((u_int32_t)(src) <<\
33837 #define WOW_EXACT__OFFSET__VERIFY(src) \
33838 (!((((u_int32_t)(src)\
33858 #define PCU_WOW4__OFFSET0__READ(src) (u_int32_t)(src) & 0x000000ffU
33859 #define PCU_WOW4__OFFSET0__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
33860 #define PCU_WOW4__OFFSET0__MODIFY(dst, src) \
33862 ~0x000000ffU) | ((u_int32_t)(src) &\
33864 #define PCU_WOW4__OFFSET0__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
33870 #define PCU_WOW4__OFFSET1__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
33871 #define PCU_WOW4__OFFSET1__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U)
33872 #define PCU_WOW4__OFFSET1__MODIFY(dst, src) \
33874 ~0x0000ff00U) | (((u_int32_t)(src) <<\
33876 #define PCU_WOW4__OFFSET1__VERIFY(src) \
33877 (!((((u_int32_t)(src)\
33884 #define PCU_WOW4__OFFSET2__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16)
33885 #define PCU_WOW4__OFFSET2__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U)
33886 #define PCU_WOW4__OFFSET2__MODIFY(dst, src) \
33888 ~0x00ff0000U) | (((u_int32_t)(src) <<\
33890 #define PCU_WOW4__OFFSET2__VERIFY(src) \
33891 (!((((u_int32_t)(src)\
33898 #define PCU_WOW4__OFFSET3__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24)
33899 #define PCU_WOW4__OFFSET3__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U)
33900 #define PCU_WOW4__OFFSET3__MODIFY(dst, src) \
33902 ~0xff000000U) | (((u_int32_t)(src) <<\
33904 #define PCU_WOW4__OFFSET3__VERIFY(src) \
33905 (!((((u_int32_t)(src)\
33925 #define PCU_WOW5__OFFSET4__READ(src) (u_int32_t)(src) & 0x000000ffU
33926 #define PCU_WOW5__OFFSET4__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
33927 #define PCU_WOW5__OFFSET4__MODIFY(dst, src) \
33929 ~0x000000ffU) | ((u_int32_t)(src) &\
33931 #define PCU_WOW5__OFFSET4__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
33937 #define PCU_WOW5__OFFSET5__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
33938 #define PCU_WOW5__OFFSET5__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U)
33939 #define PCU_WOW5__OFFSET5__MODIFY(dst, src) \
33941 ~0x0000ff00U) | (((u_int32_t)(src) <<\
33943 #define PCU_WOW5__OFFSET5__VERIFY(src) \
33944 (!((((u_int32_t)(src)\
33951 #define PCU_WOW5__OFFSET6__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16)
33952 #define PCU_WOW5__OFFSET6__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U)
33953 #define PCU_WOW5__OFFSET6__MODIFY(dst, src) \
33955 ~0x00ff0000U) | (((u_int32_t)(src) <<\
33957 #define PCU_WOW5__OFFSET6__VERIFY(src) \
33958 (!((((u_int32_t)(src)\
33965 #define PCU_WOW5__OFFSET7__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24)
33966 #define PCU_WOW5__OFFSET7__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U)
33967 #define PCU_WOW5__OFFSET7__MODIFY(dst, src) \
33969 ~0xff000000U) | (((u_int32_t)(src) <<\
33971 #define PCU_WOW5__OFFSET7__VERIFY(src) \
33972 (!((((u_int32_t)(src)\
33992 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__READ(src) \
33993 (u_int32_t)(src)\
33995 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__WRITE(src) \
33996 ((u_int32_t)(src)\
33998 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__MODIFY(dst, src) \
34000 ~0x000000ffU) | ((u_int32_t)(src) &\
34002 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK1__VERIFY(src) \
34003 (!(((u_int32_t)(src)\
34010 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__READ(src) \
34011 (((u_int32_t)(src)\
34013 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__WRITE(src) \
34014 (((u_int32_t)(src)\
34016 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__MODIFY(dst, src) \
34018 ~0x0000ff00U) | (((u_int32_t)(src) <<\
34020 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK2__VERIFY(src) \
34021 (!((((u_int32_t)(src)\
34028 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__READ(src) \
34029 (((u_int32_t)(src)\
34031 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__WRITE(src) \
34032 (((u_int32_t)(src)\
34034 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__MODIFY(dst, src) \
34036 ~0x00ff0000U) | (((u_int32_t)(src) <<\
34038 #define MAC_PCU_PHY_ERR_CNT_MASK_CONT__MASK3__VERIFY(src) \
34039 (!((((u_int32_t)(src)\
34059 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__READ(src) \
34060 (u_int32_t)(src)\
34062 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__WRITE(src) \
34063 ((u_int32_t)(src)\
34065 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__MODIFY(dst, src) \
34067 ~0x00000001U) | ((u_int32_t)(src) &\
34069 #define MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE__VERIFY(src) \
34070 (!(((u_int32_t)(src)\
34083 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__READ(src) \
34084 (((u_int32_t)(src)\
34086 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__WRITE(src) \
34087 (((u_int32_t)(src)\
34089 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__MODIFY(dst, src) \
34091 ~0x00000002U) | (((u_int32_t)(src) <<\
34093 #define MAC_PCU_AZIMUTH_MODE__KEY_SEARCH_AD1__VERIFY(src) \
34094 (!((((u_int32_t)(src)\
34107 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__READ(src) \
34108 (((u_int32_t)(src)\
34110 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__WRITE(src) \
34111 (((u_int32_t)(src)\
34113 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__MODIFY(dst, src) \
34115 ~0x00000004U) | (((u_int32_t)(src) <<\
34117 #define MAC_PCU_AZIMUTH_MODE__TX_TSF_STATUS_SEL__VERIFY(src) \
34118 (!((((u_int32_t)(src)\
34131 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__READ(src) \
34132 (((u_int32_t)(src)\
34134 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__WRITE(src) \
34135 (((u_int32_t)(src)\
34137 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__MODIFY(dst, src) \
34139 ~0x00000008U) | (((u_int32_t)(src) <<\
34141 #define MAC_PCU_AZIMUTH_MODE__RX_TSF_STATUS_SEL__VERIFY(src) \
34142 (!((((u_int32_t)(src)\
34155 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__READ(src) \
34156 (((u_int32_t)(src)\
34158 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__WRITE(src) \
34159 (((u_int32_t)(src)\
34161 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__MODIFY(dst, src) \
34163 ~0x00000010U) | (((u_int32_t)(src) <<\
34165 #define MAC_PCU_AZIMUTH_MODE__CLK_EN__VERIFY(src) \
34166 (!((((u_int32_t)(src)\
34179 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__READ(src) \
34180 (((u_int32_t)(src)\
34182 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__WRITE(src) \
34183 (((u_int32_t)(src)\
34185 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__MODIFY(dst, src) \
34187 ~0x00000020U) | (((u_int32_t)(src) <<\
34189 #define MAC_PCU_AZIMUTH_MODE__TX_DESC_EN__VERIFY(src) \
34190 (!((((u_int32_t)(src)\
34203 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__READ(src) \
34204 (((u_int32_t)(src)\
34206 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__WRITE(src) \
34207 (((u_int32_t)(src)\
34209 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__MODIFY(dst, src) \
34211 ~0x00000040U) | (((u_int32_t)(src) <<\
34213 #define MAC_PCU_AZIMUTH_MODE__ACK_CTS_MATCH_TX_AD2__VERIFY(src) \
34214 (!((((u_int32_t)(src)\
34227 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__READ(src) \
34228 (((u_int32_t)(src)\
34230 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__WRITE(src) \
34231 (((u_int32_t)(src)\
34233 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__MODIFY(dst, src) \
34235 ~0x00000080U) | (((u_int32_t)(src) <<\
34237 #define MAC_PCU_AZIMUTH_MODE__BA_USES_AD1__VERIFY(src) \
34238 (!((((u_int32_t)(src)\
34251 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__READ(src) \
34252 (((u_int32_t)(src)\
34254 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__WRITE(src) \
34255 (((u_int32_t)(src)\
34257 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__MODIFY(dst, src) \
34259 ~0x00000100U) | (((u_int32_t)(src) <<\
34261 #define MAC_PCU_AZIMUTH_MODE__WMAC_CLK_SEL__VERIFY(src) \
34262 (!((((u_int32_t)(src)\
34275 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__READ(src) \
34276 (((u_int32_t)(src)\
34278 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__WRITE(src) \
34279 (((u_int32_t)(src)\
34281 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__MODIFY(dst, src) \
34283 ~0x00000200U) | (((u_int32_t)(src) <<\
34285 #define MAC_PCU_AZIMUTH_MODE__FILTER_PASS_HOLD__VERIFY(src) \
34286 (!((((u_int32_t)(src)\
34312 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__READ(src) \
34313 (u_int32_t)(src)\
34315 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__WRITE(src) \
34316 ((u_int32_t)(src)\
34318 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__MODIFY(dst, src) \
34320 ~0xffffffffU) | ((u_int32_t)(src) &\
34322 #define MAC_PCU_AZIMUTH_TIME_STAMP__VALUE__VERIFY(src) \
34323 (!(((u_int32_t)(src)\
34343 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__READ(src) \
34344 (u_int32_t)(src)\
34346 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__WRITE(src) \
34347 ((u_int32_t)(src)\
34349 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__MODIFY(dst, src) \
34351 ~0x00000001U) | ((u_int32_t)(src) &\
34353 #define MAC_PCU_20_40_MODE__JOINED_RX_CLEAR__VERIFY(src) \
34354 (!(((u_int32_t)(src)\
34367 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__READ(src) \
34368 (((u_int32_t)(src)\
34370 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__WRITE(src) \
34371 (((u_int32_t)(src)\
34373 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__MODIFY(dst, src) \
34375 ~0x00000002U) | (((u_int32_t)(src) <<\
34377 #define MAC_PCU_20_40_MODE__EXT_PIFS_ENABLE__VERIFY(src) \
34378 (!((((u_int32_t)(src)\
34391 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__READ(src) \
34392 (((u_int32_t)(src)\
34394 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__WRITE(src) \
34395 (((u_int32_t)(src)\
34397 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__MODIFY(dst, src) \
34399 ~0x00000004U) | (((u_int32_t)(src) <<\
34401 #define MAC_PCU_20_40_MODE__TX_HT20_ON_EXT_BUSY__VERIFY(src) \
34402 (!((((u_int32_t)(src)\
34415 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__READ(src) \
34416 (((u_int32_t)(src)\
34418 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__WRITE(src) \
34419 (((u_int32_t)(src)\
34421 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__MODIFY(dst, src) \
34423 ~0x00000008U) | (((u_int32_t)(src) <<\
34425 #define MAC_PCU_20_40_MODE__SWAMPED_FORCES_RX_CLEAR_CTL_IDLE__VERIFY(src) \
34426 (!((((u_int32_t)(src)\
34439 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__READ(src) \
34440 (((u_int32_t)(src)\
34442 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__WRITE(src) \
34443 (((u_int32_t)(src)\
34445 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__MODIFY(dst, src) \
34447 ~0x0000fff0U) | (((u_int32_t)(src) <<\
34449 #define MAC_PCU_20_40_MODE__PIFS_CYCLES__VERIFY(src) \
34450 (!((((u_int32_t)(src)\
34470 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__READ(src) (u_int32_t)(src) & 0x0000001fU
34471 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__WRITE(src) \
34472 ((u_int32_t)(src)\
34474 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__MODIFY(dst, src) \
34476 ~0x0000001fU) | ((u_int32_t)(src) &\
34478 #define MAC_PCU_H_XFER_TIMEOUT__VALUE__VERIFY(src) \
34479 (!(((u_int32_t)(src)\
34486 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__READ(src) \
34487 (((u_int32_t)(src)\
34489 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__WRITE(src) \
34490 (((u_int32_t)(src)\
34492 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__MODIFY(dst, src) \
34494 ~0x00000020U) | (((u_int32_t)(src) <<\
34496 #define MAC_PCU_H_XFER_TIMEOUT__DISABLE__VERIFY(src) \
34497 (!((((u_int32_t)(src)\
34510 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__READ(src) \
34511 (((u_int32_t)(src)\
34513 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__WRITE(src) \
34514 (((u_int32_t)(src)\
34516 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__MODIFY(dst, src) \
34518 ~0x00000040U) | (((u_int32_t)(src) <<\
34520 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_IMMEDIATE_RESP__VERIFY(src) \
34521 (!((((u_int32_t)(src)\
34534 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__READ(src) \
34535 (((u_int32_t)(src)\
34537 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__WRITE(src) \
34538 (((u_int32_t)(src)\
34540 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__MODIFY(dst, src) \
34542 ~0x00000080U) | (((u_int32_t)(src) <<\
34544 #define MAC_PCU_H_XFER_TIMEOUT__DELAY_EXTXBF_ONLY_UPLOAD_H__VERIFY(src) \
34545 (!((((u_int32_t)(src)\
34558 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__READ(src) \
34559 (((u_int32_t)(src)\
34561 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__WRITE(src) \
34562 (((u_int32_t)(src)\
34564 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__MODIFY(dst, src) \
34566 ~0x00000100U) | (((u_int32_t)(src) <<\
34568 #define MAC_PCU_H_XFER_TIMEOUT__EXTXBF_NOACK_NORPT__VERIFY(src) \
34569 (!((((u_int32_t)(src)\
34595 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__READ(src) \
34596 (u_int32_t)(src)\
34598 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__WRITE(src) \
34599 ((u_int32_t)(src)\
34601 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__MODIFY(dst, src) \
34603 ~0xffffffffU) | ((u_int32_t)(src) &\
34605 #define MAC_PCU_RX_CLEAR_DIFF_CNT__VALUE__VERIFY(src) \
34606 (!(((u_int32_t)(src)\
34626 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__READ(src) \
34627 (u_int32_t)(src)\
34629 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__WRITE(src) \
34630 ((u_int32_t)(src)\
34632 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__MODIFY(dst, src) \
34634 ~0x00000007U) | ((u_int32_t)(src) &\
34636 #define MAC_PCU_SELF_GEN_ANTENNA_MASK__VALUE__VERIFY(src) \
34637 (!(((u_int32_t)(src)\
34657 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__READ(src) \
34658 (u_int32_t)(src)\
34660 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__WRITE(src) \
34661 ((u_int32_t)(src)\
34663 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__MODIFY(dst, src) \
34665 ~0x0000000fU) | ((u_int32_t)(src) &\
34667 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_OFFSET__VERIFY(src) \
34668 (!(((u_int32_t)(src)\
34675 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__READ(src) \
34676 (((u_int32_t)(src)\
34678 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__WRITE(src) \
34679 (((u_int32_t)(src)\
34681 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__MODIFY(dst, src) \
34683 ~0x000000f0U) | (((u_int32_t)(src) <<\
34685 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_OFFSET__VERIFY(src) \
34686 (!((((u_int32_t)(src)\
34693 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__READ(src) \
34694 (((u_int32_t)(src)\
34696 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__WRITE(src) \
34697 (((u_int32_t)(src)\
34699 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__MODIFY(dst, src) \
34701 ~0x00000100U) | (((u_int32_t)(src) <<\
34703 #define MAC_PCU_BA_BAR_CONTROL__COMPRESSED_VALUE__VERIFY(src) \
34704 (!((((u_int32_t)(src)\
34717 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__READ(src) \
34718 (((u_int32_t)(src)\
34720 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__WRITE(src) \
34721 (((u_int32_t)(src)\
34723 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__MODIFY(dst, src) \
34725 ~0x00000200U) | (((u_int32_t)(src) <<\
34727 #define MAC_PCU_BA_BAR_CONTROL__ACK_POLICY_VALUE__VERIFY(src) \
34728 (!((((u_int32_t)(src)\
34741 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__READ(src) \
34742 (((u_int32_t)(src)\
34744 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__WRITE(src) \
34745 (((u_int32_t)(src)\
34747 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__MODIFY(dst, src) \
34749 ~0x00000400U) | (((u_int32_t)(src) <<\
34751 #define MAC_PCU_BA_BAR_CONTROL__FORCE_NO_MATCH__VERIFY(src) \
34752 (!((((u_int32_t)(src)\
34765 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__READ(src) \
34766 (((u_int32_t)(src)\
34768 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__WRITE(src) \
34769 (((u_int32_t)(src)\
34771 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__MODIFY(dst, src) \
34773 ~0x00000800U) | (((u_int32_t)(src) <<\
34775 #define MAC_PCU_BA_BAR_CONTROL__TX_BA_CLEAR_BA_VALID__VERIFY(src) \
34776 (!((((u_int32_t)(src)\
34789 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__READ(src) \
34790 (((u_int32_t)(src)\
34792 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__WRITE(src) \
34793 (((u_int32_t)(src)\
34795 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__MODIFY(dst, src) \
34797 ~0x00001000U) | (((u_int32_t)(src) <<\
34799 #define MAC_PCU_BA_BAR_CONTROL__UPDATE_BA_BITMAP_QOS_NULL__VERIFY(src) \
34800 (!((((u_int32_t)(src)\
34826 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__READ(src) \
34827 (u_int32_t)(src)\
34829 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__WRITE(src) \
34830 ((u_int32_t)(src)\
34832 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__MODIFY(dst, src) \
34834 ~0x000000ffU) | ((u_int32_t)(src) &\
34836 #define MAC_PCU_LEGACY_PLCP_SPOOF__EIFS_MINUS_DIFS__VERIFY(src) \
34837 (!(((u_int32_t)(src)\
34844 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__READ(src) \
34845 (((u_int32_t)(src)\
34847 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__WRITE(src) \
34848 (((u_int32_t)(src)\
34850 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__MODIFY(dst, src) \
34852 ~0x00001f00U) | (((u_int32_t)(src) <<\
34854 #define MAC_PCU_LEGACY_PLCP_SPOOF__MIN_LENGTH__VERIFY(src) \
34855 (!((((u_int32_t)(src)\
34875 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__READ(src) \
34876 (u_int32_t)(src)\
34878 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__WRITE(src) \
34879 ((u_int32_t)(src)\
34881 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__MODIFY(dst, src) \
34883 ~0x000000ffU) | ((u_int32_t)(src) &\
34885 #define MAC_PCU_PHY_ERROR_MASK_CONT__MASK_VALUE__VERIFY(src) \
34886 (!(((u_int32_t)(src)\
34893 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__READ(src) \
34894 (((u_int32_t)(src)\
34896 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__WRITE(src) \
34897 (((u_int32_t)(src)\
34899 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__MODIFY(dst, src) \
34901 ~0x00ff0000U) | (((u_int32_t)(src) <<\
34903 #define MAC_PCU_PHY_ERROR_MASK_CONT__EIFS_VALUE__VERIFY(src) \
34904 (!((((u_int32_t)(src)\
34924 #define MAC_PCU_TX_TIMER__TX_TIMER__READ(src) (u_int32_t)(src) & 0x00007fffU
34925 #define MAC_PCU_TX_TIMER__TX_TIMER__WRITE(src) ((u_int32_t)(src) & 0x00007fffU)
34926 #define MAC_PCU_TX_TIMER__TX_TIMER__MODIFY(dst, src) \
34928 ~0x00007fffU) | ((u_int32_t)(src) &\
34930 #define MAC_PCU_TX_TIMER__TX_TIMER__VERIFY(src) \
34931 (!(((u_int32_t)(src)\
34938 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__READ(src) \
34939 (((u_int32_t)(src)\
34941 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__WRITE(src) \
34942 (((u_int32_t)(src)\
34944 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__MODIFY(dst, src) \
34946 ~0x00008000U) | (((u_int32_t)(src) <<\
34948 #define MAC_PCU_TX_TIMER__TX_TIMER_ENABLE__VERIFY(src) \
34949 (!((((u_int32_t)(src)\
34962 #define MAC_PCU_TX_TIMER__RIFS_TIMER__READ(src) \
34963 (((u_int32_t)(src)\
34965 #define MAC_PCU_TX_TIMER__RIFS_TIMER__WRITE(src) \
34966 (((u_int32_t)(src)\
34968 #define MAC_PCU_TX_TIMER__RIFS_TIMER__MODIFY(dst, src) \
34970 ~0x000f0000U) | (((u_int32_t)(src) <<\
34972 #define MAC_PCU_TX_TIMER__RIFS_TIMER__VERIFY(src) \
34973 (!((((u_int32_t)(src)\
34980 #define MAC_PCU_TX_TIMER__QUIET_TIMER__READ(src) \
34981 (((u_int32_t)(src)\
34983 #define MAC_PCU_TX_TIMER__QUIET_TIMER__WRITE(src) \
34984 (((u_int32_t)(src)\
34986 #define MAC_PCU_TX_TIMER__QUIET_TIMER__MODIFY(dst, src) \
34988 ~0x01f00000U) | (((u_int32_t)(src) <<\
34990 #define MAC_PCU_TX_TIMER__QUIET_TIMER__VERIFY(src) \
34991 (!((((u_int32_t)(src)\
34998 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__READ(src) \
34999 (((u_int32_t)(src)\
35001 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__WRITE(src) \
35002 (((u_int32_t)(src)\
35004 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__MODIFY(dst, src) \
35006 ~0x02000000U) | (((u_int32_t)(src) <<\
35008 #define MAC_PCU_TX_TIMER__QUIET_TIMER_ENABLE__VERIFY(src) \
35009 (!((((u_int32_t)(src)\
35035 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__READ(src) \
35036 (u_int32_t)(src)\
35038 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__WRITE(src) \
35039 ((u_int32_t)(src)\
35041 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__MODIFY(dst, src) \
35043 ~0x00000fffU) | ((u_int32_t)(src) &\
35045 #define MAC_PCU_TXBUF_CTRL__USABLE_ENTRIES__VERIFY(src) \
35046 (!(((u_int32_t)(src)\
35053 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__READ(src) \
35054 (((u_int32_t)(src)\
35056 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__WRITE(src) \
35057 (((u_int32_t)(src)\
35059 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__MODIFY(dst, src) \
35061 ~0x00010000U) | (((u_int32_t)(src) <<\
35063 #define MAC_PCU_TXBUF_CTRL__TX_FIFO_WRAP_ENABLE__VERIFY(src) \
35064 (!((((u_int32_t)(src)\
35090 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__READ(src) \
35091 (u_int32_t)(src)\
35093 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__WRITE(src) \
35094 ((u_int32_t)(src)\
35096 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__MODIFY(dst, src) \
35098 ~0x00000001U) | ((u_int32_t)(src) &\
35100 #define MAC_PCU_MISC_MODE2__BUG_21532_FIX_ENABLE__VERIFY(src) \
35101 (!(((u_int32_t)(src)\
35114 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__READ(src) \
35115 (((u_int32_t)(src)\
35117 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__WRITE(src) \
35118 (((u_int32_t)(src)\
35120 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__MODIFY(dst, src) \
35122 ~0x00000002U) | (((u_int32_t)(src) <<\
35124 #define MAC_PCU_MISC_MODE2__MGMT_CRYPTO_ENABLE__VERIFY(src) \
35125 (!((((u_int32_t)(src)\
35138 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__READ(src) \
35139 (((u_int32_t)(src)\
35141 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__WRITE(src) \
35142 (((u_int32_t)(src)\
35144 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__MODIFY(dst, src) \
35146 ~0x00000004U) | (((u_int32_t)(src) <<\
35148 #define MAC_PCU_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT__VERIFY(src) \
35149 (!((((u_int32_t)(src)\
35162 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__READ(src) \
35163 (((u_int32_t)(src)\
35165 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__WRITE(src) \
35166 (((u_int32_t)(src)\
35168 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__MODIFY(dst, src) \
35170 ~0x00000008U) | (((u_int32_t)(src) <<\
35172 #define MAC_PCU_MISC_MODE2__BUG_58603_FIX_ENABLE__VERIFY(src) \
35173 (!((((u_int32_t)(src)\
35186 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__READ(src) \
35187 (((u_int32_t)(src)\
35189 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__WRITE(src) \
35190 (((u_int32_t)(src)\
35192 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__MODIFY(dst, src) \
35194 ~0x00000010U) | (((u_int32_t)(src) <<\
35196 #define MAC_PCU_MISC_MODE2__BUG_58057_FIX_ENABLE__VERIFY(src) \
35197 (!((((u_int32_t)(src)\
35210 #define MAC_PCU_MISC_MODE2__RESERVED_0__READ(src) \
35211 (((u_int32_t)(src)\
35213 #define MAC_PCU_MISC_MODE2__RESERVED_0__WRITE(src) \
35214 (((u_int32_t)(src)\
35216 #define MAC_PCU_MISC_MODE2__RESERVED_0__MODIFY(dst, src) \
35218 ~0x00000020U) | (((u_int32_t)(src) <<\
35220 #define MAC_PCU_MISC_MODE2__RESERVED_0__VERIFY(src) \
35221 (!((((u_int32_t)(src)\
35234 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__READ(src) \
35235 (((u_int32_t)(src)\
35237 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__WRITE(src) \
35238 (((u_int32_t)(src)\
35240 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__MODIFY(dst, src) \
35242 ~0x00000040U) | (((u_int32_t)(src) <<\
35244 #define MAC_PCU_MISC_MODE2__ADHOC_MCAST_KEYID_ENABLE__VERIFY(src) \
35245 (!((((u_int32_t)(src)\
35258 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__READ(src) \
35259 (((u_int32_t)(src)\
35261 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__WRITE(src) \
35262 (((u_int32_t)(src)\
35264 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__MODIFY(dst, src) \
35266 ~0x00000080U) | (((u_int32_t)(src) <<\
35268 #define MAC_PCU_MISC_MODE2__CFP_IGNORE__VERIFY(src) \
35269 (!((((u_int32_t)(src)\
35282 #define MAC_PCU_MISC_MODE2__MGMT_QOS__READ(src) \
35283 (((u_int32_t)(src)\
35285 #define MAC_PCU_MISC_MODE2__MGMT_QOS__WRITE(src) \
35286 (((u_int32_t)(src)\
35288 #define MAC_PCU_MISC_MODE2__MGMT_QOS__MODIFY(dst, src) \
35290 ~0x0000ff00U) | (((u_int32_t)(src) <<\
35292 #define MAC_PCU_MISC_MODE2__MGMT_QOS__VERIFY(src) \
35293 (!((((u_int32_t)(src)\
35300 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__READ(src) \
35301 (((u_int32_t)(src)\
35303 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__WRITE(src) \
35304 (((u_int32_t)(src)\
35306 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__MODIFY(dst, src) \
35308 ~0x00010000U) | (((u_int32_t)(src) <<\
35310 #define MAC_PCU_MISC_MODE2__ENABLE_LOAD_NAV_BEACON_DURATION__VERIFY(src) \
35311 (!((((u_int32_t)(src)\
35324 #define MAC_PCU_MISC_MODE2__AGG_WEP__READ(src) \
35325 (((u_int32_t)(src)\
35327 #define MAC_PCU_MISC_MODE2__AGG_WEP__WRITE(src) \
35328 (((u_int32_t)(src)\
35330 #define MAC_PCU_MISC_MODE2__AGG_WEP__MODIFY(dst, src) \
35332 ~0x00020000U) | (((u_int32_t)(src) <<\
35334 #define MAC_PCU_MISC_MODE2__AGG_WEP__VERIFY(src) \
35335 (!((((u_int32_t)(src)\
35348 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__READ(src) \
35349 (((u_int32_t)(src)\
35351 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__WRITE(src) \
35352 (((u_int32_t)(src)\
35354 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__MODIFY(dst, src) \
35356 ~0x00040000U) | (((u_int32_t)(src) <<\
35358 #define MAC_PCU_MISC_MODE2__BC_MC_WAPI_MODE__VERIFY(src) \
35359 (!((((u_int32_t)(src)\
35372 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__READ(src) \
35373 (((u_int32_t)(src)\
35375 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__WRITE(src) \
35376 (((u_int32_t)(src)\
35378 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__MODIFY(dst, src) \
35380 ~0x00080000U) | (((u_int32_t)(src) <<\
35382 #define MAC_PCU_MISC_MODE2__DUR_ACCOUNT_BY_BA__VERIFY(src) \
35383 (!((((u_int32_t)(src)\
35396 #define MAC_PCU_MISC_MODE2__BUG_28676__READ(src) \
35397 (((u_int32_t)(src)\
35399 #define MAC_PCU_MISC_MODE2__BUG_28676__WRITE(src) \
35400 (((u_int32_t)(src)\
35402 #define MAC_PCU_MISC_MODE2__BUG_28676__MODIFY(dst, src) \
35404 ~0x00100000U) | (((u_int32_t)(src) <<\
35406 #define MAC_PCU_MISC_MODE2__BUG_28676__VERIFY(src) \
35407 (!((((u_int32_t)(src)\
35420 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__READ(src) \
35421 (((u_int32_t)(src)\
35423 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__WRITE(src) \
35424 (((u_int32_t)(src)\
35426 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__MODIFY(dst, src) \
35428 ~0x00200000U) | (((u_int32_t)(src) <<\
35430 #define MAC_PCU_MISC_MODE2__CLEAR_MORE_FRAG__VERIFY(src) \
35431 (!((((u_int32_t)(src)\
35444 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__READ(src) \
35445 (((u_int32_t)(src)\
35447 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__WRITE(src) \
35448 (((u_int32_t)(src)\
35450 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__MODIFY(dst, src) \
35452 ~0x00400000U) | (((u_int32_t)(src) <<\
35454 #define MAC_PCU_MISC_MODE2__IGNORE_TXOP_1ST_PKT__VERIFY(src) \
35455 (!((((u_int32_t)(src)\
35468 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__READ(src) \
35469 (((u_int32_t)(src)\
35471 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__WRITE(src) \
35472 (((u_int32_t)(src)\
35474 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__MODIFY(dst, src) \
35476 ~0x00800000U) | (((u_int32_t)(src) <<\
35478 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_STS_FIX__VERIFY(src) \
35479 (!((((u_int32_t)(src)\
35492 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__READ(src) \
35493 (((u_int32_t)(src)\
35495 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__WRITE(src) \
35496 (((u_int32_t)(src)\
35498 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__MODIFY(dst, src) \
35500 ~0x01000000U) | (((u_int32_t)(src) <<\
35502 #define MAC_PCU_MISC_MODE2__MPDU_DENSITY_WAIT_WEP__VERIFY(src) \
35503 (!((((u_int32_t)(src)\
35516 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__READ(src) \
35517 (((u_int32_t)(src)\
35519 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__WRITE(src) \
35520 (((u_int32_t)(src)\
35522 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__MODIFY(dst, src) \
35524 ~0x02000000U) | (((u_int32_t)(src) <<\
35526 #define MAC_PCU_MISC_MODE2__RCV_TIMESTAMP_FIX__VERIFY(src) \
35527 (!((((u_int32_t)(src)\
35540 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__READ(src) \
35541 (((u_int32_t)(src)\
35543 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__WRITE(src) \
35544 (((u_int32_t)(src)\
35546 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__MODIFY(dst, src) \
35548 ~0x04000000U) | (((u_int32_t)(src) <<\
35550 #define MAC_PCU_MISC_MODE2__PM_FIELD_FOR_NON_CTRL__VERIFY(src) \
35551 (!((((u_int32_t)(src)\
35564 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__READ(src) \
35565 (((u_int32_t)(src)\
35567 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__WRITE(src) \
35568 (((u_int32_t)(src)\
35570 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__MODIFY(dst, src) \
35572 ~0x08000000U) | (((u_int32_t)(src) <<\
35574 #define MAC_PCU_MISC_MODE2__DECOUPLE_DECRYPTION__VERIFY(src) \
35575 (!((((u_int32_t)(src)\
35588 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__READ(src) \
35589 (((u_int32_t)(src)\
35591 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__WRITE(src) \
35592 (((u_int32_t)(src)\
35594 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__MODIFY(dst, src) \
35596 ~0x10000000U) | (((u_int32_t)(src) <<\
35598 #define MAC_PCU_MISC_MODE2__H_TO_SW_DEBUG_MODE__VERIFY(src) \
35599 (!((((u_int32_t)(src)\
35612 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__READ(src) \
35613 (((u_int32_t)(src)\
35615 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__WRITE(src) \
35616 (((u_int32_t)(src)\
35618 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__MODIFY(dst, src) \
35620 ~0x20000000U) | (((u_int32_t)(src) <<\
35622 #define MAC_PCU_MISC_MODE2__TXBF_ACT_RPT_DONE_PASS__VERIFY(src) \
35623 (!((((u_int32_t)(src)\
35636 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__READ(src) \
35637 (((u_int32_t)(src)\
35639 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__WRITE(src) \
35640 (((u_int32_t)(src)\
35642 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__MODIFY(dst, src) \
35644 ~0x40000000U) | (((u_int32_t)(src) <<\
35646 #define MAC_PCU_MISC_MODE2__PCU_LOOP_TXBF__VERIFY(src) \
35647 (!((((u_int32_t)(src)\
35660 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__READ(src) \
35661 (((u_int32_t)(src)\
35663 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__WRITE(src) \
35664 (((u_int32_t)(src)\
35666 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__MODIFY(dst, src) \
35668 ~0x80000000U) | (((u_int32_t)(src) <<\
35670 #define MAC_PCU_MISC_MODE2__CLEAR_WEP_TXBUSY_ON_TXURN__VERIFY(src) \
35671 (!((((u_int32_t)(src)\
35697 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__READ(src) \
35698 (((u_int32_t)(src)\
35700 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__WRITE(src) \
35701 (((u_int32_t)(src)\
35703 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__MODIFY(dst, src) \
35705 ~0xffff0000U) | (((u_int32_t)(src) <<\
35707 #define MAC_PCU_ALT_AES_MUTE_MASK__QOS__VERIFY(src) \
35708 (!((((u_int32_t)(src)\
35728 #define MAC_PCU_WOW6__RXBUF_START_ADDR__READ(src) \
35729 (u_int32_t)(src)\
35748 #define ASYNC_FIFO_REG1__DBG__READ(src) (u_int32_t)(src) & 0x3fffffffU
35749 #define ASYNC_FIFO_REG1__DBG__WRITE(src) ((u_int32_t)(src) & 0x3fffffffU)
35750 #define ASYNC_FIFO_REG1__DBG__MODIFY(dst, src) \
35752 ~0x3fffffffU) | ((u_int32_t)(src) &\
35754 #define ASYNC_FIFO_REG1__DBG__VERIFY(src) \
35755 (!(((u_int32_t)(src)\
35775 #define ASYNC_FIFO_REG2__DBG__READ(src) (u_int32_t)(src) & 0x0fffffffU
35776 #define ASYNC_FIFO_REG2__DBG__WRITE(src) ((u_int32_t)(src) & 0x0fffffffU)
35777 #define ASYNC_FIFO_REG2__DBG__MODIFY(dst, src) \
35779 ~0x0fffffffU) | ((u_int32_t)(src) &\
35781 #define ASYNC_FIFO_REG2__DBG__VERIFY(src) \
35782 (!(((u_int32_t)(src)\
35802 #define ASYNC_FIFO_REG3__DBG__READ(src) (u_int32_t)(src) & 0x000003ffU
35803 #define ASYNC_FIFO_REG3__DBG__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
35804 #define ASYNC_FIFO_REG3__DBG__MODIFY(dst, src) \
35806 ~0x000003ffU) | ((u_int32_t)(src) &\
35808 #define ASYNC_FIFO_REG3__DBG__VERIFY(src) \
35809 (!(((u_int32_t)(src)\
35816 #define ASYNC_FIFO_REG3__DATAPATH_SEL__READ(src) \
35817 (((u_int32_t)(src)\
35819 #define ASYNC_FIFO_REG3__DATAPATH_SEL__WRITE(src) \
35820 (((u_int32_t)(src)\
35822 #define ASYNC_FIFO_REG3__DATAPATH_SEL__MODIFY(dst, src) \
35824 ~0x00000400U) | (((u_int32_t)(src) <<\
35826 #define ASYNC_FIFO_REG3__DATAPATH_SEL__VERIFY(src) \
35827 (!((((u_int32_t)(src)\
35840 #define ASYNC_FIFO_REG3__SFT_RST_N__READ(src) \
35841 (((u_int32_t)(src)\
35843 #define ASYNC_FIFO_REG3__SFT_RST_N__WRITE(src) \
35844 (((u_int32_t)(src)\
35846 #define ASYNC_FIFO_REG3__SFT_RST_N__MODIFY(dst, src) \
35848 ~0x80000000U) | (((u_int32_t)(src) <<\
35850 #define ASYNC_FIFO_REG3__SFT_RST_N__VERIFY(src) \
35851 (!((((u_int32_t)(src)\
35877 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__READ(src) (u_int32_t)(src) & 0x0000ffffU
35878 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__WRITE(src) \
35879 ((u_int32_t)(src)\
35881 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__MODIFY(dst, src) \
35883 ~0x0000ffffU) | ((u_int32_t)(src) &\
35885 #define MAC_PCU_WOW5__RX_ABORT_ENABLE__VERIFY(src) \
35886 (!(((u_int32_t)(src)\
35906 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__READ(src) \
35907 (u_int32_t)(src)\
35909 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__WRITE(src) \
35910 ((u_int32_t)(src)\
35912 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__MODIFY(dst, src) \
35914 ~0x000000ffU) | ((u_int32_t)(src) &\
35916 #define MAC_PCU_WOW_LENGTH1__PATTERN_3__VERIFY(src) \
35917 (!(((u_int32_t)(src)\
35924 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__READ(src) \
35925 (((u_int32_t)(src)\
35927 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__WRITE(src) \
35928 (((u_int32_t)(src)\
35930 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__MODIFY(dst, src) \
35932 ~0x0000ff00U) | (((u_int32_t)(src) <<\
35934 #define MAC_PCU_WOW_LENGTH1__PATTERN_2__VERIFY(src) \
35935 (!((((u_int32_t)(src)\
35942 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__READ(src) \
35943 (((u_int32_t)(src)\
35945 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__WRITE(src) \
35946 (((u_int32_t)(src)\
35948 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__MODIFY(dst, src) \
35950 ~0x00ff0000U) | (((u_int32_t)(src) <<\
35952 #define MAC_PCU_WOW_LENGTH1__PATTERN_1__VERIFY(src) \
35953 (!((((u_int32_t)(src)\
35960 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__READ(src) \
35961 (((u_int32_t)(src)\
35963 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__WRITE(src) \
35964 (((u_int32_t)(src)\
35966 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__MODIFY(dst, src) \
35968 ~0xff000000U) | (((u_int32_t)(src) <<\
35970 #define MAC_PCU_WOW_LENGTH1__PATTERN_0__VERIFY(src) \
35971 (!((((u_int32_t)(src)\
35991 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__READ(src) \
35992 (u_int32_t)(src)\
35994 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__WRITE(src) \
35995 ((u_int32_t)(src)\
35997 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__MODIFY(dst, src) \
35999 ~0x000000ffU) | ((u_int32_t)(src) &\
36001 #define MAC_PCU_WOW_LENGTH2__PATTERN_7__VERIFY(src) \
36002 (!(((u_int32_t)(src)\
36009 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__READ(src) \
36010 (((u_int32_t)(src)\
36012 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__WRITE(src) \
36013 (((u_int32_t)(src)\
36015 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__MODIFY(dst, src) \
36017 ~0x0000ff00U) | (((u_int32_t)(src) <<\
36019 #define MAC_PCU_WOW_LENGTH2__PATTERN_6__VERIFY(src) \
36020 (!((((u_int32_t)(src)\
36027 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__READ(src) \
36028 (((u_int32_t)(src)\
36030 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__WRITE(src) \
36031 (((u_int32_t)(src)\
36033 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__MODIFY(dst, src) \
36035 ~0x00ff0000U) | (((u_int32_t)(src) <<\
36037 #define MAC_PCU_WOW_LENGTH2__PATTERN_5__VERIFY(src) \
36038 (!((((u_int32_t)(src)\
36045 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__READ(src) \
36046 (((u_int32_t)(src)\
36048 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__WRITE(src) \
36049 (((u_int32_t)(src)\
36051 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__MODIFY(dst, src) \
36053 ~0xff000000U) | (((u_int32_t)(src) <<\
36055 #define MAC_PCU_WOW_LENGTH2__PATTERN_4__VERIFY(src) \
36056 (!((((u_int32_t)(src)\
36076 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__READ(src) \
36077 (u_int32_t)(src)\
36079 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__WRITE(src) \
36080 ((u_int32_t)(src)\
36082 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__MODIFY(dst, src) \
36084 ~0x0000ffffU) | ((u_int32_t)(src) &\
36086 #define WOW_PATTERN_MATCH_LESS_THAN_256_BYTES__EN__VERIFY(src) \
36087 (!(((u_int32_t)(src)\
36107 #define MAC_PCU_WOW4__PATTERN_ENABLE__READ(src) (u_int32_t)(src) & 0x000000ffU
36108 #define MAC_PCU_WOW4__PATTERN_ENABLE__WRITE(src) \
36109 ((u_int32_t)(src)\
36111 #define MAC_PCU_WOW4__PATTERN_ENABLE__MODIFY(dst, src) \
36113 ~0x000000ffU) | ((u_int32_t)(src) &\
36115 #define MAC_PCU_WOW4__PATTERN_ENABLE__VERIFY(src) \
36116 (!(((u_int32_t)(src)\
36123 #define MAC_PCU_WOW4__PATTERN_DETECT__READ(src) \
36124 (((u_int32_t)(src)\
36144 #define WOW2_EXACT__LENGTH__READ(src) (u_int32_t)(src) & 0x000000ffU
36145 #define WOW2_EXACT__LENGTH__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
36146 #define WOW2_EXACT__LENGTH__MODIFY(dst, src) \
36148 ~0x000000ffU) | ((u_int32_t)(src) &\
36150 #define WOW2_EXACT__LENGTH__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
36156 #define WOW2_EXACT__OFFSET__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
36157 #define WOW2_EXACT__OFFSET__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U)
36158 #define WOW2_EXACT__OFFSET__MODIFY(dst, src) \
36160 ~0x0000ff00U) | (((u_int32_t)(src) <<\
36162 #define WOW2_EXACT__OFFSET__VERIFY(src) \
36163 (!((((u_int32_t)(src)\
36183 #define PCU_WOW6__OFFSET8__READ(src) (u_int32_t)(src) & 0x000000ffU
36184 #define PCU_WOW6__OFFSET8__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
36185 #define PCU_WOW6__OFFSET8__MODIFY(dst, src) \
36187 ~0x000000ffU) | ((u_int32_t)(src) &\
36189 #define PCU_WOW6__OFFSET8__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
36195 #define PCU_WOW6__OFFSET9__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
36196 #define PCU_WOW6__OFFSET9__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U)
36197 #define PCU_WOW6__OFFSET9__MODIFY(dst, src) \
36199 ~0x0000ff00U) | (((u_int32_t)(src) <<\
36201 #define PCU_WOW6__OFFSET9__VERIFY(src) \
36202 (!((((u_int32_t)(src)\
36209 #define PCU_WOW6__OFFSET10__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16)
36210 #define PCU_WOW6__OFFSET10__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U)
36211 #define PCU_WOW6__OFFSET10__MODIFY(dst, src) \
36213 ~0x00ff0000U) | (((u_int32_t)(src) <<\
36215 #define PCU_WOW6__OFFSET10__VERIFY(src) \
36216 (!((((u_int32_t)(src)\
36223 #define PCU_WOW6__OFFSET11__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24)
36224 #define PCU_WOW6__OFFSET11__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U)
36225 #define PCU_WOW6__OFFSET11__MODIFY(dst, src) \
36227 ~0xff000000U) | (((u_int32_t)(src) <<\
36229 #define PCU_WOW6__OFFSET11__VERIFY(src) \
36230 (!((((u_int32_t)(src)\
36250 #define PCU_WOW7__OFFSET12__READ(src) (u_int32_t)(src) & 0x000000ffU
36251 #define PCU_WOW7__OFFSET12__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
36252 #define PCU_WOW7__OFFSET12__MODIFY(dst, src) \
36254 ~0x000000ffU) | ((u_int32_t)(src) &\
36256 #define PCU_WOW7__OFFSET12__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
36262 #define PCU_WOW7__OFFSET13__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
36263 #define PCU_WOW7__OFFSET13__WRITE(src) (((u_int32_t)(src) << 8) & 0x0000ff00U)
36264 #define PCU_WOW7__OFFSET13__MODIFY(dst, src) \
36266 ~0x0000ff00U) | (((u_int32_t)(src) <<\
36268 #define PCU_WOW7__OFFSET13__VERIFY(src) \
36269 (!((((u_int32_t)(src)\
36276 #define PCU_WOW7__OFFSET14__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16)
36277 #define PCU_WOW7__OFFSET14__WRITE(src) (((u_int32_t)(src) << 16) & 0x00ff0000U)
36278 #define PCU_WOW7__OFFSET14__MODIFY(dst, src) \
36280 ~0x00ff0000U) | (((u_int32_t)(src) <<\
36282 #define PCU_WOW7__OFFSET14__VERIFY(src) \
36283 (!((((u_int32_t)(src)\
36290 #define PCU_WOW7__OFFSET15__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24)
36291 #define PCU_WOW7__OFFSET15__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U)
36292 #define PCU_WOW7__OFFSET15__MODIFY(dst, src) \
36294 ~0xff000000U) | (((u_int32_t)(src) <<\
36296 #define PCU_WOW7__OFFSET15__VERIFY(src) \
36297 (!((((u_int32_t)(src)\
36317 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__READ(src) \
36318 (u_int32_t)(src)\
36320 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__WRITE(src) \
36321 ((u_int32_t)(src)\
36323 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__MODIFY(dst, src) \
36325 ~0x000000ffU) | ((u_int32_t)(src) &\
36327 #define MAC_PCU_WOW_LENGTH3__PATTERN_11__VERIFY(src) \
36328 (!(((u_int32_t)(src)\
36335 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__READ(src) \
36336 (((u_int32_t)(src)\
36338 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__WRITE(src) \
36339 (((u_int32_t)(src)\
36341 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__MODIFY(dst, src) \
36343 ~0x0000ff00U) | (((u_int32_t)(src) <<\
36345 #define MAC_PCU_WOW_LENGTH3__PATTERN_10__VERIFY(src) \
36346 (!((((u_int32_t)(src)\
36353 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__READ(src) \
36354 (((u_int32_t)(src)\
36356 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__WRITE(src) \
36357 (((u_int32_t)(src)\
36359 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__MODIFY(dst, src) \
36361 ~0x00ff0000U) | (((u_int32_t)(src) <<\
36363 #define MAC_PCU_WOW_LENGTH3__PATTERN_9__VERIFY(src) \
36364 (!((((u_int32_t)(src)\
36371 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__READ(src) \
36372 (((u_int32_t)(src)\
36374 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__WRITE(src) \
36375 (((u_int32_t)(src)\
36377 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__MODIFY(dst, src) \
36379 ~0xff000000U) | (((u_int32_t)(src) <<\
36381 #define MAC_PCU_WOW_LENGTH3__PATTERN_8__VERIFY(src) \
36382 (!((((u_int32_t)(src)\
36402 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__READ(src) \
36403 (u_int32_t)(src)\
36405 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__WRITE(src) \
36406 ((u_int32_t)(src)\
36408 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__MODIFY(dst, src) \
36410 ~0x000000ffU) | ((u_int32_t)(src) &\
36412 #define MAC_PCU_WOW_LENGTH4__PATTERN_15__VERIFY(src) \
36413 (!(((u_int32_t)(src)\
36420 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__READ(src) \
36421 (((u_int32_t)(src)\
36423 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__WRITE(src) \
36424 (((u_int32_t)(src)\
36426 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__MODIFY(dst, src) \
36428 ~0x0000ff00U) | (((u_int32_t)(src) <<\
36430 #define MAC_PCU_WOW_LENGTH4__PATTERN_14__VERIFY(src) \
36431 (!((((u_int32_t)(src)\
36438 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__READ(src) \
36439 (((u_int32_t)(src)\
36441 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__WRITE(src) \
36442 (((u_int32_t)(src)\
36444 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__MODIFY(dst, src) \
36446 ~0x00ff0000U) | (((u_int32_t)(src) <<\
36448 #define MAC_PCU_WOW_LENGTH4__PATTERN_13__VERIFY(src) \
36449 (!((((u_int32_t)(src)\
36456 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__READ(src) \
36457 (((u_int32_t)(src)\
36459 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__WRITE(src) \
36460 (((u_int32_t)(src)\
36462 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__MODIFY(dst, src) \
36464 ~0xff000000U) | (((u_int32_t)(src) <<\
36466 #define MAC_PCU_WOW_LENGTH4__PATTERN_12__VERIFY(src) \
36467 (!((((u_int32_t)(src)\
36487 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__READ(src) \
36488 (u_int32_t)(src)\
36490 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__WRITE(src) \
36491 ((u_int32_t)(src)\
36493 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__MODIFY(dst, src) \
36495 ~0x00000001U) | ((u_int32_t)(src) &\
36497 #define MAC_PCU_LOCATION_MODE_CONTROL__ENABLE__VERIFY(src) \
36498 (!(((u_int32_t)(src)\
36524 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__READ(src) \
36525 (u_int32_t)(src)\
36527 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__WRITE(src) \
36528 ((u_int32_t)(src)\
36530 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__MODIFY(dst, src) \
36532 ~0xffffffffU) | ((u_int32_t)(src) &\
36534 #define MAC_PCU_LOCATION_MODE_TIMER__VALUE__VERIFY(src) \
36535 (!(((u_int32_t)(src)\
36555 #define MAC_PCU_TSF2_L32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
36556 #define MAC_PCU_TSF2_L32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
36557 #define MAC_PCU_TSF2_L32__VALUE__MODIFY(dst, src) \
36559 ~0xffffffffU) | ((u_int32_t)(src) &\
36561 #define MAC_PCU_TSF2_L32__VALUE__VERIFY(src) \
36562 (!(((u_int32_t)(src)\
36582 #define MAC_PCU_TSF2_U32__VALUE__READ(src) (u_int32_t)(src) & 0xffffffffU
36583 #define MAC_PCU_TSF2_U32__VALUE__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
36584 #define MAC_PCU_TSF2_U32__VALUE__MODIFY(dst, src) \
36586 ~0xffffffffU) | ((u_int32_t)(src) &\
36588 #define MAC_PCU_TSF2_U32__VALUE__VERIFY(src) \
36589 (!(((u_int32_t)(src)\
36609 #define MAC_PCU_BSSID2_L32__ADDR__READ(src) (u_int32_t)(src) & 0xffffffffU
36610 #define MAC_PCU_BSSID2_L32__ADDR__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
36611 #define MAC_PCU_BSSID2_L32__ADDR__MODIFY(dst, src) \
36613 ~0xffffffffU) | ((u_int32_t)(src) &\
36615 #define MAC_PCU_BSSID2_L32__ADDR__VERIFY(src) \
36616 (!(((u_int32_t)(src)\
36636 #define MAC_PCU_BSSID2_U16__ADDR__READ(src) (u_int32_t)(src) & 0x0000ffffU
36637 #define MAC_PCU_BSSID2_U16__ADDR__WRITE(src) ((u_int32_t)(src) & 0x0000ffffU)
36638 #define MAC_PCU_BSSID2_U16__ADDR__MODIFY(dst, src) \
36640 ~0x0000ffffU) | ((u_int32_t)(src) &\
36642 #define MAC_PCU_BSSID2_U16__ADDR__VERIFY(src) \
36643 (!(((u_int32_t)(src)\
36650 #define MAC_PCU_BSSID2_U16__ENABLE__READ(src) \
36651 (((u_int32_t)(src)\
36653 #define MAC_PCU_BSSID2_U16__ENABLE__WRITE(src) \
36654 (((u_int32_t)(src)\
36656 #define MAC_PCU_BSSID2_U16__ENABLE__MODIFY(dst, src) \
36658 ~0x00010000U) | (((u_int32_t)(src) <<\
36660 #define MAC_PCU_BSSID2_U16__ENABLE__VERIFY(src) \
36661 (!((((u_int32_t)(src)\
36687 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__READ(src) \
36688 (u_int32_t)(src)\
36690 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__WRITE(src) \
36691 ((u_int32_t)(src)\
36693 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__MODIFY(dst, src) \
36695 ~0x00000001U) | ((u_int32_t)(src) &\
36697 #define MAC_PCU_DIRECT_CONNECT__AP_STA_ENABLE__VERIFY(src) \
36698 (!(((u_int32_t)(src)\
36711 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__READ(src) \
36712 (((u_int32_t)(src)\
36714 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__WRITE(src) \
36715 (((u_int32_t)(src)\
36717 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__MODIFY(dst, src) \
36719 ~0x00000010U) | (((u_int32_t)(src) <<\
36721 #define MAC_PCU_DIRECT_CONNECT__TBTT_TIMER_0_8_SEL__VERIFY(src) \
36722 (!((((u_int32_t)(src)\
36735 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__READ(src) \
36736 (((u_int32_t)(src)\
36738 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__WRITE(src) \
36739 (((u_int32_t)(src)\
36741 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__MODIFY(dst, src) \
36743 ~0x00000020U) | (((u_int32_t)(src) <<\
36745 #define MAC_PCU_DIRECT_CONNECT__DMA_BALERT_TIMER_1_9_SEL__VERIFY(src) \
36746 (!((((u_int32_t)(src)\
36759 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__READ(src) \
36760 (((u_int32_t)(src)\
36762 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__WRITE(src) \
36763 (((u_int32_t)(src)\
36765 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__MODIFY(dst, src) \
36767 ~0x00000040U) | (((u_int32_t)(src) <<\
36769 #define MAC_PCU_DIRECT_CONNECT__SW_BALERT_TIMER_2_10_SEL__VERIFY(src) \
36770 (!((((u_int32_t)(src)\
36783 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__READ(src) \
36784 (((u_int32_t)(src)\
36786 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__WRITE(src) \
36787 (((u_int32_t)(src)\
36789 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__MODIFY(dst, src) \
36791 ~0x00000080U) | (((u_int32_t)(src) <<\
36793 #define MAC_PCU_DIRECT_CONNECT__HCF_TO_TIMER_3_11_SEL__VERIFY(src) \
36794 (!((((u_int32_t)(src)\
36807 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__READ(src) \
36808 (((u_int32_t)(src)\
36810 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__WRITE(src) \
36811 (((u_int32_t)(src)\
36813 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__MODIFY(dst, src) \
36815 ~0x00000100U) | (((u_int32_t)(src) <<\
36817 #define MAC_PCU_DIRECT_CONNECT__NEXT_TIM_TIMER_4_12_SEL__VERIFY(src) \
36818 (!((((u_int32_t)(src)\
36831 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__READ(src) \
36832 (((u_int32_t)(src)\
36834 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__WRITE(src) \
36835 (((u_int32_t)(src)\
36837 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__MODIFY(dst, src) \
36839 ~0x00000200U) | (((u_int32_t)(src) <<\
36841 #define MAC_PCU_DIRECT_CONNECT__NEXT_DTIM_TIMER_5_13_SEL__VERIFY(src) \
36842 (!((((u_int32_t)(src)\
36855 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__READ(src) \
36856 (((u_int32_t)(src)\
36858 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__WRITE(src) \
36859 (((u_int32_t)(src)\
36861 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__MODIFY(dst, src) \
36863 ~0x00000400U) | (((u_int32_t)(src) <<\
36865 #define MAC_PCU_DIRECT_CONNECT__QUIET_TM_TIMER_6_14_SEL__VERIFY(src) \
36866 (!((((u_int32_t)(src)\
36879 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__READ(src) \
36880 (((u_int32_t)(src)\
36882 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__WRITE(src) \
36883 (((u_int32_t)(src)\
36885 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__MODIFY(dst, src) \
36887 ~0x00000800U) | (((u_int32_t)(src) <<\
36889 #define MAC_PCU_DIRECT_CONNECT__TBTT2_TIMER_0_8_SEL__VERIFY(src) \
36890 (!((((u_int32_t)(src)\
36903 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__READ(src) \
36904 (((u_int32_t)(src)\
36906 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__WRITE(src) \
36907 (((u_int32_t)(src)\
36909 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__MODIFY(dst, src) \
36911 ~0x00001000U) | (((u_int32_t)(src) <<\
36913 #define MAC_PCU_DIRECT_CONNECT__AP_TSF_1_2_SEL__VERIFY(src) \
36914 (!((((u_int32_t)(src)\
36927 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__READ(src) \
36928 (((u_int32_t)(src)\
36930 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__WRITE(src) \
36931 (((u_int32_t)(src)\
36933 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__MODIFY(dst, src) \
36935 ~0x00002000U) | (((u_int32_t)(src) <<\
36937 #define MAC_PCU_DIRECT_CONNECT__STA_TSF_1_2_SEL__VERIFY(src) \
36938 (!((((u_int32_t)(src)\
36964 #define MAC_PCU_TID_TO_AC__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
36965 #define MAC_PCU_TID_TO_AC__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
36966 #define MAC_PCU_TID_TO_AC__DATA__MODIFY(dst, src) \
36968 ~0xffffffffU) | ((u_int32_t)(src) &\
36970 #define MAC_PCU_TID_TO_AC__DATA__VERIFY(src) \
36971 (!(((u_int32_t)(src)\
36991 #define MAC_PCU_HP_QUEUE__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U
36992 #define MAC_PCU_HP_QUEUE__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
36993 #define MAC_PCU_HP_QUEUE__ENABLE__MODIFY(dst, src) \
36995 ~0x00000001U) | ((u_int32_t)(src) &\
36997 #define MAC_PCU_HP_QUEUE__ENABLE__VERIFY(src) \
36998 (!(((u_int32_t)(src)\
37011 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__READ(src) \
37012 (((u_int32_t)(src)\
37014 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__WRITE(src) \
37015 (((u_int32_t)(src)\
37017 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__MODIFY(dst, src) \
37019 ~0x00000002U) | (((u_int32_t)(src) <<\
37021 #define MAC_PCU_HP_QUEUE__AC_MASK_BE__VERIFY(src) \
37022 (!((((u_int32_t)(src)\
37035 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__READ(src) \
37036 (((u_int32_t)(src)\
37038 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__WRITE(src) \
37039 (((u_int32_t)(src)\
37041 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__MODIFY(dst, src) \
37043 ~0x00000004U) | (((u_int32_t)(src) <<\
37045 #define MAC_PCU_HP_QUEUE__AC_MASK_BK__VERIFY(src) \
37046 (!((((u_int32_t)(src)\
37059 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__READ(src) \
37060 (((u_int32_t)(src)\
37062 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__WRITE(src) \
37063 (((u_int32_t)(src)\
37065 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__MODIFY(dst, src) \
37067 ~0x00000008U) | (((u_int32_t)(src) <<\
37069 #define MAC_PCU_HP_QUEUE__AC_MASK_VI__VERIFY(src) \
37070 (!((((u_int32_t)(src)\
37083 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__READ(src) \
37084 (((u_int32_t)(src)\
37086 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__WRITE(src) \
37087 (((u_int32_t)(src)\
37089 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__MODIFY(dst, src) \
37091 ~0x00000010U) | (((u_int32_t)(src) <<\
37093 #define MAC_PCU_HP_QUEUE__AC_MASK_VO__VERIFY(src) \
37094 (!((((u_int32_t)(src)\
37107 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__READ(src) \
37108 (((u_int32_t)(src)\
37110 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__WRITE(src) \
37111 (((u_int32_t)(src)\
37113 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__MODIFY(dst, src) \
37115 ~0x00000020U) | (((u_int32_t)(src) <<\
37117 #define MAC_PCU_HP_QUEUE__HPQON_UAPSD__VERIFY(src) \
37118 (!((((u_int32_t)(src)\
37131 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__READ(src) \
37132 (((u_int32_t)(src)\
37134 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__WRITE(src) \
37135 (((u_int32_t)(src)\
37137 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__MODIFY(dst, src) \
37139 ~0x00000040U) | (((u_int32_t)(src) <<\
37141 #define MAC_PCU_HP_QUEUE__FRAME_FILTER_ENABLE0__VERIFY(src) \
37142 (!((((u_int32_t)(src)\
37155 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__READ(src) \
37156 (((u_int32_t)(src)\
37158 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__WRITE(src) \
37159 (((u_int32_t)(src)\
37161 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__MODIFY(dst, src) \
37163 ~0x00000080U) | (((u_int32_t)(src) <<\
37165 #define MAC_PCU_HP_QUEUE__FRAME_BSSID_MATCH0__VERIFY(src) \
37166 (!((((u_int32_t)(src)\
37179 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__READ(src) \
37180 (((u_int32_t)(src)\
37182 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__WRITE(src) \
37183 (((u_int32_t)(src)\
37185 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__MODIFY(dst, src) \
37187 ~0x00000300U) | (((u_int32_t)(src) <<\
37189 #define MAC_PCU_HP_QUEUE__FRAME_TYPE0__VERIFY(src) \
37190 (!((((u_int32_t)(src)\
37197 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__READ(src) \
37198 (((u_int32_t)(src)\
37200 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__WRITE(src) \
37201 (((u_int32_t)(src)\
37203 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__MODIFY(dst, src) \
37205 ~0x00000c00U) | (((u_int32_t)(src) <<\
37207 #define MAC_PCU_HP_QUEUE__FRAME_TYPE_MASK0__VERIFY(src) \
37208 (!((((u_int32_t)(src)\
37215 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__READ(src) \
37216 (((u_int32_t)(src)\
37218 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__WRITE(src) \
37219 (((u_int32_t)(src)\
37221 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__MODIFY(dst, src) \
37223 ~0x0000f000U) | (((u_int32_t)(src) <<\
37225 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE0__VERIFY(src) \
37226 (!((((u_int32_t)(src)\
37233 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__READ(src) \
37234 (((u_int32_t)(src)\
37236 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__WRITE(src) \
37237 (((u_int32_t)(src)\
37239 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__MODIFY(dst, src) \
37241 ~0x000f0000U) | (((u_int32_t)(src) <<\
37243 #define MAC_PCU_HP_QUEUE__FRAME_SUBTYPE_MASK0__VERIFY(src) \
37244 (!((((u_int32_t)(src)\
37251 #define MAC_PCU_HP_QUEUE__UAPSD_EN__READ(src) \
37252 (((u_int32_t)(src)\
37254 #define MAC_PCU_HP_QUEUE__UAPSD_EN__WRITE(src) \
37255 (((u_int32_t)(src)\
37257 #define MAC_PCU_HP_QUEUE__UAPSD_EN__MODIFY(dst, src) \
37259 ~0x00100000U) | (((u_int32_t)(src) <<\
37261 #define MAC_PCU_HP_QUEUE__UAPSD_EN__VERIFY(src) \
37262 (!((((u_int32_t)(src)\
37288 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__READ(src) \
37289 (u_int32_t)(src)\
37291 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__WRITE(src) \
37292 ((u_int32_t)(src)\
37294 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__MODIFY(dst, src) \
37296 ~0xffffffffU) | ((u_int32_t)(src) &\
37298 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS0__VALUE__VERIFY(src) \
37299 (!(((u_int32_t)(src)\
37319 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__READ(src) \
37320 (u_int32_t)(src)\
37322 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__WRITE(src) \
37323 ((u_int32_t)(src)\
37325 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__MODIFY(dst, src) \
37327 ~0xffffffffU) | ((u_int32_t)(src) &\
37329 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS1__VALUE__VERIFY(src) \
37330 (!(((u_int32_t)(src)\
37350 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__READ(src) \
37351 (u_int32_t)(src)\
37353 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__WRITE(src) \
37354 ((u_int32_t)(src)\
37356 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__MODIFY(dst, src) \
37358 ~0xffffffffU) | ((u_int32_t)(src) &\
37360 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS2__VALUE__VERIFY(src) \
37361 (!(((u_int32_t)(src)\
37381 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__READ(src) \
37382 (u_int32_t)(src)\
37384 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__WRITE(src) \
37385 ((u_int32_t)(src)\
37387 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__MODIFY(dst, src) \
37389 ~0xffffffffU) | ((u_int32_t)(src) &\
37391 #define MAC_PCU_BLUETOOTH_BT_WEIGHTS3__VALUE__VERIFY(src) \
37392 (!(((u_int32_t)(src)\
37412 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__READ(src) \
37413 (u_int32_t)(src)\
37415 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__WRITE(src) \
37416 ((u_int32_t)(src)\
37418 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__MODIFY(dst, src) \
37420 ~0xffffffffU) | ((u_int32_t)(src) &\
37422 #define MAC_PCU_AGC_SATURATION_CNT0__VALUE__VERIFY(src) \
37423 (!(((u_int32_t)(src)\
37443 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__READ(src) \
37444 (u_int32_t)(src)\
37446 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__WRITE(src) \
37447 ((u_int32_t)(src)\
37449 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__MODIFY(dst, src) \
37451 ~0xffffffffU) | ((u_int32_t)(src) &\
37453 #define MAC_PCU_AGC_SATURATION_CNT1__VALUE__VERIFY(src) \
37454 (!(((u_int32_t)(src)\
37474 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__READ(src) \
37475 (u_int32_t)(src)\
37477 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__WRITE(src) \
37478 ((u_int32_t)(src)\
37480 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__MODIFY(dst, src) \
37482 ~0xffffffffU) | ((u_int32_t)(src) &\
37484 #define MAC_PCU_AGC_SATURATION_CNT2__VALUE__VERIFY(src) \
37485 (!(((u_int32_t)(src)\
37505 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__READ(src) \
37506 (u_int32_t)(src)\
37508 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__WRITE(src) \
37509 ((u_int32_t)(src)\
37511 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__MODIFY(dst, src) \
37513 ~0x00000001U) | ((u_int32_t)(src) &\
37515 #define MAC_PCU_HW_BCN_PROC1__CRC_ENABLE__VERIFY(src) \
37516 (!(((u_int32_t)(src)\
37529 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__READ(src) \
37530 (((u_int32_t)(src)\
37532 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__WRITE(src) \
37533 (((u_int32_t)(src)\
37535 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__MODIFY(dst, src) \
37537 ~0x00000002U) | (((u_int32_t)(src) <<\
37539 #define MAC_PCU_HW_BCN_PROC1__RESET_CRC__VERIFY(src) \
37540 (!((((u_int32_t)(src)\
37553 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__READ(src) \
37554 (((u_int32_t)(src)\
37556 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__WRITE(src) \
37557 (((u_int32_t)(src)\
37559 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__MODIFY(dst, src) \
37561 ~0x00000004U) | (((u_int32_t)(src) <<\
37563 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_BCN_INTVL__VERIFY(src) \
37564 (!((((u_int32_t)(src)\
37577 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__READ(src) \
37578 (((u_int32_t)(src)\
37580 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__WRITE(src) \
37581 (((u_int32_t)(src)\
37583 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__MODIFY(dst, src) \
37585 ~0x00000008U) | (((u_int32_t)(src) <<\
37587 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_CAP_INFO__VERIFY(src) \
37588 (!((((u_int32_t)(src)\
37601 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__READ(src) \
37602 (((u_int32_t)(src)\
37604 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__WRITE(src) \
37605 (((u_int32_t)(src)\
37607 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__MODIFY(dst, src) \
37609 ~0x00000010U) | (((u_int32_t)(src) <<\
37611 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_TIM_ELM__VERIFY(src) \
37612 (!((((u_int32_t)(src)\
37625 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__READ(src) \
37626 (((u_int32_t)(src)\
37628 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__WRITE(src) \
37629 (((u_int32_t)(src)\
37631 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__MODIFY(dst, src) \
37633 ~0x00000020U) | (((u_int32_t)(src) <<\
37635 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM0__VERIFY(src) \
37636 (!((((u_int32_t)(src)\
37649 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__READ(src) \
37650 (((u_int32_t)(src)\
37652 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__WRITE(src) \
37653 (((u_int32_t)(src)\
37655 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__MODIFY(dst, src) \
37657 ~0x00000040U) | (((u_int32_t)(src) <<\
37659 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM1__VERIFY(src) \
37660 (!((((u_int32_t)(src)\
37673 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__READ(src) \
37674 (((u_int32_t)(src)\
37676 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__WRITE(src) \
37677 (((u_int32_t)(src)\
37679 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__MODIFY(dst, src) \
37681 ~0x00000080U) | (((u_int32_t)(src) <<\
37683 #define MAC_PCU_HW_BCN_PROC1__EXCLUDE_ELM2__VERIFY(src) \
37684 (!((((u_int32_t)(src)\
37697 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__READ(src) \
37698 (((u_int32_t)(src)\
37700 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__WRITE(src) \
37701 (((u_int32_t)(src)\
37703 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__MODIFY(dst, src) \
37705 ~0x0000ff00U) | (((u_int32_t)(src) <<\
37707 #define MAC_PCU_HW_BCN_PROC1__ELM0_ID__VERIFY(src) \
37708 (!((((u_int32_t)(src)\
37715 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__READ(src) \
37716 (((u_int32_t)(src)\
37718 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__WRITE(src) \
37719 (((u_int32_t)(src)\
37721 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__MODIFY(dst, src) \
37723 ~0x00ff0000U) | (((u_int32_t)(src) <<\
37725 #define MAC_PCU_HW_BCN_PROC1__ELM1_ID__VERIFY(src) \
37726 (!((((u_int32_t)(src)\
37733 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__READ(src) \
37734 (((u_int32_t)(src)\
37736 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__WRITE(src) \
37737 (((u_int32_t)(src)\
37739 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__MODIFY(dst, src) \
37741 ~0xff000000U) | (((u_int32_t)(src) <<\
37743 #define MAC_PCU_HW_BCN_PROC1__ELM2_ID__VERIFY(src) \
37744 (!((((u_int32_t)(src)\
37764 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__READ(src) \
37765 (u_int32_t)(src)\
37767 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__WRITE(src) \
37768 ((u_int32_t)(src)\
37770 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__MODIFY(dst, src) \
37772 ~0x00000001U) | ((u_int32_t)(src) &\
37774 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL_ENABLE__VERIFY(src) \
37775 (!(((u_int32_t)(src)\
37788 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__READ(src) \
37789 (((u_int32_t)(src)\
37791 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__WRITE(src) \
37792 (((u_int32_t)(src)\
37794 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__MODIFY(dst, src) \
37796 ~0x00000002U) | (((u_int32_t)(src) <<\
37798 #define MAC_PCU_HW_BCN_PROC2__RESET_INTERVAL__VERIFY(src) \
37799 (!((((u_int32_t)(src)\
37812 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__READ(src) \
37813 (((u_int32_t)(src)\
37815 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__WRITE(src) \
37816 (((u_int32_t)(src)\
37818 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__MODIFY(dst, src) \
37820 ~0x00000004U) | (((u_int32_t)(src) <<\
37822 #define MAC_PCU_HW_BCN_PROC2__EXCLUDE_ELM3__VERIFY(src) \
37823 (!((((u_int32_t)(src)\
37836 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__READ(src) \
37837 (((u_int32_t)(src)\
37839 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__WRITE(src) \
37840 (((u_int32_t)(src)\
37842 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__MODIFY(dst, src) \
37844 ~0x0000ff00U) | (((u_int32_t)(src) <<\
37846 #define MAC_PCU_HW_BCN_PROC2__FILTER_INTERVAL__VERIFY(src) \
37847 (!((((u_int32_t)(src)\
37854 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__READ(src) \
37855 (((u_int32_t)(src)\
37857 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__WRITE(src) \
37858 (((u_int32_t)(src)\
37860 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__MODIFY(dst, src) \
37862 ~0x00ff0000U) | (((u_int32_t)(src) <<\
37864 #define MAC_PCU_HW_BCN_PROC2__ELM3_ID__VERIFY(src) \
37865 (!((((u_int32_t)(src)\
37885 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__READ(src) \
37886 (u_int32_t)(src)\
37888 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__WRITE(src) \
37889 ((u_int32_t)(src)\
37891 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__MODIFY(dst, src) \
37893 ~0x00000001U) | ((u_int32_t)(src) &\
37895 #define MAC_PCU_MISC_MODE3__BUG_55702_FIX_ENABLE__VERIFY(src) \
37896 (!(((u_int32_t)(src)\
37909 #define MAC_PCU_MISC_MODE3__AES_3STREAM__READ(src) \
37910 (((u_int32_t)(src)\
37912 #define MAC_PCU_MISC_MODE3__AES_3STREAM__WRITE(src) \
37913 (((u_int32_t)(src)\
37915 #define MAC_PCU_MISC_MODE3__AES_3STREAM__MODIFY(dst, src) \
37917 ~0x00000002U) | (((u_int32_t)(src) <<\
37919 #define MAC_PCU_MISC_MODE3__AES_3STREAM__VERIFY(src) \
37920 (!((((u_int32_t)(src)\
37933 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__READ(src) \
37934 (((u_int32_t)(src)\
37936 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__WRITE(src) \
37937 (((u_int32_t)(src)\
37939 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__MODIFY(dst, src) \
37941 ~0x00000004U) | (((u_int32_t)(src) <<\
37943 #define MAC_PCU_MISC_MODE3__REGULAR_SOUNDING__VERIFY(src) \
37944 (!((((u_int32_t)(src)\
37957 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__READ(src) \
37958 (((u_int32_t)(src)\
37960 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__WRITE(src) \
37961 (((u_int32_t)(src)\
37963 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__MODIFY(dst, src) \
37965 ~0x00000008U) | (((u_int32_t)(src) <<\
37967 #define MAC_PCU_MISC_MODE3__BUG_58011_FIX_ENABLE__VERIFY(src) \
37968 (!((((u_int32_t)(src)\
37981 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__READ(src) \
37982 (((u_int32_t)(src)\
37984 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__WRITE(src) \
37985 (((u_int32_t)(src)\
37987 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__MODIFY(dst, src) \
37989 ~0x00000010U) | (((u_int32_t)(src) <<\
37991 #define MAC_PCU_MISC_MODE3__BUG_56991_FIX_ENABLE__VERIFY(src) \
37992 (!((((u_int32_t)(src)\
38005 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__READ(src) \
38006 (((u_int32_t)(src)\
38008 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__WRITE(src) \
38009 (((u_int32_t)(src)\
38011 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__MODIFY(dst, src) \
38013 ~0x00000020U) | (((u_int32_t)(src) <<\
38015 #define MAC_PCU_MISC_MODE3__WOW_ADDR1_MASK_ENABLE__VERIFY(src) \
38016 (!((((u_int32_t)(src)\
38029 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__READ(src) \
38030 (((u_int32_t)(src)\
38032 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__WRITE(src) \
38033 (((u_int32_t)(src)\
38035 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__MODIFY(dst, src) \
38037 ~0x00000040U) | (((u_int32_t)(src) <<\
38039 #define MAC_PCU_MISC_MODE3__BUG_61936_FIX_ENABLE__VERIFY(src) \
38040 (!((((u_int32_t)(src)\
38053 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__READ(src) \
38054 (((u_int32_t)(src)\
38056 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__WRITE(src) \
38057 (((u_int32_t)(src)\
38059 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__MODIFY(dst, src) \
38061 ~0x00000080U) | (((u_int32_t)(src) <<\
38063 #define MAC_PCU_MISC_MODE3__CHECK_LENGTH_FOR_BA__VERIFY(src) \
38064 (!((((u_int32_t)(src)\
38077 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__READ(src) \
38078 (((u_int32_t)(src)\
38080 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__WRITE(src) \
38081 (((u_int32_t)(src)\
38083 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__MODIFY(dst, src) \
38085 ~0x0000ff00U) | (((u_int32_t)(src) <<\
38087 #define MAC_PCU_MISC_MODE3__BA_FRAME_LENGTH__VERIFY(src) \
38088 (!((((u_int32_t)(src)\
38095 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__READ(src) \
38096 (((u_int32_t)(src)\
38098 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__WRITE(src) \
38099 (((u_int32_t)(src)\
38101 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__MODIFY(dst, src) \
38103 ~0x00010000U) | (((u_int32_t)(src) <<\
38105 #define MAC_PCU_MISC_MODE3__MATCH_TID_FOR_BA__VERIFY(src) \
38106 (!((((u_int32_t)(src)\
38119 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__READ(src) \
38120 (((u_int32_t)(src)\
38122 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__WRITE(src) \
38123 (((u_int32_t)(src)\
38125 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__MODIFY(dst, src) \
38127 ~0x00020000U) | (((u_int32_t)(src) <<\
38129 #define MAC_PCU_MISC_MODE3__WAPI_ORDER_MASK__VERIFY(src) \
38130 (!((((u_int32_t)(src)\
38143 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__READ(src) \
38144 (((u_int32_t)(src)\
38146 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__WRITE(src) \
38147 (((u_int32_t)(src)\
38149 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__MODIFY(dst, src) \
38151 ~0x00040000U) | (((u_int32_t)(src) <<\
38153 #define MAC_PCU_MISC_MODE3__BB_LDPC_EN__VERIFY(src) \
38154 (!((((u_int32_t)(src)\
38180 #define MAC_PCU_TXBUF_BA__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
38181 #define MAC_PCU_TXBUF_BA__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
38182 #define MAC_PCU_TXBUF_BA__DATA__MODIFY(dst, src) \
38184 ~0xffffffffU) | ((u_int32_t)(src) &\
38186 #define MAC_PCU_TXBUF_BA__DATA__VERIFY(src) \
38187 (!(((u_int32_t)(src)\
38207 #define MAC_PCU_KEY_CACHE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
38208 #define MAC_PCU_KEY_CACHE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
38209 #define MAC_PCU_KEY_CACHE__DATA__MODIFY(dst, src) \
38211 ~0xffffffffU) | ((u_int32_t)(src) &\
38213 #define MAC_PCU_KEY_CACHE__DATA__VERIFY(src) \
38214 (!(((u_int32_t)(src)\
38234 #define MAC_PCU_BUF__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
38235 #define MAC_PCU_BUF__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
38236 #define MAC_PCU_BUF__DATA__MODIFY(dst, src) \
38238 ~0xffffffffU) | ((u_int32_t)(src) &\
38240 #define MAC_PCU_BUF__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
38259 #define TIMING_CONTROLS_1__STE_THR__READ(src) (u_int32_t)(src) & 0x0000007fU
38260 #define TIMING_CONTROLS_1__STE_THR__WRITE(src) ((u_int32_t)(src) & 0x0000007fU)
38261 #define TIMING_CONTROLS_1__STE_THR__MODIFY(dst, src) \
38263 ~0x0000007fU) | ((u_int32_t)(src) &\
38265 #define TIMING_CONTROLS_1__STE_THR__VERIFY(src) \
38266 (!(((u_int32_t)(src)\
38273 #define TIMING_CONTROLS_1__STE_TO_LONG1__READ(src) \
38274 (((u_int32_t)(src)\
38276 #define TIMING_CONTROLS_1__STE_TO_LONG1__WRITE(src) \
38277 (((u_int32_t)(src)\
38279 #define TIMING_CONTROLS_1__STE_TO_LONG1__MODIFY(dst, src) \
38281 ~0x00001f80U) | (((u_int32_t)(src) <<\
38283 #define TIMING_CONTROLS_1__STE_TO_LONG1__VERIFY(src) \
38284 (!((((u_int32_t)(src)\
38291 #define TIMING_CONTROLS_1__TIMING_BACKOFF__READ(src) \
38292 (((u_int32_t)(src)\
38294 #define TIMING_CONTROLS_1__TIMING_BACKOFF__WRITE(src) \
38295 (((u_int32_t)(src)\
38297 #define TIMING_CONTROLS_1__TIMING_BACKOFF__MODIFY(dst, src) \
38299 ~0x0001e000U) | (((u_int32_t)(src) <<\
38301 #define TIMING_CONTROLS_1__TIMING_BACKOFF__VERIFY(src) \
38302 (!((((u_int32_t)(src)\
38309 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__READ(src) \
38310 (((u_int32_t)(src)\
38312 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__WRITE(src) \
38313 (((u_int32_t)(src)\
38315 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__MODIFY(dst, src) \
38317 ~0x00020000U) | (((u_int32_t)(src) <<\
38319 #define TIMING_CONTROLS_1__ENABLE_HT_FINE_PPM__VERIFY(src) \
38320 (!((((u_int32_t)(src)\
38333 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__READ(src) \
38334 (((u_int32_t)(src)\
38336 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__WRITE(src) \
38337 (((u_int32_t)(src)\
38339 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__MODIFY(dst, src) \
38341 ~0x000c0000U) | (((u_int32_t)(src) <<\
38343 #define TIMING_CONTROLS_1__HT_FINE_PPM_STREAM__VERIFY(src) \
38344 (!((((u_int32_t)(src)\
38351 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__READ(src) \
38352 (((u_int32_t)(src)\
38354 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__WRITE(src) \
38355 (((u_int32_t)(src)\
38357 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__MODIFY(dst, src) \
38359 ~0x00300000U) | (((u_int32_t)(src) <<\
38361 #define TIMING_CONTROLS_1__HT_FINE_PPM_QAM__VERIFY(src) \
38362 (!((((u_int32_t)(src)\
38369 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__READ(src) \
38370 (((u_int32_t)(src)\
38372 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__WRITE(src) \
38373 (((u_int32_t)(src)\
38375 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__MODIFY(dst, src) \
38377 ~0x00400000U) | (((u_int32_t)(src) <<\
38379 #define TIMING_CONTROLS_1__ENABLE_LONG_CHANFIL__VERIFY(src) \
38380 (!((((u_int32_t)(src)\
38393 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__READ(src) \
38394 (((u_int32_t)(src)\
38396 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__WRITE(src) \
38397 (((u_int32_t)(src)\
38399 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__MODIFY(dst, src) \
38401 ~0x00800000U) | (((u_int32_t)(src) <<\
38403 #define TIMING_CONTROLS_1__ENABLE_RX_STBC__VERIFY(src) \
38404 (!((((u_int32_t)(src)\
38417 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__READ(src) \
38418 (((u_int32_t)(src)\
38420 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__WRITE(src) \
38421 (((u_int32_t)(src)\
38423 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__MODIFY(dst, src) \
38425 ~0x01000000U) | (((u_int32_t)(src) <<\
38427 #define TIMING_CONTROLS_1__ENABLE_CHANNEL_FILTER__VERIFY(src) \
38428 (!((((u_int32_t)(src)\
38441 #define TIMING_CONTROLS_1__FALSE_ALARM__READ(src) \
38442 (((u_int32_t)(src)\
38444 #define TIMING_CONTROLS_1__FALSE_ALARM__WRITE(src) \
38445 (((u_int32_t)(src)\
38447 #define TIMING_CONTROLS_1__FALSE_ALARM__MODIFY(dst, src) \
38449 ~0x06000000U) | (((u_int32_t)(src) <<\
38451 #define TIMING_CONTROLS_1__FALSE_ALARM__VERIFY(src) \
38452 (!((((u_int32_t)(src)\
38459 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__READ(src) \
38460 (((u_int32_t)(src)\
38462 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__WRITE(src) \
38463 (((u_int32_t)(src)\
38465 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__MODIFY(dst, src) \
38467 ~0x08000000U) | (((u_int32_t)(src) <<\
38469 #define TIMING_CONTROLS_1__ENABLE_LONG_RESCALE__VERIFY(src) \
38470 (!((((u_int32_t)(src)\
38483 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__READ(src) \
38484 (((u_int32_t)(src)\
38486 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__WRITE(src) \
38487 (((u_int32_t)(src)\
38489 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__MODIFY(dst, src) \
38491 ~0x10000000U) | (((u_int32_t)(src) <<\
38493 #define TIMING_CONTROLS_1__TIMING_LEAK_ENABLE__VERIFY(src) \
38494 (!((((u_int32_t)(src)\
38507 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__READ(src) \
38508 (((u_int32_t)(src)\
38510 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__WRITE(src) \
38511 (((u_int32_t)(src)\
38513 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__MODIFY(dst, src) \
38515 ~0x60000000U) | (((u_int32_t)(src) <<\
38517 #define TIMING_CONTROLS_1__COARSE_PPM_SELECT__VERIFY(src) \
38518 (!((((u_int32_t)(src)\
38525 #define TIMING_CONTROLS_1__FFT_SCALING__READ(src) \
38526 (((u_int32_t)(src)\
38528 #define TIMING_CONTROLS_1__FFT_SCALING__WRITE(src) \
38529 (((u_int32_t)(src)\
38531 #define TIMING_CONTROLS_1__FFT_SCALING__MODIFY(dst, src) \
38533 ~0x80000000U) | (((u_int32_t)(src) <<\
38535 #define TIMING_CONTROLS_1__FFT_SCALING__VERIFY(src) \
38536 (!((((u_int32_t)(src)\
38562 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__READ(src) \
38563 (u_int32_t)(src)\
38565 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__WRITE(src) \
38566 ((u_int32_t)(src)\
38568 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__MODIFY(dst, src) \
38570 ~0x00000fffU) | ((u_int32_t)(src) &\
38572 #define TIMING_CONTROLS_2__FORCED_DELTA_PHI_SYMBOL__VERIFY(src) \
38573 (!(((u_int32_t)(src)\
38580 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__READ(src) \
38581 (((u_int32_t)(src)\
38583 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__WRITE(src) \
38584 (((u_int32_t)(src)\
38586 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__MODIFY(dst, src) \
38588 ~0x00001000U) | (((u_int32_t)(src) <<\
38590 #define TIMING_CONTROLS_2__FORCE_DELTA_PHI_SYMBOL__VERIFY(src) \
38591 (!((((u_int32_t)(src)\
38604 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__READ(src) \
38605 (((u_int32_t)(src)\
38607 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__WRITE(src) \
38608 (((u_int32_t)(src)\
38610 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__MODIFY(dst, src) \
38612 ~0x00002000U) | (((u_int32_t)(src) <<\
38614 #define TIMING_CONTROLS_2__ENABLE_MAGNITUDE_TRACK__VERIFY(src) \
38615 (!((((u_int32_t)(src)\
38628 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__READ(src) \
38629 (((u_int32_t)(src)\
38631 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__WRITE(src) \
38632 (((u_int32_t)(src)\
38634 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__MODIFY(dst, src) \
38636 ~0x00004000U) | (((u_int32_t)(src) <<\
38638 #define TIMING_CONTROLS_2__ENABLE_SLOPE_FILTER__VERIFY(src) \
38639 (!((((u_int32_t)(src)\
38652 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__READ(src) \
38653 (((u_int32_t)(src)\
38655 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__WRITE(src) \
38656 (((u_int32_t)(src)\
38658 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__MODIFY(dst, src) \
38660 ~0x00008000U) | (((u_int32_t)(src) <<\
38662 #define TIMING_CONTROLS_2__ENABLE_OFFSET_FILTER__VERIFY(src) \
38663 (!((((u_int32_t)(src)\
38676 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__READ(src) \
38677 (((u_int32_t)(src)\
38679 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__WRITE(src) \
38680 (((u_int32_t)(src)\
38682 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__MODIFY(dst, src) \
38684 ~0x007f0000U) | (((u_int32_t)(src) <<\
38686 #define TIMING_CONTROLS_2__DC_OFF_DELTAF_THRES__VERIFY(src) \
38687 (!((((u_int32_t)(src)\
38694 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__READ(src) \
38695 (((u_int32_t)(src)\
38697 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__WRITE(src) \
38698 (((u_int32_t)(src)\
38700 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__MODIFY(dst, src) \
38702 ~0x07000000U) | (((u_int32_t)(src) <<\
38704 #define TIMING_CONTROLS_2__DC_OFF_TIM_CONST__VERIFY(src) \
38705 (!((((u_int32_t)(src)\
38712 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__READ(src) \
38713 (((u_int32_t)(src)\
38715 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__WRITE(src) \
38716 (((u_int32_t)(src)\
38718 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__MODIFY(dst, src) \
38720 ~0x08000000U) | (((u_int32_t)(src) <<\
38722 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET__VERIFY(src) \
38723 (!((((u_int32_t)(src)\
38736 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__READ(src) \
38737 (((u_int32_t)(src)\
38739 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__WRITE(src) \
38740 (((u_int32_t)(src)\
38742 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__MODIFY(dst, src) \
38744 ~0x10000000U) | (((u_int32_t)(src) <<\
38746 #define TIMING_CONTROLS_2__ENABLE_DC_OFFSET_TRACK__VERIFY(src) \
38747 (!((((u_int32_t)(src)\
38760 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__READ(src) \
38761 (((u_int32_t)(src)\
38763 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__WRITE(src) \
38764 (((u_int32_t)(src)\
38766 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__MODIFY(dst, src) \
38768 ~0x20000000U) | (((u_int32_t)(src) <<\
38770 #define TIMING_CONTROLS_2__ENABLE_WEIGHTING__VERIFY(src) \
38771 (!((((u_int32_t)(src)\
38784 #define TIMING_CONTROLS_2__TRACEBACK128__READ(src) \
38785 (((u_int32_t)(src)\
38787 #define TIMING_CONTROLS_2__TRACEBACK128__WRITE(src) \
38788 (((u_int32_t)(src)\
38790 #define TIMING_CONTROLS_2__TRACEBACK128__MODIFY(dst, src) \
38792 ~0x40000000U) | (((u_int32_t)(src) <<\
38794 #define TIMING_CONTROLS_2__TRACEBACK128__VERIFY(src) \
38795 (!((((u_int32_t)(src)\
38808 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__READ(src) \
38809 (((u_int32_t)(src)\
38811 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__WRITE(src) \
38812 (((u_int32_t)(src)\
38814 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__MODIFY(dst, src) \
38816 ~0x80000000U) | (((u_int32_t)(src) <<\
38818 #define TIMING_CONTROLS_2__ENABLE_HT_FINE_TIMING__VERIFY(src) \
38819 (!((((u_int32_t)(src)\
38845 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__READ(src) \
38846 (u_int32_t)(src)\
38848 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__WRITE(src) \
38849 ((u_int32_t)(src)\
38851 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__MODIFY(dst, src) \
38853 ~0x000000ffU) | ((u_int32_t)(src) &\
38855 #define TIMING_CONTROLS_3__PPM_RESCUE_INTERVAL__VERIFY(src) \
38856 (!(((u_int32_t)(src)\
38863 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__READ(src) \
38864 (((u_int32_t)(src)\
38866 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__WRITE(src) \
38867 (((u_int32_t)(src)\
38869 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__MODIFY(dst, src) \
38871 ~0x00000100U) | (((u_int32_t)(src) <<\
38873 #define TIMING_CONTROLS_3__ENABLE_PPM_RESCUE__VERIFY(src) \
38874 (!((((u_int32_t)(src)\
38887 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__READ(src) \
38888 (((u_int32_t)(src)\
38890 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__WRITE(src) \
38891 (((u_int32_t)(src)\
38893 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__MODIFY(dst, src) \
38895 ~0x00000200U) | (((u_int32_t)(src) <<\
38897 #define TIMING_CONTROLS_3__ENABLE_FINE_PPM__VERIFY(src) \
38898 (!((((u_int32_t)(src)\
38911 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__READ(src) \
38912 (((u_int32_t)(src)\
38914 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__WRITE(src) \
38915 (((u_int32_t)(src)\
38917 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__MODIFY(dst, src) \
38919 ~0x00000400U) | (((u_int32_t)(src) <<\
38921 #define TIMING_CONTROLS_3__ENABLE_FINE_INTERP__VERIFY(src) \
38922 (!((((u_int32_t)(src)\
38935 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__READ(src) \
38936 (((u_int32_t)(src)\
38938 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__WRITE(src) \
38939 (((u_int32_t)(src)\
38941 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__MODIFY(dst, src) \
38943 ~0x00000800U) | (((u_int32_t)(src) <<\
38945 #define TIMING_CONTROLS_3__CONTINUOUS_PPM_RESCUE__VERIFY(src) \
38946 (!((((u_int32_t)(src)\
38959 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__READ(src) \
38960 (((u_int32_t)(src)\
38962 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__WRITE(src) \
38963 (((u_int32_t)(src)\
38965 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__MODIFY(dst, src) \
38967 ~0x00001000U) | (((u_int32_t)(src) <<\
38969 #define TIMING_CONTROLS_3__ENABLE_DF_CHANEST__VERIFY(src) \
38970 (!((((u_int32_t)(src)\
38983 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__READ(src) \
38984 (((u_int32_t)(src)\
38986 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__WRITE(src) \
38987 (((u_int32_t)(src)\
38989 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__MODIFY(dst, src) \
38991 ~0x0001e000U) | (((u_int32_t)(src) <<\
38993 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_EXP__VERIFY(src) \
38994 (!((((u_int32_t)(src)\
39001 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__READ(src) \
39002 (((u_int32_t)(src)\
39004 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__WRITE(src) \
39005 (((u_int32_t)(src)\
39007 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__MODIFY(dst, src) \
39009 ~0xfffe0000U) | (((u_int32_t)(src) <<\
39011 #define TIMING_CONTROLS_3__DELTA_SLOPE_COEF_MAN__VERIFY(src) \
39012 (!((((u_int32_t)(src)\
39032 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__READ(src) \
39033 (((u_int32_t)(src)\
39035 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__WRITE(src) \
39036 (((u_int32_t)(src)\
39038 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__MODIFY(dst, src) \
39040 ~0x0000f000U) | (((u_int32_t)(src) <<\
39042 #define TIMING_CONTROL_4__CAL_LG_COUNT_MAX__VERIFY(src) \
39043 (!((((u_int32_t)(src)\
39050 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__READ(src) \
39051 (((u_int32_t)(src)\
39053 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__WRITE(src) \
39054 (((u_int32_t)(src)\
39056 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__MODIFY(dst, src) \
39058 ~0x00010000U) | (((u_int32_t)(src) <<\
39060 #define TIMING_CONTROL_4__DO_GAIN_DC_IQ_CAL__VERIFY(src) \
39061 (!((((u_int32_t)(src)\
39074 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__READ(src) \
39075 (((u_int32_t)(src)\
39077 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__WRITE(src) \
39078 (((u_int32_t)(src)\
39080 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__MODIFY(dst, src) \
39082 ~0x001e0000U) | (((u_int32_t)(src) <<\
39084 #define TIMING_CONTROL_4__USE_PILOT_TRACK_DF__VERIFY(src) \
39085 (!((((u_int32_t)(src)\
39092 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__READ(src) \
39093 (((u_int32_t)(src)\
39095 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__WRITE(src) \
39096 (((u_int32_t)(src)\
39098 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__MODIFY(dst, src) \
39100 ~0x0fe00000U) | (((u_int32_t)(src) <<\
39102 #define TIMING_CONTROL_4__EARLY_TRIGGER_THR__VERIFY(src) \
39103 (!((((u_int32_t)(src)\
39110 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__READ(src) \
39111 (((u_int32_t)(src)\
39113 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__WRITE(src) \
39114 (((u_int32_t)(src)\
39116 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__MODIFY(dst, src) \
39118 ~0x10000000U) | (((u_int32_t)(src) <<\
39120 #define TIMING_CONTROL_4__ENABLE_PILOT_MASK__VERIFY(src) \
39121 (!((((u_int32_t)(src)\
39134 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__READ(src) \
39135 (((u_int32_t)(src)\
39137 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__WRITE(src) \
39138 (((u_int32_t)(src)\
39140 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__MODIFY(dst, src) \
39142 ~0x20000000U) | (((u_int32_t)(src) <<\
39144 #define TIMING_CONTROL_4__ENABLE_CHAN_MASK__VERIFY(src) \
39145 (!((((u_int32_t)(src)\
39158 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__READ(src) \
39159 (((u_int32_t)(src)\
39161 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__WRITE(src) \
39162 (((u_int32_t)(src)\
39164 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__MODIFY(dst, src) \
39166 ~0x40000000U) | (((u_int32_t)(src) <<\
39168 #define TIMING_CONTROL_4__ENABLE_SPUR_FILTER__VERIFY(src) \
39169 (!((((u_int32_t)(src)\
39182 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__READ(src) \
39183 (((u_int32_t)(src)\
39185 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__WRITE(src) \
39186 (((u_int32_t)(src)\
39188 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__MODIFY(dst, src) \
39190 ~0x80000000U) | (((u_int32_t)(src) <<\
39192 #define TIMING_CONTROL_4__ENABLE_SPUR_RSSI__VERIFY(src) \
39193 (!((((u_int32_t)(src)\
39219 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__READ(src) \
39220 (u_int32_t)(src)\
39222 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__WRITE(src) \
39223 ((u_int32_t)(src)\
39225 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__MODIFY(dst, src) \
39227 ~0x00000001U) | ((u_int32_t)(src) &\
39229 #define TIMING_CONTROL_5__ENABLE_CYCPWR_THR1__VERIFY(src) \
39230 (!(((u_int32_t)(src)\
39243 #define TIMING_CONTROL_5__CYCPWR_THR1__READ(src) \
39244 (((u_int32_t)(src)\
39246 #define TIMING_CONTROL_5__CYCPWR_THR1__WRITE(src) \
39247 (((u_int32_t)(src)\
39249 #define TIMING_CONTROL_5__CYCPWR_THR1__MODIFY(dst, src) \
39251 ~0x000000feU) | (((u_int32_t)(src) <<\
39253 #define TIMING_CONTROL_5__CYCPWR_THR1__VERIFY(src) \
39254 (!((((u_int32_t)(src)\
39261 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__READ(src) \
39262 (((u_int32_t)(src)\
39264 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__WRITE(src) \
39265 (((u_int32_t)(src)\
39267 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__MODIFY(dst, src) \
39269 ~0x00008000U) | (((u_int32_t)(src) <<\
39271 #define TIMING_CONTROL_5__ENABLE_RSSI_THR1A__VERIFY(src) \
39272 (!((((u_int32_t)(src)\
39285 #define TIMING_CONTROL_5__RSSI_THR1A__READ(src) \
39286 (((u_int32_t)(src)\
39288 #define TIMING_CONTROL_5__RSSI_THR1A__WRITE(src) \
39289 (((u_int32_t)(src)\
39291 #define TIMING_CONTROL_5__RSSI_THR1A__MODIFY(dst, src) \
39293 ~0x007f0000U) | (((u_int32_t)(src) <<\
39295 #define TIMING_CONTROL_5__RSSI_THR1A__VERIFY(src) \
39296 (!((((u_int32_t)(src)\
39303 #define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__READ(src) \
39304 (((u_int32_t)(src)\
39306 #define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__WRITE(src) \
39307 (((u_int32_t)(src)\
39309 #define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__MODIFY(dst, src) \
39311 ~0x3f800000U) | (((u_int32_t)(src) <<\
39313 #define TIMING_CONTROL_5__LONG_SC_THRESH_HI_RSSI__VERIFY(src) \
39314 (!((((u_int32_t)(src)\
39321 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__READ(src) \
39322 (((u_int32_t)(src)\
39324 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__WRITE(src) \
39325 (((u_int32_t)(src)\
39327 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__MODIFY(dst, src) \
39329 ~0x40000000U) | (((u_int32_t)(src) <<\
39331 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI__VERIFY(src) \
39332 (!((((u_int32_t)(src)\
39345 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__READ(src) \
39346 (((u_int32_t)(src)\
39348 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__WRITE(src) \
39349 (((u_int32_t)(src)\
39351 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__MODIFY(dst, src) \
39353 ~0x80000000U) | (((u_int32_t)(src) <<\
39355 #define TIMING_CONTROL_5__FORCED_AGC_STR_PRI_EN__VERIFY(src) \
39356 (!((((u_int32_t)(src)\
39382 #define TIMING_CONTROL_6__HI_RSSI_THRESH__READ(src) \
39383 (u_int32_t)(src)\
39385 #define TIMING_CONTROL_6__HI_RSSI_THRESH__WRITE(src) \
39386 ((u_int32_t)(src)\
39388 #define TIMING_CONTROL_6__HI_RSSI_THRESH__MODIFY(dst, src) \
39390 ~0x000000ffU) | ((u_int32_t)(src) &\
39392 #define TIMING_CONTROL_6__HI_RSSI_THRESH__VERIFY(src) \
39393 (!(((u_int32_t)(src)\
39400 #define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__READ(src) \
39401 (((u_int32_t)(src)\
39403 #define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__WRITE(src) \
39404 (((u_int32_t)(src)\
39406 #define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__MODIFY(dst, src) \
39408 ~0x00007f00U) | (((u_int32_t)(src) <<\
39410 #define TIMING_CONTROL_6__EARLY_TRIGGER_THR_HI_RSSI__VERIFY(src) \
39411 (!((((u_int32_t)(src)\
39418 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH__READ(src) \
39419 (((u_int32_t)(src)\
39421 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH__WRITE(src) \
39422 (((u_int32_t)(src)\
39424 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH__MODIFY(dst, src) \
39426 ~0x001f8000U) | (((u_int32_t)(src) <<\
39428 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH__VERIFY(src) \
39429 (!((((u_int32_t)(src)\
39436 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__READ(src) \
39437 (((u_int32_t)(src)\
39439 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__WRITE(src) \
39440 (((u_int32_t)(src)\
39442 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__MODIFY(dst, src) \
39444 ~0x0fe00000U) | (((u_int32_t)(src) <<\
39446 #define TIMING_CONTROL_6__OFDM_XCORR_THRESH_HI_RSSI__VERIFY(src) \
39447 (!((((u_int32_t)(src)\
39454 #define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__READ(src) \
39455 (((u_int32_t)(src)\
39457 #define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__WRITE(src) \
39458 (((u_int32_t)(src)\
39460 #define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__MODIFY(dst, src) \
39462 ~0xf0000000U) | (((u_int32_t)(src) <<\
39464 #define TIMING_CONTROL_6__LONG_MEDIUM_RATIO_THR__VERIFY(src) \
39465 (!((((u_int32_t)(src)\
39485 #define TIMING_CONTROL_11__SPUR_DELTA_PHASE__READ(src) \
39486 (u_int32_t)(src)\
39488 #define TIMING_CONTROL_11__SPUR_DELTA_PHASE__WRITE(src) \
39489 ((u_int32_t)(src)\
39491 #define TIMING_CONTROL_11__SPUR_DELTA_PHASE__MODIFY(dst, src) \
39493 ~0x000fffffU) | ((u_int32_t)(src) &\
39495 #define TIMING_CONTROL_11__SPUR_DELTA_PHASE__VERIFY(src) \
39496 (!(((u_int32_t)(src)\
39503 #define TIMING_CONTROL_11__SPUR_FREQ_SD__READ(src) \
39504 (((u_int32_t)(src)\
39506 #define TIMING_CONTROL_11__SPUR_FREQ_SD__WRITE(src) \
39507 (((u_int32_t)(src)\
39509 #define TIMING_CONTROL_11__SPUR_FREQ_SD__MODIFY(dst, src) \
39511 ~0x3ff00000U) | (((u_int32_t)(src) <<\
39513 #define TIMING_CONTROL_11__SPUR_FREQ_SD__VERIFY(src) \
39514 (!((((u_int32_t)(src)\
39521 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__READ(src) \
39522 (((u_int32_t)(src)\
39524 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__WRITE(src) \
39525 (((u_int32_t)(src)\
39527 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__MODIFY(dst, src) \
39529 ~0x40000000U) | (((u_int32_t)(src) <<\
39531 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_AGC__VERIFY(src) \
39532 (!((((u_int32_t)(src)\
39545 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__READ(src) \
39546 (((u_int32_t)(src)\
39548 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__WRITE(src) \
39549 (((u_int32_t)(src)\
39551 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__MODIFY(dst, src) \
39553 ~0x80000000U) | (((u_int32_t)(src) <<\
39555 #define TIMING_CONTROL_11__USE_SPUR_FILTER_IN_SELFCOR__VERIFY(src) \
39556 (!((((u_int32_t)(src)\
39582 #define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__READ(src) \
39583 (u_int32_t)(src)\
39585 #define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__WRITE(src) \
39586 ((u_int32_t)(src)\
39588 #define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__MODIFY(dst, src) \
39590 ~0x000000ffU) | ((u_int32_t)(src) &\
39592 #define SPUR_MASK_CONTROLS__SPUR_RSSI_THRESH__VERIFY(src) \
39593 (!(((u_int32_t)(src)\
39600 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__READ(src) \
39601 (((u_int32_t)(src)\
39603 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__WRITE(src) \
39604 (((u_int32_t)(src)\
39606 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__MODIFY(dst, src) \
39608 ~0x00000100U) | (((u_int32_t)(src) <<\
39610 #define SPUR_MASK_CONTROLS__EN_VIT_SPUR_RSSI__VERIFY(src) \
39611 (!((((u_int32_t)(src)\
39624 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__READ(src) \
39625 (((u_int32_t)(src)\
39627 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__WRITE(src) \
39628 (((u_int32_t)(src)\
39630 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__MODIFY(dst, src) \
39632 ~0x00020000U) | (((u_int32_t)(src) <<\
39634 #define SPUR_MASK_CONTROLS__ENABLE_MASK_PPM__VERIFY(src) \
39635 (!((((u_int32_t)(src)\
39648 #define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__READ(src) \
39649 (((u_int32_t)(src)\
39651 #define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__WRITE(src) \
39652 (((u_int32_t)(src)\
39654 #define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__MODIFY(dst, src) \
39656 ~0x03fc0000U) | (((u_int32_t)(src) <<\
39658 #define SPUR_MASK_CONTROLS__MASK_RATE_CNTL__VERIFY(src) \
39659 (!((((u_int32_t)(src)\
39666 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__READ(src) \
39667 (((u_int32_t)(src)\
39669 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__WRITE(src) \
39670 (((u_int32_t)(src)\
39672 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__MODIFY(dst, src) \
39674 ~0x04000000U) | (((u_int32_t)(src) <<\
39676 #define SPUR_MASK_CONTROLS__ENABLE_NF_RSSI_SPUR_MIT__VERIFY(src) \
39677 (!((((u_int32_t)(src)\
39703 #define FIND_SIGNAL_LOW__RELSTEP_LOW__READ(src) (u_int32_t)(src) & 0x0000003fU
39704 #define FIND_SIGNAL_LOW__RELSTEP_LOW__WRITE(src) \
39705 ((u_int32_t)(src)\
39707 #define FIND_SIGNAL_LOW__RELSTEP_LOW__MODIFY(dst, src) \
39709 ~0x0000003fU) | ((u_int32_t)(src) &\
39711 #define FIND_SIGNAL_LOW__RELSTEP_LOW__VERIFY(src) \
39712 (!(((u_int32_t)(src)\
39719 #define FIND_SIGNAL_LOW__FIRSTEP_LOW__READ(src) \
39720 (((u_int32_t)(src)\
39722 #define FIND_SIGNAL_LOW__FIRSTEP_LOW__WRITE(src) \
39723 (((u_int32_t)(src)\
39725 #define FIND_SIGNAL_LOW__FIRSTEP_LOW__MODIFY(dst, src) \
39727 ~0x00000fc0U) | (((u_int32_t)(src) <<\
39729 #define FIND_SIGNAL_LOW__FIRSTEP_LOW__VERIFY(src) \
39730 (!((((u_int32_t)(src)\
39737 #define FIND_SIGNAL_LOW__FIRPWR_LOW__READ(src) \
39738 (((u_int32_t)(src)\
39740 #define FIND_SIGNAL_LOW__FIRPWR_LOW__WRITE(src) \
39741 (((u_int32_t)(src)\
39743 #define FIND_SIGNAL_LOW__FIRPWR_LOW__MODIFY(dst, src) \
39745 ~0x000ff000U) | (((u_int32_t)(src) <<\
39747 #define FIND_SIGNAL_LOW__FIRPWR_LOW__VERIFY(src) \
39748 (!((((u_int32_t)(src)\
39755 #define FIND_SIGNAL_LOW__YCOK_MAX_LOW__READ(src) \
39756 (((u_int32_t)(src)\
39758 #define FIND_SIGNAL_LOW__YCOK_MAX_LOW__WRITE(src) \
39759 (((u_int32_t)(src)\
39761 #define FIND_SIGNAL_LOW__YCOK_MAX_LOW__MODIFY(dst, src) \
39763 ~0x00f00000U) | (((u_int32_t)(src) <<\
39765 #define FIND_SIGNAL_LOW__YCOK_MAX_LOW__VERIFY(src) \
39766 (!((((u_int32_t)(src)\
39773 #define FIND_SIGNAL_LOW__LONG_SC_THRESH__READ(src) \
39774 (((u_int32_t)(src)\
39776 #define FIND_SIGNAL_LOW__LONG_SC_THRESH__WRITE(src) \
39777 (((u_int32_t)(src)\
39779 #define FIND_SIGNAL_LOW__LONG_SC_THRESH__MODIFY(dst, src) \
39781 ~0x7f000000U) | (((u_int32_t)(src) <<\
39783 #define FIND_SIGNAL_LOW__LONG_SC_THRESH__VERIFY(src) \
39784 (!((((u_int32_t)(src)\
39804 #define SFCORR__M2COUNT_THR__READ(src) (u_int32_t)(src) & 0x0000001fU
39805 #define SFCORR__M2COUNT_THR__WRITE(src) ((u_int32_t)(src) & 0x0000001fU)
39806 #define SFCORR__M2COUNT_THR__MODIFY(dst, src) \
39808 ~0x0000001fU) | ((u_int32_t)(src) &\
39810 #define SFCORR__M2COUNT_THR__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))
39816 #define SFCORR__ADCSAT_THRESH__READ(src) \
39817 (((u_int32_t)(src)\
39819 #define SFCORR__ADCSAT_THRESH__WRITE(src) \
39820 (((u_int32_t)(src)\
39822 #define SFCORR__ADCSAT_THRESH__MODIFY(dst, src) \
39824 ~0x000007e0U) | (((u_int32_t)(src) <<\
39826 #define SFCORR__ADCSAT_THRESH__VERIFY(src) \
39827 (!((((u_int32_t)(src)\
39834 #define SFCORR__ADCSAT_ICOUNT__READ(src) \
39835 (((u_int32_t)(src)\
39837 #define SFCORR__ADCSAT_ICOUNT__WRITE(src) \
39838 (((u_int32_t)(src)\
39840 #define SFCORR__ADCSAT_ICOUNT__MODIFY(dst, src) \
39842 ~0x0001f800U) | (((u_int32_t)(src) <<\
39844 #define SFCORR__ADCSAT_ICOUNT__VERIFY(src) \
39845 (!((((u_int32_t)(src)\
39852 #define SFCORR__M1_THRES__READ(src) (((u_int32_t)(src) & 0x00fe0000U) >> 17)
39853 #define SFCORR__M1_THRES__WRITE(src) (((u_int32_t)(src) << 17) & 0x00fe0000U)
39854 #define SFCORR__M1_THRES__MODIFY(dst, src) \
39856 ~0x00fe0000U) | (((u_int32_t)(src) <<\
39858 #define SFCORR__M1_THRES__VERIFY(src) \
39859 (!((((u_int32_t)(src)\
39866 #define SFCORR__M2_THRES__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24)
39867 #define SFCORR__M2_THRES__WRITE(src) (((u_int32_t)(src) << 24) & 0x7f000000U)
39868 #define SFCORR__M2_THRES__MODIFY(dst, src) \
39870 ~0x7f000000U) | (((u_int32_t)(src) <<\
39872 #define SFCORR__M2_THRES__VERIFY(src) \
39873 (!((((u_int32_t)(src)\
39893 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__READ(src) \
39894 (u_int32_t)(src)\
39896 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__WRITE(src) \
39897 ((u_int32_t)(src)\
39899 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__MODIFY(dst, src) \
39901 ~0x00000001U) | ((u_int32_t)(src) &\
39903 #define SELF_CORR_LOW__USE_SELF_CORR_LOW__VERIFY(src) \
39904 (!(((u_int32_t)(src)\
39917 #define SELF_CORR_LOW__M1COUNT_MAX_LOW__READ(src) \
39918 (((u_int32_t)(src)\
39920 #define SELF_CORR_LOW__M1COUNT_MAX_LOW__WRITE(src) \
39921 (((u_int32_t)(src)\
39923 #define SELF_CORR_LOW__M1COUNT_MAX_LOW__MODIFY(dst, src) \
39925 ~0x000000feU) | (((u_int32_t)(src) <<\
39927 #define SELF_CORR_LOW__M1COUNT_MAX_LOW__VERIFY(src) \
39928 (!((((u_int32_t)(src)\
39935 #define SELF_CORR_LOW__M2COUNT_THR_LOW__READ(src) \
39936 (((u_int32_t)(src)\
39938 #define SELF_CORR_LOW__M2COUNT_THR_LOW__WRITE(src) \
39939 (((u_int32_t)(src)\
39941 #define SELF_CORR_LOW__M2COUNT_THR_LOW__MODIFY(dst, src) \
39943 ~0x00003f00U) | (((u_int32_t)(src) <<\
39945 #define SELF_CORR_LOW__M2COUNT_THR_LOW__VERIFY(src) \
39946 (!((((u_int32_t)(src)\
39953 #define SELF_CORR_LOW__M1_THRESH_LOW__READ(src) \
39954 (((u_int32_t)(src)\
39956 #define SELF_CORR_LOW__M1_THRESH_LOW__WRITE(src) \
39957 (((u_int32_t)(src)\
39959 #define SELF_CORR_LOW__M1_THRESH_LOW__MODIFY(dst, src) \
39961 ~0x001fc000U) | (((u_int32_t)(src) <<\
39963 #define SELF_CORR_LOW__M1_THRESH_LOW__VERIFY(src) \
39964 (!((((u_int32_t)(src)\
39971 #define SELF_CORR_LOW__M2_THRESH_LOW__READ(src) \
39972 (((u_int32_t)(src)\
39974 #define SELF_CORR_LOW__M2_THRESH_LOW__WRITE(src) \
39975 (((u_int32_t)(src)\
39977 #define SELF_CORR_LOW__M2_THRESH_LOW__MODIFY(dst, src) \
39979 ~0x0fe00000U) | (((u_int32_t)(src) <<\
39981 #define SELF_CORR_LOW__M2_THRESH_LOW__VERIFY(src) \
39982 (!((((u_int32_t)(src)\
40002 #define EXT_CHAN_SCORR_THR__M1_THRES_EXT__READ(src) \
40003 (u_int32_t)(src)\
40005 #define EXT_CHAN_SCORR_THR__M1_THRES_EXT__WRITE(src) \
40006 ((u_int32_t)(src)\
40008 #define EXT_CHAN_SCORR_THR__M1_THRES_EXT__MODIFY(dst, src) \
40010 ~0x0000007fU) | ((u_int32_t)(src) &\
40012 #define EXT_CHAN_SCORR_THR__M1_THRES_EXT__VERIFY(src) \
40013 (!(((u_int32_t)(src)\
40020 #define EXT_CHAN_SCORR_THR__M2_THRES_EXT__READ(src) \
40021 (((u_int32_t)(src)\
40023 #define EXT_CHAN_SCORR_THR__M2_THRES_EXT__WRITE(src) \
40024 (((u_int32_t)(src)\
40026 #define EXT_CHAN_SCORR_THR__M2_THRES_EXT__MODIFY(dst, src) \
40028 ~0x00003f80U) | (((u_int32_t)(src) <<\
40030 #define EXT_CHAN_SCORR_THR__M2_THRES_EXT__VERIFY(src) \
40031 (!((((u_int32_t)(src)\
40038 #define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__READ(src) \
40039 (((u_int32_t)(src)\
40041 #define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__WRITE(src) \
40042 (((u_int32_t)(src)\
40044 #define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__MODIFY(dst, src) \
40046 ~0x001fc000U) | (((u_int32_t)(src) <<\
40048 #define EXT_CHAN_SCORR_THR__M1_THRES_LOW_EXT__VERIFY(src) \
40049 (!((((u_int32_t)(src)\
40056 #define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__READ(src) \
40057 (((u_int32_t)(src)\
40059 #define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__WRITE(src) \
40060 (((u_int32_t)(src)\
40062 #define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__MODIFY(dst, src) \
40064 ~0x0fe00000U) | (((u_int32_t)(src) <<\
40066 #define EXT_CHAN_SCORR_THR__M2_THRES_LOW_EXT__VERIFY(src) \
40067 (!((((u_int32_t)(src)\
40074 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__READ(src) \
40075 (((u_int32_t)(src)\
40077 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__WRITE(src) \
40078 (((u_int32_t)(src)\
40080 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__MODIFY(dst, src) \
40082 ~0x10000000U) | (((u_int32_t)(src) <<\
40084 #define EXT_CHAN_SCORR_THR__SPUR_SUBCHANNEL_SD__VERIFY(src) \
40085 (!((((u_int32_t)(src)\
40111 #define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__READ(src) \
40112 (u_int32_t)(src)\
40114 #define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__WRITE(src) \
40115 ((u_int32_t)(src)\
40117 #define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__MODIFY(dst, src) \
40119 ~0x000001ffU) | ((u_int32_t)(src) &\
40121 #define EXT_CHAN_PWR_THR_2_B0__CF_MAXCCAPWR_EXT_0__VERIFY(src) \
40122 (!(((u_int32_t)(src)\
40129 #define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__READ(src) \
40130 (((u_int32_t)(src)\
40132 #define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__WRITE(src) \
40133 (((u_int32_t)(src)\
40135 #define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__MODIFY(dst, src) \
40137 ~0x0000fe00U) | (((u_int32_t)(src) <<\
40139 #define EXT_CHAN_PWR_THR_2_B0__CYCPWR_THR1_EXT__VERIFY(src) \
40140 (!((((u_int32_t)(src)\
40147 #define EXT_CHAN_PWR_THR_2_B0__MINCCAPWR_EXT_0__READ(src) \
40148 (((u_int32_t)(src)\
40168 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__READ(src) \
40169 (u_int32_t)(src)\
40171 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__WRITE(src) \
40172 ((u_int32_t)(src)\
40174 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__MODIFY(dst, src) \
40176 ~0x00000001U) | ((u_int32_t)(src) &\
40178 #define RADAR_DETECTION__PULSE_DETECT_ENABLE__VERIFY(src) \
40179 (!(((u_int32_t)(src)\
40192 #define RADAR_DETECTION__PULSE_IN_BAND_THRESH__READ(src) \
40193 (((u_int32_t)(src)\
40195 #define RADAR_DETECTION__PULSE_IN_BAND_THRESH__WRITE(src) \
40196 (((u_int32_t)(src)\
40198 #define RADAR_DETECTION__PULSE_IN_BAND_THRESH__MODIFY(dst, src) \
40200 ~0x0000003eU) | (((u_int32_t)(src) <<\
40202 #define RADAR_DETECTION__PULSE_IN_BAND_THRESH__VERIFY(src) \
40203 (!((((u_int32_t)(src)\
40210 #define RADAR_DETECTION__PULSE_RSSI_THRESH__READ(src) \
40211 (((u_int32_t)(src)\
40213 #define RADAR_DETECTION__PULSE_RSSI_THRESH__WRITE(src) \
40214 (((u_int32_t)(src)\
40216 #define RADAR_DETECTION__PULSE_RSSI_THRESH__MODIFY(dst, src) \
40218 ~0x00000fc0U) | (((u_int32_t)(src) <<\
40220 #define RADAR_DETECTION__PULSE_RSSI_THRESH__VERIFY(src) \
40221 (!((((u_int32_t)(src)\
40228 #define RADAR_DETECTION__PULSE_HEIGHT_THRESH__READ(src) \
40229 (((u_int32_t)(src)\
40231 #define RADAR_DETECTION__PULSE_HEIGHT_THRESH__WRITE(src) \
40232 (((u_int32_t)(src)\
40234 #define RADAR_DETECTION__PULSE_HEIGHT_THRESH__MODIFY(dst, src) \
40236 ~0x0003f000U) | (((u_int32_t)(src) <<\
40238 #define RADAR_DETECTION__PULSE_HEIGHT_THRESH__VERIFY(src) \
40239 (!((((u_int32_t)(src)\
40246 #define RADAR_DETECTION__RADAR_RSSI_THRESH__READ(src) \
40247 (((u_int32_t)(src)\
40249 #define RADAR_DETECTION__RADAR_RSSI_THRESH__WRITE(src) \
40250 (((u_int32_t)(src)\
40252 #define RADAR_DETECTION__RADAR_RSSI_THRESH__MODIFY(dst, src) \
40254 ~0x00fc0000U) | (((u_int32_t)(src) <<\
40256 #define RADAR_DETECTION__RADAR_RSSI_THRESH__VERIFY(src) \
40257 (!((((u_int32_t)(src)\
40264 #define RADAR_DETECTION__RADAR_FIRPWR_THRESH__READ(src) \
40265 (((u_int32_t)(src)\
40267 #define RADAR_DETECTION__RADAR_FIRPWR_THRESH__WRITE(src) \
40268 (((u_int32_t)(src)\
40270 #define RADAR_DETECTION__RADAR_FIRPWR_THRESH__MODIFY(dst, src) \
40272 ~0x7f000000U) | (((u_int32_t)(src) <<\
40274 #define RADAR_DETECTION__RADAR_FIRPWR_THRESH__VERIFY(src) \
40275 (!((((u_int32_t)(src)\
40282 #define RADAR_DETECTION__ENABLE_RADAR_FFT__READ(src) \
40283 (((u_int32_t)(src)\
40285 #define RADAR_DETECTION__ENABLE_RADAR_FFT__WRITE(src) \
40286 (((u_int32_t)(src)\
40288 #define RADAR_DETECTION__ENABLE_RADAR_FFT__MODIFY(dst, src) \
40290 ~0x80000000U) | (((u_int32_t)(src) <<\
40292 #define RADAR_DETECTION__ENABLE_RADAR_FFT__VERIFY(src) \
40293 (!((((u_int32_t)(src)\
40319 #define RADAR_DETECTION_2__RADAR_LENGTH_MAX__READ(src) \
40320 (u_int32_t)(src)\
40322 #define RADAR_DETECTION_2__RADAR_LENGTH_MAX__WRITE(src) \
40323 ((u_int32_t)(src)\
40325 #define RADAR_DETECTION_2__RADAR_LENGTH_MAX__MODIFY(dst, src) \
40327 ~0x000000ffU) | ((u_int32_t)(src) &\
40329 #define RADAR_DETECTION_2__RADAR_LENGTH_MAX__VERIFY(src) \
40330 (!(((u_int32_t)(src)\
40337 #define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__READ(src) \
40338 (((u_int32_t)(src)\
40340 #define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__WRITE(src) \
40341 (((u_int32_t)(src)\
40343 #define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__MODIFY(dst, src) \
40345 ~0x00001f00U) | (((u_int32_t)(src) <<\
40347 #define RADAR_DETECTION_2__PULSE_RELSTEP_THRESH__VERIFY(src) \
40348 (!((((u_int32_t)(src)\
40355 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__READ(src) \
40356 (((u_int32_t)(src)\
40358 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__WRITE(src) \
40359 (((u_int32_t)(src)\
40361 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__MODIFY(dst, src) \
40363 ~0x00002000U) | (((u_int32_t)(src) <<\
40365 #define RADAR_DETECTION_2__ENABLE_PULSE_RELSTEP_CHECK__VERIFY(src) \
40366 (!((((u_int32_t)(src)\
40379 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__READ(src) \
40380 (((u_int32_t)(src)\
40382 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__WRITE(src) \
40383 (((u_int32_t)(src)\
40385 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__MODIFY(dst, src) \
40387 ~0x00004000U) | (((u_int32_t)(src) <<\
40389 #define RADAR_DETECTION_2__ENABLE_MAX_RADAR_RSSI__VERIFY(src) \
40390 (!((((u_int32_t)(src)\
40403 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__READ(src) \
40404 (((u_int32_t)(src)\
40406 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__WRITE(src) \
40407 (((u_int32_t)(src)\
40409 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__MODIFY(dst, src) \
40411 ~0x00008000U) | (((u_int32_t)(src) <<\
40413 #define RADAR_DETECTION_2__ENABLE_BLOCK_RADAR_CHECK__VERIFY(src) \
40414 (!((((u_int32_t)(src)\
40427 #define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__READ(src) \
40428 (((u_int32_t)(src)\
40430 #define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__WRITE(src) \
40431 (((u_int32_t)(src)\
40433 #define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__MODIFY(dst, src) \
40435 ~0x003f0000U) | (((u_int32_t)(src) <<\
40437 #define RADAR_DETECTION_2__RADAR_RELPWR_THRESH__VERIFY(src) \
40438 (!((((u_int32_t)(src)\
40445 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__READ(src) \
40446 (((u_int32_t)(src)\
40448 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__WRITE(src) \
40449 (((u_int32_t)(src)\
40451 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__MODIFY(dst, src) \
40453 ~0x00400000U) | (((u_int32_t)(src) <<\
40455 #define RADAR_DETECTION_2__RADAR_USE_FIRPWR_128__VERIFY(src) \
40456 (!((((u_int32_t)(src)\
40469 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__READ(src) \
40470 (((u_int32_t)(src)\
40472 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__WRITE(src) \
40473 (((u_int32_t)(src)\
40475 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__MODIFY(dst, src) \
40477 ~0x00800000U) | (((u_int32_t)(src) <<\
40479 #define RADAR_DETECTION_2__ENABLE_RADAR_RELPWR_CHECK__VERIFY(src) \
40480 (!((((u_int32_t)(src)\
40493 #define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__READ(src) \
40494 (((u_int32_t)(src)\
40496 #define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__WRITE(src) \
40497 (((u_int32_t)(src)\
40499 #define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__MODIFY(dst, src) \
40501 ~0x07000000U) | (((u_int32_t)(src) <<\
40503 #define RADAR_DETECTION_2__CF_RADAR_BIN_THRESH_SEL__VERIFY(src) \
40504 (!((((u_int32_t)(src)\
40511 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__READ(src) \
40512 (((u_int32_t)(src)\
40514 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__WRITE(src) \
40515 (((u_int32_t)(src)\
40517 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__MODIFY(dst, src) \
40519 ~0x08000000U) | (((u_int32_t)(src) <<\
40521 #define RADAR_DETECTION_2__ENABLE_PULSE_GC_COUNT_CHECK__VERIFY(src) \
40522 (!((((u_int32_t)(src)\
40548 #define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__READ(src) \
40549 (((u_int32_t)(src)\
40551 #define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__WRITE(src) \
40552 (((u_int32_t)(src)\
40554 #define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__MODIFY(dst, src) \
40556 ~0x00003f00U) | (((u_int32_t)(src) <<\
40558 #define EXTENSION_RADAR__BLOCKER40_MAX_RADAR__VERIFY(src) \
40559 (!((((u_int32_t)(src)\
40566 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__READ(src) \
40567 (((u_int32_t)(src)\
40569 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__WRITE(src) \
40570 (((u_int32_t)(src)\
40572 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__MODIFY(dst, src) \
40574 ~0x00004000U) | (((u_int32_t)(src) <<\
40576 #define EXTENSION_RADAR__ENABLE_EXT_RADAR__VERIFY(src) \
40577 (!((((u_int32_t)(src)\
40590 #define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__READ(src) \
40591 (((u_int32_t)(src)\
40593 #define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__WRITE(src) \
40594 (((u_int32_t)(src)\
40596 #define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__MODIFY(dst, src) \
40598 ~0x007f8000U) | (((u_int32_t)(src) <<\
40600 #define EXTENSION_RADAR__RADAR_DC_PWR_THRESH__VERIFY(src) \
40601 (!((((u_int32_t)(src)\
40608 #define EXTENSION_RADAR__RADAR_LB_DC_CAP__READ(src) \
40609 (((u_int32_t)(src)\
40611 #define EXTENSION_RADAR__RADAR_LB_DC_CAP__WRITE(src) \
40612 (((u_int32_t)(src)\
40614 #define EXTENSION_RADAR__RADAR_LB_DC_CAP__MODIFY(dst, src) \
40616 ~0x7f800000U) | (((u_int32_t)(src) <<\
40618 #define EXTENSION_RADAR__RADAR_LB_DC_CAP__VERIFY(src) \
40619 (!((((u_int32_t)(src)\
40626 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__READ(src) \
40627 (((u_int32_t)(src)\
40629 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__WRITE(src) \
40630 (((u_int32_t)(src)\
40632 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__MODIFY(dst, src) \
40634 ~0x80000000U) | (((u_int32_t)(src) <<\
40636 #define EXTENSION_RADAR__DISABLE_ADCSAT_HOLD__VERIFY(src) \
40637 (!((((u_int32_t)(src)\
40663 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__READ(src) \
40664 (u_int32_t)(src)\
40666 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__WRITE(src) \
40667 ((u_int32_t)(src)\
40669 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__MODIFY(dst, src) \
40671 ~0x00000001U) | ((u_int32_t)(src) &\
40673 #define MULTICHAIN_CONTROL__FORCE_ANALOG_GAIN_DIFF__VERIFY(src) \
40674 (!(((u_int32_t)(src)\
40687 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__READ(src) \
40688 (((u_int32_t)(src)\
40690 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__WRITE(src) \
40691 (((u_int32_t)(src)\
40693 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__MODIFY(dst, src) \
40695 ~0x000000feU) | (((u_int32_t)(src) <<\
40697 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_01__VERIFY(src) \
40698 (!((((u_int32_t)(src)\
40705 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__READ(src) \
40706 (((u_int32_t)(src)\
40708 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__WRITE(src) \
40709 (((u_int32_t)(src)\
40711 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__MODIFY(dst, src) \
40713 ~0x00000100U) | (((u_int32_t)(src) <<\
40715 #define MULTICHAIN_CONTROL__SYNC_SYNTHON__VERIFY(src) \
40716 (!((((u_int32_t)(src)\
40729 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__READ(src) \
40730 (((u_int32_t)(src)\
40732 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__WRITE(src) \
40733 (((u_int32_t)(src)\
40735 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__MODIFY(dst, src) \
40737 ~0x00000200U) | (((u_int32_t)(src) <<\
40739 #define MULTICHAIN_CONTROL__USE_POSEDGE_REFCLK__VERIFY(src) \
40740 (!((((u_int32_t)(src)\
40753 #define MULTICHAIN_CONTROL__CF_SHORT_SAT__READ(src) \
40754 (((u_int32_t)(src)\
40756 #define MULTICHAIN_CONTROL__CF_SHORT_SAT__WRITE(src) \
40757 (((u_int32_t)(src)\
40759 #define MULTICHAIN_CONTROL__CF_SHORT_SAT__MODIFY(dst, src) \
40761 ~0x001ffc00U) | (((u_int32_t)(src) <<\
40763 #define MULTICHAIN_CONTROL__CF_SHORT_SAT__VERIFY(src) \
40764 (!((((u_int32_t)(src)\
40771 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__READ(src) \
40772 (((u_int32_t)(src)\
40774 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__WRITE(src) \
40775 (((u_int32_t)(src)\
40777 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__MODIFY(dst, src) \
40779 ~0x1fc00000U) | (((u_int32_t)(src) <<\
40781 #define MULTICHAIN_CONTROL__FORCED_GAIN_DIFF_02__VERIFY(src) \
40782 (!((((u_int32_t)(src)\
40789 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__READ(src) \
40790 (((u_int32_t)(src)\
40792 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__WRITE(src) \
40793 (((u_int32_t)(src)\
40795 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__MODIFY(dst, src) \
40797 ~0x20000000U) | (((u_int32_t)(src) <<\
40799 #define MULTICHAIN_CONTROL__FORCE_SIGMA_ZERO__VERIFY(src) \
40800 (!((((u_int32_t)(src)\
40826 #define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__READ(src) \
40827 (u_int32_t)(src)\
40829 #define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__WRITE(src) \
40830 ((u_int32_t)(src)\
40832 #define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__MODIFY(dst, src) \
40834 ~0x0000001fU) | ((u_int32_t)(src) &\
40836 #define PER_CHAIN_CSD__CSD_CHN1_2CHAINS__VERIFY(src) \
40837 (!(((u_int32_t)(src)\
40844 #define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__READ(src) \
40845 (((u_int32_t)(src)\
40847 #define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__WRITE(src) \
40848 (((u_int32_t)(src)\
40850 #define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__MODIFY(dst, src) \
40852 ~0x000003e0U) | (((u_int32_t)(src) <<\
40854 #define PER_CHAIN_CSD__CSD_CHN1_3CHAINS__VERIFY(src) \
40855 (!((((u_int32_t)(src)\
40862 #define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__READ(src) \
40863 (((u_int32_t)(src)\
40865 #define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__WRITE(src) \
40866 (((u_int32_t)(src)\
40868 #define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__MODIFY(dst, src) \
40870 ~0x00007c00U) | (((u_int32_t)(src) <<\
40872 #define PER_CHAIN_CSD__CSD_CHN2_3CHAINS__VERIFY(src) \
40873 (!((((u_int32_t)(src)\
40893 #define TX_CRC__TX_CRC__READ(src) (u_int32_t)(src) & 0x0000ffffU
40911 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__READ(src) \
40912 (u_int32_t)(src)\
40914 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__WRITE(src) \
40915 ((u_int32_t)(src)\
40917 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__MODIFY(dst, src) \
40919 ~0x000007ffU) | ((u_int32_t)(src) &\
40921 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_I__VERIFY(src) \
40922 (!(((u_int32_t)(src)\
40929 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__READ(src) \
40930 (((u_int32_t)(src)\
40932 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__WRITE(src) \
40933 (((u_int32_t)(src)\
40935 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__MODIFY(dst, src) \
40937 ~0x003ff800U) | (((u_int32_t)(src) <<\
40939 #define TSTDAC_CONSTANT__CF_TSTDAC_CONSTANT_Q__VERIFY(src) \
40940 (!((((u_int32_t)(src)\
40960 #define SPUR_REPORT_B0__SPUR_EST_I_0__READ(src) (u_int32_t)(src) & 0x000000ffU
40966 #define SPUR_REPORT_B0__SPUR_EST_Q_0__READ(src) \
40967 (((u_int32_t)(src)\
40974 #define SPUR_REPORT_B0__POWER_WITH_SPUR_REMOVED_0__READ(src) \
40975 (((u_int32_t)(src)\
40994 #define TXIQCAL_CONTROL_3__PWR_HIGH_DB__READ(src) \
40995 (u_int32_t)(src)\
40997 #define TXIQCAL_CONTROL_3__PWR_HIGH_DB__WRITE(src) \
40998 ((u_int32_t)(src)\
41000 #define TXIQCAL_CONTROL_3__PWR_HIGH_DB__MODIFY(dst, src) \
41002 ~0x0000003fU) | ((u_int32_t)(src) &\
41004 #define TXIQCAL_CONTROL_3__PWR_HIGH_DB__VERIFY(src) \
41005 (!(((u_int32_t)(src)\
41012 #define TXIQCAL_CONTROL_3__PWR_LOW_DB__READ(src) \
41013 (((u_int32_t)(src)\
41015 #define TXIQCAL_CONTROL_3__PWR_LOW_DB__WRITE(src) \
41016 (((u_int32_t)(src)\
41018 #define TXIQCAL_CONTROL_3__PWR_LOW_DB__MODIFY(dst, src) \
41020 ~0x00000fc0U) | (((u_int32_t)(src) <<\
41022 #define TXIQCAL_CONTROL_3__PWR_LOW_DB__VERIFY(src) \
41023 (!((((u_int32_t)(src)\
41030 #define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__READ(src) \
41031 (((u_int32_t)(src)\
41033 #define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__WRITE(src) \
41034 (((u_int32_t)(src)\
41036 #define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__MODIFY(dst, src) \
41038 ~0x003ff000U) | (((u_int32_t)(src) <<\
41040 #define TXIQCAL_CONTROL_3__IQCAL_TONE_PHS_STEP__VERIFY(src) \
41041 (!((((u_int32_t)(src)\
41048 #define TXIQCAL_CONTROL_3__DC_EST_LEN__READ(src) \
41049 (((u_int32_t)(src)\
41051 #define TXIQCAL_CONTROL_3__DC_EST_LEN__WRITE(src) \
41052 (((u_int32_t)(src)\
41054 #define TXIQCAL_CONTROL_3__DC_EST_LEN__MODIFY(dst, src) \
41056 ~0x00c00000U) | (((u_int32_t)(src) <<\
41058 #define TXIQCAL_CONTROL_3__DC_EST_LEN__VERIFY(src) \
41059 (!((((u_int32_t)(src)\
41066 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__READ(src) \
41067 (((u_int32_t)(src)\
41069 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__WRITE(src) \
41070 (((u_int32_t)(src)\
41072 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__MODIFY(dst, src) \
41074 ~0x01000000U) | (((u_int32_t)(src) <<\
41076 #define TXIQCAL_CONTROL_3__ADC_SAT_LEN__VERIFY(src) \
41077 (!((((u_int32_t)(src)\
41090 #define TXIQCAL_CONTROL_3__ADC_SAT_SEL__READ(src) \
41091 (((u_int32_t)(src)\
41093 #define TXIQCAL_CONTROL_3__ADC_SAT_SEL__WRITE(src) \
41094 (((u_int32_t)(src)\
41096 #define TXIQCAL_CONTROL_3__ADC_SAT_SEL__MODIFY(dst, src) \
41098 ~0x06000000U) | (((u_int32_t)(src) <<\
41100 #define TXIQCAL_CONTROL_3__ADC_SAT_SEL__VERIFY(src) \
41101 (!((((u_int32_t)(src)\
41108 #define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__READ(src) \
41109 (((u_int32_t)(src)\
41111 #define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__WRITE(src) \
41112 (((u_int32_t)(src)\
41114 #define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__MODIFY(dst, src) \
41116 ~0x18000000U) | (((u_int32_t)(src) <<\
41118 #define TXIQCAL_CONTROL_3__IQCAL_MEAS_LEN__VERIFY(src) \
41119 (!((((u_int32_t)(src)\
41126 #define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__READ(src) \
41127 (((u_int32_t)(src)\
41129 #define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__WRITE(src) \
41130 (((u_int32_t)(src)\
41132 #define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__MODIFY(dst, src) \
41134 ~0x60000000U) | (((u_int32_t)(src) <<\
41136 #define TXIQCAL_CONTROL_3__DESIRED_SIZE_DB__VERIFY(src) \
41137 (!((((u_int32_t)(src)\
41144 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__READ(src) \
41145 (((u_int32_t)(src)\
41147 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__WRITE(src) \
41148 (((u_int32_t)(src)\
41150 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__MODIFY(dst, src) \
41152 ~0x80000000U) | (((u_int32_t)(src) <<\
41154 #define TXIQCAL_CONTROL_3__TX_IQCORR_EN__VERIFY(src) \
41155 (!((((u_int32_t)(src)\
41181 #define IQ_ADC_MEAS_0_B0__GAIN_DC_IQ_CAL_MEAS_0_0__READ(src) \
41182 (u_int32_t)(src)\
41201 #define IQ_ADC_MEAS_1_B0__GAIN_DC_IQ_CAL_MEAS_1_0__READ(src) \
41202 (u_int32_t)(src)\
41221 #define IQ_ADC_MEAS_2_B0__GAIN_DC_IQ_CAL_MEAS_2_0__READ(src) \
41222 (u_int32_t)(src)\
41241 #define IQ_ADC_MEAS_3_B0__GAIN_DC_IQ_CAL_MEAS_3_0__READ(src) \
41242 (u_int32_t)(src)\
41261 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__READ(src) \
41262 (u_int32_t)(src)\
41264 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__WRITE(src) \
41265 ((u_int32_t)(src)\
41267 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__MODIFY(dst, src) \
41269 ~0x00000001U) | ((u_int32_t)(src) &\
41271 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ENABLE_0__VERIFY(src) \
41272 (!(((u_int32_t)(src)\
41285 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__READ(src) \
41286 (((u_int32_t)(src)\
41288 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__WRITE(src) \
41289 (((u_int32_t)(src)\
41291 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__MODIFY(dst, src) \
41293 ~0x0000007eU) | (((u_int32_t)(src) <<\
41295 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_BIAS_0__VERIFY(src) \
41296 (!((((u_int32_t)(src)\
41303 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__READ(src) \
41304 (((u_int32_t)(src)\
41306 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__WRITE(src) \
41307 (((u_int32_t)(src)\
41309 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__MODIFY(dst, src) \
41311 ~0x0001ff80U) | (((u_int32_t)(src) <<\
41313 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_INIT_0__VERIFY(src) \
41314 (!((((u_int32_t)(src)\
41321 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__READ(src) \
41322 (((u_int32_t)(src)\
41324 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__WRITE(src) \
41325 (((u_int32_t)(src)\
41327 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__MODIFY(dst, src) \
41329 ~0x01fe0000U) | (((u_int32_t)(src) <<\
41331 #define TX_PHASE_RAMP_B0__CF_PHASE_RAMP_ALPHA_0__VERIFY(src) \
41332 (!((((u_int32_t)(src)\
41352 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__READ(src) \
41353 (u_int32_t)(src)\
41355 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__WRITE(src) \
41356 ((u_int32_t)(src)\
41358 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__MODIFY(dst, src) \
41360 ~0x0000003fU) | ((u_int32_t)(src) &\
41362 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_Q_COEFF_0__VERIFY(src) \
41363 (!(((u_int32_t)(src)\
41370 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__READ(src) \
41371 (((u_int32_t)(src)\
41373 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__WRITE(src) \
41374 (((u_int32_t)(src)\
41376 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__MODIFY(dst, src) \
41378 ~0x00000fc0U) | (((u_int32_t)(src) <<\
41380 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_I_COEFF_0__VERIFY(src) \
41381 (!((((u_int32_t)(src)\
41388 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__READ(src) \
41389 (((u_int32_t)(src)\
41391 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__WRITE(src) \
41392 (((u_int32_t)(src)\
41394 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__MODIFY(dst, src) \
41396 ~0x001ff000U) | (((u_int32_t)(src) <<\
41398 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_Q_COEFF_0__VERIFY(src) \
41399 (!((((u_int32_t)(src)\
41406 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__READ(src) \
41407 (((u_int32_t)(src)\
41409 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__WRITE(src) \
41410 (((u_int32_t)(src)\
41412 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__MODIFY(dst, src) \
41414 ~0x3fe00000U) | (((u_int32_t)(src) <<\
41416 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_I_COEFF_0__VERIFY(src) \
41417 (!((((u_int32_t)(src)\
41424 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__READ(src) \
41425 (((u_int32_t)(src)\
41427 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__WRITE(src) \
41428 (((u_int32_t)(src)\
41430 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__MODIFY(dst, src) \
41432 ~0x40000000U) | (((u_int32_t)(src) <<\
41434 #define ADC_GAIN_DC_CORR_B0__ADC_GAIN_CORR_ENABLE__VERIFY(src) \
41435 (!((((u_int32_t)(src)\
41448 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__READ(src) \
41449 (((u_int32_t)(src)\
41451 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__WRITE(src) \
41452 (((u_int32_t)(src)\
41454 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__MODIFY(dst, src) \
41456 ~0x80000000U) | (((u_int32_t)(src) <<\
41458 #define ADC_GAIN_DC_CORR_B0__ADC_DC_CORR_ENABLE__VERIFY(src) \
41459 (!((((u_int32_t)(src)\
41485 #define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__READ(src) \
41486 (u_int32_t)(src)\
41488 #define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__WRITE(src) \
41489 ((u_int32_t)(src)\
41491 #define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \
41493 ~0x0000007fU) | ((u_int32_t)(src) &\
41495 #define RX_IQ_CORR_B0__RX_IQCORR_Q_Q_COFF_0__VERIFY(src) \
41496 (!(((u_int32_t)(src)\
41503 #define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__READ(src) \
41504 (((u_int32_t)(src)\
41506 #define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__WRITE(src) \
41507 (((u_int32_t)(src)\
41509 #define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \
41511 ~0x00003f80U) | (((u_int32_t)(src) <<\
41513 #define RX_IQ_CORR_B0__RX_IQCORR_Q_I_COFF_0__VERIFY(src) \
41514 (!((((u_int32_t)(src)\
41521 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__READ(src) \
41522 (((u_int32_t)(src)\
41524 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__WRITE(src) \
41525 (((u_int32_t)(src)\
41527 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__MODIFY(dst, src) \
41529 ~0x00004000U) | (((u_int32_t)(src) <<\
41531 #define RX_IQ_CORR_B0__RX_IQCORR_ENABLE__VERIFY(src) \
41532 (!((((u_int32_t)(src)\
41545 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__READ(src) \
41546 (((u_int32_t)(src)\
41548 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__WRITE(src) \
41549 (((u_int32_t)(src)\
41551 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__MODIFY(dst, src) \
41553 ~0x003f8000U) | (((u_int32_t)(src) <<\
41555 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_Q_COFF_0__VERIFY(src) \
41556 (!((((u_int32_t)(src)\
41563 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__READ(src) \
41564 (((u_int32_t)(src)\
41566 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__WRITE(src) \
41567 (((u_int32_t)(src)\
41569 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__MODIFY(dst, src) \
41571 ~0x1fc00000U) | (((u_int32_t)(src) <<\
41573 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_Q_I_COFF_0__VERIFY(src) \
41574 (!((((u_int32_t)(src)\
41581 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__READ(src) \
41582 (((u_int32_t)(src)\
41584 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__WRITE(src) \
41585 (((u_int32_t)(src)\
41587 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__MODIFY(dst, src) \
41589 ~0x20000000U) | (((u_int32_t)(src) <<\
41591 #define RX_IQ_CORR_B0__LOOPBACK_IQCORR_ENABLE__VERIFY(src) \
41592 (!((((u_int32_t)(src)\
41618 #define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__READ(src) \
41619 (u_int32_t)(src)\
41621 #define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__WRITE(src) \
41622 ((u_int32_t)(src)\
41624 #define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__MODIFY(dst, src) \
41626 ~0x01ffffffU) | ((u_int32_t)(src) &\
41628 #define PAPRD_AM2AM_MASK__PAPRD_AM2AM_MASK__VERIFY(src) \
41629 (!(((u_int32_t)(src)\
41649 #define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__READ(src) \
41650 (u_int32_t)(src)\
41652 #define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__WRITE(src) \
41653 ((u_int32_t)(src)\
41655 #define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__MODIFY(dst, src) \
41657 ~0x01ffffffU) | ((u_int32_t)(src) &\
41659 #define PAPRD_AM2PM_MASK__PAPRD_AM2PM_MASK__VERIFY(src) \
41660 (!(((u_int32_t)(src)\
41680 #define PAPRD_HT40_MASK__PAPRD_HT40_MASK__READ(src) \
41681 (u_int32_t)(src)\
41683 #define PAPRD_HT40_MASK__PAPRD_HT40_MASK__WRITE(src) \
41684 ((u_int32_t)(src)\
41686 #define PAPRD_HT40_MASK__PAPRD_HT40_MASK__MODIFY(dst, src) \
41688 ~0x01ffffffU) | ((u_int32_t)(src) &\
41690 #define PAPRD_HT40_MASK__PAPRD_HT40_MASK__VERIFY(src) \
41691 (!(((u_int32_t)(src)\
41711 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__READ(src) \
41712 (u_int32_t)(src)\
41714 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__WRITE(src) \
41715 ((u_int32_t)(src)\
41717 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__MODIFY(dst, src) \
41719 ~0x00000001U) | ((u_int32_t)(src) &\
41721 #define PAPRD_CTRL0_B0__PAPRD_ENABLE_0__VERIFY(src) \
41722 (!(((u_int32_t)(src)\
41735 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__READ(src) \
41736 (((u_int32_t)(src)\
41738 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__WRITE(src) \
41739 (((u_int32_t)(src)\
41741 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__MODIFY(dst, src) \
41743 ~0x00000002U) | (((u_int32_t)(src) <<\
41745 #define PAPRD_CTRL0_B0__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_0__VERIFY(src) \
41746 (!((((u_int32_t)(src)\
41759 #define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__READ(src) \
41760 (((u_int32_t)(src)\
41762 #define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__WRITE(src) \
41763 (((u_int32_t)(src)\
41765 #define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__MODIFY(dst, src) \
41767 ~0x07fffffcU) | (((u_int32_t)(src) <<\
41769 #define PAPRD_CTRL0_B0__PAPRD_VALID_GAIN_0__VERIFY(src) \
41770 (!((((u_int32_t)(src)\
41777 #define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__READ(src) \
41778 (((u_int32_t)(src)\
41780 #define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__WRITE(src) \
41781 (((u_int32_t)(src)\
41783 #define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__MODIFY(dst, src) \
41785 ~0xf8000000U) | (((u_int32_t)(src) <<\
41787 #define PAPRD_CTRL0_B0__PAPRD_MAG_THRSH_0__VERIFY(src) \
41788 (!((((u_int32_t)(src)\
41808 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__READ(src) \
41809 (u_int32_t)(src)\
41811 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__WRITE(src) \
41812 ((u_int32_t)(src)\
41814 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__MODIFY(dst, src) \
41816 ~0x00000001U) | ((u_int32_t)(src) &\
41818 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_SCALING_ENABLE_0__VERIFY(src) \
41819 (!(((u_int32_t)(src)\
41832 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__READ(src) \
41833 (((u_int32_t)(src)\
41835 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__WRITE(src) \
41836 (((u_int32_t)(src)\
41838 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__MODIFY(dst, src) \
41840 ~0x00000002U) | (((u_int32_t)(src) <<\
41842 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2AM_ENABLE_0__VERIFY(src) \
41843 (!((((u_int32_t)(src)\
41856 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__READ(src) \
41857 (((u_int32_t)(src)\
41859 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__WRITE(src) \
41860 (((u_int32_t)(src)\
41862 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__MODIFY(dst, src) \
41864 ~0x00000004U) | (((u_int32_t)(src) <<\
41866 #define PAPRD_CTRL1_B0__PAPRD_ADAPTIVE_AM2PM_ENABLE_0__VERIFY(src) \
41867 (!((((u_int32_t)(src)\
41880 #define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__READ(src) \
41881 (((u_int32_t)(src)\
41883 #define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__WRITE(src) \
41884 (((u_int32_t)(src)\
41886 #define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__MODIFY(dst, src) \
41888 ~0x000001f8U) | (((u_int32_t)(src) <<\
41890 #define PAPRD_CTRL1_B0__PAPRD_POWER_AT_AM2AM_CAL_0__VERIFY(src) \
41891 (!((((u_int32_t)(src)\
41898 #define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__READ(src) \
41899 (((u_int32_t)(src)\
41901 #define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__WRITE(src) \
41902 (((u_int32_t)(src)\
41904 #define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__MODIFY(dst, src) \
41906 ~0x0001fe00U) | (((u_int32_t)(src) <<\
41908 #define PAPRD_CTRL1_B0__PA_GAIN_SCALE_FACTOR_0__VERIFY(src) \
41909 (!((((u_int32_t)(src)\
41916 #define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__READ(src) \
41917 (((u_int32_t)(src)\
41919 #define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__WRITE(src) \
41920 (((u_int32_t)(src)\
41922 #define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__MODIFY(dst, src) \
41924 ~0x07fe0000U) | (((u_int32_t)(src) <<\
41926 #define PAPRD_CTRL1_B0__PAPRD_MAG_SCALE_FACTOR_0__VERIFY(src) \
41927 (!((((u_int32_t)(src)\
41934 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__READ(src) \
41935 (((u_int32_t)(src)\
41937 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__WRITE(src) \
41938 (((u_int32_t)(src)\
41940 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__MODIFY(dst, src) \
41942 ~0x08000000U) | (((u_int32_t)(src) <<\
41944 #define PAPRD_CTRL1_B0__PAPRD_TRAINER_IANDQ_SEL_0__VERIFY(src) \
41945 (!((((u_int32_t)(src)\
41971 #define PA_GAIN123_B0__PA_GAIN1_0__READ(src) (u_int32_t)(src) & 0x000003ffU
41972 #define PA_GAIN123_B0__PA_GAIN1_0__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
41973 #define PA_GAIN123_B0__PA_GAIN1_0__MODIFY(dst, src) \
41975 ~0x000003ffU) | ((u_int32_t)(src) &\
41977 #define PA_GAIN123_B0__PA_GAIN1_0__VERIFY(src) \
41978 (!(((u_int32_t)(src)\
41985 #define PA_GAIN123_B0__PA_GAIN2_0__READ(src) \
41986 (((u_int32_t)(src)\
41988 #define PA_GAIN123_B0__PA_GAIN2_0__WRITE(src) \
41989 (((u_int32_t)(src)\
41991 #define PA_GAIN123_B0__PA_GAIN2_0__MODIFY(dst, src) \
41993 ~0x000ffc00U) | (((u_int32_t)(src) <<\
41995 #define PA_GAIN123_B0__PA_GAIN2_0__VERIFY(src) \
41996 (!((((u_int32_t)(src)\
42003 #define PA_GAIN123_B0__PA_GAIN3_0__READ(src) \
42004 (((u_int32_t)(src)\
42006 #define PA_GAIN123_B0__PA_GAIN3_0__WRITE(src) \
42007 (((u_int32_t)(src)\
42009 #define PA_GAIN123_B0__PA_GAIN3_0__MODIFY(dst, src) \
42011 ~0x3ff00000U) | (((u_int32_t)(src) <<\
42013 #define PA_GAIN123_B0__PA_GAIN3_0__VERIFY(src) \
42014 (!((((u_int32_t)(src)\
42034 #define PA_GAIN45_B0__PA_GAIN4_0__READ(src) (u_int32_t)(src) & 0x000003ffU
42035 #define PA_GAIN45_B0__PA_GAIN4_0__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
42036 #define PA_GAIN45_B0__PA_GAIN4_0__MODIFY(dst, src) \
42038 ~0x000003ffU) | ((u_int32_t)(src) &\
42040 #define PA_GAIN45_B0__PA_GAIN4_0__VERIFY(src) \
42041 (!(((u_int32_t)(src)\
42048 #define PA_GAIN45_B0__PA_GAIN5_0__READ(src) \
42049 (((u_int32_t)(src)\
42051 #define PA_GAIN45_B0__PA_GAIN5_0__WRITE(src) \
42052 (((u_int32_t)(src)\
42054 #define PA_GAIN45_B0__PA_GAIN5_0__MODIFY(dst, src) \
42056 ~0x000ffc00U) | (((u_int32_t)(src) <<\
42058 #define PA_GAIN45_B0__PA_GAIN5_0__VERIFY(src) \
42059 (!((((u_int32_t)(src)\
42066 #define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__READ(src) \
42067 (((u_int32_t)(src)\
42069 #define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__WRITE(src) \
42070 (((u_int32_t)(src)\
42072 #define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__MODIFY(dst, src) \
42074 ~0x01f00000U) | (((u_int32_t)(src) <<\
42076 #define PA_GAIN45_B0__PAPRD_ADAPTIVE_TABLE_VALID_0__VERIFY(src) \
42077 (!((((u_int32_t)(src)\
42097 #define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__READ(src) \
42098 (u_int32_t)(src)\
42100 #define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__WRITE(src) \
42101 ((u_int32_t)(src)\
42103 #define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__MODIFY(dst, src) \
42105 ~0x0003ffffU) | ((u_int32_t)(src) &\
42107 #define PAPRD_PRE_POST_SCALE_0_B0__PAPRD_PRE_POST_SCALING_0_0__VERIFY(src) \
42108 (!(((u_int32_t)(src)\
42128 #define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__READ(src) \
42129 (u_int32_t)(src)\
42131 #define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__WRITE(src) \
42132 ((u_int32_t)(src)\
42134 #define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__MODIFY(dst, src) \
42136 ~0x0003ffffU) | ((u_int32_t)(src) &\
42138 #define PAPRD_PRE_POST_SCALE_1_B0__PAPRD_PRE_POST_SCALING_1_0__VERIFY(src) \
42139 (!(((u_int32_t)(src)\
42159 #define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__READ(src) \
42160 (u_int32_t)(src)\
42162 #define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__WRITE(src) \
42163 ((u_int32_t)(src)\
42165 #define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__MODIFY(dst, src) \
42167 ~0x0003ffffU) | ((u_int32_t)(src) &\
42169 #define PAPRD_PRE_POST_SCALE_2_B0__PAPRD_PRE_POST_SCALING_2_0__VERIFY(src) \
42170 (!(((u_int32_t)(src)\
42190 #define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__READ(src) \
42191 (u_int32_t)(src)\
42193 #define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__WRITE(src) \
42194 ((u_int32_t)(src)\
42196 #define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__MODIFY(dst, src) \
42198 ~0x0003ffffU) | ((u_int32_t)(src) &\
42200 #define PAPRD_PRE_POST_SCALE_3_B0__PAPRD_PRE_POST_SCALING_3_0__VERIFY(src) \
42201 (!(((u_int32_t)(src)\
42221 #define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__READ(src) \
42222 (u_int32_t)(src)\
42224 #define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__WRITE(src) \
42225 ((u_int32_t)(src)\
42227 #define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__MODIFY(dst, src) \
42229 ~0x0003ffffU) | ((u_int32_t)(src) &\
42231 #define PAPRD_PRE_POST_SCALE_4_B0__PAPRD_PRE_POST_SCALING_4_0__VERIFY(src) \
42232 (!(((u_int32_t)(src)\
42252 #define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__READ(src) \
42253 (u_int32_t)(src)\
42255 #define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__WRITE(src) \
42256 ((u_int32_t)(src)\
42258 #define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__MODIFY(dst, src) \
42260 ~0x0003ffffU) | ((u_int32_t)(src) &\
42262 #define PAPRD_PRE_POST_SCALE_5_B0__PAPRD_PRE_POST_SCALING_5_0__VERIFY(src) \
42263 (!(((u_int32_t)(src)\
42283 #define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__READ(src) \
42284 (u_int32_t)(src)\
42286 #define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__WRITE(src) \
42287 ((u_int32_t)(src)\
42289 #define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__MODIFY(dst, src) \
42291 ~0x0003ffffU) | ((u_int32_t)(src) &\
42293 #define PAPRD_PRE_POST_SCALE_6_B0__PAPRD_PRE_POST_SCALING_6_0__VERIFY(src) \
42294 (!(((u_int32_t)(src)\
42314 #define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__READ(src) \
42315 (u_int32_t)(src)\
42317 #define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__WRITE(src) \
42318 ((u_int32_t)(src)\
42320 #define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__MODIFY(dst, src) \
42322 ~0x0003ffffU) | ((u_int32_t)(src) &\
42324 #define PAPRD_PRE_POST_SCALE_7_B0__PAPRD_PRE_POST_SCALING_7_0__VERIFY(src) \
42325 (!(((u_int32_t)(src)\
42345 #define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU
42346 #define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU)
42347 #define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
42349 ~0x003fffffU) | ((u_int32_t)(src) &\
42351 #define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \
42352 (!(((u_int32_t)(src)\
42372 #define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \
42373 (u_int32_t)(src)\
42392 #define TIMING_CONTROL_3A__STE_THR_HI_RSSI__READ(src) \
42393 (u_int32_t)(src)\
42395 #define TIMING_CONTROL_3A__STE_THR_HI_RSSI__WRITE(src) \
42396 ((u_int32_t)(src)\
42398 #define TIMING_CONTROL_3A__STE_THR_HI_RSSI__MODIFY(dst, src) \
42400 ~0x0000007fU) | ((u_int32_t)(src) &\
42402 #define TIMING_CONTROL_3A__STE_THR_HI_RSSI__VERIFY(src) \
42403 (!(((u_int32_t)(src)\
42410 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__READ(src) \
42411 (((u_int32_t)(src)\
42413 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__WRITE(src) \
42414 (((u_int32_t)(src)\
42416 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__MODIFY(dst, src) \
42418 ~0x00000080U) | (((u_int32_t)(src) <<\
42420 #define TIMING_CONTROL_3A__USE_HTSIG1_20_40_BW_VALUE__VERIFY(src) \
42421 (!((((u_int32_t)(src)\
42447 #define LDPC_CNTL1__LDPC_LLR_SCALING0__READ(src) (u_int32_t)(src) & 0xffffffffU
42448 #define LDPC_CNTL1__LDPC_LLR_SCALING0__WRITE(src) \
42449 ((u_int32_t)(src)\
42451 #define LDPC_CNTL1__LDPC_LLR_SCALING0__MODIFY(dst, src) \
42453 ~0xffffffffU) | ((u_int32_t)(src) &\
42455 #define LDPC_CNTL1__LDPC_LLR_SCALING0__VERIFY(src) \
42456 (!(((u_int32_t)(src)\
42476 #define LDPC_CNTL2__LDPC_LLR_SCALING1__READ(src) (u_int32_t)(src) & 0x0000ffffU
42477 #define LDPC_CNTL2__LDPC_LLR_SCALING1__WRITE(src) \
42478 ((u_int32_t)(src)\
42480 #define LDPC_CNTL2__LDPC_LLR_SCALING1__MODIFY(dst, src) \
42482 ~0x0000ffffU) | ((u_int32_t)(src) &\
42484 #define LDPC_CNTL2__LDPC_LLR_SCALING1__VERIFY(src) \
42485 (!(((u_int32_t)(src)\
42492 #define LDPC_CNTL2__LDPC_LATENCY__READ(src) \
42493 (((u_int32_t)(src)\
42495 #define LDPC_CNTL2__LDPC_LATENCY__WRITE(src) \
42496 (((u_int32_t)(src)\
42498 #define LDPC_CNTL2__LDPC_LATENCY__MODIFY(dst, src) \
42500 ~0x07ff0000U) | (((u_int32_t)(src) <<\
42502 #define LDPC_CNTL2__LDPC_LATENCY__VERIFY(src) \
42503 (!((((u_int32_t)(src)\
42523 #define PILOT_SPUR_MASK__CF_PILOT_MASK_A__READ(src) \
42524 (u_int32_t)(src)\
42526 #define PILOT_SPUR_MASK__CF_PILOT_MASK_A__WRITE(src) \
42527 ((u_int32_t)(src)\
42529 #define PILOT_SPUR_MASK__CF_PILOT_MASK_A__MODIFY(dst, src) \
42531 ~0x0000001fU) | ((u_int32_t)(src) &\
42533 #define PILOT_SPUR_MASK__CF_PILOT_MASK_A__VERIFY(src) \
42534 (!(((u_int32_t)(src)\
42541 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__READ(src) \
42542 (((u_int32_t)(src)\
42544 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__WRITE(src) \
42545 (((u_int32_t)(src)\
42547 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__MODIFY(dst, src) \
42549 ~0x00000fe0U) | (((u_int32_t)(src) <<\
42551 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_A__VERIFY(src) \
42552 (!((((u_int32_t)(src)\
42559 #define PILOT_SPUR_MASK__CF_PILOT_MASK_B__READ(src) \
42560 (((u_int32_t)(src)\
42562 #define PILOT_SPUR_MASK__CF_PILOT_MASK_B__WRITE(src) \
42563 (((u_int32_t)(src)\
42565 #define PILOT_SPUR_MASK__CF_PILOT_MASK_B__MODIFY(dst, src) \
42567 ~0x0001f000U) | (((u_int32_t)(src) <<\
42569 #define PILOT_SPUR_MASK__CF_PILOT_MASK_B__VERIFY(src) \
42570 (!((((u_int32_t)(src)\
42577 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__READ(src) \
42578 (((u_int32_t)(src)\
42580 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__WRITE(src) \
42581 (((u_int32_t)(src)\
42583 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__MODIFY(dst, src) \
42585 ~0x00fe0000U) | (((u_int32_t)(src) <<\
42587 #define PILOT_SPUR_MASK__CF_PILOT_MASK_IDX_B__VERIFY(src) \
42588 (!((((u_int32_t)(src)\
42608 #define CHAN_SPUR_MASK__CF_CHAN_MASK_A__READ(src) \
42609 (u_int32_t)(src)\
42611 #define CHAN_SPUR_MASK__CF_CHAN_MASK_A__WRITE(src) \
42612 ((u_int32_t)(src)\
42614 #define CHAN_SPUR_MASK__CF_CHAN_MASK_A__MODIFY(dst, src) \
42616 ~0x0000001fU) | ((u_int32_t)(src) &\
42618 #define CHAN_SPUR_MASK__CF_CHAN_MASK_A__VERIFY(src) \
42619 (!(((u_int32_t)(src)\
42626 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__READ(src) \
42627 (((u_int32_t)(src)\
42629 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__WRITE(src) \
42630 (((u_int32_t)(src)\
42632 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__MODIFY(dst, src) \
42634 ~0x00000fe0U) | (((u_int32_t)(src) <<\
42636 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_A__VERIFY(src) \
42637 (!((((u_int32_t)(src)\
42644 #define CHAN_SPUR_MASK__CF_CHAN_MASK_B__READ(src) \
42645 (((u_int32_t)(src)\
42647 #define CHAN_SPUR_MASK__CF_CHAN_MASK_B__WRITE(src) \
42648 (((u_int32_t)(src)\
42650 #define CHAN_SPUR_MASK__CF_CHAN_MASK_B__MODIFY(dst, src) \
42652 ~0x0001f000U) | (((u_int32_t)(src) <<\
42654 #define CHAN_SPUR_MASK__CF_CHAN_MASK_B__VERIFY(src) \
42655 (!((((u_int32_t)(src)\
42662 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__READ(src) \
42663 (((u_int32_t)(src)\
42665 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__WRITE(src) \
42666 (((u_int32_t)(src)\
42668 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__MODIFY(dst, src) \
42670 ~0x00fe0000U) | (((u_int32_t)(src) <<\
42672 #define CHAN_SPUR_MASK__CF_CHAN_MASK_IDX_B__VERIFY(src) \
42673 (!((((u_int32_t)(src)\
42693 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__READ(src) \
42694 (u_int32_t)(src)\
42696 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__WRITE(src) \
42697 ((u_int32_t)(src)\
42699 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__MODIFY(dst, src) \
42701 ~0x0000000fU) | ((u_int32_t)(src) &\
42703 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_EXP_SHORT_GI__VERIFY(src) \
42704 (!(((u_int32_t)(src)\
42711 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__READ(src) \
42712 (((u_int32_t)(src)\
42714 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__WRITE(src) \
42715 (((u_int32_t)(src)\
42717 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__MODIFY(dst, src) \
42719 ~0x0007fff0U) | (((u_int32_t)(src) <<\
42721 #define SHORT_GI_DELTA_SLOPE__DELTA_SLOPE_COEF_MAN_SHORT_GI__VERIFY(src) \
42722 (!((((u_int32_t)(src)\
42742 #define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__READ(src) \
42743 (u_int32_t)(src)\
42745 #define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__WRITE(src) \
42746 ((u_int32_t)(src)\
42748 #define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__MODIFY(dst, src) \
42750 ~0x00ffffffU) | ((u_int32_t)(src) &\
42752 #define ML_CNTL1__CF_ML_2S_WEIGHT_TABLE__VERIFY(src) \
42753 (!(((u_int32_t)(src)\
42760 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__READ(src) \
42761 (((u_int32_t)(src)\
42763 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__WRITE(src) \
42764 (((u_int32_t)(src)\
42766 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__MODIFY(dst, src) \
42768 ~0x03000000U) | (((u_int32_t)(src) <<\
42770 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ML__VERIFY(src) \
42771 (!((((u_int32_t)(src)\
42778 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__READ(src) \
42779 (((u_int32_t)(src)\
42781 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__WRITE(src) \
42782 (((u_int32_t)(src)\
42784 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__MODIFY(dst, src) \
42786 ~0x0c000000U) | (((u_int32_t)(src) <<\
42788 #define ML_CNTL1__CF_IS_FLAT_CH_THR_ZF__VERIFY(src) \
42789 (!((((u_int32_t)(src)\
42809 #define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__READ(src) \
42810 (u_int32_t)(src)\
42812 #define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__WRITE(src) \
42813 ((u_int32_t)(src)\
42815 #define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__MODIFY(dst, src) \
42817 ~0x00ffffffU) | ((u_int32_t)(src) &\
42819 #define ML_CNTL2__CF_ML_3S_WEIGHT_TABLE__VERIFY(src) \
42820 (!(((u_int32_t)(src)\
42840 #define TSTADC__TSTADC_OUT_Q__READ(src) (u_int32_t)(src) & 0x000003ffU
42846 #define TSTADC__TSTADC_OUT_I__READ(src) \
42847 (((u_int32_t)(src)\
42866 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__READ(src) \
42867 (u_int32_t)(src)\
42869 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__WRITE(src) \
42870 ((u_int32_t)(src)\
42872 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__MODIFY(dst, src) \
42874 ~0x00000007U) | ((u_int32_t)(src) &\
42876 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD_2__VERIFY(src) \
42877 (!(((u_int32_t)(src)\
42884 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__READ(src) \
42885 (((u_int32_t)(src)\
42887 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__WRITE(src) \
42888 (((u_int32_t)(src)\
42890 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__MODIFY(dst, src) \
42892 ~0x000000f8U) | (((u_int32_t)(src) <<\
42894 #define BBB_RX_CTRL_1__COARSE_TIM_THRESHOLD__VERIFY(src) \
42895 (!((((u_int32_t)(src)\
42902 #define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__READ(src) \
42903 (((u_int32_t)(src)\
42905 #define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__WRITE(src) \
42906 (((u_int32_t)(src)\
42908 #define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__MODIFY(dst, src) \
42910 ~0x00000700U) | (((u_int32_t)(src) <<\
42912 #define BBB_RX_CTRL_1__COARSE_TIM_N_SYNC__VERIFY(src) \
42913 (!((((u_int32_t)(src)\
42920 #define BBB_RX_CTRL_1__MAX_BAL_LONG__READ(src) \
42921 (((u_int32_t)(src)\
42923 #define BBB_RX_CTRL_1__MAX_BAL_LONG__WRITE(src) \
42924 (((u_int32_t)(src)\
42926 #define BBB_RX_CTRL_1__MAX_BAL_LONG__MODIFY(dst, src) \
42928 ~0x0000f800U) | (((u_int32_t)(src) <<\
42930 #define BBB_RX_CTRL_1__MAX_BAL_LONG__VERIFY(src) \
42931 (!((((u_int32_t)(src)\
42938 #define BBB_RX_CTRL_1__MAX_BAL_SHORT__READ(src) \
42939 (((u_int32_t)(src)\
42941 #define BBB_RX_CTRL_1__MAX_BAL_SHORT__WRITE(src) \
42942 (((u_int32_t)(src)\
42944 #define BBB_RX_CTRL_1__MAX_BAL_SHORT__MODIFY(dst, src) \
42946 ~0x001f0000U) | (((u_int32_t)(src) <<\
42948 #define BBB_RX_CTRL_1__MAX_BAL_SHORT__VERIFY(src) \
42949 (!((((u_int32_t)(src)\
42956 #define BBB_RX_CTRL_1__RECON_LMS_STEP__READ(src) \
42957 (((u_int32_t)(src)\
42959 #define BBB_RX_CTRL_1__RECON_LMS_STEP__WRITE(src) \
42960 (((u_int32_t)(src)\
42962 #define BBB_RX_CTRL_1__RECON_LMS_STEP__MODIFY(dst, src) \
42964 ~0x00e00000U) | (((u_int32_t)(src) <<\
42966 #define BBB_RX_CTRL_1__RECON_LMS_STEP__VERIFY(src) \
42967 (!((((u_int32_t)(src)\
42974 #define BBB_RX_CTRL_1__SB_CHECK_WIN__READ(src) \
42975 (((u_int32_t)(src)\
42977 #define BBB_RX_CTRL_1__SB_CHECK_WIN__WRITE(src) \
42978 (((u_int32_t)(src)\
42980 #define BBB_RX_CTRL_1__SB_CHECK_WIN__MODIFY(dst, src) \
42982 ~0x7f000000U) | (((u_int32_t)(src) <<\
42984 #define BBB_RX_CTRL_1__SB_CHECK_WIN__VERIFY(src) \
42985 (!((((u_int32_t)(src)\
42992 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__READ(src) \
42993 (((u_int32_t)(src)\
42995 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__WRITE(src) \
42996 (((u_int32_t)(src)\
42998 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__MODIFY(dst, src) \
43000 ~0x80000000U) | (((u_int32_t)(src) <<\
43002 #define BBB_RX_CTRL_1__EN_RX_ABORT_CCK__VERIFY(src) \
43003 (!((((u_int32_t)(src)\
43029 #define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__READ(src) \
43030 (u_int32_t)(src)\
43032 #define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__WRITE(src) \
43033 ((u_int32_t)(src)\
43035 #define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__MODIFY(dst, src) \
43037 ~0x0000003fU) | ((u_int32_t)(src) &\
43039 #define BBB_RX_CTRL_2__FREQ_EST_N_AVG_LONG__VERIFY(src) \
43040 (!(((u_int32_t)(src)\
43047 #define BBB_RX_CTRL_2__CHAN_AVG_LONG__READ(src) \
43048 (((u_int32_t)(src)\
43050 #define BBB_RX_CTRL_2__CHAN_AVG_LONG__WRITE(src) \
43051 (((u_int32_t)(src)\
43053 #define BBB_RX_CTRL_2__CHAN_AVG_LONG__MODIFY(dst, src) \
43055 ~0x00000fc0U) | (((u_int32_t)(src) <<\
43057 #define BBB_RX_CTRL_2__CHAN_AVG_LONG__VERIFY(src) \
43058 (!((((u_int32_t)(src)\
43065 #define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__READ(src) \
43066 (((u_int32_t)(src)\
43068 #define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__WRITE(src) \
43069 (((u_int32_t)(src)\
43071 #define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__MODIFY(dst, src) \
43073 ~0x0001f000U) | (((u_int32_t)(src) <<\
43075 #define BBB_RX_CTRL_2__COARSE_TIM_THRESHOLD_3__VERIFY(src) \
43076 (!((((u_int32_t)(src)\
43083 #define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__READ(src) \
43084 (((u_int32_t)(src)\
43086 #define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__WRITE(src) \
43087 (((u_int32_t)(src)\
43089 #define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__MODIFY(dst, src) \
43091 ~0x003e0000U) | (((u_int32_t)(src) <<\
43093 #define BBB_RX_CTRL_2__FREQ_TRACK_UPDATE_PERIOD__VERIFY(src) \
43094 (!((((u_int32_t)(src)\
43101 #define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__READ(src) \
43102 (((u_int32_t)(src)\
43104 #define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__WRITE(src) \
43105 (((u_int32_t)(src)\
43107 #define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__MODIFY(dst, src) \
43109 ~0x03c00000U) | (((u_int32_t)(src) <<\
43111 #define BBB_RX_CTRL_2__FREQ_EST_SCALING_PERIOD__VERIFY(src) \
43112 (!((((u_int32_t)(src)\
43119 #define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__READ(src) \
43120 (((u_int32_t)(src)\
43122 #define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__WRITE(src) \
43123 (((u_int32_t)(src)\
43125 #define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__MODIFY(dst, src) \
43127 ~0xfc000000U) | (((u_int32_t)(src) <<\
43129 #define BBB_RX_CTRL_2__LOOP_COEF_DPSK_C2_DATA__VERIFY(src) \
43130 (!((((u_int32_t)(src)\
43150 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__READ(src) \
43151 (u_int32_t)(src)\
43153 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__WRITE(src) \
43154 ((u_int32_t)(src)\
43156 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__MODIFY(dst, src) \
43158 ~0x000000ffU) | ((u_int32_t)(src) &\
43160 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_DPSK__VERIFY(src) \
43161 (!(((u_int32_t)(src)\
43168 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__READ(src) \
43169 (((u_int32_t)(src)\
43171 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__WRITE(src) \
43172 (((u_int32_t)(src)\
43174 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__MODIFY(dst, src) \
43176 ~0x0000ff00U) | (((u_int32_t)(src) <<\
43178 #define BBB_RX_CTRL_3__TIM_ADJUST_FREQ_CCK__VERIFY(src) \
43179 (!((((u_int32_t)(src)\
43186 #define BBB_RX_CTRL_3__TIMER_N_SFD__READ(src) \
43187 (((u_int32_t)(src)\
43189 #define BBB_RX_CTRL_3__TIMER_N_SFD__WRITE(src) \
43190 (((u_int32_t)(src)\
43192 #define BBB_RX_CTRL_3__TIMER_N_SFD__MODIFY(dst, src) \
43194 ~0x00ff0000U) | (((u_int32_t)(src) <<\
43196 #define BBB_RX_CTRL_3__TIMER_N_SFD__VERIFY(src) \
43197 (!((((u_int32_t)(src)\
43217 #define BBB_RX_CTRL_4__TIMER_N_SYNC__READ(src) (u_int32_t)(src) & 0x0000000fU
43218 #define BBB_RX_CTRL_4__TIMER_N_SYNC__WRITE(src) \
43219 ((u_int32_t)(src)\
43221 #define BBB_RX_CTRL_4__TIMER_N_SYNC__MODIFY(dst, src) \
43223 ~0x0000000fU) | ((u_int32_t)(src) &\
43225 #define BBB_RX_CTRL_4__TIMER_N_SYNC__VERIFY(src) \
43226 (!(((u_int32_t)(src)\
43233 #define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__READ(src) \
43234 (((u_int32_t)(src)\
43236 #define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__WRITE(src) \
43237 (((u_int32_t)(src)\
43239 #define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__MODIFY(dst, src) \
43241 ~0x0000fff0U) | (((u_int32_t)(src) <<\
43243 #define BBB_RX_CTRL_4__TIM_ADJUST_TIMER_EXP__VERIFY(src) \
43244 (!((((u_int32_t)(src)\
43251 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__READ(src) \
43252 (((u_int32_t)(src)\
43254 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__WRITE(src) \
43255 (((u_int32_t)(src)\
43257 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__MODIFY(dst, src) \
43259 ~0x00010000U) | (((u_int32_t)(src) <<\
43261 #define BBB_RX_CTRL_4__FORCE_UNLOCKED_CLOCKS__VERIFY(src) \
43262 (!((((u_int32_t)(src)\
43275 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__READ(src) \
43276 (((u_int32_t)(src)\
43278 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__WRITE(src) \
43279 (((u_int32_t)(src)\
43281 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__MODIFY(dst, src) \
43283 ~0x00020000U) | (((u_int32_t)(src) <<\
43285 #define BBB_RX_CTRL_4__DYNAMIC_PREAM_SEL__VERIFY(src) \
43286 (!((((u_int32_t)(src)\
43299 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__READ(src) \
43300 (((u_int32_t)(src)\
43302 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__WRITE(src) \
43303 (((u_int32_t)(src)\
43305 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__MODIFY(dst, src) \
43307 ~0x00040000U) | (((u_int32_t)(src) <<\
43309 #define BBB_RX_CTRL_4__SHORT_PREAMBLE__VERIFY(src) \
43310 (!((((u_int32_t)(src)\
43323 #define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__READ(src) \
43324 (((u_int32_t)(src)\
43326 #define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__WRITE(src) \
43327 (((u_int32_t)(src)\
43329 #define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__MODIFY(dst, src) \
43331 ~0x01f80000U) | (((u_int32_t)(src) <<\
43333 #define BBB_RX_CTRL_4__FREQ_EST_N_AVG_SHORT__VERIFY(src) \
43334 (!((((u_int32_t)(src)\
43341 #define BBB_RX_CTRL_4__CHAN_AVG_SHORT__READ(src) \
43342 (((u_int32_t)(src)\
43344 #define BBB_RX_CTRL_4__CHAN_AVG_SHORT__WRITE(src) \
43345 (((u_int32_t)(src)\
43347 #define BBB_RX_CTRL_4__CHAN_AVG_SHORT__MODIFY(dst, src) \
43349 ~0x7e000000U) | (((u_int32_t)(src) <<\
43351 #define BBB_RX_CTRL_4__CHAN_AVG_SHORT__VERIFY(src) \
43352 (!((((u_int32_t)(src)\
43359 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__READ(src) \
43360 (((u_int32_t)(src)\
43362 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__WRITE(src) \
43363 (((u_int32_t)(src)\
43365 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__MODIFY(dst, src) \
43367 ~0x80000000U) | (((u_int32_t)(src) <<\
43369 #define BBB_RX_CTRL_4__USE_MRC_WEIGHT__VERIFY(src) \
43370 (!((((u_int32_t)(src)\
43396 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__READ(src) \
43397 (u_int32_t)(src)\
43399 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__WRITE(src) \
43400 ((u_int32_t)(src)\
43402 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__MODIFY(dst, src) \
43404 ~0x0000001fU) | ((u_int32_t)(src) &\
43406 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_DATA__VERIFY(src) \
43407 (!(((u_int32_t)(src)\
43414 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__READ(src) \
43415 (((u_int32_t)(src)\
43417 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__WRITE(src) \
43418 (((u_int32_t)(src)\
43420 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__MODIFY(dst, src) \
43422 ~0x000003e0U) | (((u_int32_t)(src) <<\
43424 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C1_HEAD__VERIFY(src) \
43425 (!((((u_int32_t)(src)\
43432 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__READ(src) \
43433 (((u_int32_t)(src)\
43435 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__WRITE(src) \
43436 (((u_int32_t)(src)\
43438 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__MODIFY(dst, src) \
43440 ~0x0000fc00U) | (((u_int32_t)(src) <<\
43442 #define BBB_RX_CTRL_5__LOOP_COEF_DPSK_C2_HEAD__VERIFY(src) \
43443 (!((((u_int32_t)(src)\
43450 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__READ(src) \
43451 (((u_int32_t)(src)\
43453 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__WRITE(src) \
43454 (((u_int32_t)(src)\
43456 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__MODIFY(dst, src) \
43458 ~0x001f0000U) | (((u_int32_t)(src) <<\
43460 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C1__VERIFY(src) \
43461 (!((((u_int32_t)(src)\
43468 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__READ(src) \
43469 (((u_int32_t)(src)\
43471 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__WRITE(src) \
43472 (((u_int32_t)(src)\
43474 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__MODIFY(dst, src) \
43476 ~0x07e00000U) | (((u_int32_t)(src) <<\
43478 #define BBB_RX_CTRL_5__LOOP_COEF_CCK_C2__VERIFY(src) \
43479 (!((((u_int32_t)(src)\
43499 #define BBB_RX_CTRL_6__SYNC_START_DELAY__READ(src) \
43500 (u_int32_t)(src)\
43502 #define BBB_RX_CTRL_6__SYNC_START_DELAY__WRITE(src) \
43503 ((u_int32_t)(src)\
43505 #define BBB_RX_CTRL_6__SYNC_START_DELAY__MODIFY(dst, src) \
43507 ~0x000003ffU) | ((u_int32_t)(src) &\
43509 #define BBB_RX_CTRL_6__SYNC_START_DELAY__VERIFY(src) \
43510 (!(((u_int32_t)(src)\
43517 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__READ(src) \
43518 (((u_int32_t)(src)\
43520 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__WRITE(src) \
43521 (((u_int32_t)(src)\
43523 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__MODIFY(dst, src) \
43525 ~0x00000400U) | (((u_int32_t)(src) <<\
43527 #define BBB_RX_CTRL_6__MAP_1S_TO_2S__VERIFY(src) \
43528 (!((((u_int32_t)(src)\
43541 #define BBB_RX_CTRL_6__START_IIR_DELAY__READ(src) \
43542 (((u_int32_t)(src)\
43544 #define BBB_RX_CTRL_6__START_IIR_DELAY__WRITE(src) \
43545 (((u_int32_t)(src)\
43547 #define BBB_RX_CTRL_6__START_IIR_DELAY__MODIFY(dst, src) \
43549 ~0x001ff800U) | (((u_int32_t)(src) <<\
43551 #define BBB_RX_CTRL_6__START_IIR_DELAY__VERIFY(src) \
43552 (!((((u_int32_t)(src)\
43559 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__READ(src) \
43560 (((u_int32_t)(src)\
43562 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__WRITE(src) \
43563 (((u_int32_t)(src)\
43565 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__MODIFY(dst, src) \
43567 ~0x00200000U) | (((u_int32_t)(src) <<\
43569 #define BBB_RX_CTRL_6__USE_MCORR_WEIGHT__VERIFY(src) \
43570 (!((((u_int32_t)(src)\
43583 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__READ(src) \
43584 (((u_int32_t)(src)\
43586 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__WRITE(src) \
43587 (((u_int32_t)(src)\
43589 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__MODIFY(dst, src) \
43591 ~0x00400000U) | (((u_int32_t)(src) <<\
43593 #define BBB_RX_CTRL_6__USE_BKPWR_FOR_CENTER_INDEX__VERIFY(src) \
43594 (!((((u_int32_t)(src)\
43607 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__READ(src) \
43608 (((u_int32_t)(src)\
43610 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__WRITE(src) \
43611 (((u_int32_t)(src)\
43613 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__MODIFY(dst, src) \
43615 ~0x00800000U) | (((u_int32_t)(src) <<\
43617 #define BBB_RX_CTRL_6__CCK_SEL_CHAIN_BY_EO__VERIFY(src) \
43618 (!((((u_int32_t)(src)\
43631 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__READ(src) \
43632 (((u_int32_t)(src)\
43634 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__WRITE(src) \
43635 (((u_int32_t)(src)\
43637 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__MODIFY(dst, src) \
43639 ~0x01000000U) | (((u_int32_t)(src) <<\
43641 #define BBB_RX_CTRL_6__FORCE_CCK_SEL_CHAIN__VERIFY(src) \
43642 (!((((u_int32_t)(src)\
43655 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__READ(src) \
43656 (((u_int32_t)(src)\
43658 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__WRITE(src) \
43659 (((u_int32_t)(src)\
43661 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__MODIFY(dst, src) \
43663 ~0x02000000U) | (((u_int32_t)(src) <<\
43665 #define BBB_RX_CTRL_6__FORCE_CENTER_INDEX__VERIFY(src) \
43666 (!((((u_int32_t)(src)\
43692 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__READ(src) \
43693 (u_int32_t)(src)\
43695 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__WRITE(src) \
43696 ((u_int32_t)(src)\
43698 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__MODIFY(dst, src) \
43700 ~0x00000001U) | ((u_int32_t)(src) &\
43702 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE0__VERIFY(src) \
43703 (!(((u_int32_t)(src)\
43716 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__READ(src) \
43717 (((u_int32_t)(src)\
43719 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__WRITE(src) \
43720 (((u_int32_t)(src)\
43722 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__MODIFY(dst, src) \
43724 ~0x00000002U) | (((u_int32_t)(src) <<\
43726 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE1__VERIFY(src) \
43727 (!((((u_int32_t)(src)\
43740 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__READ(src) \
43741 (((u_int32_t)(src)\
43743 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__WRITE(src) \
43744 (((u_int32_t)(src)\
43746 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__MODIFY(dst, src) \
43748 ~0x00000004U) | (((u_int32_t)(src) <<\
43750 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE2__VERIFY(src) \
43751 (!((((u_int32_t)(src)\
43764 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__READ(src) \
43765 (((u_int32_t)(src)\
43767 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__WRITE(src) \
43768 (((u_int32_t)(src)\
43770 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__MODIFY(dst, src) \
43772 ~0x00000008U) | (((u_int32_t)(src) <<\
43774 #define FORCE_CLKEN_CCK__FORCE_RX_ENABLE3__VERIFY(src) \
43775 (!((((u_int32_t)(src)\
43788 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__READ(src) \
43789 (((u_int32_t)(src)\
43791 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__WRITE(src) \
43792 (((u_int32_t)(src)\
43794 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__MODIFY(dst, src) \
43796 ~0x00000010U) | (((u_int32_t)(src) <<\
43798 #define FORCE_CLKEN_CCK__FORCE_RX_ALWAYS__VERIFY(src) \
43799 (!((((u_int32_t)(src)\
43812 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__READ(src) \
43813 (((u_int32_t)(src)\
43815 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__WRITE(src) \
43816 (((u_int32_t)(src)\
43818 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__MODIFY(dst, src) \
43820 ~0x00000020U) | (((u_int32_t)(src) <<\
43822 #define FORCE_CLKEN_CCK__FORCE_TXSM_CLKEN__VERIFY(src) \
43823 (!((((u_int32_t)(src)\
43849 #define SETTLING_TIME__AGC_SETTLING__READ(src) (u_int32_t)(src) & 0x0000007fU
43850 #define SETTLING_TIME__AGC_SETTLING__WRITE(src) \
43851 ((u_int32_t)(src)\
43853 #define SETTLING_TIME__AGC_SETTLING__MODIFY(dst, src) \
43855 ~0x0000007fU) | ((u_int32_t)(src) &\
43857 #define SETTLING_TIME__AGC_SETTLING__VERIFY(src) \
43858 (!(((u_int32_t)(src)\
43865 #define SETTLING_TIME__SWITCH_SETTLING__READ(src) \
43866 (((u_int32_t)(src)\
43868 #define SETTLING_TIME__SWITCH_SETTLING__WRITE(src) \
43869 (((u_int32_t)(src)\
43871 #define SETTLING_TIME__SWITCH_SETTLING__MODIFY(dst, src) \
43873 ~0x00003f80U) | (((u_int32_t)(src) <<\
43875 #define SETTLING_TIME__SWITCH_SETTLING__VERIFY(src) \
43876 (!((((u_int32_t)(src)\
43883 #define SETTLING_TIME__ADCSAT_THRL__READ(src) \
43884 (((u_int32_t)(src)\
43886 #define SETTLING_TIME__ADCSAT_THRL__WRITE(src) \
43887 (((u_int32_t)(src)\
43889 #define SETTLING_TIME__ADCSAT_THRL__MODIFY(dst, src) \
43891 ~0x000fc000U) | (((u_int32_t)(src) <<\
43893 #define SETTLING_TIME__ADCSAT_THRL__VERIFY(src) \
43894 (!((((u_int32_t)(src)\
43901 #define SETTLING_TIME__ADCSAT_THRH__READ(src) \
43902 (((u_int32_t)(src)\
43904 #define SETTLING_TIME__ADCSAT_THRH__WRITE(src) \
43905 (((u_int32_t)(src)\
43907 #define SETTLING_TIME__ADCSAT_THRH__MODIFY(dst, src) \
43909 ~0x03f00000U) | (((u_int32_t)(src) <<\
43911 #define SETTLING_TIME__ADCSAT_THRH__VERIFY(src) \
43912 (!((((u_int32_t)(src)\
43919 #define SETTLING_TIME__LBRESET_ADVANCE__READ(src) \
43920 (((u_int32_t)(src)\
43922 #define SETTLING_TIME__LBRESET_ADVANCE__WRITE(src) \
43923 (((u_int32_t)(src)\
43925 #define SETTLING_TIME__LBRESET_ADVANCE__MODIFY(dst, src) \
43927 ~0x3c000000U) | (((u_int32_t)(src) <<\
43929 #define SETTLING_TIME__LBRESET_ADVANCE__VERIFY(src) \
43930 (!((((u_int32_t)(src)\
43950 #define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__READ(src) \
43951 (u_int32_t)(src)\
43953 #define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__WRITE(src) \
43954 ((u_int32_t)(src)\
43956 #define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__MODIFY(dst, src) \
43958 ~0x000000ffU) | ((u_int32_t)(src) &\
43960 #define GAIN_FORCE_MAX_GAINS_B0__RF_GAIN_F_0__VERIFY(src) \
43961 (!(((u_int32_t)(src)\
43968 #define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__READ(src) \
43969 (((u_int32_t)(src)\
43971 #define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__WRITE(src) \
43972 (((u_int32_t)(src)\
43974 #define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__MODIFY(dst, src) \
43976 ~0x0000ff00U) | (((u_int32_t)(src) <<\
43978 #define GAIN_FORCE_MAX_GAINS_B0__MB_GAIN_F_0__VERIFY(src) \
43979 (!((((u_int32_t)(src)\
43986 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__READ(src) \
43987 (((u_int32_t)(src)\
43989 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__WRITE(src) \
43990 (((u_int32_t)(src)\
43992 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__MODIFY(dst, src) \
43994 ~0x00010000U) | (((u_int32_t)(src) <<\
43996 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_SW_F_0__VERIFY(src) \
43997 (!((((u_int32_t)(src)\
44010 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__READ(src) \
44011 (((u_int32_t)(src)\
44013 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__WRITE(src) \
44014 (((u_int32_t)(src)\
44016 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__MODIFY(dst, src) \
44018 ~0x00020000U) | (((u_int32_t)(src) <<\
44020 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_SW_F_0__VERIFY(src) \
44021 (!((((u_int32_t)(src)\
44034 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__READ(src) \
44035 (((u_int32_t)(src)\
44037 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__WRITE(src) \
44038 (((u_int32_t)(src)\
44040 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__MODIFY(dst, src) \
44042 ~0x01fc0000U) | (((u_int32_t)(src) <<\
44044 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN1_HYST_MARGIN_0__VERIFY(src) \
44045 (!((((u_int32_t)(src)\
44052 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__READ(src) \
44053 (((u_int32_t)(src)\
44055 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__WRITE(src) \
44056 (((u_int32_t)(src)\
44058 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__MODIFY(dst, src) \
44060 ~0xfe000000U) | (((u_int32_t)(src) <<\
44062 #define GAIN_FORCE_MAX_GAINS_B0__XATTEN2_HYST_MARGIN_0__VERIFY(src) \
44063 (!((((u_int32_t)(src)\
44083 #define GAINS_MIN_OFFSETS__OFFSETC1__READ(src) (u_int32_t)(src) & 0x0000007fU
44084 #define GAINS_MIN_OFFSETS__OFFSETC1__WRITE(src) \
44085 ((u_int32_t)(src)\
44087 #define GAINS_MIN_OFFSETS__OFFSETC1__MODIFY(dst, src) \
44089 ~0x0000007fU) | ((u_int32_t)(src) &\
44091 #define GAINS_MIN_OFFSETS__OFFSETC1__VERIFY(src) \
44092 (!(((u_int32_t)(src)\
44099 #define GAINS_MIN_OFFSETS__OFFSETC2__READ(src) \
44100 (((u_int32_t)(src)\
44102 #define GAINS_MIN_OFFSETS__OFFSETC2__WRITE(src) \
44103 (((u_int32_t)(src)\
44105 #define GAINS_MIN_OFFSETS__OFFSETC2__MODIFY(dst, src) \
44107 ~0x00000f80U) | (((u_int32_t)(src) <<\
44109 #define GAINS_MIN_OFFSETS__OFFSETC2__VERIFY(src) \
44110 (!((((u_int32_t)(src)\
44117 #define GAINS_MIN_OFFSETS__OFFSETC3__READ(src) \
44118 (((u_int32_t)(src)\
44120 #define GAINS_MIN_OFFSETS__OFFSETC3__WRITE(src) \
44121 (((u_int32_t)(src)\
44123 #define GAINS_MIN_OFFSETS__OFFSETC3__MODIFY(dst, src) \
44125 ~0x0001f000U) | (((u_int32_t)(src) <<\
44127 #define GAINS_MIN_OFFSETS__OFFSETC3__VERIFY(src) \
44128 (!((((u_int32_t)(src)\
44135 #define GAINS_MIN_OFFSETS__GAIN_FORCE__READ(src) \
44136 (((u_int32_t)(src)\
44138 #define GAINS_MIN_OFFSETS__GAIN_FORCE__WRITE(src) \
44139 (((u_int32_t)(src)\
44141 #define GAINS_MIN_OFFSETS__GAIN_FORCE__MODIFY(dst, src) \
44143 ~0x00020000U) | (((u_int32_t)(src) <<\
44145 #define GAINS_MIN_OFFSETS__GAIN_FORCE__VERIFY(src) \
44146 (!((((u_int32_t)(src)\
44159 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__READ(src) \
44160 (((u_int32_t)(src)\
44162 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__WRITE(src) \
44163 (((u_int32_t)(src)\
44165 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__MODIFY(dst, src) \
44167 ~0x00040000U) | (((u_int32_t)(src) <<\
44169 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_ENABLE__VERIFY(src) \
44170 (!((((u_int32_t)(src)\
44183 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__READ(src) \
44184 (((u_int32_t)(src)\
44186 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__WRITE(src) \
44187 (((u_int32_t)(src)\
44189 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__MODIFY(dst, src) \
44191 ~0x00080000U) | (((u_int32_t)(src) <<\
44193 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_GC__VERIFY(src) \
44194 (!((((u_int32_t)(src)\
44207 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__READ(src) \
44208 (((u_int32_t)(src)\
44210 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__WRITE(src) \
44211 (((u_int32_t)(src)\
44213 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__MODIFY(dst, src) \
44215 ~0x00100000U) | (((u_int32_t)(src) <<\
44217 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_VOTING__VERIFY(src) \
44218 (!((((u_int32_t)(src)\
44231 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__READ(src) \
44232 (((u_int32_t)(src)\
44234 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__WRITE(src) \
44235 (((u_int32_t)(src)\
44237 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__MODIFY(dst, src) \
44239 ~0x00200000U) | (((u_int32_t)(src) <<\
44241 #define GAINS_MIN_OFFSETS__CF_AGC_HIST_PHY_ERR__VERIFY(src) \
44242 (!((((u_int32_t)(src)\
44268 #define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__READ(src) \
44269 (u_int32_t)(src)\
44271 #define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__WRITE(src) \
44272 ((u_int32_t)(src)\
44274 #define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__MODIFY(dst, src) \
44276 ~0x000000ffU) | ((u_int32_t)(src) &\
44278 #define DESIRED_SIGSIZE__ADC_DESIRED_SIZE__VERIFY(src) \
44279 (!(((u_int32_t)(src)\
44286 #define DESIRED_SIGSIZE__TOTAL_DESIRED__READ(src) \
44287 (((u_int32_t)(src)\
44289 #define DESIRED_SIGSIZE__TOTAL_DESIRED__WRITE(src) \
44290 (((u_int32_t)(src)\
44292 #define DESIRED_SIGSIZE__TOTAL_DESIRED__MODIFY(dst, src) \
44294 ~0x0ff00000U) | (((u_int32_t)(src) <<\
44296 #define DESIRED_SIGSIZE__TOTAL_DESIRED__VERIFY(src) \
44297 (!((((u_int32_t)(src)\
44304 #define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__READ(src) \
44305 (((u_int32_t)(src)\
44307 #define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__WRITE(src) \
44308 (((u_int32_t)(src)\
44310 #define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__MODIFY(dst, src) \
44312 ~0x30000000U) | (((u_int32_t)(src) <<\
44314 #define DESIRED_SIGSIZE__INIT_GC_COUNT_MAX__VERIFY(src) \
44315 (!((((u_int32_t)(src)\
44322 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__READ(src) \
44323 (((u_int32_t)(src)\
44325 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__WRITE(src) \
44326 (((u_int32_t)(src)\
44328 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__MODIFY(dst, src) \
44330 ~0x40000000U) | (((u_int32_t)(src) <<\
44332 #define DESIRED_SIGSIZE__REDUCE_INIT_GC_COUNT__VERIFY(src) \
44333 (!((((u_int32_t)(src)\
44346 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__READ(src) \
44347 (((u_int32_t)(src)\
44349 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__WRITE(src) \
44350 (((u_int32_t)(src)\
44352 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__MODIFY(dst, src) \
44354 ~0x80000000U) | (((u_int32_t)(src) <<\
44356 #define DESIRED_SIGSIZE__ENA_INIT_GAIN__VERIFY(src) \
44357 (!((((u_int32_t)(src)\
44383 #define FIND_SIGNAL__RELSTEP__READ(src) (u_int32_t)(src) & 0x0000003fU
44384 #define FIND_SIGNAL__RELSTEP__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
44385 #define FIND_SIGNAL__RELSTEP__MODIFY(dst, src) \
44387 ~0x0000003fU) | ((u_int32_t)(src) &\
44389 #define FIND_SIGNAL__RELSTEP__VERIFY(src) \
44390 (!(((u_int32_t)(src)\
44397 #define FIND_SIGNAL__RELPWR__READ(src) (((u_int32_t)(src) & 0x00000fc0U) >> 6)
44398 #define FIND_SIGNAL__RELPWR__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000fc0U)
44399 #define FIND_SIGNAL__RELPWR__MODIFY(dst, src) \
44401 ~0x00000fc0U) | (((u_int32_t)(src) <<\
44403 #define FIND_SIGNAL__RELPWR__VERIFY(src) \
44404 (!((((u_int32_t)(src)\
44411 #define FIND_SIGNAL__FIRSTEP__READ(src) \
44412 (((u_int32_t)(src)\
44414 #define FIND_SIGNAL__FIRSTEP__WRITE(src) \
44415 (((u_int32_t)(src)\
44417 #define FIND_SIGNAL__FIRSTEP__MODIFY(dst, src) \
44419 ~0x0003f000U) | (((u_int32_t)(src) <<\
44421 #define FIND_SIGNAL__FIRSTEP__VERIFY(src) \
44422 (!((((u_int32_t)(src)\
44429 #define FIND_SIGNAL__FIRPWR__READ(src) (((u_int32_t)(src) & 0x03fc0000U) >> 18)
44430 #define FIND_SIGNAL__FIRPWR__WRITE(src) \
44431 (((u_int32_t)(src)\
44433 #define FIND_SIGNAL__FIRPWR__MODIFY(dst, src) \
44435 ~0x03fc0000U) | (((u_int32_t)(src) <<\
44437 #define FIND_SIGNAL__FIRPWR__VERIFY(src) \
44438 (!((((u_int32_t)(src)\
44445 #define FIND_SIGNAL__M1COUNT_MAX__READ(src) \
44446 (((u_int32_t)(src)\
44448 #define FIND_SIGNAL__M1COUNT_MAX__WRITE(src) \
44449 (((u_int32_t)(src)\
44451 #define FIND_SIGNAL__M1COUNT_MAX__MODIFY(dst, src) \
44453 ~0xfc000000U) | (((u_int32_t)(src) <<\
44455 #define FIND_SIGNAL__M1COUNT_MAX__VERIFY(src) \
44456 (!((((u_int32_t)(src)\
44476 #define AGC__COARSEPWR_CONST__READ(src) (u_int32_t)(src) & 0x0000007fU
44477 #define AGC__COARSEPWR_CONST__WRITE(src) ((u_int32_t)(src) & 0x0000007fU)
44478 #define AGC__COARSEPWR_CONST__MODIFY(dst, src) \
44480 ~0x0000007fU) | ((u_int32_t)(src) &\
44482 #define AGC__COARSEPWR_CONST__VERIFY(src) \
44483 (!(((u_int32_t)(src)\
44490 #define AGC__COARSE_LOW__READ(src) (((u_int32_t)(src) & 0x00007f80U) >> 7)
44491 #define AGC__COARSE_LOW__WRITE(src) (((u_int32_t)(src) << 7) & 0x00007f80U)
44492 #define AGC__COARSE_LOW__MODIFY(dst, src) \
44494 ~0x00007f80U) | (((u_int32_t)(src) <<\
44496 #define AGC__COARSE_LOW__VERIFY(src) \
44497 (!((((u_int32_t)(src)\
44504 #define AGC__COARSE_HIGH__READ(src) (((u_int32_t)(src) & 0x003f8000U) >> 15)
44505 #define AGC__COARSE_HIGH__WRITE(src) (((u_int32_t)(src) << 15) & 0x003f8000U)
44506 #define AGC__COARSE_HIGH__MODIFY(dst, src) \
44508 ~0x003f8000U) | (((u_int32_t)(src) <<\
44510 #define AGC__COARSE_HIGH__VERIFY(src) \
44511 (!((((u_int32_t)(src)\
44518 #define AGC__QUICK_DROP__READ(src) (((u_int32_t)(src) & 0x3fc00000U) >> 22)
44519 #define AGC__QUICK_DROP__WRITE(src) (((u_int32_t)(src) << 22) & 0x3fc00000U)
44520 #define AGC__QUICK_DROP__MODIFY(dst, src) \
44522 ~0x3fc00000U) | (((u_int32_t)(src) <<\
44524 #define AGC__QUICK_DROP__VERIFY(src) \
44525 (!((((u_int32_t)(src)\
44532 #define AGC__RSSI_OUT_SELECT__READ(src) \
44533 (((u_int32_t)(src)\
44535 #define AGC__RSSI_OUT_SELECT__WRITE(src) \
44536 (((u_int32_t)(src)\
44538 #define AGC__RSSI_OUT_SELECT__MODIFY(dst, src) \
44540 ~0xc0000000U) | (((u_int32_t)(src) <<\
44542 #define AGC__RSSI_OUT_SELECT__VERIFY(src) \
44543 (!((((u_int32_t)(src)\
44563 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__READ(src) \
44564 (u_int32_t)(src)\
44566 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__WRITE(src) \
44567 ((u_int32_t)(src)\
44569 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__MODIFY(dst, src) \
44571 ~0x0000003fU) | ((u_int32_t)(src) &\
44573 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_DB_0__VERIFY(src) \
44574 (!(((u_int32_t)(src)\
44581 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__READ(src) \
44582 (((u_int32_t)(src)\
44584 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__WRITE(src) \
44585 (((u_int32_t)(src)\
44587 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__MODIFY(dst, src) \
44589 ~0x00000fc0U) | (((u_int32_t)(src) <<\
44591 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_DB_0__VERIFY(src) \
44592 (!((((u_int32_t)(src)\
44599 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__READ(src) \
44600 (((u_int32_t)(src)\
44602 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__WRITE(src) \
44603 (((u_int32_t)(src)\
44605 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__MODIFY(dst, src) \
44607 ~0x0001f000U) | (((u_int32_t)(src) <<\
44609 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN1_MARGIN_0__VERIFY(src) \
44610 (!((((u_int32_t)(src)\
44617 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__READ(src) \
44618 (((u_int32_t)(src)\
44620 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__WRITE(src) \
44621 (((u_int32_t)(src)\
44623 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__MODIFY(dst, src) \
44625 ~0x003e0000U) | (((u_int32_t)(src) <<\
44627 #define EXT_ATTEN_SWITCH_CTL_B0__XATTEN2_MARGIN_0__VERIFY(src) \
44628 (!((((u_int32_t)(src)\
44635 #define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__READ(src) \
44636 (((u_int32_t)(src)\
44638 #define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__WRITE(src) \
44639 (((u_int32_t)(src)\
44641 #define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__MODIFY(dst, src) \
44643 ~0x07c00000U) | (((u_int32_t)(src) <<\
44645 #define EXT_ATTEN_SWITCH_CTL_B0__XLNA_GAIN_DB_0__VERIFY(src) \
44646 (!((((u_int32_t)(src)\
44666 #define CCA_B0__CF_MAXCCAPWR_0__READ(src) (u_int32_t)(src) & 0x000001ffU
44667 #define CCA_B0__CF_MAXCCAPWR_0__WRITE(src) ((u_int32_t)(src) & 0x000001ffU)
44668 #define CCA_B0__CF_MAXCCAPWR_0__MODIFY(dst, src) \
44670 ~0x000001ffU) | ((u_int32_t)(src) &\
44672 #define CCA_B0__CF_MAXCCAPWR_0__VERIFY(src) \
44673 (!(((u_int32_t)(src)\
44680 #define CCA_B0__CF_CCA_COUNT_MAXC__READ(src) \
44681 (((u_int32_t)(src)\
44683 #define CCA_B0__CF_CCA_COUNT_MAXC__WRITE(src) \
44684 (((u_int32_t)(src)\
44686 #define CCA_B0__CF_CCA_COUNT_MAXC__MODIFY(dst, src) \
44688 ~0x00000e00U) | (((u_int32_t)(src) <<\
44690 #define CCA_B0__CF_CCA_COUNT_MAXC__VERIFY(src) \
44691 (!((((u_int32_t)(src)\
44698 #define CCA_B0__CF_THRESH62__READ(src) (((u_int32_t)(src) & 0x000ff000U) >> 12)
44699 #define CCA_B0__CF_THRESH62__WRITE(src) \
44700 (((u_int32_t)(src)\
44702 #define CCA_B0__CF_THRESH62__MODIFY(dst, src) \
44704 ~0x000ff000U) | (((u_int32_t)(src) <<\
44706 #define CCA_B0__CF_THRESH62__VERIFY(src) \
44707 (!((((u_int32_t)(src)\
44714 #define CCA_B0__MINCCAPWR_0__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20)
44733 #define CCA_CTRL_2_B0__MINCCAPWR_THR_0__READ(src) \
44734 (u_int32_t)(src)\
44736 #define CCA_CTRL_2_B0__MINCCAPWR_THR_0__WRITE(src) \
44737 ((u_int32_t)(src)\
44739 #define CCA_CTRL_2_B0__MINCCAPWR_THR_0__MODIFY(dst, src) \
44741 ~0x000001ffU) | ((u_int32_t)(src) &\
44743 #define CCA_CTRL_2_B0__MINCCAPWR_THR_0__VERIFY(src) \
44744 (!(((u_int32_t)(src)\
44751 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__READ(src) \
44752 (((u_int32_t)(src)\
44754 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__WRITE(src) \
44755 (((u_int32_t)(src)\
44757 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__MODIFY(dst, src) \
44759 ~0x00000200U) | (((u_int32_t)(src) <<\
44761 #define CCA_CTRL_2_B0__ENABLE_MINCCAPWR_THR__VERIFY(src) \
44762 (!((((u_int32_t)(src)\
44775 #define CCA_CTRL_2_B0__NF_GAIN_COMP_0__READ(src) \
44776 (((u_int32_t)(src)\
44778 #define CCA_CTRL_2_B0__NF_GAIN_COMP_0__WRITE(src) \
44779 (((u_int32_t)(src)\
44781 #define CCA_CTRL_2_B0__NF_GAIN_COMP_0__MODIFY(dst, src) \
44783 ~0x0003fc00U) | (((u_int32_t)(src) <<\
44785 #define CCA_CTRL_2_B0__NF_GAIN_COMP_0__VERIFY(src) \
44786 (!((((u_int32_t)(src)\
44793 #define CCA_CTRL_2_B0__THRESH62_MODE__READ(src) \
44794 (((u_int32_t)(src)\
44796 #define CCA_CTRL_2_B0__THRESH62_MODE__WRITE(src) \
44797 (((u_int32_t)(src)\
44799 #define CCA_CTRL_2_B0__THRESH62_MODE__MODIFY(dst, src) \
44801 ~0x00040000U) | (((u_int32_t)(src) <<\
44803 #define CCA_CTRL_2_B0__THRESH62_MODE__VERIFY(src) \
44804 (!((((u_int32_t)(src)\
44830 #define RESTART__ENABLE_RESTART__READ(src) (u_int32_t)(src) & 0x00000001U
44831 #define RESTART__ENABLE_RESTART__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
44832 #define RESTART__ENABLE_RESTART__MODIFY(dst, src) \
44834 ~0x00000001U) | ((u_int32_t)(src) &\
44836 #define RESTART__ENABLE_RESTART__VERIFY(src) \
44837 (!(((u_int32_t)(src)\
44850 #define RESTART__RESTART_LGFIRPWR_DELTA__READ(src) \
44851 (((u_int32_t)(src)\
44853 #define RESTART__RESTART_LGFIRPWR_DELTA__WRITE(src) \
44854 (((u_int32_t)(src)\
44856 #define RESTART__RESTART_LGFIRPWR_DELTA__MODIFY(dst, src) \
44858 ~0x0000003eU) | (((u_int32_t)(src) <<\
44860 #define RESTART__RESTART_LGFIRPWR_DELTA__VERIFY(src) \
44861 (!((((u_int32_t)(src)\
44868 #define RESTART__ENABLE_PWR_DROP_ERR__READ(src) \
44869 (((u_int32_t)(src)\
44871 #define RESTART__ENABLE_PWR_DROP_ERR__WRITE(src) \
44872 (((u_int32_t)(src)\
44874 #define RESTART__ENABLE_PWR_DROP_ERR__MODIFY(dst, src) \
44876 ~0x00000040U) | (((u_int32_t)(src) <<\
44878 #define RESTART__ENABLE_PWR_DROP_ERR__VERIFY(src) \
44879 (!((((u_int32_t)(src)\
44892 #define RESTART__PWRDROP_LGFIRPWR_DELTA__READ(src) \
44893 (((u_int32_t)(src)\
44895 #define RESTART__PWRDROP_LGFIRPWR_DELTA__WRITE(src) \
44896 (((u_int32_t)(src)\
44898 #define RESTART__PWRDROP_LGFIRPWR_DELTA__MODIFY(dst, src) \
44900 ~0x00000f80U) | (((u_int32_t)(src) <<\
44902 #define RESTART__PWRDROP_LGFIRPWR_DELTA__VERIFY(src) \
44903 (!((((u_int32_t)(src)\
44910 #define RESTART__OFDM_CCK_RSSI_BIAS__READ(src) \
44911 (((u_int32_t)(src)\
44913 #define RESTART__OFDM_CCK_RSSI_BIAS__WRITE(src) \
44914 (((u_int32_t)(src)\
44916 #define RESTART__OFDM_CCK_RSSI_BIAS__MODIFY(dst, src) \
44918 ~0x0003f000U) | (((u_int32_t)(src) <<\
44920 #define RESTART__OFDM_CCK_RSSI_BIAS__VERIFY(src) \
44921 (!((((u_int32_t)(src)\
44928 #define RESTART__ANT_FAST_DIV_GC_LIMIT__READ(src) \
44929 (((u_int32_t)(src)\
44931 #define RESTART__ANT_FAST_DIV_GC_LIMIT__WRITE(src) \
44932 (((u_int32_t)(src)\
44934 #define RESTART__ANT_FAST_DIV_GC_LIMIT__MODIFY(dst, src) \
44936 ~0x001c0000U) | (((u_int32_t)(src) <<\
44938 #define RESTART__ANT_FAST_DIV_GC_LIMIT__VERIFY(src) \
44939 (!((((u_int32_t)(src)\
44946 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__READ(src) \
44947 (((u_int32_t)(src)\
44949 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__WRITE(src) \
44950 (((u_int32_t)(src)\
44952 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MODIFY(dst, src) \
44954 ~0x00200000U) | (((u_int32_t)(src) <<\
44956 #define RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__VERIFY(src) \
44957 (!((((u_int32_t)(src)\
44970 #define RESTART__WEAK_RSSI_VOTE_THR__READ(src) \
44971 (((u_int32_t)(src)\
44973 #define RESTART__WEAK_RSSI_VOTE_THR__WRITE(src) \
44974 (((u_int32_t)(src)\
44976 #define RESTART__WEAK_RSSI_VOTE_THR__MODIFY(dst, src) \
44978 ~0x1fc00000U) | (((u_int32_t)(src) <<\
44980 #define RESTART__WEAK_RSSI_VOTE_THR__VERIFY(src) \
44981 (!((((u_int32_t)(src)\
44988 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__READ(src) \
44989 (((u_int32_t)(src)\
44991 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__WRITE(src) \
44992 (((u_int32_t)(src)\
44994 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__MODIFY(dst, src) \
44996 ~0x20000000U) | (((u_int32_t)(src) <<\
44998 #define RESTART__ENABLE_PWR_DROP_ERR_CCK__VERIFY(src) \
44999 (!((((u_int32_t)(src)\
45012 #define RESTART__DISABLE_DC_RESTART__READ(src) \
45013 (((u_int32_t)(src)\
45015 #define RESTART__DISABLE_DC_RESTART__WRITE(src) \
45016 (((u_int32_t)(src)\
45018 #define RESTART__DISABLE_DC_RESTART__MODIFY(dst, src) \
45020 ~0x40000000U) | (((u_int32_t)(src) <<\
45022 #define RESTART__DISABLE_DC_RESTART__VERIFY(src) \
45023 (!((((u_int32_t)(src)\
45036 #define RESTART__RESTART_MODE_BW40__READ(src) \
45037 (((u_int32_t)(src)\
45039 #define RESTART__RESTART_MODE_BW40__WRITE(src) \
45040 (((u_int32_t)(src)\
45042 #define RESTART__RESTART_MODE_BW40__MODIFY(dst, src) \
45044 ~0x80000000U) | (((u_int32_t)(src) <<\
45046 #define RESTART__RESTART_MODE_BW40__VERIFY(src) \
45047 (!((((u_int32_t)(src)\
45073 #define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__READ(src) \
45074 (u_int32_t)(src)\
45076 #define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__WRITE(src) \
45077 ((u_int32_t)(src)\
45079 #define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__MODIFY(dst, src) \
45081 ~0x000000ffU) | ((u_int32_t)(src) &\
45083 #define MULTICHAIN_GAIN_CTRL__QUICKDROP_LOW__VERIFY(src) \
45084 (!(((u_int32_t)(src)\
45091 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__READ(src) \
45092 (((u_int32_t)(src)\
45094 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__WRITE(src) \
45095 (((u_int32_t)(src)\
45097 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__MODIFY(dst, src) \
45099 ~0x00000100U) | (((u_int32_t)(src) <<\
45101 #define MULTICHAIN_GAIN_CTRL__ENABLE_CHECK_STRONG_ANT__VERIFY(src) \
45102 (!((((u_int32_t)(src)\
45115 #define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__READ(src) \
45116 (((u_int32_t)(src)\
45118 #define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__WRITE(src) \
45119 (((u_int32_t)(src)\
45121 #define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__MODIFY(dst, src) \
45123 ~0x00007e00U) | (((u_int32_t)(src) <<\
45125 #define MULTICHAIN_GAIN_CTRL__ANT_FAST_DIV_BIAS__VERIFY(src) \
45126 (!((((u_int32_t)(src)\
45133 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__READ(src) \
45134 (((u_int32_t)(src)\
45136 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__WRITE(src) \
45137 (((u_int32_t)(src)\
45139 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__MODIFY(dst, src) \
45141 ~0x001f8000U) | (((u_int32_t)(src) <<\
45143 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_SNR__VERIFY(src) \
45144 (!((((u_int32_t)(src)\
45151 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__READ(src) \
45152 (((u_int32_t)(src)\
45154 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__WRITE(src) \
45155 (((u_int32_t)(src)\
45157 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__MODIFY(dst, src) \
45159 ~0x00200000U) | (((u_int32_t)(src) <<\
45161 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_ENA__VERIFY(src) \
45162 (!((((u_int32_t)(src)\
45175 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__READ(src) \
45176 (((u_int32_t)(src)\
45178 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__WRITE(src) \
45179 (((u_int32_t)(src)\
45181 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__MODIFY(dst, src) \
45183 ~0x00400000U) | (((u_int32_t)(src) <<\
45185 #define MULTICHAIN_GAIN_CTRL__CAP_GAIN_RATIO_MODE__VERIFY(src) \
45186 (!((((u_int32_t)(src)\
45199 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__READ(src) \
45200 (((u_int32_t)(src)\
45202 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__WRITE(src) \
45203 (((u_int32_t)(src)\
45205 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__MODIFY(dst, src) \
45207 ~0x00800000U) | (((u_int32_t)(src) <<\
45209 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__VERIFY(src) \
45210 (!((((u_int32_t)(src)\
45223 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__READ(src) \
45224 (((u_int32_t)(src)\
45226 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__WRITE(src) \
45227 (((u_int32_t)(src)\
45229 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__MODIFY(dst, src) \
45231 ~0x01000000U) | (((u_int32_t)(src) <<\
45233 #define MULTICHAIN_GAIN_CTRL__ENABLE_ANT_DIV_LNADIV__VERIFY(src) \
45234 (!((((u_int32_t)(src)\
45247 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__READ(src) \
45248 (((u_int32_t)(src)\
45250 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__WRITE(src) \
45251 (((u_int32_t)(src)\
45253 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__MODIFY(dst, src) \
45255 ~0x06000000U) | (((u_int32_t)(src) <<\
45257 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_LNACONF__VERIFY(src) \
45258 (!((((u_int32_t)(src)\
45265 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__READ(src) \
45266 (((u_int32_t)(src)\
45268 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__WRITE(src) \
45269 (((u_int32_t)(src)\
45271 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__MODIFY(dst, src) \
45273 ~0x18000000U) | (((u_int32_t)(src) <<\
45275 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_LNACONF__VERIFY(src) \
45276 (!((((u_int32_t)(src)\
45283 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__READ(src) \
45284 (((u_int32_t)(src)\
45286 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__WRITE(src) \
45287 (((u_int32_t)(src)\
45289 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__MODIFY(dst, src) \
45291 ~0x20000000U) | (((u_int32_t)(src) <<\
45293 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_ALT_GAINTB__VERIFY(src) \
45294 (!((((u_int32_t)(src)\
45307 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__READ(src) \
45308 (((u_int32_t)(src)\
45310 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__WRITE(src) \
45311 (((u_int32_t)(src)\
45313 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__MODIFY(dst, src) \
45315 ~0x40000000U) | (((u_int32_t)(src) <<\
45317 #define MULTICHAIN_GAIN_CTRL__ANT_DIV_MAIN_GAINTB__VERIFY(src) \
45318 (!((((u_int32_t)(src)\
45344 #define EXT_CHAN_PWR_THR_1__THRESH62_EXT__READ(src) \
45345 (u_int32_t)(src)\
45347 #define EXT_CHAN_PWR_THR_1__THRESH62_EXT__WRITE(src) \
45348 ((u_int32_t)(src)\
45350 #define EXT_CHAN_PWR_THR_1__THRESH62_EXT__MODIFY(dst, src) \
45352 ~0x000000ffU) | ((u_int32_t)(src) &\
45354 #define EXT_CHAN_PWR_THR_1__THRESH62_EXT__VERIFY(src) \
45355 (!(((u_int32_t)(src)\
45362 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__READ(src) \
45363 (((u_int32_t)(src)\
45365 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__WRITE(src) \
45366 (((u_int32_t)(src)\
45368 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__MODIFY(dst, src) \
45370 ~0x0000ff00U) | (((u_int32_t)(src) <<\
45372 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_MINGAINIDX__VERIFY(src) \
45373 (!((((u_int32_t)(src)\
45380 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__READ(src) \
45381 (((u_int32_t)(src)\
45383 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__WRITE(src) \
45384 (((u_int32_t)(src)\
45386 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__MODIFY(dst, src) \
45388 ~0x001f0000U) | (((u_int32_t)(src) <<\
45390 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTAGAINIDX__VERIFY(src) \
45391 (!((((u_int32_t)(src)\
45398 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__READ(src) \
45399 (((u_int32_t)(src)\
45401 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__WRITE(src) \
45402 (((u_int32_t)(src)\
45404 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__MODIFY(dst, src) \
45406 ~0x07e00000U) | (((u_int32_t)(src) <<\
45408 #define EXT_CHAN_PWR_THR_1__ANT_DIV_ALT_ANT_DELTANF__VERIFY(src) \
45409 (!((((u_int32_t)(src)\
45429 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__READ(src) \
45430 (u_int32_t)(src)\
45432 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__WRITE(src) \
45433 ((u_int32_t)(src)\
45435 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__MODIFY(dst, src) \
45437 ~0x0000000fU) | ((u_int32_t)(src) &\
45439 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK__VERIFY(src) \
45440 (!(((u_int32_t)(src)\
45447 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__READ(src) \
45448 (((u_int32_t)(src)\
45450 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__WRITE(src) \
45451 (((u_int32_t)(src)\
45453 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__MODIFY(dst, src) \
45455 ~0x000000f0U) | (((u_int32_t)(src) <<\
45457 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_LOW__VERIFY(src) \
45458 (!((((u_int32_t)(src)\
45465 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__READ(src) \
45466 (((u_int32_t)(src)\
45468 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__WRITE(src) \
45469 (((u_int32_t)(src)\
45471 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__MODIFY(dst, src) \
45473 ~0x00001f00U) | (((u_int32_t)(src) <<\
45475 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_WEAK_CCK__VERIFY(src) \
45476 (!((((u_int32_t)(src)\
45483 #define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__READ(src) \
45484 (((u_int32_t)(src)\
45486 #define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__WRITE(src) \
45487 (((u_int32_t)(src)\
45489 #define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__MODIFY(dst, src) \
45491 ~0x0000e000U) | (((u_int32_t)(src) <<\
45493 #define EXT_CHAN_DETECT_WIN__DET_20H_COUNT__VERIFY(src) \
45494 (!((((u_int32_t)(src)\
45501 #define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__READ(src) \
45502 (((u_int32_t)(src)\
45504 #define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__WRITE(src) \
45505 (((u_int32_t)(src)\
45507 #define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__MODIFY(dst, src) \
45509 ~0x00070000U) | (((u_int32_t)(src) <<\
45511 #define EXT_CHAN_DETECT_WIN__DET_EXT_BLK_COUNT__VERIFY(src) \
45512 (!((((u_int32_t)(src)\
45519 #define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__READ(src) \
45520 (((u_int32_t)(src)\
45522 #define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__WRITE(src) \
45523 (((u_int32_t)(src)\
45525 #define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__MODIFY(dst, src) \
45527 ~0x01f80000U) | (((u_int32_t)(src) <<\
45529 #define EXT_CHAN_DETECT_WIN__WEAK_SIG_THR_CCK_EXT__VERIFY(src) \
45530 (!((((u_int32_t)(src)\
45537 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__READ(src) \
45538 (((u_int32_t)(src)\
45540 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__WRITE(src) \
45541 (((u_int32_t)(src)\
45543 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__MODIFY(dst, src) \
45545 ~0x1e000000U) | (((u_int32_t)(src) <<\
45547 #define EXT_CHAN_DETECT_WIN__DET_DIFF_WIN_THRESH__VERIFY(src) \
45548 (!((((u_int32_t)(src)\
45568 #define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__READ(src) \
45569 (u_int32_t)(src)\
45571 #define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__WRITE(src) \
45572 ((u_int32_t)(src)\
45574 #define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__MODIFY(dst, src) \
45576 ~0x0000001fU) | ((u_int32_t)(src) &\
45578 #define PWR_THR_20_40_DET__PWRDIFF40_THRSTR__VERIFY(src) \
45579 (!(((u_int32_t)(src)\
45586 #define PWR_THR_20_40_DET__BLOCKER40_MAX__READ(src) \
45587 (((u_int32_t)(src)\
45589 #define PWR_THR_20_40_DET__BLOCKER40_MAX__WRITE(src) \
45590 (((u_int32_t)(src)\
45592 #define PWR_THR_20_40_DET__BLOCKER40_MAX__MODIFY(dst, src) \
45594 ~0x000007e0U) | (((u_int32_t)(src) <<\
45596 #define PWR_THR_20_40_DET__BLOCKER40_MAX__VERIFY(src) \
45597 (!((((u_int32_t)(src)\
45604 #define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__READ(src) \
45605 (((u_int32_t)(src)\
45607 #define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__WRITE(src) \
45608 (((u_int32_t)(src)\
45610 #define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__MODIFY(dst, src) \
45612 ~0x0000f800U) | (((u_int32_t)(src) <<\
45614 #define PWR_THR_20_40_DET__DET40_PWRSTEP_MAX__VERIFY(src) \
45615 (!((((u_int32_t)(src)\
45622 #define PWR_THR_20_40_DET__DET40_THR_SNR__READ(src) \
45623 (((u_int32_t)(src)\
45625 #define PWR_THR_20_40_DET__DET40_THR_SNR__WRITE(src) \
45626 (((u_int32_t)(src)\
45628 #define PWR_THR_20_40_DET__DET40_THR_SNR__MODIFY(dst, src) \
45630 ~0x00ff0000U) | (((u_int32_t)(src) <<\
45632 #define PWR_THR_20_40_DET__DET40_THR_SNR__VERIFY(src) \
45633 (!((((u_int32_t)(src)\
45640 #define PWR_THR_20_40_DET__DET40_PRI_BIAS__READ(src) \
45641 (((u_int32_t)(src)\
45643 #define PWR_THR_20_40_DET__DET40_PRI_BIAS__WRITE(src) \
45644 (((u_int32_t)(src)\
45646 #define PWR_THR_20_40_DET__DET40_PRI_BIAS__MODIFY(dst, src) \
45648 ~0x1f000000U) | (((u_int32_t)(src) <<\
45650 #define PWR_THR_20_40_DET__DET40_PRI_BIAS__VERIFY(src) \
45651 (!((((u_int32_t)(src)\
45658 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__READ(src) \
45659 (((u_int32_t)(src)\
45661 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__WRITE(src) \
45662 (((u_int32_t)(src)\
45664 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__MODIFY(dst, src) \
45666 ~0x20000000U) | (((u_int32_t)(src) <<\
45668 #define PWR_THR_20_40_DET__PWRSTEP40_ENA__VERIFY(src) \
45669 (!((((u_int32_t)(src)\
45682 #define PWR_THR_20_40_DET__LOWSNR40_ENA__READ(src) \
45683 (((u_int32_t)(src)\
45685 #define PWR_THR_20_40_DET__LOWSNR40_ENA__WRITE(src) \
45686 (((u_int32_t)(src)\
45688 #define PWR_THR_20_40_DET__LOWSNR40_ENA__MODIFY(dst, src) \
45690 ~0x40000000U) | (((u_int32_t)(src) <<\
45692 #define PWR_THR_20_40_DET__LOWSNR40_ENA__VERIFY(src) \
45693 (!((((u_int32_t)(src)\
45719 #define RIFS_SRCH__INIT_GAIN_DB_OFFSET__READ(src) \
45720 (((u_int32_t)(src)\
45722 #define RIFS_SRCH__INIT_GAIN_DB_OFFSET__WRITE(src) \
45723 (((u_int32_t)(src)\
45725 #define RIFS_SRCH__INIT_GAIN_DB_OFFSET__MODIFY(dst, src) \
45727 ~0x0000ff00U) | (((u_int32_t)(src) <<\
45729 #define RIFS_SRCH__INIT_GAIN_DB_OFFSET__VERIFY(src) \
45730 (!((((u_int32_t)(src)\
45737 #define RIFS_SRCH__RIFS_INIT_DELAY__READ(src) \
45738 (((u_int32_t)(src)\
45740 #define RIFS_SRCH__RIFS_INIT_DELAY__WRITE(src) \
45741 (((u_int32_t)(src)\
45743 #define RIFS_SRCH__RIFS_INIT_DELAY__MODIFY(dst, src) \
45745 ~0x03ff0000U) | (((u_int32_t)(src) <<\
45747 #define RIFS_SRCH__RIFS_INIT_DELAY__VERIFY(src) \
45748 (!((((u_int32_t)(src)\
45755 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__READ(src) \
45756 (((u_int32_t)(src)\
45758 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__WRITE(src) \
45759 (((u_int32_t)(src)\
45761 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__MODIFY(dst, src) \
45763 ~0x04000000U) | (((u_int32_t)(src) <<\
45765 #define RIFS_SRCH__RIFS_DISABLE_PWRLOW_GC__VERIFY(src) \
45766 (!((((u_int32_t)(src)\
45779 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__READ(src) \
45780 (((u_int32_t)(src)\
45782 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__WRITE(src) \
45783 (((u_int32_t)(src)\
45785 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__MODIFY(dst, src) \
45787 ~0x08000000U) | (((u_int32_t)(src) <<\
45789 #define RIFS_SRCH__RIFS_DISABLE_CCK_DET__VERIFY(src) \
45790 (!((((u_int32_t)(src)\
45816 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__READ(src) \
45817 (u_int32_t)(src)\
45819 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__WRITE(src) \
45820 ((u_int32_t)(src)\
45822 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__MODIFY(dst, src) \
45824 ~0x00000001U) | ((u_int32_t)(src) &\
45826 #define PEAK_DET_CTRL_1__USE_OC_GAIN_TABLE__VERIFY(src) \
45827 (!(((u_int32_t)(src)\
45840 #define PEAK_DET_CTRL_1__USE_PEAK_DET__READ(src) \
45841 (((u_int32_t)(src)\
45843 #define PEAK_DET_CTRL_1__USE_PEAK_DET__WRITE(src) \
45844 (((u_int32_t)(src)\
45846 #define PEAK_DET_CTRL_1__USE_PEAK_DET__MODIFY(dst, src) \
45848 ~0x00000002U) | (((u_int32_t)(src) <<\
45850 #define PEAK_DET_CTRL_1__USE_PEAK_DET__VERIFY(src) \
45851 (!((((u_int32_t)(src)\
45864 #define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__READ(src) \
45865 (((u_int32_t)(src)\
45867 #define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__WRITE(src) \
45868 (((u_int32_t)(src)\
45870 #define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__MODIFY(dst, src) \
45872 ~0x000000fcU) | (((u_int32_t)(src) <<\
45874 #define PEAK_DET_CTRL_1__PEAK_DET_WIN_LEN__VERIFY(src) \
45875 (!((((u_int32_t)(src)\
45882 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__READ(src) \
45883 (((u_int32_t)(src)\
45885 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__WRITE(src) \
45886 (((u_int32_t)(src)\
45888 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__MODIFY(dst, src) \
45890 ~0x00001f00U) | (((u_int32_t)(src) <<\
45892 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_LOW__VERIFY(src) \
45893 (!((((u_int32_t)(src)\
45900 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__READ(src) \
45901 (((u_int32_t)(src)\
45903 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__WRITE(src) \
45904 (((u_int32_t)(src)\
45906 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__MODIFY(dst, src) \
45908 ~0x0003e000U) | (((u_int32_t)(src) <<\
45910 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_MED__VERIFY(src) \
45911 (!((((u_int32_t)(src)\
45918 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__READ(src) \
45919 (((u_int32_t)(src)\
45921 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__WRITE(src) \
45922 (((u_int32_t)(src)\
45924 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__MODIFY(dst, src) \
45926 ~0x007c0000U) | (((u_int32_t)(src) <<\
45928 #define PEAK_DET_CTRL_1__PEAK_DET_TALLY_THR_HIGH__VERIFY(src) \
45929 (!((((u_int32_t)(src)\
45936 #define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__READ(src) \
45937 (((u_int32_t)(src)\
45939 #define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__WRITE(src) \
45940 (((u_int32_t)(src)\
45942 #define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__MODIFY(dst, src) \
45944 ~0x3f800000U) | (((u_int32_t)(src) <<\
45946 #define PEAK_DET_CTRL_1__PEAK_DET_SETTLING__VERIFY(src) \
45947 (!((((u_int32_t)(src)\
45954 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__READ(src) \
45955 (((u_int32_t)(src)\
45957 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__WRITE(src) \
45958 (((u_int32_t)(src)\
45960 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__MODIFY(dst, src) \
45962 ~0x40000000U) | (((u_int32_t)(src) <<\
45964 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_CAL__VERIFY(src) \
45965 (!((((u_int32_t)(src)\
45978 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__READ(src) \
45979 (((u_int32_t)(src)\
45981 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__WRITE(src) \
45982 (((u_int32_t)(src)\
45984 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__MODIFY(dst, src) \
45986 ~0x80000000U) | (((u_int32_t)(src) <<\
45988 #define PEAK_DET_CTRL_1__PWD_PKDET_DURING_RX__VERIFY(src) \
45989 (!((((u_int32_t)(src)\
46015 #define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__READ(src) \
46016 (u_int32_t)(src)\
46018 #define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__WRITE(src) \
46019 ((u_int32_t)(src)\
46021 #define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__MODIFY(dst, src) \
46023 ~0x000003ffU) | ((u_int32_t)(src) &\
46025 #define PEAK_DET_CTRL_2__RFSAT_2_ADD_RFGAIN_DEL__VERIFY(src) \
46026 (!(((u_int32_t)(src)\
46033 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__READ(src) \
46034 (((u_int32_t)(src)\
46036 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__WRITE(src) \
46037 (((u_int32_t)(src)\
46039 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__MODIFY(dst, src) \
46041 ~0x00007c00U) | (((u_int32_t)(src) <<\
46043 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_LOW__VERIFY(src) \
46044 (!((((u_int32_t)(src)\
46051 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__READ(src) \
46052 (((u_int32_t)(src)\
46054 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__WRITE(src) \
46055 (((u_int32_t)(src)\
46057 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__MODIFY(dst, src) \
46059 ~0x000f8000U) | (((u_int32_t)(src) <<\
46061 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_MED__VERIFY(src) \
46062 (!((((u_int32_t)(src)\
46069 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__READ(src) \
46070 (((u_int32_t)(src)\
46072 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__WRITE(src) \
46073 (((u_int32_t)(src)\
46075 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__MODIFY(dst, src) \
46077 ~0x01f00000U) | (((u_int32_t)(src) <<\
46079 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_HIGH__VERIFY(src) \
46080 (!((((u_int32_t)(src)\
46087 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__READ(src) \
46088 (((u_int32_t)(src)\
46090 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__WRITE(src) \
46091 (((u_int32_t)(src)\
46093 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__MODIFY(dst, src) \
46095 ~0x3e000000U) | (((u_int32_t)(src) <<\
46097 #define PEAK_DET_CTRL_2__RF_GAIN_DROP_DB_NON__VERIFY(src) \
46098 (!((((u_int32_t)(src)\
46118 #define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__READ(src) \
46119 (u_int32_t)(src)\
46121 #define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__WRITE(src) \
46122 ((u_int32_t)(src)\
46124 #define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__MODIFY(dst, src) \
46126 ~0x000000ffU) | ((u_int32_t)(src) &\
46128 #define RX_GAIN_BOUNDS_1__RX_MAX_MB_GAIN__VERIFY(src) \
46129 (!(((u_int32_t)(src)\
46136 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__READ(src) \
46137 (((u_int32_t)(src)\
46139 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__WRITE(src) \
46140 (((u_int32_t)(src)\
46142 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__MODIFY(dst, src) \
46144 ~0x0000ff00U) | (((u_int32_t)(src) <<\
46146 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN_REF__VERIFY(src) \
46147 (!((((u_int32_t)(src)\
46154 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__READ(src) \
46155 (((u_int32_t)(src)\
46157 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__WRITE(src) \
46158 (((u_int32_t)(src)\
46160 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__MODIFY(dst, src) \
46162 ~0x00ff0000U) | (((u_int32_t)(src) <<\
46164 #define RX_GAIN_BOUNDS_1__RX_MAX_RF_GAIN__VERIFY(src) \
46165 (!((((u_int32_t)(src)\
46172 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__READ(src) \
46173 (((u_int32_t)(src)\
46175 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__WRITE(src) \
46176 (((u_int32_t)(src)\
46178 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__MODIFY(dst, src) \
46180 ~0x01000000U) | (((u_int32_t)(src) <<\
46182 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_2G__VERIFY(src) \
46183 (!((((u_int32_t)(src)\
46196 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__READ(src) \
46197 (((u_int32_t)(src)\
46199 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__WRITE(src) \
46200 (((u_int32_t)(src)\
46202 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__MODIFY(dst, src) \
46204 ~0x02000000U) | (((u_int32_t)(src) <<\
46206 #define RX_GAIN_BOUNDS_1__RX_OCGAIN_SEL_5G__VERIFY(src) \
46207 (!((((u_int32_t)(src)\
46233 #define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__READ(src) \
46234 (u_int32_t)(src)\
46236 #define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__WRITE(src) \
46237 ((u_int32_t)(src)\
46239 #define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__MODIFY(dst, src) \
46241 ~0x000000ffU) | ((u_int32_t)(src) &\
46243 #define RX_GAIN_BOUNDS_2__GC_RSSI_LOW_DB__VERIFY(src) \
46244 (!(((u_int32_t)(src)\
46251 #define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__READ(src) \
46252 (((u_int32_t)(src)\
46254 #define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__WRITE(src) \
46255 (((u_int32_t)(src)\
46257 #define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__MODIFY(dst, src) \
46259 ~0x0000ff00U) | (((u_int32_t)(src) <<\
46261 #define RX_GAIN_BOUNDS_2__RF_GAIN_REF_BASE_ADDR__VERIFY(src) \
46262 (!((((u_int32_t)(src)\
46269 #define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__READ(src) \
46270 (((u_int32_t)(src)\
46272 #define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__WRITE(src) \
46273 (((u_int32_t)(src)\
46275 #define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__MODIFY(dst, src) \
46277 ~0x00ff0000U) | (((u_int32_t)(src) <<\
46279 #define RX_GAIN_BOUNDS_2__RF_GAIN_BASE_ADDR__VERIFY(src) \
46280 (!((((u_int32_t)(src)\
46287 #define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__READ(src) \
46288 (((u_int32_t)(src)\
46290 #define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__WRITE(src) \
46291 (((u_int32_t)(src)\
46293 #define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__MODIFY(dst, src) \
46295 ~0xff000000U) | (((u_int32_t)(src) <<\
46297 #define RX_GAIN_BOUNDS_2__RF_GAIN_DIV_BASE_ADDR__VERIFY(src) \
46298 (!((((u_int32_t)(src)\
46318 #define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__READ(src) \
46319 (u_int32_t)(src)\
46321 #define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__WRITE(src) \
46322 ((u_int32_t)(src)\
46324 #define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__MODIFY(dst, src) \
46326 ~0x0000003fU) | ((u_int32_t)(src) &\
46328 #define PEAK_DET_CAL_CTRL__PKDET_CAL_WIN_THR__VERIFY(src) \
46329 (!(((u_int32_t)(src)\
46336 #define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__READ(src) \
46337 (((u_int32_t)(src)\
46339 #define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__WRITE(src) \
46340 (((u_int32_t)(src)\
46342 #define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__MODIFY(dst, src) \
46344 ~0x00000fc0U) | (((u_int32_t)(src) <<\
46346 #define PEAK_DET_CAL_CTRL__PKDET_CAL_BIAS__VERIFY(src) \
46347 (!((((u_int32_t)(src)\
46354 #define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__READ(src) \
46355 (((u_int32_t)(src)\
46357 #define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__WRITE(src) \
46358 (((u_int32_t)(src)\
46360 #define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__MODIFY(dst, src) \
46362 ~0x00003000U) | (((u_int32_t)(src) <<\
46364 #define PEAK_DET_CAL_CTRL__PKDET_CAL_MEAS_TIME_SEL__VERIFY(src) \
46365 (!((((u_int32_t)(src)\
46385 #define AGC_DIG_DC_CTRL__USE_DIG_DC__READ(src) (u_int32_t)(src) & 0x00000001U
46386 #define AGC_DIG_DC_CTRL__USE_DIG_DC__WRITE(src) \
46387 ((u_int32_t)(src)\
46389 #define AGC_DIG_DC_CTRL__USE_DIG_DC__MODIFY(dst, src) \
46391 ~0x00000001U) | ((u_int32_t)(src) &\
46393 #define AGC_DIG_DC_CTRL__USE_DIG_DC__VERIFY(src) \
46394 (!(((u_int32_t)(src)\
46407 #define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__READ(src) \
46408 (((u_int32_t)(src)\
46410 #define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__WRITE(src) \
46411 (((u_int32_t)(src)\
46413 #define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__MODIFY(dst, src) \
46415 ~0x0000000eU) | (((u_int32_t)(src) <<\
46417 #define AGC_DIG_DC_CTRL__DIG_DC_SCALE_BIAS__VERIFY(src) \
46418 (!((((u_int32_t)(src)\
46425 #define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__READ(src) \
46426 (((u_int32_t)(src)\
46428 #define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__WRITE(src) \
46429 (((u_int32_t)(src)\
46431 #define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__MODIFY(dst, src) \
46433 ~0x000003f0U) | (((u_int32_t)(src) <<\
46435 #define AGC_DIG_DC_CTRL__DIG_DC_CORRECT_CAP__VERIFY(src) \
46436 (!((((u_int32_t)(src)\
46443 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__READ(src) \
46444 (((u_int32_t)(src)\
46446 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__WRITE(src) \
46447 (((u_int32_t)(src)\
46449 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__MODIFY(dst, src) \
46451 ~0x00000400U) | (((u_int32_t)(src) <<\
46453 #define AGC_DIG_DC_CTRL__DIG_DC_SWITCH_CCK__VERIFY(src) \
46454 (!((((u_int32_t)(src)\
46467 #define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__READ(src) \
46468 (((u_int32_t)(src)\
46470 #define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__WRITE(src) \
46471 (((u_int32_t)(src)\
46473 #define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__MODIFY(dst, src) \
46475 ~0xffff0000U) | (((u_int32_t)(src) <<\
46477 #define AGC_DIG_DC_CTRL__DIG_DC_MIXER_SEL_MASK__VERIFY(src) \
46478 (!((((u_int32_t)(src)\
46498 #define BT_COEX__ENABLE_BT_COEX__READ(src) (u_int32_t)(src) & 0x00000001U
46499 #define BT_COEX__ENABLE_BT_COEX__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
46500 #define BT_COEX__ENABLE_BT_COEX__MODIFY(dst, src) \
46502 ~0x00000001U) | ((u_int32_t)(src) &\
46504 #define BT_COEX__ENABLE_BT_COEX__VERIFY(src) \
46505 (!(((u_int32_t)(src)\
46518 #define BT_COEX__WLAN_BT_PRIORITY__READ(src) \
46519 (((u_int32_t)(src)\
46521 #define BT_COEX__WLAN_BT_PRIORITY__WRITE(src) \
46522 (((u_int32_t)(src)\
46524 #define BT_COEX__WLAN_BT_PRIORITY__MODIFY(dst, src) \
46526 ~0x00000002U) | (((u_int32_t)(src) <<\
46528 #define BT_COEX__WLAN_BT_PRIORITY__VERIFY(src) \
46529 (!((((u_int32_t)(src)\
46542 #define BT_COEX__RFSAT_RESTART_THRESH__READ(src) \
46543 (((u_int32_t)(src)\
46545 #define BT_COEX__RFSAT_RESTART_THRESH__WRITE(src) \
46546 (((u_int32_t)(src)\
46548 #define BT_COEX__RFSAT_RESTART_THRESH__MODIFY(dst, src) \
46550 ~0x0000000cU) | (((u_int32_t)(src) <<\
46552 #define BT_COEX__RFSAT_RESTART_THRESH__VERIFY(src) \
46553 (!((((u_int32_t)(src)\
46560 #define BT_COEX__ENABLE_RFSAT_RESTART__READ(src) \
46561 (((u_int32_t)(src)\
46563 #define BT_COEX__ENABLE_RFSAT_RESTART__WRITE(src) \
46564 (((u_int32_t)(src)\
46566 #define BT_COEX__ENABLE_RFSAT_RESTART__MODIFY(dst, src) \
46568 ~0x00000010U) | (((u_int32_t)(src) <<\
46570 #define BT_COEX__ENABLE_RFSAT_RESTART__VERIFY(src) \
46571 (!((((u_int32_t)(src)\
46597 #define RSSI_B0__RSSI_0__READ(src) (u_int32_t)(src) & 0x000000ffU
46603 #define RSSI_B0__RSSI_EXT_0__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
46621 #define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_I_0_CCK__READ(src) \
46622 (u_int32_t)(src)\
46629 #define SPUR_EST_CCK_REPORT_B0__SPUR_EST_SD_Q_0_CCK__READ(src) \
46630 (((u_int32_t)(src)\
46637 #define SPUR_EST_CCK_REPORT_B0__SPUR_EST_I_0_CCK__READ(src) \
46638 (((u_int32_t)(src)\
46645 #define SPUR_EST_CCK_REPORT_B0__SPUR_EST_Q_0_CCK__READ(src) \
46646 (((u_int32_t)(src)\
46665 #define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C1_RES_I_0__READ(src) \
46666 (u_int32_t)(src)\
46673 #define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C2_RES_I_0__READ(src) \
46674 (((u_int32_t)(src)\
46681 #define AGC_DIG_DC_STATUS_I_B0__DIG_DC_C3_RES_I_0__READ(src) \
46682 (((u_int32_t)(src)\
46701 #define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C1_RES_Q_0__READ(src) \
46702 (u_int32_t)(src)\
46709 #define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C2_RES_Q_0__READ(src) \
46710 (((u_int32_t)(src)\
46717 #define AGC_DIG_DC_STATUS_Q_B0__DIG_DC_C3_RES_Q_0__READ(src) \
46718 (((u_int32_t)(src)\
46737 #define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__READ(src) \
46738 (u_int32_t)(src)\
46740 #define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__WRITE(src) \
46741 ((u_int32_t)(src)\
46743 #define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__MODIFY(dst, src) \
46745 ~0x0000003fU) | ((u_int32_t)(src) &\
46747 #define BBB_SIG_DETECT__WEAK_SIG_THR_CCK__VERIFY(src) \
46748 (!(((u_int32_t)(src)\
46755 #define BBB_SIG_DETECT__ANT_SWITCH_TIME__READ(src) \
46756 (((u_int32_t)(src)\
46758 #define BBB_SIG_DETECT__ANT_SWITCH_TIME__WRITE(src) \
46759 (((u_int32_t)(src)\
46761 #define BBB_SIG_DETECT__ANT_SWITCH_TIME__MODIFY(dst, src) \
46763 ~0x00001fc0U) | (((u_int32_t)(src) <<\
46765 #define BBB_SIG_DETECT__ANT_SWITCH_TIME__VERIFY(src) \
46766 (!((((u_int32_t)(src)\
46773 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__READ(src) \
46774 (((u_int32_t)(src)\
46776 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__WRITE(src) \
46777 (((u_int32_t)(src)\
46779 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__MODIFY(dst, src) \
46781 ~0x00002000U) | (((u_int32_t)(src) <<\
46783 #define BBB_SIG_DETECT__ENABLE_ANT_FAST_DIV__VERIFY(src) \
46784 (!((((u_int32_t)(src)\
46797 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__READ(src) \
46798 (((u_int32_t)(src)\
46800 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__WRITE(src) \
46801 (((u_int32_t)(src)\
46803 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__MODIFY(dst, src) \
46805 ~0x00004000U) | (((u_int32_t)(src) <<\
46807 #define BBB_SIG_DETECT__LB_ALPHA_128_CCK__VERIFY(src) \
46808 (!((((u_int32_t)(src)\
46821 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__READ(src) \
46822 (((u_int32_t)(src)\
46824 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__WRITE(src) \
46825 (((u_int32_t)(src)\
46827 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__MODIFY(dst, src) \
46829 ~0x00008000U) | (((u_int32_t)(src) <<\
46831 #define BBB_SIG_DETECT__LB_RX_ENABLE_CCK__VERIFY(src) \
46832 (!((((u_int32_t)(src)\
46845 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__READ(src) \
46846 (((u_int32_t)(src)\
46848 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__WRITE(src) \
46849 (((u_int32_t)(src)\
46851 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__MODIFY(dst, src) \
46853 ~0x00010000U) | (((u_int32_t)(src) <<\
46855 #define BBB_SIG_DETECT__CYC32_COARSE_DC_EST_CCK__VERIFY(src) \
46856 (!((((u_int32_t)(src)\
46869 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__READ(src) \
46870 (((u_int32_t)(src)\
46872 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__WRITE(src) \
46873 (((u_int32_t)(src)\
46875 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__MODIFY(dst, src) \
46877 ~0x00020000U) | (((u_int32_t)(src) <<\
46879 #define BBB_SIG_DETECT__CYC64_COARSE_DC_EST_CCK__VERIFY(src) \
46880 (!((((u_int32_t)(src)\
46893 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__READ(src) \
46894 (((u_int32_t)(src)\
46896 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__WRITE(src) \
46897 (((u_int32_t)(src)\
46899 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__MODIFY(dst, src) \
46901 ~0x00040000U) | (((u_int32_t)(src) <<\
46903 #define BBB_SIG_DETECT__ENABLE_COARSE_DC_CCK__VERIFY(src) \
46904 (!((((u_int32_t)(src)\
46917 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__READ(src) \
46918 (((u_int32_t)(src)\
46920 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__WRITE(src) \
46921 (((u_int32_t)(src)\
46923 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__MODIFY(dst, src) \
46925 ~0x00080000U) | (((u_int32_t)(src) <<\
46927 #define BBB_SIG_DETECT__CYC256_FINE_DC_EST_CCK__VERIFY(src) \
46928 (!((((u_int32_t)(src)\
46941 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__READ(src) \
46942 (((u_int32_t)(src)\
46944 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__WRITE(src) \
46945 (((u_int32_t)(src)\
46947 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__MODIFY(dst, src) \
46949 ~0x00100000U) | (((u_int32_t)(src) <<\
46951 #define BBB_SIG_DETECT__ENABLE_FINE_DC_CCK__VERIFY(src) \
46952 (!((((u_int32_t)(src)\
46965 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__READ(src) \
46966 (((u_int32_t)(src)\
46968 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__WRITE(src) \
46969 (((u_int32_t)(src)\
46971 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__MODIFY(dst, src) \
46973 ~0x00200000U) | (((u_int32_t)(src) <<\
46975 #define BBB_SIG_DETECT__DELAY_START_SYNC_CCK__VERIFY(src) \
46976 (!((((u_int32_t)(src)\
46989 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__READ(src) \
46990 (((u_int32_t)(src)\
46992 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__WRITE(src) \
46993 (((u_int32_t)(src)\
46995 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__MODIFY(dst, src) \
46997 ~0x00400000U) | (((u_int32_t)(src) <<\
46999 #define BBB_SIG_DETECT__USE_DC_EST_DURING_SRCH__VERIFY(src) \
47000 (!((((u_int32_t)(src)\
47013 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__READ(src) \
47014 (((u_int32_t)(src)\
47016 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__WRITE(src) \
47017 (((u_int32_t)(src)\
47019 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__MODIFY(dst, src) \
47021 ~0x80000000U) | (((u_int32_t)(src) <<\
47023 #define BBB_SIG_DETECT__ENABLE_BARKER_TWO_PHASE__VERIFY(src) \
47024 (!((((u_int32_t)(src)\
47050 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__READ(src) \
47051 (u_int32_t)(src)\
47053 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__WRITE(src) \
47054 ((u_int32_t)(src)\
47056 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__MODIFY(dst, src) \
47058 ~0x00000001U) | ((u_int32_t)(src) &\
47060 #define BBB_DAGC_CTRL__ENABLE_DAGC_CCK__VERIFY(src) \
47061 (!(((u_int32_t)(src)\
47074 #define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__READ(src) \
47075 (((u_int32_t)(src)\
47077 #define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__WRITE(src) \
47078 (((u_int32_t)(src)\
47080 #define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__MODIFY(dst, src) \
47082 ~0x000001feU) | (((u_int32_t)(src) <<\
47084 #define BBB_DAGC_CTRL__DAGC_TARGET_PWR_CCK__VERIFY(src) \
47085 (!((((u_int32_t)(src)\
47092 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__READ(src) \
47093 (((u_int32_t)(src)\
47095 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__WRITE(src) \
47096 (((u_int32_t)(src)\
47098 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__MODIFY(dst, src) \
47100 ~0x00000200U) | (((u_int32_t)(src) <<\
47102 #define BBB_DAGC_CTRL__ENABLE_BARKER_RSSI_THR__VERIFY(src) \
47103 (!((((u_int32_t)(src)\
47116 #define BBB_DAGC_CTRL__BARKER_RSSI_THR__READ(src) \
47117 (((u_int32_t)(src)\
47119 #define BBB_DAGC_CTRL__BARKER_RSSI_THR__WRITE(src) \
47120 (((u_int32_t)(src)\
47122 #define BBB_DAGC_CTRL__BARKER_RSSI_THR__MODIFY(dst, src) \
47124 ~0x0001fc00U) | (((u_int32_t)(src) <<\
47126 #define BBB_DAGC_CTRL__BARKER_RSSI_THR__VERIFY(src) \
47127 (!((((u_int32_t)(src)\
47134 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__READ(src) \
47135 (((u_int32_t)(src)\
47137 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__WRITE(src) \
47138 (((u_int32_t)(src)\
47140 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__MODIFY(dst, src) \
47142 ~0x00020000U) | (((u_int32_t)(src) <<\
47144 #define BBB_DAGC_CTRL__ENABLE_FIRSTEP_SEL__VERIFY(src) \
47145 (!((((u_int32_t)(src)\
47158 #define BBB_DAGC_CTRL__FIRSTEP_2__READ(src) \
47159 (((u_int32_t)(src)\
47161 #define BBB_DAGC_CTRL__FIRSTEP_2__WRITE(src) \
47162 (((u_int32_t)(src)\
47164 #define BBB_DAGC_CTRL__FIRSTEP_2__MODIFY(dst, src) \
47166 ~0x00fc0000U) | (((u_int32_t)(src) <<\
47168 #define BBB_DAGC_CTRL__FIRSTEP_2__VERIFY(src) \
47169 (!((((u_int32_t)(src)\
47176 #define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__READ(src) \
47177 (((u_int32_t)(src)\
47179 #define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__WRITE(src) \
47180 (((u_int32_t)(src)\
47182 #define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__MODIFY(dst, src) \
47184 ~0x0f000000U) | (((u_int32_t)(src) <<\
47186 #define BBB_DAGC_CTRL__FIRSTEP_COUNT_LGMAX__VERIFY(src) \
47187 (!((((u_int32_t)(src)\
47194 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__READ(src) \
47195 (((u_int32_t)(src)\
47197 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__WRITE(src) \
47198 (((u_int32_t)(src)\
47200 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__MODIFY(dst, src) \
47202 ~0x30000000U) | (((u_int32_t)(src) <<\
47204 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_0__VERIFY(src) \
47205 (!((((u_int32_t)(src)\
47212 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__READ(src) \
47213 (((u_int32_t)(src)\
47215 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__WRITE(src) \
47216 (((u_int32_t)(src)\
47218 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__MODIFY(dst, src) \
47220 ~0xc0000000U) | (((u_int32_t)(src) <<\
47222 #define BBB_DAGC_CTRL__FORCE_RX_CHAIN_CCK_1__VERIFY(src) \
47223 (!((((u_int32_t)(src)\
47243 #define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__READ(src) \
47244 (u_int32_t)(src)\
47246 #define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__WRITE(src) \
47247 ((u_int32_t)(src)\
47249 #define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__MODIFY(dst, src) \
47251 ~0x0000001fU) | ((u_int32_t)(src) &\
47253 #define IQCORR_CTRL_CCK__IQCORR_Q_Q_COFF_CCK__VERIFY(src) \
47254 (!(((u_int32_t)(src)\
47261 #define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__READ(src) \
47262 (((u_int32_t)(src)\
47264 #define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__WRITE(src) \
47265 (((u_int32_t)(src)\
47267 #define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__MODIFY(dst, src) \
47269 ~0x000007e0U) | (((u_int32_t)(src) <<\
47271 #define IQCORR_CTRL_CCK__IQCORR_Q_I_COFF_CCK__VERIFY(src) \
47272 (!((((u_int32_t)(src)\
47279 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__READ(src) \
47280 (((u_int32_t)(src)\
47282 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__WRITE(src) \
47283 (((u_int32_t)(src)\
47285 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__MODIFY(dst, src) \
47287 ~0x00000800U) | (((u_int32_t)(src) <<\
47289 #define IQCORR_CTRL_CCK__ENABLE_IQCORR_CCK__VERIFY(src) \
47290 (!((((u_int32_t)(src)\
47303 #define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__READ(src) \
47304 (((u_int32_t)(src)\
47306 #define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__WRITE(src) \
47307 (((u_int32_t)(src)\
47309 #define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__MODIFY(dst, src) \
47311 ~0x00003000U) | (((u_int32_t)(src) <<\
47313 #define IQCORR_CTRL_CCK__RXCAL_MEAS_TIME_SEL__VERIFY(src) \
47314 (!((((u_int32_t)(src)\
47321 #define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__READ(src) \
47322 (((u_int32_t)(src)\
47324 #define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__WRITE(src) \
47325 (((u_int32_t)(src)\
47327 #define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__MODIFY(dst, src) \
47329 ~0x0000c000U) | (((u_int32_t)(src) <<\
47331 #define IQCORR_CTRL_CCK__CLCAL_MEAS_TIME_SEL__VERIFY(src) \
47332 (!((((u_int32_t)(src)\
47339 #define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__READ(src) \
47340 (((u_int32_t)(src)\
47342 #define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__WRITE(src) \
47343 (((u_int32_t)(src)\
47345 #define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__MODIFY(dst, src) \
47347 ~0x001f0000U) | (((u_int32_t)(src) <<\
47349 #define IQCORR_CTRL_CCK__CF_CLC_INIT_RFGAIN__VERIFY(src) \
47350 (!((((u_int32_t)(src)\
47370 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__READ(src) \
47371 (u_int32_t)(src)\
47373 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__WRITE(src) \
47374 ((u_int32_t)(src)\
47376 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__MODIFY(dst, src) \
47378 ~0x00000001U) | ((u_int32_t)(src) &\
47380 #define CCK_SPUR_MIT__USE_CCK_SPUR_MIT__VERIFY(src) \
47381 (!(((u_int32_t)(src)\
47394 #define CCK_SPUR_MIT__SPUR_RSSI_THR__READ(src) \
47395 (((u_int32_t)(src)\
47397 #define CCK_SPUR_MIT__SPUR_RSSI_THR__WRITE(src) \
47398 (((u_int32_t)(src)\
47400 #define CCK_SPUR_MIT__SPUR_RSSI_THR__MODIFY(dst, src) \
47402 ~0x000001feU) | (((u_int32_t)(src) <<\
47404 #define CCK_SPUR_MIT__SPUR_RSSI_THR__VERIFY(src) \
47405 (!((((u_int32_t)(src)\
47412 #define CCK_SPUR_MIT__CCK_SPUR_FREQ__READ(src) \
47413 (((u_int32_t)(src)\
47415 #define CCK_SPUR_MIT__CCK_SPUR_FREQ__WRITE(src) \
47416 (((u_int32_t)(src)\
47418 #define CCK_SPUR_MIT__CCK_SPUR_FREQ__MODIFY(dst, src) \
47420 ~0x1ffffe00U) | (((u_int32_t)(src) <<\
47422 #define CCK_SPUR_MIT__CCK_SPUR_FREQ__VERIFY(src) \
47423 (!((((u_int32_t)(src)\
47430 #define CCK_SPUR_MIT__SPUR_FILTER_TYPE__READ(src) \
47431 (((u_int32_t)(src)\
47433 #define CCK_SPUR_MIT__SPUR_FILTER_TYPE__WRITE(src) \
47434 (((u_int32_t)(src)\
47436 #define CCK_SPUR_MIT__SPUR_FILTER_TYPE__MODIFY(dst, src) \
47438 ~0x60000000U) | (((u_int32_t)(src) <<\
47440 #define CCK_SPUR_MIT__SPUR_FILTER_TYPE__VERIFY(src) \
47441 (!((((u_int32_t)(src)\
47461 #define MRC_CCK_CTRL__BBB_MRC_EN__READ(src) (u_int32_t)(src) & 0x00000001U
47462 #define MRC_CCK_CTRL__BBB_MRC_EN__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
47463 #define MRC_CCK_CTRL__BBB_MRC_EN__MODIFY(dst, src) \
47465 ~0x00000001U) | ((u_int32_t)(src) &\
47467 #define MRC_CCK_CTRL__BBB_MRC_EN__VERIFY(src) \
47468 (!(((u_int32_t)(src)\
47481 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__READ(src) \
47482 (((u_int32_t)(src)\
47484 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__WRITE(src) \
47485 (((u_int32_t)(src)\
47487 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__MODIFY(dst, src) \
47489 ~0x00000002U) | (((u_int32_t)(src) <<\
47491 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_MUX_REG__VERIFY(src) \
47492 (!((((u_int32_t)(src)\
47505 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__READ(src) \
47506 (((u_int32_t)(src)\
47508 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__WRITE(src) \
47509 (((u_int32_t)(src)\
47511 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__MODIFY(dst, src) \
47513 ~0x0000001cU) | (((u_int32_t)(src) <<\
47515 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_HI__VERIFY(src) \
47516 (!((((u_int32_t)(src)\
47523 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__READ(src) \
47524 (((u_int32_t)(src)\
47526 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__WRITE(src) \
47527 (((u_int32_t)(src)\
47529 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__MODIFY(dst, src) \
47531 ~0x000000e0U) | (((u_int32_t)(src) <<\
47533 #define MRC_CCK_CTRL__AGCDP_CCK_PD_ACCU_THR_LOW__VERIFY(src) \
47534 (!((((u_int32_t)(src)\
47541 #define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__READ(src) \
47542 (((u_int32_t)(src)\
47544 #define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__WRITE(src) \
47545 (((u_int32_t)(src)\
47547 #define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__MODIFY(dst, src) \
47549 ~0x00000f00U) | (((u_int32_t)(src) <<\
47551 #define MRC_CCK_CTRL__AGCDP_CCK_BARKER_RSSI_THR__VERIFY(src) \
47552 (!((((u_int32_t)(src)\
47559 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__READ(src) \
47560 (((u_int32_t)(src)\
47562 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__WRITE(src) \
47563 (((u_int32_t)(src)\
47565 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__MODIFY(dst, src) \
47567 ~0x0001f000U) | (((u_int32_t)(src) <<\
47569 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_HI__VERIFY(src) \
47570 (!((((u_int32_t)(src)\
47577 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__READ(src) \
47578 (((u_int32_t)(src)\
47580 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__WRITE(src) \
47581 (((u_int32_t)(src)\
47583 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__MODIFY(dst, src) \
47585 ~0x003e0000U) | (((u_int32_t)(src) <<\
47587 #define MRC_CCK_CTRL__AGCDP_CCK_MRC_BK_THR_LOW__VERIFY(src) \
47588 (!((((u_int32_t)(src)\
47595 #define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__READ(src) \
47596 (((u_int32_t)(src)\
47598 #define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__WRITE(src) \
47599 (((u_int32_t)(src)\
47601 #define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__MODIFY(dst, src) \
47603 ~0x0fc00000U) | (((u_int32_t)(src) <<\
47605 #define MRC_CCK_CTRL__AGCDP_CCK_MIN_VALUE__VERIFY(src) \
47606 (!((((u_int32_t)(src)\
47626 #define RX_OCGAIN__GAIN_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
47627 #define RX_OCGAIN__GAIN_ENTRY__MODIFY(dst, src) \
47629 ~0xffffffffU) | ((u_int32_t)(src) &\
47631 #define RX_OCGAIN__GAIN_ENTRY__VERIFY(src) \
47632 (!(((u_int32_t)(src)\
47651 #define D2_CHIP_ID__OLD_ID__READ(src) (u_int32_t)(src) & 0x000000ffU
47657 #define D2_CHIP_ID__ID__READ(src) (((u_int32_t)(src) & 0xffffff00U) >> 8)
47675 #define GEN_CONTROLS__TURBO__READ(src) (u_int32_t)(src) & 0x00000001U
47676 #define GEN_CONTROLS__TURBO__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
47677 #define GEN_CONTROLS__TURBO__MODIFY(dst, src) \
47679 ~0x00000001U) | ((u_int32_t)(src) &\
47681 #define GEN_CONTROLS__TURBO__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
47693 #define GEN_CONTROLS__CF_SHORT20__READ(src) \
47694 (((u_int32_t)(src)\
47696 #define GEN_CONTROLS__CF_SHORT20__WRITE(src) \
47697 (((u_int32_t)(src)\
47699 #define GEN_CONTROLS__CF_SHORT20__MODIFY(dst, src) \
47701 ~0x00000002U) | (((u_int32_t)(src) <<\
47703 #define GEN_CONTROLS__CF_SHORT20__VERIFY(src) \
47704 (!((((u_int32_t)(src)\
47717 #define GEN_CONTROLS__DYN_20_40__READ(src) \
47718 (((u_int32_t)(src)\
47720 #define GEN_CONTROLS__DYN_20_40__WRITE(src) \
47721 (((u_int32_t)(src)\
47723 #define GEN_CONTROLS__DYN_20_40__MODIFY(dst, src) \
47725 ~0x00000004U) | (((u_int32_t)(src) <<\
47727 #define GEN_CONTROLS__DYN_20_40__VERIFY(src) \
47728 (!((((u_int32_t)(src)\
47741 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__READ(src) \
47742 (((u_int32_t)(src)\
47744 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__WRITE(src) \
47745 (((u_int32_t)(src)\
47747 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__MODIFY(dst, src) \
47749 ~0x00000008U) | (((u_int32_t)(src) <<\
47751 #define GEN_CONTROLS__DYN_20_40_PRI_ONLY__VERIFY(src) \
47752 (!((((u_int32_t)(src)\
47765 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__READ(src) \
47766 (((u_int32_t)(src)\
47768 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__WRITE(src) \
47769 (((u_int32_t)(src)\
47771 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__MODIFY(dst, src) \
47773 ~0x00000010U) | (((u_int32_t)(src) <<\
47775 #define GEN_CONTROLS__DYN_20_40_PRI_CHN__VERIFY(src) \
47776 (!((((u_int32_t)(src)\
47789 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__READ(src) \
47790 (((u_int32_t)(src)\
47792 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__WRITE(src) \
47793 (((u_int32_t)(src)\
47795 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__MODIFY(dst, src) \
47797 ~0x00000020U) | (((u_int32_t)(src) <<\
47799 #define GEN_CONTROLS__DYN_20_40_EXT_CHN__VERIFY(src) \
47800 (!((((u_int32_t)(src)\
47813 #define GEN_CONTROLS__HT_ENABLE__READ(src) \
47814 (((u_int32_t)(src)\
47816 #define GEN_CONTROLS__HT_ENABLE__WRITE(src) \
47817 (((u_int32_t)(src)\
47819 #define GEN_CONTROLS__HT_ENABLE__MODIFY(dst, src) \
47821 ~0x00000040U) | (((u_int32_t)(src) <<\
47823 #define GEN_CONTROLS__HT_ENABLE__VERIFY(src) \
47824 (!((((u_int32_t)(src)\
47837 #define GEN_CONTROLS__ALLOW_SHORT_GI__READ(src) \
47838 (((u_int32_t)(src)\
47840 #define GEN_CONTROLS__ALLOW_SHORT_GI__WRITE(src) \
47841 (((u_int32_t)(src)\
47843 #define GEN_CONTROLS__ALLOW_SHORT_GI__MODIFY(dst, src) \
47845 ~0x00000080U) | (((u_int32_t)(src) <<\
47847 #define GEN_CONTROLS__ALLOW_SHORT_GI__VERIFY(src) \
47848 (!((((u_int32_t)(src)\
47861 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__READ(src) \
47862 (((u_int32_t)(src)\
47864 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__WRITE(src) \
47865 (((u_int32_t)(src)\
47867 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__MODIFY(dst, src) \
47869 ~0x00000100U) | (((u_int32_t)(src) <<\
47871 #define GEN_CONTROLS__CF_2_CHAINS_USE_WALSH__VERIFY(src) \
47872 (!((((u_int32_t)(src)\
47885 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__READ(src) \
47886 (((u_int32_t)(src)\
47888 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__WRITE(src) \
47889 (((u_int32_t)(src)\
47891 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__MODIFY(dst, src) \
47893 ~0x00000200U) | (((u_int32_t)(src) <<\
47895 #define GEN_CONTROLS__CF_3_CHAINS_USE_WALSH__VERIFY(src) \
47896 (!((((u_int32_t)(src)\
47909 #define GEN_CONTROLS__GF_ENABLE__READ(src) \
47910 (((u_int32_t)(src)\
47912 #define GEN_CONTROLS__GF_ENABLE__WRITE(src) \
47913 (((u_int32_t)(src)\
47915 #define GEN_CONTROLS__GF_ENABLE__MODIFY(dst, src) \
47917 ~0x00000400U) | (((u_int32_t)(src) <<\
47919 #define GEN_CONTROLS__GF_ENABLE__VERIFY(src) \
47920 (!((((u_int32_t)(src)\
47933 #define GEN_CONTROLS__BYPASS_DAC_FIFO_N__READ(src) \
47934 (((u_int32_t)(src)\
47936 #define GEN_CONTROLS__BYPASS_DAC_FIFO_N__WRITE(src) \
47937 (((u_int32_t)(src)\
47939 #define GEN_CONTROLS__BYPASS_DAC_FIFO_N__MODIFY(dst, src) \
47941 ~0x00000800U) | (((u_int32_t)(src) <<\
47943 #define GEN_CONTROLS__BYPASS_DAC_FIFO_N__VERIFY(src) \
47944 (!((((u_int32_t)(src)\
47957 #define GEN_CONTROLS__ML_ENABLE__READ(src) \
47958 (((u_int32_t)(src)\
47960 #define GEN_CONTROLS__ML_ENABLE__WRITE(src) \
47961 (((u_int32_t)(src)\
47963 #define GEN_CONTROLS__ML_ENABLE__MODIFY(dst, src) \
47965 ~0x00001000U) | (((u_int32_t)(src) <<\
47967 #define GEN_CONTROLS__ML_ENABLE__VERIFY(src) \
47968 (!((((u_int32_t)(src)\
47981 #define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__READ(src) \
47982 (((u_int32_t)(src)\
47984 #define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__WRITE(src) \
47985 (((u_int32_t)(src)\
47987 #define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__MODIFY(dst, src) \
47989 ~0x00002000U) | (((u_int32_t)(src) <<\
47991 #define GEN_CONTROLS__CF_CORR_TIM_HT_DLTF__VERIFY(src) \
47992 (!((((u_int32_t)(src)\
48005 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__READ(src) \
48006 (((u_int32_t)(src)\
48008 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__WRITE(src) \
48009 (((u_int32_t)(src)\
48011 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__MODIFY(dst, src) \
48013 ~0x00004000U) | (((u_int32_t)(src) <<\
48015 #define GEN_CONTROLS__BOND_OPT_CHAIN_SEL__VERIFY(src) \
48016 (!((((u_int32_t)(src)\
48042 #define MODES_SELECT__CCK_MODE__READ(src) (u_int32_t)(src) & 0x00000001U
48043 #define MODES_SELECT__CCK_MODE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
48044 #define MODES_SELECT__CCK_MODE__MODIFY(dst, src) \
48046 ~0x00000001U) | ((u_int32_t)(src) &\
48048 #define MODES_SELECT__CCK_MODE__VERIFY(src) \
48049 (!(((u_int32_t)(src)\
48062 #define MODES_SELECT__DYN_OFDM_CCK_MODE__READ(src) \
48063 (((u_int32_t)(src)\
48065 #define MODES_SELECT__DYN_OFDM_CCK_MODE__WRITE(src) \
48066 (((u_int32_t)(src)\
48068 #define MODES_SELECT__DYN_OFDM_CCK_MODE__MODIFY(dst, src) \
48070 ~0x00000004U) | (((u_int32_t)(src) <<\
48072 #define MODES_SELECT__DYN_OFDM_CCK_MODE__VERIFY(src) \
48073 (!((((u_int32_t)(src)\
48086 #define MODES_SELECT__HALF_RATE_MODE__READ(src) \
48087 (((u_int32_t)(src)\
48089 #define MODES_SELECT__HALF_RATE_MODE__WRITE(src) \
48090 (((u_int32_t)(src)\
48092 #define MODES_SELECT__HALF_RATE_MODE__MODIFY(dst, src) \
48094 ~0x00000020U) | (((u_int32_t)(src) <<\
48096 #define MODES_SELECT__HALF_RATE_MODE__VERIFY(src) \
48097 (!((((u_int32_t)(src)\
48110 #define MODES_SELECT__QUARTER_RATE_MODE__READ(src) \
48111 (((u_int32_t)(src)\
48113 #define MODES_SELECT__QUARTER_RATE_MODE__WRITE(src) \
48114 (((u_int32_t)(src)\
48116 #define MODES_SELECT__QUARTER_RATE_MODE__MODIFY(dst, src) \
48118 ~0x00000040U) | (((u_int32_t)(src) <<\
48120 #define MODES_SELECT__QUARTER_RATE_MODE__VERIFY(src) \
48121 (!((((u_int32_t)(src)\
48134 #define MODES_SELECT__MAC_CLK_MODE__READ(src) \
48135 (((u_int32_t)(src)\
48137 #define MODES_SELECT__MAC_CLK_MODE__WRITE(src) \
48138 (((u_int32_t)(src)\
48140 #define MODES_SELECT__MAC_CLK_MODE__MODIFY(dst, src) \
48142 ~0x00000080U) | (((u_int32_t)(src) <<\
48144 #define MODES_SELECT__MAC_CLK_MODE__VERIFY(src) \
48145 (!((((u_int32_t)(src)\
48158 #define MODES_SELECT__DISABLE_DYN_CCK_DET__READ(src) \
48159 (((u_int32_t)(src)\
48161 #define MODES_SELECT__DISABLE_DYN_CCK_DET__WRITE(src) \
48162 (((u_int32_t)(src)\
48164 #define MODES_SELECT__DISABLE_DYN_CCK_DET__MODIFY(dst, src) \
48166 ~0x00000100U) | (((u_int32_t)(src) <<\
48168 #define MODES_SELECT__DISABLE_DYN_CCK_DET__VERIFY(src) \
48169 (!((((u_int32_t)(src)\
48182 #define MODES_SELECT__SVD_HALF_RATE_MODE__READ(src) \
48183 (((u_int32_t)(src)\
48185 #define MODES_SELECT__SVD_HALF_RATE_MODE__WRITE(src) \
48186 (((u_int32_t)(src)\
48188 #define MODES_SELECT__SVD_HALF_RATE_MODE__MODIFY(dst, src) \
48190 ~0x00000200U) | (((u_int32_t)(src) <<\
48192 #define MODES_SELECT__SVD_HALF_RATE_MODE__VERIFY(src) \
48193 (!((((u_int32_t)(src)\
48219 #define ACTIVE__CF_ACTIVE__READ(src) (u_int32_t)(src) & 0x00000001U
48220 #define ACTIVE__CF_ACTIVE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
48221 #define ACTIVE__CF_ACTIVE__MODIFY(dst, src) \
48223 ~0x00000001U) | ((u_int32_t)(src) &\
48225 #define ACTIVE__CF_ACTIVE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
48250 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__READ(src) \
48251 (u_int32_t)(src)\
48253 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__WRITE(src) \
48254 ((u_int32_t)(src)\
48256 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__MODIFY(dst, src) \
48258 ~0x000003ffU) | ((u_int32_t)(src) &\
48260 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_A__VERIFY(src) \
48261 (!(((u_int32_t)(src)\
48268 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__READ(src) \
48269 (((u_int32_t)(src)\
48271 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__WRITE(src) \
48272 (((u_int32_t)(src)\
48274 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__MODIFY(dst, src) \
48276 ~0x0001fc00U) | (((u_int32_t)(src) <<\
48278 #define VIT_SPUR_MASK_A__CF_PUNC_MASK_IDX_A__VERIFY(src) \
48279 (!((((u_int32_t)(src)\
48299 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__READ(src) \
48300 (u_int32_t)(src)\
48302 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__WRITE(src) \
48303 ((u_int32_t)(src)\
48305 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__MODIFY(dst, src) \
48307 ~0x000003ffU) | ((u_int32_t)(src) &\
48309 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_B__VERIFY(src) \
48310 (!(((u_int32_t)(src)\
48317 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__READ(src) \
48318 (((u_int32_t)(src)\
48320 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__WRITE(src) \
48321 (((u_int32_t)(src)\
48323 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__MODIFY(dst, src) \
48325 ~0x0001fc00U) | (((u_int32_t)(src) <<\
48327 #define VIT_SPUR_MASK_B__CF_PUNC_MASK_IDX_B__VERIFY(src) \
48328 (!((((u_int32_t)(src)\
48348 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__READ(src) \
48349 (u_int32_t)(src)\
48351 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__WRITE(src) \
48352 ((u_int32_t)(src)\
48354 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__MODIFY(dst, src) \
48356 ~0x00000001U) | ((u_int32_t)(src) &\
48358 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ENA__VERIFY(src) \
48359 (!(((u_int32_t)(src)\
48372 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__READ(src) \
48373 (((u_int32_t)(src)\
48375 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__WRITE(src) \
48376 (((u_int32_t)(src)\
48378 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__MODIFY(dst, src) \
48380 ~0x00000002U) | (((u_int32_t)(src) <<\
48382 #define SPECTRAL_SCAN__SPECTRAL_SCAN_ACTIVE__VERIFY(src) \
48383 (!((((u_int32_t)(src)\
48396 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__READ(src) \
48397 (((u_int32_t)(src)\
48399 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__WRITE(src) \
48400 (((u_int32_t)(src)\
48402 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__MODIFY(dst, src) \
48404 ~0x00000004U) | (((u_int32_t)(src) <<\
48406 #define SPECTRAL_SCAN__DISABLE_RADAR_TCTL_RST__VERIFY(src) \
48407 (!((((u_int32_t)(src)\
48420 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__READ(src) \
48421 (((u_int32_t)(src)\
48423 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__WRITE(src) \
48424 (((u_int32_t)(src)\
48426 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__MODIFY(dst, src) \
48428 ~0x00000008U) | (((u_int32_t)(src) <<\
48430 #define SPECTRAL_SCAN__DISABLE_PULSE_COARSE_LOW__VERIFY(src) \
48431 (!((((u_int32_t)(src)\
48444 #define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__READ(src) \
48445 (((u_int32_t)(src)\
48447 #define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__WRITE(src) \
48448 (((u_int32_t)(src)\
48450 #define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__MODIFY(dst, src) \
48452 ~0x000000f0U) | (((u_int32_t)(src) <<\
48454 #define SPECTRAL_SCAN__SPECTRAL_SCAN_FFT_PERIOD__VERIFY(src) \
48455 (!((((u_int32_t)(src)\
48462 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__READ(src) \
48463 (((u_int32_t)(src)\
48465 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__WRITE(src) \
48466 (((u_int32_t)(src)\
48468 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__MODIFY(dst, src) \
48470 ~0x0000ff00U) | (((u_int32_t)(src) <<\
48472 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PERIOD__VERIFY(src) \
48473 (!((((u_int32_t)(src)\
48480 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__READ(src) \
48481 (((u_int32_t)(src)\
48483 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__WRITE(src) \
48484 (((u_int32_t)(src)\
48486 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__MODIFY(dst, src) \
48488 ~0x0fff0000U) | (((u_int32_t)(src) <<\
48490 #define SPECTRAL_SCAN__SPECTRAL_SCAN_COUNT__VERIFY(src) \
48491 (!((((u_int32_t)(src)\
48498 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__READ(src) \
48499 (((u_int32_t)(src)\
48501 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__WRITE(src) \
48502 (((u_int32_t)(src)\
48504 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__MODIFY(dst, src) \
48506 ~0x10000000U) | (((u_int32_t)(src) <<\
48508 #define SPECTRAL_SCAN__SPECTRAL_SCAN_SHORT_RPT__VERIFY(src) \
48509 (!((((u_int32_t)(src)\
48522 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__READ(src) \
48523 (((u_int32_t)(src)\
48525 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__WRITE(src) \
48526 (((u_int32_t)(src)\
48528 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__MODIFY(dst, src) \
48530 ~0x20000000U) | (((u_int32_t)(src) <<\
48532 #define SPECTRAL_SCAN__SPECTRAL_SCAN_PRIORITY__VERIFY(src) \
48533 (!((((u_int32_t)(src)\
48546 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__READ(src) \
48547 (((u_int32_t)(src)\
48549 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__WRITE(src) \
48550 (((u_int32_t)(src)\
48552 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__MODIFY(dst, src) \
48554 ~0x40000000U) | (((u_int32_t)(src) <<\
48556 #define SPECTRAL_SCAN__SPECTRAL_SCAN_USE_ERR5__VERIFY(src) \
48557 (!((((u_int32_t)(src)\
48583 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__READ(src) \
48584 (u_int32_t)(src)\
48586 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__WRITE(src) \
48587 ((u_int32_t)(src)\
48589 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__MODIFY(dst, src) \
48591 ~0x00000001U) | ((u_int32_t)(src) &\
48593 #define RADAR_BW_FILTER__RADAR_AVG_BW_CHECK__VERIFY(src) \
48594 (!(((u_int32_t)(src)\
48607 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__READ(src) \
48608 (((u_int32_t)(src)\
48610 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__WRITE(src) \
48611 (((u_int32_t)(src)\
48613 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__MODIFY(dst, src) \
48615 ~0x00000002U) | (((u_int32_t)(src) <<\
48617 #define RADAR_BW_FILTER__RADAR_DC_SRC_SEL__VERIFY(src) \
48618 (!((((u_int32_t)(src)\
48631 #define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__READ(src) \
48632 (((u_int32_t)(src)\
48634 #define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__WRITE(src) \
48635 (((u_int32_t)(src)\
48637 #define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__MODIFY(dst, src) \
48639 ~0x0000000cU) | (((u_int32_t)(src) <<\
48641 #define RADAR_BW_FILTER__RADAR_FIRPWR_SEL__VERIFY(src) \
48642 (!((((u_int32_t)(src)\
48649 #define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__READ(src) \
48650 (((u_int32_t)(src)\
48652 #define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__WRITE(src) \
48653 (((u_int32_t)(src)\
48655 #define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__MODIFY(dst, src) \
48657 ~0x00000030U) | (((u_int32_t)(src) <<\
48659 #define RADAR_BW_FILTER__RADAR_PULSE_WIDTH_SEL__VERIFY(src) \
48660 (!((((u_int32_t)(src)\
48667 #define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__READ(src) \
48668 (((u_int32_t)(src)\
48670 #define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__WRITE(src) \
48671 (((u_int32_t)(src)\
48673 #define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__MODIFY(dst, src) \
48675 ~0x00007f00U) | (((u_int32_t)(src) <<\
48677 #define RADAR_BW_FILTER__RADAR_DC_FIRPWR_THRESH__VERIFY(src) \
48678 (!((((u_int32_t)(src)\
48685 #define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__READ(src) \
48686 (((u_int32_t)(src)\
48688 #define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__WRITE(src) \
48689 (((u_int32_t)(src)\
48691 #define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__MODIFY(dst, src) \
48693 ~0x001f8000U) | (((u_int32_t)(src) <<\
48695 #define RADAR_BW_FILTER__RADAR_DC_PWR_BIAS__VERIFY(src) \
48696 (!((((u_int32_t)(src)\
48703 #define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__READ(src) \
48704 (((u_int32_t)(src)\
48706 #define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__WRITE(src) \
48707 (((u_int32_t)(src)\
48709 #define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__MODIFY(dst, src) \
48711 ~0x07e00000U) | (((u_int32_t)(src) <<\
48713 #define RADAR_BW_FILTER__RADAR_BIN_MAX_BW__VERIFY(src) \
48714 (!((((u_int32_t)(src)\
48734 #define SEARCH_START_DELAY__SEARCH_START_DELAY__READ(src) \
48735 (u_int32_t)(src)\
48737 #define SEARCH_START_DELAY__SEARCH_START_DELAY__WRITE(src) \
48738 ((u_int32_t)(src)\
48740 #define SEARCH_START_DELAY__SEARCH_START_DELAY__MODIFY(dst, src) \
48742 ~0x00000fffU) | ((u_int32_t)(src) &\
48744 #define SEARCH_START_DELAY__SEARCH_START_DELAY__VERIFY(src) \
48745 (!(((u_int32_t)(src)\
48752 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__READ(src) \
48753 (((u_int32_t)(src)\
48755 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__WRITE(src) \
48756 (((u_int32_t)(src)\
48758 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__MODIFY(dst, src) \
48760 ~0x00001000U) | (((u_int32_t)(src) <<\
48762 #define SEARCH_START_DELAY__ENABLE_FLT_SVD__VERIFY(src) \
48763 (!((((u_int32_t)(src)\
48776 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__READ(src) \
48777 (((u_int32_t)(src)\
48779 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__WRITE(src) \
48780 (((u_int32_t)(src)\
48782 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__MODIFY(dst, src) \
48784 ~0x00002000U) | (((u_int32_t)(src) <<\
48786 #define SEARCH_START_DELAY__ENABLE_SEND_CHAN__VERIFY(src) \
48787 (!((((u_int32_t)(src)\
48813 #define MAX_RX_LENGTH__MAX_RX_LENGTH__READ(src) (u_int32_t)(src) & 0x00000fffU
48814 #define MAX_RX_LENGTH__MAX_RX_LENGTH__WRITE(src) \
48815 ((u_int32_t)(src)\
48817 #define MAX_RX_LENGTH__MAX_RX_LENGTH__MODIFY(dst, src) \
48819 ~0x00000fffU) | ((u_int32_t)(src) &\
48821 #define MAX_RX_LENGTH__MAX_RX_LENGTH__VERIFY(src) \
48822 (!(((u_int32_t)(src)\
48829 #define MAX_RX_LENGTH__MAX_HT_LENGTH__READ(src) \
48830 (((u_int32_t)(src)\
48832 #define MAX_RX_LENGTH__MAX_HT_LENGTH__WRITE(src) \
48833 (((u_int32_t)(src)\
48835 #define MAX_RX_LENGTH__MAX_HT_LENGTH__MODIFY(dst, src) \
48837 ~0x3ffff000U) | (((u_int32_t)(src) <<\
48839 #define MAX_RX_LENGTH__MAX_HT_LENGTH__VERIFY(src) \
48840 (!((((u_int32_t)(src)\
48860 #define FRAME_CONTROL__CF_OVERLAP_WINDOW__READ(src) \
48861 (u_int32_t)(src)\
48863 #define FRAME_CONTROL__CF_OVERLAP_WINDOW__WRITE(src) \
48864 ((u_int32_t)(src)\
48866 #define FRAME_CONTROL__CF_OVERLAP_WINDOW__MODIFY(dst, src) \
48868 ~0x00000003U) | ((u_int32_t)(src) &\
48870 #define FRAME_CONTROL__CF_OVERLAP_WINDOW__VERIFY(src) \
48871 (!(((u_int32_t)(src)\
48878 #define FRAME_CONTROL__CF_SCALE_SHORT__READ(src) \
48879 (((u_int32_t)(src)\
48881 #define FRAME_CONTROL__CF_SCALE_SHORT__WRITE(src) \
48882 (((u_int32_t)(src)\
48884 #define FRAME_CONTROL__CF_SCALE_SHORT__MODIFY(dst, src) \
48886 ~0x00000004U) | (((u_int32_t)(src) <<\
48888 #define FRAME_CONTROL__CF_SCALE_SHORT__VERIFY(src) \
48889 (!((((u_int32_t)(src)\
48902 #define FRAME_CONTROL__CF_TX_CLIP__READ(src) \
48903 (((u_int32_t)(src)\
48905 #define FRAME_CONTROL__CF_TX_CLIP__WRITE(src) \
48906 (((u_int32_t)(src)\
48908 #define FRAME_CONTROL__CF_TX_CLIP__MODIFY(dst, src) \
48910 ~0x00000038U) | (((u_int32_t)(src) <<\
48912 #define FRAME_CONTROL__CF_TX_CLIP__VERIFY(src) \
48913 (!((((u_int32_t)(src)\
48920 #define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__READ(src) \
48921 (((u_int32_t)(src)\
48923 #define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__WRITE(src) \
48924 (((u_int32_t)(src)\
48926 #define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__MODIFY(dst, src) \
48928 ~0x000000c0U) | (((u_int32_t)(src) <<\
48930 #define FRAME_CONTROL__CF_TX_DOUBLESAMP_DAC__VERIFY(src) \
48931 (!((((u_int32_t)(src)\
48938 #define FRAME_CONTROL__TX_END_ADJUST__READ(src) \
48939 (((u_int32_t)(src)\
48941 #define FRAME_CONTROL__TX_END_ADJUST__WRITE(src) \
48942 (((u_int32_t)(src)\
48944 #define FRAME_CONTROL__TX_END_ADJUST__MODIFY(dst, src) \
48946 ~0x0000ff00U) | (((u_int32_t)(src) <<\
48948 #define FRAME_CONTROL__TX_END_ADJUST__VERIFY(src) \
48949 (!((((u_int32_t)(src)\
48956 #define FRAME_CONTROL__PREPEND_CHAN_INFO__READ(src) \
48957 (((u_int32_t)(src)\
48959 #define FRAME_CONTROL__PREPEND_CHAN_INFO__WRITE(src) \
48960 (((u_int32_t)(src)\
48962 #define FRAME_CONTROL__PREPEND_CHAN_INFO__MODIFY(dst, src) \
48964 ~0x00010000U) | (((u_int32_t)(src) <<\
48966 #define FRAME_CONTROL__PREPEND_CHAN_INFO__VERIFY(src) \
48967 (!((((u_int32_t)(src)\
48980 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__READ(src) \
48981 (((u_int32_t)(src)\
48983 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__WRITE(src) \
48984 (((u_int32_t)(src)\
48986 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__MODIFY(dst, src) \
48988 ~0x00020000U) | (((u_int32_t)(src) <<\
48990 #define FRAME_CONTROL__SHORT_HIGH_PAR_NORM__VERIFY(src) \
48991 (!((((u_int32_t)(src)\
49004 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__READ(src) \
49005 (((u_int32_t)(src)\
49007 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__WRITE(src) \
49008 (((u_int32_t)(src)\
49010 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__MODIFY(dst, src) \
49012 ~0x00040000U) | (((u_int32_t)(src) <<\
49014 #define FRAME_CONTROL__EN_ERR_GREEN_FIELD__VERIFY(src) \
49015 (!((((u_int32_t)(src)\
49028 #define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__READ(src) \
49029 (((u_int32_t)(src)\
49031 #define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__WRITE(src) \
49032 (((u_int32_t)(src)\
49034 #define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__MODIFY(dst, src) \
49036 ~0x00080000U) | (((u_int32_t)(src) <<\
49038 #define FRAME_CONTROL__EN_ERR_XR_POWER_RATIO__VERIFY(src) \
49039 (!((((u_int32_t)(src)\
49052 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__READ(src) \
49053 (((u_int32_t)(src)\
49055 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__WRITE(src) \
49056 (((u_int32_t)(src)\
49058 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__MODIFY(dst, src) \
49060 ~0x00100000U) | (((u_int32_t)(src) <<\
49062 #define FRAME_CONTROL__EN_ERR_OFDM_XCORR__VERIFY(src) \
49063 (!((((u_int32_t)(src)\
49076 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__READ(src) \
49077 (((u_int32_t)(src)\
49079 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__WRITE(src) \
49080 (((u_int32_t)(src)\
49082 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__MODIFY(dst, src) \
49084 ~0x00200000U) | (((u_int32_t)(src) <<\
49086 #define FRAME_CONTROL__EN_ERR_LONG_SC_THR__VERIFY(src) \
49087 (!((((u_int32_t)(src)\
49100 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__READ(src) \
49101 (((u_int32_t)(src)\
49103 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__WRITE(src) \
49104 (((u_int32_t)(src)\
49106 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__MODIFY(dst, src) \
49108 ~0x00400000U) | (((u_int32_t)(src) <<\
49110 #define FRAME_CONTROL__EN_ERR_TIM_LONG1__VERIFY(src) \
49111 (!((((u_int32_t)(src)\
49124 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__READ(src) \
49125 (((u_int32_t)(src)\
49127 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__WRITE(src) \
49128 (((u_int32_t)(src)\
49130 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__MODIFY(dst, src) \
49132 ~0x00800000U) | (((u_int32_t)(src) <<\
49134 #define FRAME_CONTROL__EN_ERR_TIM_EARLY_TRIG__VERIFY(src) \
49135 (!((((u_int32_t)(src)\
49148 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__READ(src) \
49149 (((u_int32_t)(src)\
49151 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__WRITE(src) \
49152 (((u_int32_t)(src)\
49154 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__MODIFY(dst, src) \
49156 ~0x01000000U) | (((u_int32_t)(src) <<\
49158 #define FRAME_CONTROL__EN_ERR_TIM_TIMEOUT__VERIFY(src) \
49159 (!((((u_int32_t)(src)\
49172 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__READ(src) \
49173 (((u_int32_t)(src)\
49175 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__WRITE(src) \
49176 (((u_int32_t)(src)\
49178 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__MODIFY(dst, src) \
49180 ~0x02000000U) | (((u_int32_t)(src) <<\
49182 #define FRAME_CONTROL__EN_ERR_SIGNAL_PARITY__VERIFY(src) \
49183 (!((((u_int32_t)(src)\
49196 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__READ(src) \
49197 (((u_int32_t)(src)\
49199 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__WRITE(src) \
49200 (((u_int32_t)(src)\
49202 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__MODIFY(dst, src) \
49204 ~0x04000000U) | (((u_int32_t)(src) <<\
49206 #define FRAME_CONTROL__EN_ERR_RATE_ILLEGAL__VERIFY(src) \
49207 (!((((u_int32_t)(src)\
49220 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__READ(src) \
49221 (((u_int32_t)(src)\
49223 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__WRITE(src) \
49224 (((u_int32_t)(src)\
49226 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__MODIFY(dst, src) \
49228 ~0x08000000U) | (((u_int32_t)(src) <<\
49230 #define FRAME_CONTROL__EN_ERR_LENGTH_ILLEGAL__VERIFY(src) \
49231 (!((((u_int32_t)(src)\
49244 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__READ(src) \
49245 (((u_int32_t)(src)\
49247 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__WRITE(src) \
49248 (((u_int32_t)(src)\
49250 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__MODIFY(dst, src) \
49252 ~0x10000000U) | (((u_int32_t)(src) <<\
49254 #define FRAME_CONTROL__NO_6MBPS_SERVICE_ERR__VERIFY(src) \
49255 (!((((u_int32_t)(src)\
49268 #define FRAME_CONTROL__EN_ERR_SERVICE__READ(src) \
49269 (((u_int32_t)(src)\
49271 #define FRAME_CONTROL__EN_ERR_SERVICE__WRITE(src) \
49272 (((u_int32_t)(src)\
49274 #define FRAME_CONTROL__EN_ERR_SERVICE__MODIFY(dst, src) \
49276 ~0x20000000U) | (((u_int32_t)(src) <<\
49278 #define FRAME_CONTROL__EN_ERR_SERVICE__VERIFY(src) \
49279 (!((((u_int32_t)(src)\
49292 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__READ(src) \
49293 (((u_int32_t)(src)\
49295 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__WRITE(src) \
49296 (((u_int32_t)(src)\
49298 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__MODIFY(dst, src) \
49300 ~0x40000000U) | (((u_int32_t)(src) <<\
49302 #define FRAME_CONTROL__EN_ERR_TX_UNDERRUN__VERIFY(src) \
49303 (!((((u_int32_t)(src)\
49316 #define FRAME_CONTROL__EN_ERR_RX_ABORT__READ(src) \
49317 (((u_int32_t)(src)\
49319 #define FRAME_CONTROL__EN_ERR_RX_ABORT__WRITE(src) \
49320 (((u_int32_t)(src)\
49322 #define FRAME_CONTROL__EN_ERR_RX_ABORT__MODIFY(dst, src) \
49324 ~0x80000000U) | (((u_int32_t)(src) <<\
49326 #define FRAME_CONTROL__EN_ERR_RX_ABORT__VERIFY(src) \
49327 (!((((u_int32_t)(src)\
49353 #define RFBUS_REQUEST__RFBUS_REQUEST__READ(src) (u_int32_t)(src) & 0x00000001U
49354 #define RFBUS_REQUEST__RFBUS_REQUEST__WRITE(src) \
49355 ((u_int32_t)(src)\
49357 #define RFBUS_REQUEST__RFBUS_REQUEST__MODIFY(dst, src) \
49359 ~0x00000001U) | ((u_int32_t)(src) &\
49361 #define RFBUS_REQUEST__RFBUS_REQUEST__VERIFY(src) \
49362 (!(((u_int32_t)(src)\
49388 #define RFBUS_GRANT__RFBUS_GRANT__READ(src) (u_int32_t)(src) & 0x00000001U
49400 #define RFBUS_GRANT__BT_ANT__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
49424 #define RIFS__DISABLE_FCC_FIX__READ(src) \
49425 (((u_int32_t)(src)\
49427 #define RIFS__DISABLE_FCC_FIX__WRITE(src) \
49428 (((u_int32_t)(src)\
49430 #define RIFS__DISABLE_FCC_FIX__MODIFY(dst, src) \
49432 ~0x02000000U) | (((u_int32_t)(src) <<\
49434 #define RIFS__DISABLE_FCC_FIX__VERIFY(src) \
49435 (!((((u_int32_t)(src)\
49448 #define RIFS__ENABLE_RESET_TDOMAIN__READ(src) \
49449 (((u_int32_t)(src)\
49451 #define RIFS__ENABLE_RESET_TDOMAIN__WRITE(src) \
49452 (((u_int32_t)(src)\
49454 #define RIFS__ENABLE_RESET_TDOMAIN__MODIFY(dst, src) \
49456 ~0x04000000U) | (((u_int32_t)(src) <<\
49458 #define RIFS__ENABLE_RESET_TDOMAIN__VERIFY(src) \
49459 (!((((u_int32_t)(src)\
49472 #define RIFS__DISABLE_FCC_FIX2__READ(src) \
49473 (((u_int32_t)(src)\
49475 #define RIFS__DISABLE_FCC_FIX2__WRITE(src) \
49476 (((u_int32_t)(src)\
49478 #define RIFS__DISABLE_FCC_FIX2__MODIFY(dst, src) \
49480 ~0x08000000U) | (((u_int32_t)(src) <<\
49482 #define RIFS__DISABLE_FCC_FIX2__VERIFY(src) \
49483 (!((((u_int32_t)(src)\
49496 #define RIFS__DISABLE_RIFS_CCK_FIX__READ(src) \
49497 (((u_int32_t)(src)\
49499 #define RIFS__DISABLE_RIFS_CCK_FIX__WRITE(src) \
49500 (((u_int32_t)(src)\
49502 #define RIFS__DISABLE_RIFS_CCK_FIX__MODIFY(dst, src) \
49504 ~0x10000000U) | (((u_int32_t)(src) <<\
49506 #define RIFS__DISABLE_RIFS_CCK_FIX__VERIFY(src) \
49507 (!((((u_int32_t)(src)\
49520 #define RIFS__DISABLE_ERROR_RESET_FIX__READ(src) \
49521 (((u_int32_t)(src)\
49523 #define RIFS__DISABLE_ERROR_RESET_FIX__WRITE(src) \
49524 (((u_int32_t)(src)\
49526 #define RIFS__DISABLE_ERROR_RESET_FIX__MODIFY(dst, src) \
49528 ~0x20000000U) | (((u_int32_t)(src) <<\
49530 #define RIFS__DISABLE_ERROR_RESET_FIX__VERIFY(src) \
49531 (!((((u_int32_t)(src)\
49544 #define RIFS__RADAR_USE_FDOMAIN_RESET__READ(src) \
49545 (((u_int32_t)(src)\
49547 #define RIFS__RADAR_USE_FDOMAIN_RESET__WRITE(src) \
49548 (((u_int32_t)(src)\
49550 #define RIFS__RADAR_USE_FDOMAIN_RESET__MODIFY(dst, src) \
49552 ~0x40000000U) | (((u_int32_t)(src) <<\
49554 #define RIFS__RADAR_USE_FDOMAIN_RESET__VERIFY(src) \
49555 (!((((u_int32_t)(src)\
49581 #define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__READ(src) \
49582 (u_int32_t)(src)\
49584 #define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__WRITE(src) \
49585 ((u_int32_t)(src)\
49587 #define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__MODIFY(dst, src) \
49589 ~0x000003ffU) | ((u_int32_t)(src) &\
49591 #define RX_CLEAR_DELAY__OFDM_XR_RX_CLEAR_DELAY__VERIFY(src) \
49592 (!(((u_int32_t)(src)\
49612 #define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__READ(src) \
49613 (u_int32_t)(src)\
49615 #define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__WRITE(src) \
49616 ((u_int32_t)(src)\
49618 #define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__MODIFY(dst, src) \
49620 ~0x00003fffU) | ((u_int32_t)(src) &\
49622 #define ANALOG_POWER_ON_TIME__ACTIVE_TO_RECEIVE__VERIFY(src) \
49623 (!(((u_int32_t)(src)\
49643 #define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__READ(src) \
49644 (u_int32_t)(src)\
49646 #define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__WRITE(src) \
49647 ((u_int32_t)(src)\
49649 #define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__MODIFY(dst, src) \
49651 ~0x000000ffU) | ((u_int32_t)(src) &\
49653 #define TX_TIMING_1__TX_FRAME_TO_ADC_OFF__VERIFY(src) \
49654 (!(((u_int32_t)(src)\
49661 #define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__READ(src) \
49662 (((u_int32_t)(src)\
49664 #define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__WRITE(src) \
49665 (((u_int32_t)(src)\
49667 #define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__MODIFY(dst, src) \
49669 ~0x0000ff00U) | (((u_int32_t)(src) <<\
49671 #define TX_TIMING_1__TX_FRAME_TO_A2_RX_OFF__VERIFY(src) \
49672 (!((((u_int32_t)(src)\
49679 #define TX_TIMING_1__TX_FRAME_TO_DAC_ON__READ(src) \
49680 (((u_int32_t)(src)\
49682 #define TX_TIMING_1__TX_FRAME_TO_DAC_ON__WRITE(src) \
49683 (((u_int32_t)(src)\
49685 #define TX_TIMING_1__TX_FRAME_TO_DAC_ON__MODIFY(dst, src) \
49687 ~0x00ff0000U) | (((u_int32_t)(src) <<\
49689 #define TX_TIMING_1__TX_FRAME_TO_DAC_ON__VERIFY(src) \
49690 (!((((u_int32_t)(src)\
49697 #define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__READ(src) \
49698 (((u_int32_t)(src)\
49700 #define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__WRITE(src) \
49701 (((u_int32_t)(src)\
49703 #define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__MODIFY(dst, src) \
49705 ~0xff000000U) | (((u_int32_t)(src) <<\
49707 #define TX_TIMING_1__TX_FRAME_TO_A2_TX_ON__VERIFY(src) \
49708 (!((((u_int32_t)(src)\
49728 #define TX_TIMING_2__TX_FRAME_TO_TX_D_START__READ(src) \
49729 (u_int32_t)(src)\
49731 #define TX_TIMING_2__TX_FRAME_TO_TX_D_START__WRITE(src) \
49732 ((u_int32_t)(src)\
49734 #define TX_TIMING_2__TX_FRAME_TO_TX_D_START__MODIFY(dst, src) \
49736 ~0x000000ffU) | ((u_int32_t)(src) &\
49738 #define TX_TIMING_2__TX_FRAME_TO_TX_D_START__VERIFY(src) \
49739 (!(((u_int32_t)(src)\
49746 #define TX_TIMING_2__TX_FRAME_TO_PA_ON__READ(src) \
49747 (((u_int32_t)(src)\
49749 #define TX_TIMING_2__TX_FRAME_TO_PA_ON__WRITE(src) \
49750 (((u_int32_t)(src)\
49752 #define TX_TIMING_2__TX_FRAME_TO_PA_ON__MODIFY(dst, src) \
49754 ~0x0000ff00U) | (((u_int32_t)(src) <<\
49756 #define TX_TIMING_2__TX_FRAME_TO_PA_ON__VERIFY(src) \
49757 (!((((u_int32_t)(src)\
49764 #define TX_TIMING_2__TX_END_TO_PA_OFF__READ(src) \
49765 (((u_int32_t)(src)\
49767 #define TX_TIMING_2__TX_END_TO_PA_OFF__WRITE(src) \
49768 (((u_int32_t)(src)\
49770 #define TX_TIMING_2__TX_END_TO_PA_OFF__MODIFY(dst, src) \
49772 ~0x00ff0000U) | (((u_int32_t)(src) <<\
49774 #define TX_TIMING_2__TX_END_TO_PA_OFF__VERIFY(src) \
49775 (!((((u_int32_t)(src)\
49782 #define TX_TIMING_2__TX_END_TO_A2_TX_OFF__READ(src) \
49783 (((u_int32_t)(src)\
49785 #define TX_TIMING_2__TX_END_TO_A2_TX_OFF__WRITE(src) \
49786 (((u_int32_t)(src)\
49788 #define TX_TIMING_2__TX_END_TO_A2_TX_OFF__MODIFY(dst, src) \
49790 ~0xff000000U) | (((u_int32_t)(src) <<\
49792 #define TX_TIMING_2__TX_END_TO_A2_TX_OFF__VERIFY(src) \
49793 (!((((u_int32_t)(src)\
49813 #define TX_TIMING_3__TX_END_TO_DAC_OFF__READ(src) \
49814 (u_int32_t)(src)\
49816 #define TX_TIMING_3__TX_END_TO_DAC_OFF__WRITE(src) \
49817 ((u_int32_t)(src)\
49819 #define TX_TIMING_3__TX_END_TO_DAC_OFF__MODIFY(dst, src) \
49821 ~0x000000ffU) | ((u_int32_t)(src) &\
49823 #define TX_TIMING_3__TX_END_TO_DAC_OFF__VERIFY(src) \
49824 (!(((u_int32_t)(src)\
49831 #define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__READ(src) \
49832 (((u_int32_t)(src)\
49834 #define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__WRITE(src) \
49835 (((u_int32_t)(src)\
49837 #define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__MODIFY(dst, src) \
49839 ~0x0000ff00U) | (((u_int32_t)(src) <<\
49841 #define TX_TIMING_3__TX_FRAME_TO_THERM_CHAIN_ON__VERIFY(src) \
49842 (!((((u_int32_t)(src)\
49849 #define TX_TIMING_3__TX_END_TO_A2_RX_ON__READ(src) \
49850 (((u_int32_t)(src)\
49852 #define TX_TIMING_3__TX_END_TO_A2_RX_ON__WRITE(src) \
49853 (((u_int32_t)(src)\
49855 #define TX_TIMING_3__TX_END_TO_A2_RX_ON__MODIFY(dst, src) \
49857 ~0x00ff0000U) | (((u_int32_t)(src) <<\
49859 #define TX_TIMING_3__TX_END_TO_A2_RX_ON__VERIFY(src) \
49860 (!((((u_int32_t)(src)\
49867 #define TX_TIMING_3__TX_END_TO_ADC_ON__READ(src) \
49868 (((u_int32_t)(src)\
49870 #define TX_TIMING_3__TX_END_TO_ADC_ON__WRITE(src) \
49871 (((u_int32_t)(src)\
49873 #define TX_TIMING_3__TX_END_TO_ADC_ON__MODIFY(dst, src) \
49875 ~0xff000000U) | (((u_int32_t)(src) <<\
49877 #define TX_TIMING_3__TX_END_TO_ADC_ON__VERIFY(src) \
49878 (!((((u_int32_t)(src)\
49898 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__READ(src) \
49899 (u_int32_t)(src)\
49901 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__WRITE(src) \
49902 ((u_int32_t)(src)\
49904 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__MODIFY(dst, src) \
49906 ~0x000000ffU) | ((u_int32_t)(src) &\
49908 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAA_ON__VERIFY(src) \
49909 (!(((u_int32_t)(src)\
49916 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__READ(src) \
49917 (((u_int32_t)(src)\
49919 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__WRITE(src) \
49920 (((u_int32_t)(src)\
49922 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__MODIFY(dst, src) \
49924 ~0x0000ff00U) | (((u_int32_t)(src) <<\
49926 #define XPA_TIMING_CONTROL__TX_FRAME_TO_XPAB_ON__VERIFY(src) \
49927 (!((((u_int32_t)(src)\
49934 #define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__READ(src) \
49935 (((u_int32_t)(src)\
49937 #define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__WRITE(src) \
49938 (((u_int32_t)(src)\
49940 #define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__MODIFY(dst, src) \
49942 ~0x00ff0000U) | (((u_int32_t)(src) <<\
49944 #define XPA_TIMING_CONTROL__TX_END_TO_XPAA_OFF__VERIFY(src) \
49945 (!((((u_int32_t)(src)\
49952 #define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__READ(src) \
49953 (((u_int32_t)(src)\
49955 #define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__WRITE(src) \
49956 (((u_int32_t)(src)\
49958 #define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__MODIFY(dst, src) \
49960 ~0xff000000U) | (((u_int32_t)(src) <<\
49962 #define XPA_TIMING_CONTROL__TX_END_TO_XPAB_OFF__VERIFY(src) \
49963 (!((((u_int32_t)(src)\
49983 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__READ(src) \
49984 (u_int32_t)(src)\
49986 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__WRITE(src) \
49987 ((u_int32_t)(src)\
49989 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__MODIFY(dst, src) \
49991 ~0x00000001U) | ((u_int32_t)(src) &\
49993 #define MISC_PA_CONTROL__XPAA_ACTIVE_HIGH__VERIFY(src) \
49994 (!(((u_int32_t)(src)\
50007 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__READ(src) \
50008 (((u_int32_t)(src)\
50010 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__WRITE(src) \
50011 (((u_int32_t)(src)\
50013 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__MODIFY(dst, src) \
50015 ~0x00000002U) | (((u_int32_t)(src) <<\
50017 #define MISC_PA_CONTROL__XPAB_ACTIVE_HIGH__VERIFY(src) \
50018 (!((((u_int32_t)(src)\
50031 #define MISC_PA_CONTROL__ENABLE_XPAA__READ(src) \
50032 (((u_int32_t)(src)\
50034 #define MISC_PA_CONTROL__ENABLE_XPAA__WRITE(src) \
50035 (((u_int32_t)(src)\
50037 #define MISC_PA_CONTROL__ENABLE_XPAA__MODIFY(dst, src) \
50039 ~0x00000004U) | (((u_int32_t)(src) <<\
50041 #define MISC_PA_CONTROL__ENABLE_XPAA__VERIFY(src) \
50042 (!((((u_int32_t)(src)\
50055 #define MISC_PA_CONTROL__ENABLE_XPAB__READ(src) \
50056 (((u_int32_t)(src)\
50058 #define MISC_PA_CONTROL__ENABLE_XPAB__WRITE(src) \
50059 (((u_int32_t)(src)\
50061 #define MISC_PA_CONTROL__ENABLE_XPAB__MODIFY(dst, src) \
50063 ~0x00000008U) | (((u_int32_t)(src) <<\
50065 #define MISC_PA_CONTROL__ENABLE_XPAB__VERIFY(src) \
50066 (!((((u_int32_t)(src)\
50092 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__READ(src) \
50093 (u_int32_t)(src)\
50095 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__WRITE(src) \
50096 ((u_int32_t)(src)\
50098 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__MODIFY(dst, src) \
50100 ~0x00000003U) | ((u_int32_t)(src) &\
50102 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_IDLE_0__VERIFY(src) \
50103 (!(((u_int32_t)(src)\
50110 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__READ(src) \
50111 (((u_int32_t)(src)\
50113 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__WRITE(src) \
50114 (((u_int32_t)(src)\
50116 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__MODIFY(dst, src) \
50118 ~0x0000000cU) | (((u_int32_t)(src) <<\
50120 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_T_0__VERIFY(src) \
50121 (!((((u_int32_t)(src)\
50128 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__READ(src) \
50129 (((u_int32_t)(src)\
50131 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__WRITE(src) \
50132 (((u_int32_t)(src)\
50134 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__MODIFY(dst, src) \
50136 ~0x00000030U) | (((u_int32_t)(src) <<\
50138 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_R_0__VERIFY(src) \
50139 (!((((u_int32_t)(src)\
50146 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__READ(src) \
50147 (((u_int32_t)(src)\
50149 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__WRITE(src) \
50150 (((u_int32_t)(src)\
50152 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__MODIFY(dst, src) \
50154 ~0x000000c0U) | (((u_int32_t)(src) <<\
50156 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX1_0__VERIFY(src) \
50157 (!((((u_int32_t)(src)\
50164 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__READ(src) \
50165 (((u_int32_t)(src)\
50167 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__WRITE(src) \
50168 (((u_int32_t)(src)\
50170 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__MODIFY(dst, src) \
50172 ~0x00000300U) | (((u_int32_t)(src) <<\
50174 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_RX12_0__VERIFY(src) \
50175 (!((((u_int32_t)(src)\
50182 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__READ(src) \
50183 (((u_int32_t)(src)\
50185 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__WRITE(src) \
50186 (((u_int32_t)(src)\
50188 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__MODIFY(dst, src) \
50190 ~0x00000c00U) | (((u_int32_t)(src) <<\
50192 #define SWITCH_TABLE_CHN_B0__SWITCH_TABLE_B_0__VERIFY(src) \
50193 (!((((u_int32_t)(src)\
50213 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__READ(src) \
50214 (u_int32_t)(src)\
50216 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__WRITE(src) \
50217 ((u_int32_t)(src)\
50219 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__MODIFY(dst, src) \
50221 ~0x0000000fU) | ((u_int32_t)(src) &\
50223 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE__VERIFY(src) \
50224 (!(((u_int32_t)(src)\
50231 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__READ(src) \
50232 (((u_int32_t)(src)\
50234 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__WRITE(src) \
50235 (((u_int32_t)(src)\
50237 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__MODIFY(dst, src) \
50239 ~0x000000f0U) | (((u_int32_t)(src) <<\
50241 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T1__VERIFY(src) \
50242 (!((((u_int32_t)(src)\
50249 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__READ(src) \
50250 (((u_int32_t)(src)\
50252 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__WRITE(src) \
50253 (((u_int32_t)(src)\
50255 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__MODIFY(dst, src) \
50257 ~0x00000f00U) | (((u_int32_t)(src) <<\
50259 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_T2__VERIFY(src) \
50260 (!((((u_int32_t)(src)\
50267 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__READ(src) \
50268 (((u_int32_t)(src)\
50270 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__WRITE(src) \
50271 (((u_int32_t)(src)\
50273 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__MODIFY(dst, src) \
50275 ~0x0000f000U) | (((u_int32_t)(src) <<\
50277 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_B__VERIFY(src) \
50278 (!((((u_int32_t)(src)\
50285 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__READ(src) \
50286 (((u_int32_t)(src)\
50288 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__WRITE(src) \
50289 (((u_int32_t)(src)\
50291 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__MODIFY(dst, src) \
50293 ~0x000f0000U) | (((u_int32_t)(src) <<\
50295 #define SWITCH_TABLE_COM1__SWITCH_TABLE_COM_IDLE_ALT__VERIFY(src) \
50296 (!((((u_int32_t)(src)\
50316 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__READ(src) \
50317 (u_int32_t)(src)\
50319 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__WRITE(src) \
50320 ((u_int32_t)(src)\
50322 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__MODIFY(dst, src) \
50324 ~0x0000000fU) | ((u_int32_t)(src) &\
50326 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L1__VERIFY(src) \
50327 (!(((u_int32_t)(src)\
50334 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__READ(src) \
50335 (((u_int32_t)(src)\
50337 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__WRITE(src) \
50338 (((u_int32_t)(src)\
50340 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__MODIFY(dst, src) \
50342 ~0x000000f0U) | (((u_int32_t)(src) <<\
50344 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L1__VERIFY(src) \
50345 (!((((u_int32_t)(src)\
50352 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__READ(src) \
50353 (((u_int32_t)(src)\
50355 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__WRITE(src) \
50356 (((u_int32_t)(src)\
50358 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__MODIFY(dst, src) \
50360 ~0x00000f00U) | (((u_int32_t)(src) <<\
50362 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA1L2__VERIFY(src) \
50363 (!((((u_int32_t)(src)\
50370 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__READ(src) \
50371 (((u_int32_t)(src)\
50373 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__WRITE(src) \
50374 (((u_int32_t)(src)\
50376 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__MODIFY(dst, src) \
50378 ~0x0000f000U) | (((u_int32_t)(src) <<\
50380 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA2L2__VERIFY(src) \
50381 (!((((u_int32_t)(src)\
50388 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__READ(src) \
50389 (((u_int32_t)(src)\
50391 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__WRITE(src) \
50392 (((u_int32_t)(src)\
50394 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__MODIFY(dst, src) \
50396 ~0x000f0000U) | (((u_int32_t)(src) <<\
50398 #define SWITCH_TABLE_COM2__SWITCH_TABLE_COM_RA12__VERIFY(src) \
50399 (!((((u_int32_t)(src)\
50419 #define MULTICHAIN_ENABLE__RX_CHAIN_MASK__READ(src) \
50420 (u_int32_t)(src)\
50422 #define MULTICHAIN_ENABLE__RX_CHAIN_MASK__WRITE(src) \
50423 ((u_int32_t)(src)\
50425 #define MULTICHAIN_ENABLE__RX_CHAIN_MASK__MODIFY(dst, src) \
50427 ~0x00000007U) | ((u_int32_t)(src) &\
50429 #define MULTICHAIN_ENABLE__RX_CHAIN_MASK__VERIFY(src) \
50430 (!(((u_int32_t)(src)\
50450 #define CAL_CHAIN_MASK__CAL_CHAIN_MASK__READ(src) \
50451 (u_int32_t)(src)\
50453 #define CAL_CHAIN_MASK__CAL_CHAIN_MASK__WRITE(src) \
50454 ((u_int32_t)(src)\
50456 #define CAL_CHAIN_MASK__CAL_CHAIN_MASK__MODIFY(dst, src) \
50458 ~0x00000007U) | ((u_int32_t)(src) &\
50460 #define CAL_CHAIN_MASK__CAL_CHAIN_MASK__VERIFY(src) \
50461 (!(((u_int32_t)(src)\
50481 #define AGC_CONTROL__DO_CALIBRATE__READ(src) (u_int32_t)(src) & 0x00000001U
50482 #define AGC_CONTROL__DO_CALIBRATE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
50483 #define AGC_CONTROL__DO_CALIBRATE__MODIFY(dst, src) \
50485 ~0x00000001U) | ((u_int32_t)(src) &\
50487 #define AGC_CONTROL__DO_CALIBRATE__VERIFY(src) \
50488 (!(((u_int32_t)(src)\
50501 #define AGC_CONTROL__DO_NOISEFLOOR__READ(src) \
50502 (((u_int32_t)(src)\
50504 #define AGC_CONTROL__DO_NOISEFLOOR__WRITE(src) \
50505 (((u_int32_t)(src)\
50507 #define AGC_CONTROL__DO_NOISEFLOOR__MODIFY(dst, src) \
50509 ~0x00000002U) | (((u_int32_t)(src) <<\
50511 #define AGC_CONTROL__DO_NOISEFLOOR__VERIFY(src) \
50512 (!((((u_int32_t)(src)\
50525 #define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__READ(src) \
50526 (((u_int32_t)(src)\
50528 #define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__WRITE(src) \
50529 (((u_int32_t)(src)\
50531 #define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__MODIFY(dst, src) \
50533 ~0x00000038U) | (((u_int32_t)(src) <<\
50535 #define AGC_CONTROL__MIN_NUM_GAIN_CHANGE__VERIFY(src) \
50536 (!((((u_int32_t)(src)\
50543 #define AGC_CONTROL__YCOK_MAX__READ(src) \
50544 (((u_int32_t)(src)\
50546 #define AGC_CONTROL__YCOK_MAX__WRITE(src) \
50547 (((u_int32_t)(src)\
50549 #define AGC_CONTROL__YCOK_MAX__MODIFY(dst, src) \
50551 ~0x000003c0U) | (((u_int32_t)(src) <<\
50553 #define AGC_CONTROL__YCOK_MAX__VERIFY(src) \
50554 (!((((u_int32_t)(src)\
50561 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__READ(src) \
50562 (((u_int32_t)(src)\
50564 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__WRITE(src) \
50565 (((u_int32_t)(src)\
50567 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__MODIFY(dst, src) \
50569 ~0x00000400U) | (((u_int32_t)(src) <<\
50571 #define AGC_CONTROL__LEAKY_BUCKET_ENABLE__VERIFY(src) \
50572 (!((((u_int32_t)(src)\
50585 #define AGC_CONTROL__CAL_ENABLE__READ(src) \
50586 (((u_int32_t)(src)\
50588 #define AGC_CONTROL__CAL_ENABLE__WRITE(src) \
50589 (((u_int32_t)(src)\
50591 #define AGC_CONTROL__CAL_ENABLE__MODIFY(dst, src) \
50593 ~0x00000800U) | (((u_int32_t)(src) <<\
50595 #define AGC_CONTROL__CAL_ENABLE__VERIFY(src) \
50596 (!((((u_int32_t)(src)\
50609 #define AGC_CONTROL__USE_TABLE_SEED__READ(src) \
50610 (((u_int32_t)(src)\
50612 #define AGC_CONTROL__USE_TABLE_SEED__WRITE(src) \
50613 (((u_int32_t)(src)\
50615 #define AGC_CONTROL__USE_TABLE_SEED__MODIFY(dst, src) \
50617 ~0x00001000U) | (((u_int32_t)(src) <<\
50619 #define AGC_CONTROL__USE_TABLE_SEED__VERIFY(src) \
50620 (!((((u_int32_t)(src)\
50633 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__READ(src) \
50634 (((u_int32_t)(src)\
50636 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__WRITE(src) \
50637 (((u_int32_t)(src)\
50639 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__MODIFY(dst, src) \
50641 ~0x00002000U) | (((u_int32_t)(src) <<\
50643 #define AGC_CONTROL__AGC_UPDATE_TABLE_SEED__VERIFY(src) \
50644 (!((((u_int32_t)(src)\
50657 #define AGC_CONTROL__ENABLE_NOISEFLOOR__READ(src) \
50658 (((u_int32_t)(src)\
50660 #define AGC_CONTROL__ENABLE_NOISEFLOOR__WRITE(src) \
50661 (((u_int32_t)(src)\
50663 #define AGC_CONTROL__ENABLE_NOISEFLOOR__MODIFY(dst, src) \
50665 ~0x00008000U) | (((u_int32_t)(src) <<\
50667 #define AGC_CONTROL__ENABLE_NOISEFLOOR__VERIFY(src) \
50668 (!((((u_int32_t)(src)\
50681 #define AGC_CONTROL__ENABLE_FLTR_CAL__READ(src) \
50682 (((u_int32_t)(src)\
50684 #define AGC_CONTROL__ENABLE_FLTR_CAL__WRITE(src) \
50685 (((u_int32_t)(src)\
50687 #define AGC_CONTROL__ENABLE_FLTR_CAL__MODIFY(dst, src) \
50689 ~0x00010000U) | (((u_int32_t)(src) <<\
50691 #define AGC_CONTROL__ENABLE_FLTR_CAL__VERIFY(src) \
50692 (!((((u_int32_t)(src)\
50705 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__READ(src) \
50706 (((u_int32_t)(src)\
50708 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__WRITE(src) \
50709 (((u_int32_t)(src)\
50711 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__MODIFY(dst, src) \
50713 ~0x00020000U) | (((u_int32_t)(src) <<\
50715 #define AGC_CONTROL__NO_UPDATE_NOISEFLOOR__VERIFY(src) \
50716 (!((((u_int32_t)(src)\
50729 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__READ(src) \
50730 (((u_int32_t)(src)\
50732 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__WRITE(src) \
50733 (((u_int32_t)(src)\
50735 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__MODIFY(dst, src) \
50737 ~0x00040000U) | (((u_int32_t)(src) <<\
50739 #define AGC_CONTROL__EXTEND_NF_PWR_MEAS__VERIFY(src) \
50740 (!((((u_int32_t)(src)\
50753 #define AGC_CONTROL__CLC_SUCCESS__READ(src) \
50754 (((u_int32_t)(src)\
50767 #define AGC_CONTROL__ENABLE_PKDET_CAL__READ(src) \
50768 (((u_int32_t)(src)\
50770 #define AGC_CONTROL__ENABLE_PKDET_CAL__WRITE(src) \
50771 (((u_int32_t)(src)\
50773 #define AGC_CONTROL__ENABLE_PKDET_CAL__MODIFY(dst, src) \
50775 ~0x00100000U) | (((u_int32_t)(src) <<\
50777 #define AGC_CONTROL__ENABLE_PKDET_CAL__VERIFY(src) \
50778 (!((((u_int32_t)(src)\
50804 #define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__READ(src) \
50805 (u_int32_t)(src)\
50807 #define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__WRITE(src) \
50808 ((u_int32_t)(src)\
50810 #define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__MODIFY(dst, src) \
50812 ~0x00000003U) | ((u_int32_t)(src) &\
50814 #define IQ_ADC_CAL_MODE__GAIN_DC_IQ_CAL_MODE__VERIFY(src) \
50815 (!(((u_int32_t)(src)\
50822 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__READ(src) \
50823 (((u_int32_t)(src)\
50825 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__WRITE(src) \
50826 (((u_int32_t)(src)\
50828 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__MODIFY(dst, src) \
50830 ~0x00000004U) | (((u_int32_t)(src) <<\
50832 #define IQ_ADC_CAL_MODE__TEST_CALADCOFF__VERIFY(src) \
50833 (!((((u_int32_t)(src)\
50859 #define FCAL_1__FLC_PB_FSTEP__READ(src) (u_int32_t)(src) & 0x000003ffU
50860 #define FCAL_1__FLC_PB_FSTEP__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
50861 #define FCAL_1__FLC_PB_FSTEP__MODIFY(dst, src) \
50863 ~0x000003ffU) | ((u_int32_t)(src) &\
50865 #define FCAL_1__FLC_PB_FSTEP__VERIFY(src) \
50866 (!(((u_int32_t)(src)\
50873 #define FCAL_1__FLC_SB_FSTEP__READ(src) \
50874 (((u_int32_t)(src)\
50876 #define FCAL_1__FLC_SB_FSTEP__WRITE(src) \
50877 (((u_int32_t)(src)\
50879 #define FCAL_1__FLC_SB_FSTEP__MODIFY(dst, src) \
50881 ~0x000ffc00U) | (((u_int32_t)(src) <<\
50883 #define FCAL_1__FLC_SB_FSTEP__VERIFY(src) \
50884 (!((((u_int32_t)(src)\
50891 #define FCAL_1__FLC_PB_ATTEN__READ(src) \
50892 (((u_int32_t)(src)\
50894 #define FCAL_1__FLC_PB_ATTEN__WRITE(src) \
50895 (((u_int32_t)(src)\
50897 #define FCAL_1__FLC_PB_ATTEN__MODIFY(dst, src) \
50899 ~0x01f00000U) | (((u_int32_t)(src) <<\
50901 #define FCAL_1__FLC_PB_ATTEN__VERIFY(src) \
50902 (!((((u_int32_t)(src)\
50909 #define FCAL_1__FLC_SB_ATTEN__READ(src) \
50910 (((u_int32_t)(src)\
50912 #define FCAL_1__FLC_SB_ATTEN__WRITE(src) \
50913 (((u_int32_t)(src)\
50915 #define FCAL_1__FLC_SB_ATTEN__MODIFY(dst, src) \
50917 ~0x3e000000U) | (((u_int32_t)(src) <<\
50919 #define FCAL_1__FLC_SB_ATTEN__VERIFY(src) \
50920 (!((((u_int32_t)(src)\
50940 #define FCAL_2_B0__FLC_PWR_THRESH__READ(src) (u_int32_t)(src) & 0x00000007U
50941 #define FCAL_2_B0__FLC_PWR_THRESH__WRITE(src) ((u_int32_t)(src) & 0x00000007U)
50942 #define FCAL_2_B0__FLC_PWR_THRESH__MODIFY(dst, src) \
50944 ~0x00000007U) | ((u_int32_t)(src) &\
50946 #define FCAL_2_B0__FLC_PWR_THRESH__VERIFY(src) \
50947 (!(((u_int32_t)(src)\
50954 #define FCAL_2_B0__FLC_SW_CAP_VAL_0__READ(src) \
50955 (((u_int32_t)(src)\
50957 #define FCAL_2_B0__FLC_SW_CAP_VAL_0__WRITE(src) \
50958 (((u_int32_t)(src)\
50960 #define FCAL_2_B0__FLC_SW_CAP_VAL_0__MODIFY(dst, src) \
50962 ~0x000000f8U) | (((u_int32_t)(src) <<\
50964 #define FCAL_2_B0__FLC_SW_CAP_VAL_0__VERIFY(src) \
50965 (!((((u_int32_t)(src)\
50972 #define FCAL_2_B0__FLC_BBMISCGAIN__READ(src) \
50973 (((u_int32_t)(src)\
50975 #define FCAL_2_B0__FLC_BBMISCGAIN__WRITE(src) \
50976 (((u_int32_t)(src)\
50978 #define FCAL_2_B0__FLC_BBMISCGAIN__MODIFY(dst, src) \
50980 ~0x00000300U) | (((u_int32_t)(src) <<\
50982 #define FCAL_2_B0__FLC_BBMISCGAIN__VERIFY(src) \
50983 (!((((u_int32_t)(src)\
50990 #define FCAL_2_B0__FLC_BB1DBGAIN__READ(src) \
50991 (((u_int32_t)(src)\
50993 #define FCAL_2_B0__FLC_BB1DBGAIN__WRITE(src) \
50994 (((u_int32_t)(src)\
50996 #define FCAL_2_B0__FLC_BB1DBGAIN__MODIFY(dst, src) \
50998 ~0x00001c00U) | (((u_int32_t)(src) <<\
51000 #define FCAL_2_B0__FLC_BB1DBGAIN__VERIFY(src) \
51001 (!((((u_int32_t)(src)\
51008 #define FCAL_2_B0__FLC_BB6DBGAIN__READ(src) \
51009 (((u_int32_t)(src)\
51011 #define FCAL_2_B0__FLC_BB6DBGAIN__WRITE(src) \
51012 (((u_int32_t)(src)\
51014 #define FCAL_2_B0__FLC_BB6DBGAIN__MODIFY(dst, src) \
51016 ~0x00006000U) | (((u_int32_t)(src) <<\
51018 #define FCAL_2_B0__FLC_BB6DBGAIN__VERIFY(src) \
51019 (!((((u_int32_t)(src)\
51026 #define FCAL_2_B0__FLC_SW_CAP_SET__READ(src) \
51027 (((u_int32_t)(src)\
51029 #define FCAL_2_B0__FLC_SW_CAP_SET__WRITE(src) \
51030 (((u_int32_t)(src)\
51032 #define FCAL_2_B0__FLC_SW_CAP_SET__MODIFY(dst, src) \
51034 ~0x00008000U) | (((u_int32_t)(src) <<\
51036 #define FCAL_2_B0__FLC_SW_CAP_SET__VERIFY(src) \
51037 (!((((u_int32_t)(src)\
51050 #define FCAL_2_B0__FLC_MEAS_WIN__READ(src) \
51051 (((u_int32_t)(src)\
51053 #define FCAL_2_B0__FLC_MEAS_WIN__WRITE(src) \
51054 (((u_int32_t)(src)\
51056 #define FCAL_2_B0__FLC_MEAS_WIN__MODIFY(dst, src) \
51058 ~0x00070000U) | (((u_int32_t)(src) <<\
51060 #define FCAL_2_B0__FLC_MEAS_WIN__VERIFY(src) \
51061 (!((((u_int32_t)(src)\
51068 #define FCAL_2_B0__FLC_CAP_VAL_STATUS_0__READ(src) \
51069 (((u_int32_t)(src)\
51089 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__READ(src) \
51090 (u_int32_t)(src)\
51092 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__WRITE(src) \
51093 ((u_int32_t)(src)\
51095 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__MODIFY(dst, src) \
51097 ~0x00000001U) | ((u_int32_t)(src) &\
51099 #define DFT_TONE_CTRL_B0__DFT_TONE_EN_0__VERIFY(src) \
51100 (!(((u_int32_t)(src)\
51113 #define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__READ(src) \
51114 (((u_int32_t)(src)\
51116 #define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__WRITE(src) \
51117 (((u_int32_t)(src)\
51119 #define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__MODIFY(dst, src) \
51121 ~0x0000000cU) | (((u_int32_t)(src) <<\
51123 #define DFT_TONE_CTRL_B0__DFT_TONE_AMP_SEL_0__VERIFY(src) \
51124 (!((((u_int32_t)(src)\
51131 #define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__READ(src) \
51132 (((u_int32_t)(src)\
51134 #define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__WRITE(src) \
51135 (((u_int32_t)(src)\
51137 #define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__MODIFY(dst, src) \
51139 ~0x00001ff0U) | (((u_int32_t)(src) <<\
51141 #define DFT_TONE_CTRL_B0__DFT_TONE_FREQ_ANG_0__VERIFY(src) \
51142 (!((((u_int32_t)(src)\
51162 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__READ(src) \
51163 (u_int32_t)(src)\
51165 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__WRITE(src) \
51166 ((u_int32_t)(src)\
51168 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__MODIFY(dst, src) \
51170 ~0x00000001U) | ((u_int32_t)(src) &\
51172 #define CL_CAL_CTRL__ENABLE_PARALLEL_CAL__VERIFY(src) \
51173 (!(((u_int32_t)(src)\
51186 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__READ(src) \
51187 (((u_int32_t)(src)\
51189 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__WRITE(src) \
51190 (((u_int32_t)(src)\
51192 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__MODIFY(dst, src) \
51194 ~0x00000002U) | (((u_int32_t)(src) <<\
51196 #define CL_CAL_CTRL__ENABLE_CL_CALIBRATE__VERIFY(src) \
51197 (!((((u_int32_t)(src)\
51210 #define CL_CAL_CTRL__CF_CLC_TEST_POINT__READ(src) \
51211 (((u_int32_t)(src)\
51213 #define CL_CAL_CTRL__CF_CLC_TEST_POINT__WRITE(src) \
51214 (((u_int32_t)(src)\
51216 #define CL_CAL_CTRL__CF_CLC_TEST_POINT__MODIFY(dst, src) \
51218 ~0x0000000cU) | (((u_int32_t)(src) <<\
51220 #define CL_CAL_CTRL__CF_CLC_TEST_POINT__VERIFY(src) \
51221 (!((((u_int32_t)(src)\
51228 #define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__READ(src) \
51229 (((u_int32_t)(src)\
51231 #define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__WRITE(src) \
51232 (((u_int32_t)(src)\
51234 #define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__MODIFY(dst, src) \
51236 ~0x000000f0U) | (((u_int32_t)(src) <<\
51238 #define CL_CAL_CTRL__CF_CLC_FORCED_PAGAIN__VERIFY(src) \
51239 (!((((u_int32_t)(src)\
51246 #define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__READ(src) \
51247 (((u_int32_t)(src)\
51249 #define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__WRITE(src) \
51250 (((u_int32_t)(src)\
51252 #define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__MODIFY(dst, src) \
51254 ~0x0000ff00U) | (((u_int32_t)(src) <<\
51256 #define CL_CAL_CTRL__CARR_LEAK_MAX_OFFSET__VERIFY(src) \
51257 (!((((u_int32_t)(src)\
51264 #define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__READ(src) \
51265 (((u_int32_t)(src)\
51267 #define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__WRITE(src) \
51268 (((u_int32_t)(src)\
51270 #define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__MODIFY(dst, src) \
51272 ~0x003f0000U) | (((u_int32_t)(src) <<\
51274 #define CL_CAL_CTRL__CF_CLC_INIT_BBGAIN__VERIFY(src) \
51275 (!((((u_int32_t)(src)\
51282 #define CL_CAL_CTRL__CF_ADC_BOUND__READ(src) \
51283 (((u_int32_t)(src)\
51285 #define CL_CAL_CTRL__CF_ADC_BOUND__WRITE(src) \
51286 (((u_int32_t)(src)\
51288 #define CL_CAL_CTRL__CF_ADC_BOUND__MODIFY(dst, src) \
51290 ~0x3fc00000U) | (((u_int32_t)(src) <<\
51292 #define CL_CAL_CTRL__CF_ADC_BOUND__VERIFY(src) \
51293 (!((((u_int32_t)(src)\
51300 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__READ(src) \
51301 (((u_int32_t)(src)\
51303 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__WRITE(src) \
51304 (((u_int32_t)(src)\
51306 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__MODIFY(dst, src) \
51308 ~0x40000000U) | (((u_int32_t)(src) <<\
51310 #define CL_CAL_CTRL__USE_DAC_CL_CORRECTION__VERIFY(src) \
51311 (!((((u_int32_t)(src)\
51324 #define CL_CAL_CTRL__CL_MAP_HW_GEN__READ(src) \
51325 (((u_int32_t)(src)\
51327 #define CL_CAL_CTRL__CL_MAP_HW_GEN__WRITE(src) \
51328 (((u_int32_t)(src)\
51330 #define CL_CAL_CTRL__CL_MAP_HW_GEN__MODIFY(dst, src) \
51332 ~0x80000000U) | (((u_int32_t)(src) <<\
51334 #define CL_CAL_CTRL__CL_MAP_HW_GEN__VERIFY(src) \
51335 (!((((u_int32_t)(src)\
51361 #define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU
51362 #define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
51363 #define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
51365 ~0xffffffffU) | ((u_int32_t)(src) &\
51367 #define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
51386 #define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU
51387 #define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
51388 #define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
51390 ~0xffffffffU) | ((u_int32_t)(src) &\
51392 #define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
51411 #define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU
51412 #define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
51413 #define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
51415 ~0xffffffffU) | ((u_int32_t)(src) &\
51417 #define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
51436 #define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU
51437 #define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
51438 #define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
51440 ~0xffffffffU) | ((u_int32_t)(src) &\
51442 #define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
51461 #define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU
51462 #define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
51463 #define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
51465 ~0xffffffffU) | ((u_int32_t)(src) &\
51467 #define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \
51468 (!(((u_int32_t)(src)\
51488 #define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU
51489 #define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
51490 #define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
51492 ~0xffffffffU) | ((u_int32_t)(src) &\
51494 #define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \
51495 (!(((u_int32_t)(src)\
51515 #define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU
51516 #define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
51517 #define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
51519 ~0xffffffffU) | ((u_int32_t)(src) &\
51521 #define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \
51522 (!(((u_int32_t)(src)\
51542 #define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU
51543 #define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
51544 #define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
51546 ~0xffffffffU) | ((u_int32_t)(src) &\
51548 #define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \
51549 (!(((u_int32_t)(src)\
51569 #define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU
51570 #define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU)
51571 #define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
51573 ~0x0000001fU) | ((u_int32_t)(src) &\
51575 #define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))
51581 #define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \
51582 (((u_int32_t)(src)\
51584 #define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \
51585 (((u_int32_t)(src)\
51587 #define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
51589 ~0x0000ffe0U) | (((u_int32_t)(src) <<\
51591 #define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \
51592 (!((((u_int32_t)(src)\
51599 #define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \
51600 (((u_int32_t)(src)\
51602 #define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \
51603 (((u_int32_t)(src)\
51605 #define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
51607 ~0x07ff0000U) | (((u_int32_t)(src) <<\
51609 #define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \
51610 (!((((u_int32_t)(src)\
51617 #define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27)
51618 #define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U)
51619 #define CL_TAB__BB_GAIN__MODIFY(dst, src) \
51621 ~0x78000000U) | (((u_int32_t)(src) <<\
51623 #define CL_TAB__BB_GAIN__VERIFY(src) \
51624 (!((((u_int32_t)(src)\
51644 #define SYNTH_CONTROL__RFCHANFRAC__READ(src) (u_int32_t)(src) & 0x0001ffffU
51645 #define SYNTH_CONTROL__RFCHANFRAC__WRITE(src) ((u_int32_t)(src) & 0x0001ffffU)
51646 #define SYNTH_CONTROL__RFCHANFRAC__MODIFY(dst, src) \
51648 ~0x0001ffffU) | ((u_int32_t)(src) &\
51650 #define SYNTH_CONTROL__RFCHANFRAC__VERIFY(src) \
51651 (!(((u_int32_t)(src)\
51658 #define SYNTH_CONTROL__RFCHANNEL__READ(src) \
51659 (((u_int32_t)(src)\
51661 #define SYNTH_CONTROL__RFCHANNEL__WRITE(src) \
51662 (((u_int32_t)(src)\
51664 #define SYNTH_CONTROL__RFCHANNEL__MODIFY(dst, src) \
51666 ~0x03fe0000U) | (((u_int32_t)(src) <<\
51668 #define SYNTH_CONTROL__RFCHANNEL__VERIFY(src) \
51669 (!((((u_int32_t)(src)\
51676 #define SYNTH_CONTROL__RFAMODEREFSEL__READ(src) \
51677 (((u_int32_t)(src)\
51679 #define SYNTH_CONTROL__RFAMODEREFSEL__WRITE(src) \
51680 (((u_int32_t)(src)\
51682 #define SYNTH_CONTROL__RFAMODEREFSEL__MODIFY(dst, src) \
51684 ~0x0c000000U) | (((u_int32_t)(src) <<\
51686 #define SYNTH_CONTROL__RFAMODEREFSEL__VERIFY(src) \
51687 (!((((u_int32_t)(src)\
51694 #define SYNTH_CONTROL__RFFRACMODE__READ(src) \
51695 (((u_int32_t)(src)\
51697 #define SYNTH_CONTROL__RFFRACMODE__WRITE(src) \
51698 (((u_int32_t)(src)\
51700 #define SYNTH_CONTROL__RFFRACMODE__MODIFY(dst, src) \
51702 ~0x10000000U) | (((u_int32_t)(src) <<\
51704 #define SYNTH_CONTROL__RFFRACMODE__VERIFY(src) \
51705 (!((((u_int32_t)(src)\
51718 #define SYNTH_CONTROL__RFBMODE__READ(src) \
51719 (((u_int32_t)(src)\
51721 #define SYNTH_CONTROL__RFBMODE__WRITE(src) \
51722 (((u_int32_t)(src)\
51724 #define SYNTH_CONTROL__RFBMODE__MODIFY(dst, src) \
51726 ~0x20000000U) | (((u_int32_t)(src) <<\
51728 #define SYNTH_CONTROL__RFBMODE__VERIFY(src) \
51729 (!((((u_int32_t)(src)\
51742 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__READ(src) \
51743 (((u_int32_t)(src)\
51745 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__WRITE(src) \
51746 (((u_int32_t)(src)\
51748 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__MODIFY(dst, src) \
51750 ~0x40000000U) | (((u_int32_t)(src) <<\
51752 #define SYNTH_CONTROL__RFSYNTH_CTRL_SSHIFT__VERIFY(src) \
51753 (!((((u_int32_t)(src)\
51779 #define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__READ(src) \
51780 (((u_int32_t)(src)\
51782 #define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__WRITE(src) \
51783 (((u_int32_t)(src)\
51785 #define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__MODIFY(dst, src) \
51787 ~0x0000000eU) | (((u_int32_t)(src) <<\
51789 #define ADDAC_CLK_SELECT__BB_DAC_CLK_SELECT__VERIFY(src) \
51790 (!((((u_int32_t)(src)\
51797 #define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__READ(src) \
51798 (((u_int32_t)(src)\
51800 #define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__WRITE(src) \
51801 (((u_int32_t)(src)\
51803 #define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__MODIFY(dst, src) \
51805 ~0x000000f0U) | (((u_int32_t)(src) <<\
51807 #define ADDAC_CLK_SELECT__BB_ADC_CLK_SELECT__VERIFY(src) \
51808 (!((((u_int32_t)(src)\
51828 #define PLL_CNTL__BB_PLL_DIV__READ(src) (u_int32_t)(src) & 0x000003ffU
51829 #define PLL_CNTL__BB_PLL_DIV__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
51830 #define PLL_CNTL__BB_PLL_DIV__MODIFY(dst, src) \
51832 ~0x000003ffU) | ((u_int32_t)(src) &\
51834 #define PLL_CNTL__BB_PLL_DIV__VERIFY(src) \
51835 (!(((u_int32_t)(src)\
51842 #define PLL_CNTL__BB_PLL_REFDIV__READ(src) \
51843 (((u_int32_t)(src)\
51845 #define PLL_CNTL__BB_PLL_REFDIV__WRITE(src) \
51846 (((u_int32_t)(src)\
51848 #define PLL_CNTL__BB_PLL_REFDIV__MODIFY(dst, src) \
51850 ~0x00003c00U) | (((u_int32_t)(src) <<\
51852 #define PLL_CNTL__BB_PLL_REFDIV__VERIFY(src) \
51853 (!((((u_int32_t)(src)\
51860 #define PLL_CNTL__BB_PLL_CLK_SEL__READ(src) \
51861 (((u_int32_t)(src)\
51863 #define PLL_CNTL__BB_PLL_CLK_SEL__WRITE(src) \
51864 (((u_int32_t)(src)\
51866 #define PLL_CNTL__BB_PLL_CLK_SEL__MODIFY(dst, src) \
51868 ~0x0000c000U) | (((u_int32_t)(src) <<\
51870 #define PLL_CNTL__BB_PLL_CLK_SEL__VERIFY(src) \
51871 (!((((u_int32_t)(src)\
51878 #define PLL_CNTL__BB_PLLBYPASS__READ(src) \
51879 (((u_int32_t)(src)\
51881 #define PLL_CNTL__BB_PLLBYPASS__WRITE(src) \
51882 (((u_int32_t)(src)\
51884 #define PLL_CNTL__BB_PLLBYPASS__MODIFY(dst, src) \
51886 ~0x00010000U) | (((u_int32_t)(src) <<\
51888 #define PLL_CNTL__BB_PLLBYPASS__VERIFY(src) \
51889 (!((((u_int32_t)(src)\
51902 #define PLL_CNTL__BB_PLL_SETTLE_TIME__READ(src) \
51903 (((u_int32_t)(src)\
51905 #define PLL_CNTL__BB_PLL_SETTLE_TIME__WRITE(src) \
51906 (((u_int32_t)(src)\
51908 #define PLL_CNTL__BB_PLL_SETTLE_TIME__MODIFY(dst, src) \
51910 ~0x0ffe0000U) | (((u_int32_t)(src) <<\
51912 #define PLL_CNTL__BB_PLL_SETTLE_TIME__VERIFY(src) \
51913 (!((((u_int32_t)(src)\
51933 #define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__READ(src) \
51934 (u_int32_t)(src)\
51936 #define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__WRITE(src) \
51937 ((u_int32_t)(src)\
51939 #define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__MODIFY(dst, src) \
51941 ~0x00000007U) | ((u_int32_t)(src) &\
51943 #define ANALOG_SWAP__ANALOG_RX_SWAP_CNTL__VERIFY(src) \
51944 (!(((u_int32_t)(src)\
51951 #define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__READ(src) \
51952 (((u_int32_t)(src)\
51954 #define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__WRITE(src) \
51955 (((u_int32_t)(src)\
51957 #define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__MODIFY(dst, src) \
51959 ~0x00000038U) | (((u_int32_t)(src) <<\
51961 #define ANALOG_SWAP__ANALOG_TX_SWAP_CNTL__VERIFY(src) \
51962 (!((((u_int32_t)(src)\
51969 #define ANALOG_SWAP__SWAP_ALT_CHN__READ(src) \
51970 (((u_int32_t)(src)\
51972 #define ANALOG_SWAP__SWAP_ALT_CHN__WRITE(src) \
51973 (((u_int32_t)(src)\
51975 #define ANALOG_SWAP__SWAP_ALT_CHN__MODIFY(dst, src) \
51977 ~0x00000040U) | (((u_int32_t)(src) <<\
51979 #define ANALOG_SWAP__SWAP_ALT_CHN__VERIFY(src) \
51980 (!((((u_int32_t)(src)\
51993 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__READ(src) \
51994 (((u_int32_t)(src)\
51996 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__WRITE(src) \
51997 (((u_int32_t)(src)\
51999 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__MODIFY(dst, src) \
52001 ~0x00000080U) | (((u_int32_t)(src) <<\
52003 #define ANALOG_SWAP__ANALOG_DC_DAC_POLARITY__VERIFY(src) \
52004 (!((((u_int32_t)(src)\
52017 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__READ(src) \
52018 (((u_int32_t)(src)\
52020 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__WRITE(src) \
52021 (((u_int32_t)(src)\
52023 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__MODIFY(dst, src) \
52025 ~0x00000100U) | (((u_int32_t)(src) <<\
52027 #define ANALOG_SWAP__ANALOG_PKDET_DAC_POLARITY__VERIFY(src) \
52028 (!((((u_int32_t)(src)\
52054 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__READ(src) \
52055 (((u_int32_t)(src)\
52057 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__WRITE(src) \
52058 (((u_int32_t)(src)\
52060 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__MODIFY(dst, src) \
52062 ~0x00001000U) | (((u_int32_t)(src) <<\
52064 #define ADDAC_PARALLEL_CONTROL__OFF_DACLPMODE__VERIFY(src) \
52065 (!((((u_int32_t)(src)\
52078 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__READ(src) \
52079 (((u_int32_t)(src)\
52081 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__WRITE(src) \
52082 (((u_int32_t)(src)\
52084 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__MODIFY(dst, src) \
52086 ~0x00002000U) | (((u_int32_t)(src) <<\
52088 #define ADDAC_PARALLEL_CONTROL__OFF_PWDDAC__VERIFY(src) \
52089 (!((((u_int32_t)(src)\
52102 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__READ(src) \
52103 (((u_int32_t)(src)\
52105 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__WRITE(src) \
52106 (((u_int32_t)(src)\
52108 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__MODIFY(dst, src) \
52110 ~0x00008000U) | (((u_int32_t)(src) <<\
52112 #define ADDAC_PARALLEL_CONTROL__OFF_PWDADC__VERIFY(src) \
52113 (!((((u_int32_t)(src)\
52126 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__READ(src) \
52127 (((u_int32_t)(src)\
52129 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__WRITE(src) \
52130 (((u_int32_t)(src)\
52132 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__MODIFY(dst, src) \
52134 ~0x10000000U) | (((u_int32_t)(src) <<\
52136 #define ADDAC_PARALLEL_CONTROL__ON_DACLPMODE__VERIFY(src) \
52137 (!((((u_int32_t)(src)\
52150 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__READ(src) \
52151 (((u_int32_t)(src)\
52153 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__WRITE(src) \
52154 (((u_int32_t)(src)\
52156 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__MODIFY(dst, src) \
52158 ~0x20000000U) | (((u_int32_t)(src) <<\
52160 #define ADDAC_PARALLEL_CONTROL__ON_PWDDAC__VERIFY(src) \
52161 (!((((u_int32_t)(src)\
52174 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__READ(src) \
52175 (((u_int32_t)(src)\
52177 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__WRITE(src) \
52178 (((u_int32_t)(src)\
52180 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__MODIFY(dst, src) \
52182 ~0x80000000U) | (((u_int32_t)(src) <<\
52184 #define ADDAC_PARALLEL_CONTROL__ON_PWDADC__VERIFY(src) \
52185 (!((((u_int32_t)(src)\
52211 #define FORCE_ANALOG__FORCE_XPAON__READ(src) (u_int32_t)(src) & 0x00000001U
52212 #define FORCE_ANALOG__FORCE_XPAON__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
52213 #define FORCE_ANALOG__FORCE_XPAON__MODIFY(dst, src) \
52215 ~0x00000001U) | ((u_int32_t)(src) &\
52217 #define FORCE_ANALOG__FORCE_XPAON__VERIFY(src) \
52218 (!(((u_int32_t)(src)\
52231 #define FORCE_ANALOG__FORCED_XPAON__READ(src) \
52232 (((u_int32_t)(src)\
52234 #define FORCE_ANALOG__FORCED_XPAON__WRITE(src) \
52235 (((u_int32_t)(src)\
52237 #define FORCE_ANALOG__FORCED_XPAON__MODIFY(dst, src) \
52239 ~0x0000000eU) | (((u_int32_t)(src) <<\
52241 #define FORCE_ANALOG__FORCED_XPAON__VERIFY(src) \
52242 (!((((u_int32_t)(src)\
52249 #define FORCE_ANALOG__FORCE_PDADC_PWD__READ(src) \
52250 (((u_int32_t)(src)\
52252 #define FORCE_ANALOG__FORCE_PDADC_PWD__WRITE(src) \
52253 (((u_int32_t)(src)\
52255 #define FORCE_ANALOG__FORCE_PDADC_PWD__MODIFY(dst, src) \
52257 ~0x00000010U) | (((u_int32_t)(src) <<\
52259 #define FORCE_ANALOG__FORCE_PDADC_PWD__VERIFY(src) \
52260 (!((((u_int32_t)(src)\
52273 #define FORCE_ANALOG__FORCED_PDADC_PWD__READ(src) \
52274 (((u_int32_t)(src)\
52276 #define FORCE_ANALOG__FORCED_PDADC_PWD__WRITE(src) \
52277 (((u_int32_t)(src)\
52279 #define FORCE_ANALOG__FORCED_PDADC_PWD__MODIFY(dst, src) \
52281 ~0x000000e0U) | (((u_int32_t)(src) <<\
52283 #define FORCE_ANALOG__FORCED_PDADC_PWD__VERIFY(src) \
52284 (!((((u_int32_t)(src)\
52304 #define TEST_CONTROLS__CF_TSTTRIG_SEL__READ(src) (u_int32_t)(src) & 0x0000000fU
52305 #define TEST_CONTROLS__CF_TSTTRIG_SEL__WRITE(src) \
52306 ((u_int32_t)(src)\
52308 #define TEST_CONTROLS__CF_TSTTRIG_SEL__MODIFY(dst, src) \
52310 ~0x0000000fU) | ((u_int32_t)(src) &\
52312 #define TEST_CONTROLS__CF_TSTTRIG_SEL__VERIFY(src) \
52313 (!(((u_int32_t)(src)\
52320 #define TEST_CONTROLS__CF_TSTTRIG__READ(src) \
52321 (((u_int32_t)(src)\
52323 #define TEST_CONTROLS__CF_TSTTRIG__WRITE(src) \
52324 (((u_int32_t)(src)\
52326 #define TEST_CONTROLS__CF_TSTTRIG__MODIFY(dst, src) \
52328 ~0x00000010U) | (((u_int32_t)(src) <<\
52330 #define TEST_CONTROLS__CF_TSTTRIG__VERIFY(src) \
52331 (!((((u_int32_t)(src)\
52344 #define TEST_CONTROLS__CF_RFSHIFT_SEL__READ(src) \
52345 (((u_int32_t)(src)\
52347 #define TEST_CONTROLS__CF_RFSHIFT_SEL__WRITE(src) \
52348 (((u_int32_t)(src)\
52350 #define TEST_CONTROLS__CF_RFSHIFT_SEL__MODIFY(dst, src) \
52352 ~0x00000060U) | (((u_int32_t)(src) <<\
52354 #define TEST_CONTROLS__CF_RFSHIFT_SEL__VERIFY(src) \
52355 (!((((u_int32_t)(src)\
52362 #define TEST_CONTROLS__CARDBUS_MODE__READ(src) \
52363 (((u_int32_t)(src)\
52365 #define TEST_CONTROLS__CARDBUS_MODE__WRITE(src) \
52366 (((u_int32_t)(src)\
52368 #define TEST_CONTROLS__CARDBUS_MODE__MODIFY(dst, src) \
52370 ~0x00000300U) | (((u_int32_t)(src) <<\
52372 #define TEST_CONTROLS__CARDBUS_MODE__VERIFY(src) \
52373 (!((((u_int32_t)(src)\
52380 #define TEST_CONTROLS__CLKOUT_IS_CLK32__READ(src) \
52381 (((u_int32_t)(src)\
52383 #define TEST_CONTROLS__CLKOUT_IS_CLK32__WRITE(src) \
52384 (((u_int32_t)(src)\
52386 #define TEST_CONTROLS__CLKOUT_IS_CLK32__MODIFY(dst, src) \
52388 ~0x00000400U) | (((u_int32_t)(src) <<\
52390 #define TEST_CONTROLS__CLKOUT_IS_CLK32__VERIFY(src) \
52391 (!((((u_int32_t)(src)\
52404 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__READ(src) \
52405 (((u_int32_t)(src)\
52407 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__WRITE(src) \
52408 (((u_int32_t)(src)\
52410 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__MODIFY(dst, src) \
52412 ~0x00002000U) | (((u_int32_t)(src) <<\
52414 #define TEST_CONTROLS__ENABLE_RFSILENT_BB__VERIFY(src) \
52415 (!((((u_int32_t)(src)\
52428 #define TEST_CONTROLS__ENABLE_MINI_OBS__READ(src) \
52429 (((u_int32_t)(src)\
52431 #define TEST_CONTROLS__ENABLE_MINI_OBS__WRITE(src) \
52432 (((u_int32_t)(src)\
52434 #define TEST_CONTROLS__ENABLE_MINI_OBS__MODIFY(dst, src) \
52436 ~0x00008000U) | (((u_int32_t)(src) <<\
52438 #define TEST_CONTROLS__ENABLE_MINI_OBS__VERIFY(src) \
52439 (!((((u_int32_t)(src)\
52452 #define TEST_CONTROLS__SLOW_CLK160__READ(src) \
52453 (((u_int32_t)(src)\
52455 #define TEST_CONTROLS__SLOW_CLK160__WRITE(src) \
52456 (((u_int32_t)(src)\
52458 #define TEST_CONTROLS__SLOW_CLK160__MODIFY(dst, src) \
52460 ~0x00020000U) | (((u_int32_t)(src) <<\
52462 #define TEST_CONTROLS__SLOW_CLK160__VERIFY(src) \
52463 (!((((u_int32_t)(src)\
52476 #define TEST_CONTROLS__AGC_OBS_SEL_3__READ(src) \
52477 (((u_int32_t)(src)\
52479 #define TEST_CONTROLS__AGC_OBS_SEL_3__WRITE(src) \
52480 (((u_int32_t)(src)\
52482 #define TEST_CONTROLS__AGC_OBS_SEL_3__MODIFY(dst, src) \
52484 ~0x00040000U) | (((u_int32_t)(src) <<\
52486 #define TEST_CONTROLS__AGC_OBS_SEL_3__VERIFY(src) \
52487 (!((((u_int32_t)(src)\
52500 #define TEST_CONTROLS__CF_BBB_OBS_SEL__READ(src) \
52501 (((u_int32_t)(src)\
52503 #define TEST_CONTROLS__CF_BBB_OBS_SEL__WRITE(src) \
52504 (((u_int32_t)(src)\
52506 #define TEST_CONTROLS__CF_BBB_OBS_SEL__MODIFY(dst, src) \
52508 ~0x00780000U) | (((u_int32_t)(src) <<\
52510 #define TEST_CONTROLS__CF_BBB_OBS_SEL__VERIFY(src) \
52511 (!((((u_int32_t)(src)\
52518 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__READ(src) \
52519 (((u_int32_t)(src)\
52521 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__WRITE(src) \
52522 (((u_int32_t)(src)\
52524 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__MODIFY(dst, src) \
52526 ~0x00800000U) | (((u_int32_t)(src) <<\
52528 #define TEST_CONTROLS__RX_OBS_SEL_5TH_BIT__VERIFY(src) \
52529 (!((((u_int32_t)(src)\
52542 #define TEST_CONTROLS__AGC_OBS_SEL_4__READ(src) \
52543 (((u_int32_t)(src)\
52545 #define TEST_CONTROLS__AGC_OBS_SEL_4__WRITE(src) \
52546 (((u_int32_t)(src)\
52548 #define TEST_CONTROLS__AGC_OBS_SEL_4__MODIFY(dst, src) \
52550 ~0x01000000U) | (((u_int32_t)(src) <<\
52552 #define TEST_CONTROLS__AGC_OBS_SEL_4__VERIFY(src) \
52553 (!((((u_int32_t)(src)\
52566 #define TEST_CONTROLS__FORCE_AGC_CLEAR__READ(src) \
52567 (((u_int32_t)(src)\
52569 #define TEST_CONTROLS__FORCE_AGC_CLEAR__WRITE(src) \
52570 (((u_int32_t)(src)\
52572 #define TEST_CONTROLS__FORCE_AGC_CLEAR__MODIFY(dst, src) \
52574 ~0x10000000U) | (((u_int32_t)(src) <<\
52576 #define TEST_CONTROLS__FORCE_AGC_CLEAR__VERIFY(src) \
52577 (!((((u_int32_t)(src)\
52590 #define TEST_CONTROLS__TSTDAC_OUT_SEL__READ(src) \
52591 (((u_int32_t)(src)\
52593 #define TEST_CONTROLS__TSTDAC_OUT_SEL__WRITE(src) \
52594 (((u_int32_t)(src)\
52596 #define TEST_CONTROLS__TSTDAC_OUT_SEL__MODIFY(dst, src) \
52598 ~0xc0000000U) | (((u_int32_t)(src) <<\
52600 #define TEST_CONTROLS__TSTDAC_OUT_SEL__VERIFY(src) \
52601 (!((((u_int32_t)(src)\
52621 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__READ(src) \
52622 (u_int32_t)(src)\
52624 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__WRITE(src) \
52625 ((u_int32_t)(src)\
52627 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__MODIFY(dst, src) \
52629 ~0x00000001U) | ((u_int32_t)(src) &\
52631 #define TEST_CONTROLS_STATUS__CF_TSTDAC_EN__VERIFY(src) \
52632 (!(((u_int32_t)(src)\
52645 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__READ(src) \
52646 (((u_int32_t)(src)\
52648 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__WRITE(src) \
52649 (((u_int32_t)(src)\
52651 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__MODIFY(dst, src) \
52653 ~0x00000002U) | (((u_int32_t)(src) <<\
52655 #define TEST_CONTROLS_STATUS__CF_TX_SRC_IS_TSTDAC__VERIFY(src) \
52656 (!((((u_int32_t)(src)\
52669 #define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__READ(src) \
52670 (((u_int32_t)(src)\
52672 #define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__WRITE(src) \
52673 (((u_int32_t)(src)\
52675 #define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__MODIFY(dst, src) \
52677 ~0x0000001cU) | (((u_int32_t)(src) <<\
52679 #define TEST_CONTROLS_STATUS__CF_TX_OBS_SEL__VERIFY(src) \
52680 (!((((u_int32_t)(src)\
52687 #define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__READ(src) \
52688 (((u_int32_t)(src)\
52690 #define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__WRITE(src) \
52691 (((u_int32_t)(src)\
52693 #define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__MODIFY(dst, src) \
52695 ~0x00000060U) | (((u_int32_t)(src) <<\
52697 #define TEST_CONTROLS_STATUS__CF_TX_OBS_MUX_SEL__VERIFY(src) \
52698 (!((((u_int32_t)(src)\
52705 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__READ(src) \
52706 (((u_int32_t)(src)\
52708 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__WRITE(src) \
52709 (((u_int32_t)(src)\
52711 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__MODIFY(dst, src) \
52713 ~0x00000080U) | (((u_int32_t)(src) <<\
52715 #define TEST_CONTROLS_STATUS__CF_TX_SRC_ALTERNATE__VERIFY(src) \
52716 (!((((u_int32_t)(src)\
52729 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__READ(src) \
52730 (((u_int32_t)(src)\
52732 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__WRITE(src) \
52733 (((u_int32_t)(src)\
52735 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__MODIFY(dst, src) \
52737 ~0x00000100U) | (((u_int32_t)(src) <<\
52739 #define TEST_CONTROLS_STATUS__CF_TSTADC_EN__VERIFY(src) \
52740 (!((((u_int32_t)(src)\
52753 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__READ(src) \
52754 (((u_int32_t)(src)\
52756 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__WRITE(src) \
52757 (((u_int32_t)(src)\
52759 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__MODIFY(dst, src) \
52761 ~0x00000200U) | (((u_int32_t)(src) <<\
52763 #define TEST_CONTROLS_STATUS__CF_RX_SRC_IS_TSTADC__VERIFY(src) \
52764 (!((((u_int32_t)(src)\
52777 #define TEST_CONTROLS_STATUS__RX_OBS_SEL__READ(src) \
52778 (((u_int32_t)(src)\
52780 #define TEST_CONTROLS_STATUS__RX_OBS_SEL__WRITE(src) \
52781 (((u_int32_t)(src)\
52783 #define TEST_CONTROLS_STATUS__RX_OBS_SEL__MODIFY(dst, src) \
52785 ~0x00003c00U) | (((u_int32_t)(src) <<\
52787 #define TEST_CONTROLS_STATUS__RX_OBS_SEL__VERIFY(src) \
52788 (!((((u_int32_t)(src)\
52795 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__READ(src) \
52796 (((u_int32_t)(src)\
52798 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__WRITE(src) \
52799 (((u_int32_t)(src)\
52801 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__MODIFY(dst, src) \
52803 ~0x00004000U) | (((u_int32_t)(src) <<\
52805 #define TEST_CONTROLS_STATUS__DISABLE_A2_WARM_RESET__VERIFY(src) \
52806 (!((((u_int32_t)(src)\
52819 #define TEST_CONTROLS_STATUS__RESET_A2__READ(src) \
52820 (((u_int32_t)(src)\
52822 #define TEST_CONTROLS_STATUS__RESET_A2__WRITE(src) \
52823 (((u_int32_t)(src)\
52825 #define TEST_CONTROLS_STATUS__RESET_A2__MODIFY(dst, src) \
52827 ~0x00008000U) | (((u_int32_t)(src) <<\
52829 #define TEST_CONTROLS_STATUS__RESET_A2__VERIFY(src) \
52830 (!((((u_int32_t)(src)\
52843 #define TEST_CONTROLS_STATUS__AGC_OBS_SEL__READ(src) \
52844 (((u_int32_t)(src)\
52846 #define TEST_CONTROLS_STATUS__AGC_OBS_SEL__WRITE(src) \
52847 (((u_int32_t)(src)\
52849 #define TEST_CONTROLS_STATUS__AGC_OBS_SEL__MODIFY(dst, src) \
52851 ~0x00070000U) | (((u_int32_t)(src) <<\
52853 #define TEST_CONTROLS_STATUS__AGC_OBS_SEL__VERIFY(src) \
52854 (!((((u_int32_t)(src)\
52861 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__READ(src) \
52862 (((u_int32_t)(src)\
52864 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__WRITE(src) \
52865 (((u_int32_t)(src)\
52867 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__MODIFY(dst, src) \
52869 ~0x00080000U) | (((u_int32_t)(src) <<\
52871 #define TEST_CONTROLS_STATUS__CF_ENABLE_FFT_DUMP__VERIFY(src) \
52872 (!((((u_int32_t)(src)\
52885 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__READ(src) \
52886 (((u_int32_t)(src)\
52888 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__WRITE(src) \
52889 (((u_int32_t)(src)\
52891 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__MODIFY(dst, src) \
52893 ~0x00800000U) | (((u_int32_t)(src) <<\
52895 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_IN__VERIFY(src) \
52896 (!((((u_int32_t)(src)\
52909 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__READ(src) \
52910 (((u_int32_t)(src)\
52912 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__WRITE(src) \
52913 (((u_int32_t)(src)\
52915 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__MODIFY(dst, src) \
52917 ~0x08000000U) | (((u_int32_t)(src) <<\
52919 #define TEST_CONTROLS_STATUS__DISABLE_AGC_TO_A2__VERIFY(src) \
52920 (!((((u_int32_t)(src)\
52933 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__READ(src) \
52934 (((u_int32_t)(src)\
52936 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__WRITE(src) \
52937 (((u_int32_t)(src)\
52939 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__MODIFY(dst, src) \
52941 ~0x10000000U) | (((u_int32_t)(src) <<\
52943 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_EN__VERIFY(src) \
52944 (!((((u_int32_t)(src)\
52957 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__READ(src) \
52958 (((u_int32_t)(src)\
52960 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__WRITE(src) \
52961 (((u_int32_t)(src)\
52963 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__MODIFY(dst, src) \
52965 ~0xe0000000U) | (((u_int32_t)(src) <<\
52967 #define TEST_CONTROLS_STATUS__CF_DEBUGPORT_SEL__VERIFY(src) \
52968 (!((((u_int32_t)(src)\
52988 #define TSTDAC__TSTDAC_OUT_Q__READ(src) (u_int32_t)(src) & 0x000003ffU
52994 #define TSTDAC__TSTDAC_OUT_I__READ(src) \
52995 (((u_int32_t)(src)\
53014 #define CHANNEL_STATUS__BT_ACTIVE__READ(src) (u_int32_t)(src) & 0x00000001U
53026 #define CHANNEL_STATUS__RX_CLEAR_RAW__READ(src) \
53027 (((u_int32_t)(src)\
53040 #define CHANNEL_STATUS__RX_CLEAR_MAC__READ(src) \
53041 (((u_int32_t)(src)\
53054 #define CHANNEL_STATUS__RX_CLEAR_PAD__READ(src) \
53055 (((u_int32_t)(src)\
53068 #define CHANNEL_STATUS__BB_SW_OUT_0__READ(src) \
53069 (((u_int32_t)(src)\
53076 #define CHANNEL_STATUS__BB_SW_OUT_1__READ(src) \
53077 (((u_int32_t)(src)\
53084 #define CHANNEL_STATUS__BB_SW_OUT_2__READ(src) \
53085 (((u_int32_t)(src)\
53092 #define CHANNEL_STATUS__BB_SW_COM_OUT__READ(src) \
53093 (((u_int32_t)(src)\
53100 #define CHANNEL_STATUS__ANT_DIV_CFG_USED__READ(src) \
53101 (((u_int32_t)(src)\
53120 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__READ(src) \
53121 (u_int32_t)(src)\
53123 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__WRITE(src) \
53124 ((u_int32_t)(src)\
53126 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__MODIFY(dst, src) \
53128 ~0x00000001U) | ((u_int32_t)(src) &\
53130 #define CHANINFO_CTRL__CAPTURE_CHAN_INFO__VERIFY(src) \
53131 (!(((u_int32_t)(src)\
53144 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__READ(src) \
53145 (((u_int32_t)(src)\
53147 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__WRITE(src) \
53148 (((u_int32_t)(src)\
53150 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__MODIFY(dst, src) \
53152 ~0x00000002U) | (((u_int32_t)(src) <<\
53154 #define CHANINFO_CTRL__DISABLE_CHANINFOMEM__VERIFY(src) \
53155 (!((((u_int32_t)(src)\
53168 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__READ(src) \
53169 (((u_int32_t)(src)\
53171 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__WRITE(src) \
53172 (((u_int32_t)(src)\
53174 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__MODIFY(dst, src) \
53176 ~0x00000004U) | (((u_int32_t)(src) <<\
53178 #define CHANINFO_CTRL__CAPTURE_SOUNDING_PACKET__VERIFY(src) \
53179 (!((((u_int32_t)(src)\
53192 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__READ(src) \
53193 (((u_int32_t)(src)\
53195 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__WRITE(src) \
53196 (((u_int32_t)(src)\
53198 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__MODIFY(dst, src) \
53200 ~0x00000008U) | (((u_int32_t)(src) <<\
53202 #define CHANINFO_CTRL__CHANINFOMEM_S2_READ__VERIFY(src) \
53203 (!((((u_int32_t)(src)\
53229 #define CHAN_INFO_NOISE_PWR__NOISE_POWER__READ(src) \
53230 (u_int32_t)(src)\
53249 #define CHAN_INFO_GAIN_DIFF__FINE_PPM__READ(src) (u_int32_t)(src) & 0x00000fffU
53255 #define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_01__READ(src) \
53256 (((u_int32_t)(src)\
53263 #define CHAN_INFO_GAIN_DIFF__ANALOG_GAIN_DIFF_02__READ(src) \
53264 (((u_int32_t)(src)\
53283 #define CHAN_INFO_FINE_TIMING__COARSE_PPM__READ(src) \
53284 (u_int32_t)(src)\
53291 #define CHAN_INFO_FINE_TIMING__FINE_TIMING__READ(src) \
53292 (((u_int32_t)(src)\
53311 #define CHAN_INFO_GAIN_B0__CHAN_INFO_RSSI_0__READ(src) \
53312 (u_int32_t)(src)\
53319 #define CHAN_INFO_GAIN_B0__CHAN_INFO_RF_GAIN_0__READ(src) \
53320 (((u_int32_t)(src)\
53327 #define CHAN_INFO_GAIN_B0__CHAN_INFO_MB_GAIN_0__READ(src) \
53328 (((u_int32_t)(src)\
53335 #define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN1_SW_0__READ(src) \
53336 (((u_int32_t)(src)\
53349 #define CHAN_INFO_GAIN_B0__CHAN_INFO_XATTEN2_SW_0__READ(src) \
53350 (((u_int32_t)(src)\
53375 #define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__READ(src) \
53376 (u_int32_t)(src)\
53378 #define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__WRITE(src) \
53379 ((u_int32_t)(src)\
53381 #define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__MODIFY(dst, src) \
53383 ~0x0000007fU) | ((u_int32_t)(src) &\
53385 #define SCRAMBLER_SEED__FIXED_SCRAMBLER_SEED__VERIFY(src) \
53386 (!(((u_int32_t)(src)\
53406 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__READ(src) \
53407 (u_int32_t)(src)\
53409 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__WRITE(src) \
53410 ((u_int32_t)(src)\
53412 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__MODIFY(dst, src) \
53414 ~0x00000001U) | ((u_int32_t)(src) &\
53416 #define BBB_TX_CTRL__DISABLE_SCRAMBLER__VERIFY(src) \
53417 (!(((u_int32_t)(src)\
53430 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__READ(src) \
53431 (((u_int32_t)(src)\
53433 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__WRITE(src) \
53434 (((u_int32_t)(src)\
53436 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__MODIFY(dst, src) \
53438 ~0x00000002U) | (((u_int32_t)(src) <<\
53440 #define BBB_TX_CTRL__USE_SCRAMBLER_SEED__VERIFY(src) \
53441 (!((((u_int32_t)(src)\
53454 #define BBB_TX_CTRL__TX_DAC_SCALE_CCK__READ(src) \
53455 (((u_int32_t)(src)\
53457 #define BBB_TX_CTRL__TX_DAC_SCALE_CCK__WRITE(src) \
53458 (((u_int32_t)(src)\
53460 #define BBB_TX_CTRL__TX_DAC_SCALE_CCK__MODIFY(dst, src) \
53462 ~0x0000000cU) | (((u_int32_t)(src) <<\
53464 #define BBB_TX_CTRL__TX_DAC_SCALE_CCK__VERIFY(src) \
53465 (!((((u_int32_t)(src)\
53472 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__READ(src) \
53473 (((u_int32_t)(src)\
53475 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__WRITE(src) \
53476 (((u_int32_t)(src)\
53478 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__MODIFY(dst, src) \
53480 ~0x00000010U) | (((u_int32_t)(src) <<\
53482 #define BBB_TX_CTRL__TXFIR_JAPAN_CCK__VERIFY(src) \
53483 (!((((u_int32_t)(src)\
53496 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__READ(src) \
53497 (((u_int32_t)(src)\
53499 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__WRITE(src) \
53500 (((u_int32_t)(src)\
53502 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__MODIFY(dst, src) \
53504 ~0x00000020U) | (((u_int32_t)(src) <<\
53506 #define BBB_TX_CTRL__ALLOW_1MBPS_SHORT__VERIFY(src) \
53507 (!((((u_int32_t)(src)\
53520 #define BBB_TX_CTRL__TX_CCK_DELAY_1__READ(src) \
53521 (((u_int32_t)(src)\
53523 #define BBB_TX_CTRL__TX_CCK_DELAY_1__WRITE(src) \
53524 (((u_int32_t)(src)\
53526 #define BBB_TX_CTRL__TX_CCK_DELAY_1__MODIFY(dst, src) \
53528 ~0x000001c0U) | (((u_int32_t)(src) <<\
53530 #define BBB_TX_CTRL__TX_CCK_DELAY_1__VERIFY(src) \
53531 (!((((u_int32_t)(src)\
53538 #define BBB_TX_CTRL__TX_CCK_DELAY_2__READ(src) \
53539 (((u_int32_t)(src)\
53541 #define BBB_TX_CTRL__TX_CCK_DELAY_2__WRITE(src) \
53542 (((u_int32_t)(src)\
53544 #define BBB_TX_CTRL__TX_CCK_DELAY_2__MODIFY(dst, src) \
53546 ~0x00000e00U) | (((u_int32_t)(src) <<\
53548 #define BBB_TX_CTRL__TX_CCK_DELAY_2__VERIFY(src) \
53549 (!((((u_int32_t)(src)\
53569 #define BBB_TXFIR_0__TXFIR_COEFF_H0__READ(src) (u_int32_t)(src) & 0x0000000fU
53570 #define BBB_TXFIR_0__TXFIR_COEFF_H0__WRITE(src) \
53571 ((u_int32_t)(src)\
53573 #define BBB_TXFIR_0__TXFIR_COEFF_H0__MODIFY(dst, src) \
53575 ~0x0000000fU) | ((u_int32_t)(src) &\
53577 #define BBB_TXFIR_0__TXFIR_COEFF_H0__VERIFY(src) \
53578 (!(((u_int32_t)(src)\
53585 #define BBB_TXFIR_0__TXFIR_COEFF_H1__READ(src) \
53586 (((u_int32_t)(src)\
53588 #define BBB_TXFIR_0__TXFIR_COEFF_H1__WRITE(src) \
53589 (((u_int32_t)(src)\
53591 #define BBB_TXFIR_0__TXFIR_COEFF_H1__MODIFY(dst, src) \
53593 ~0x00000f00U) | (((u_int32_t)(src) <<\
53595 #define BBB_TXFIR_0__TXFIR_COEFF_H1__VERIFY(src) \
53596 (!((((u_int32_t)(src)\
53603 #define BBB_TXFIR_0__TXFIR_COEFF_H2__READ(src) \
53604 (((u_int32_t)(src)\
53606 #define BBB_TXFIR_0__TXFIR_COEFF_H2__WRITE(src) \
53607 (((u_int32_t)(src)\
53609 #define BBB_TXFIR_0__TXFIR_COEFF_H2__MODIFY(dst, src) \
53611 ~0x001f0000U) | (((u_int32_t)(src) <<\
53613 #define BBB_TXFIR_0__TXFIR_COEFF_H2__VERIFY(src) \
53614 (!((((u_int32_t)(src)\
53621 #define BBB_TXFIR_0__TXFIR_COEFF_H3__READ(src) \
53622 (((u_int32_t)(src)\
53624 #define BBB_TXFIR_0__TXFIR_COEFF_H3__WRITE(src) \
53625 (((u_int32_t)(src)\
53627 #define BBB_TXFIR_0__TXFIR_COEFF_H3__MODIFY(dst, src) \
53629 ~0x1f000000U) | (((u_int32_t)(src) <<\
53631 #define BBB_TXFIR_0__TXFIR_COEFF_H3__VERIFY(src) \
53632 (!((((u_int32_t)(src)\
53652 #define BBB_TXFIR_1__TXFIR_COEFF_H4__READ(src) (u_int32_t)(src) & 0x0000003fU
53653 #define BBB_TXFIR_1__TXFIR_COEFF_H4__WRITE(src) \
53654 ((u_int32_t)(src)\
53656 #define BBB_TXFIR_1__TXFIR_COEFF_H4__MODIFY(dst, src) \
53658 ~0x0000003fU) | ((u_int32_t)(src) &\
53660 #define BBB_TXFIR_1__TXFIR_COEFF_H4__VERIFY(src) \
53661 (!(((u_int32_t)(src)\
53668 #define BBB_TXFIR_1__TXFIR_COEFF_H5__READ(src) \
53669 (((u_int32_t)(src)\
53671 #define BBB_TXFIR_1__TXFIR_COEFF_H5__WRITE(src) \
53672 (((u_int32_t)(src)\
53674 #define BBB_TXFIR_1__TXFIR_COEFF_H5__MODIFY(dst, src) \
53676 ~0x00003f00U) | (((u_int32_t)(src) <<\
53678 #define BBB_TXFIR_1__TXFIR_COEFF_H5__VERIFY(src) \
53679 (!((((u_int32_t)(src)\
53686 #define BBB_TXFIR_1__TXFIR_COEFF_H6__READ(src) \
53687 (((u_int32_t)(src)\
53689 #define BBB_TXFIR_1__TXFIR_COEFF_H6__WRITE(src) \
53690 (((u_int32_t)(src)\
53692 #define BBB_TXFIR_1__TXFIR_COEFF_H6__MODIFY(dst, src) \
53694 ~0x007f0000U) | (((u_int32_t)(src) <<\
53696 #define BBB_TXFIR_1__TXFIR_COEFF_H6__VERIFY(src) \
53697 (!((((u_int32_t)(src)\
53704 #define BBB_TXFIR_1__TXFIR_COEFF_H7__READ(src) \
53705 (((u_int32_t)(src)\
53707 #define BBB_TXFIR_1__TXFIR_COEFF_H7__WRITE(src) \
53708 (((u_int32_t)(src)\
53710 #define BBB_TXFIR_1__TXFIR_COEFF_H7__MODIFY(dst, src) \
53712 ~0x7f000000U) | (((u_int32_t)(src) <<\
53714 #define BBB_TXFIR_1__TXFIR_COEFF_H7__VERIFY(src) \
53715 (!((((u_int32_t)(src)\
53735 #define BBB_TXFIR_2__TXFIR_COEFF_H8__READ(src) (u_int32_t)(src) & 0x000000ffU
53736 #define BBB_TXFIR_2__TXFIR_COEFF_H8__WRITE(src) \
53737 ((u_int32_t)(src)\
53739 #define BBB_TXFIR_2__TXFIR_COEFF_H8__MODIFY(dst, src) \
53741 ~0x000000ffU) | ((u_int32_t)(src) &\
53743 #define BBB_TXFIR_2__TXFIR_COEFF_H8__VERIFY(src) \
53744 (!(((u_int32_t)(src)\
53751 #define BBB_TXFIR_2__TXFIR_COEFF_H9__READ(src) \
53752 (((u_int32_t)(src)\
53754 #define BBB_TXFIR_2__TXFIR_COEFF_H9__WRITE(src) \
53755 (((u_int32_t)(src)\
53757 #define BBB_TXFIR_2__TXFIR_COEFF_H9__MODIFY(dst, src) \
53759 ~0x0000ff00U) | (((u_int32_t)(src) <<\
53761 #define BBB_TXFIR_2__TXFIR_COEFF_H9__VERIFY(src) \
53762 (!((((u_int32_t)(src)\
53769 #define BBB_TXFIR_2__TXFIR_COEFF_H10__READ(src) \
53770 (((u_int32_t)(src)\
53772 #define BBB_TXFIR_2__TXFIR_COEFF_H10__WRITE(src) \
53773 (((u_int32_t)(src)\
53775 #define BBB_TXFIR_2__TXFIR_COEFF_H10__MODIFY(dst, src) \
53777 ~0x00ff0000U) | (((u_int32_t)(src) <<\
53779 #define BBB_TXFIR_2__TXFIR_COEFF_H10__VERIFY(src) \
53780 (!((((u_int32_t)(src)\
53787 #define BBB_TXFIR_2__TXFIR_COEFF_H11__READ(src) \
53788 (((u_int32_t)(src)\
53790 #define BBB_TXFIR_2__TXFIR_COEFF_H11__WRITE(src) \
53791 (((u_int32_t)(src)\
53793 #define BBB_TXFIR_2__TXFIR_COEFF_H11__MODIFY(dst, src) \
53795 ~0xff000000U) | (((u_int32_t)(src) <<\
53797 #define BBB_TXFIR_2__TXFIR_COEFF_H11__VERIFY(src) \
53798 (!((((u_int32_t)(src)\
53818 #define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__READ(src) \
53819 (u_int32_t)(src)\
53821 #define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__WRITE(src) \
53822 ((u_int32_t)(src)\
53824 #define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__MODIFY(dst, src) \
53826 ~0x000001ffU) | ((u_int32_t)(src) &\
53828 #define HEAVY_CLIP_CTRL__CF_HEAVY_CLIP_ENABLE__VERIFY(src) \
53829 (!(((u_int32_t)(src)\
53836 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__READ(src) \
53837 (((u_int32_t)(src)\
53839 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__WRITE(src) \
53840 (((u_int32_t)(src)\
53842 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__MODIFY(dst, src) \
53844 ~0x00000200U) | (((u_int32_t)(src) <<\
53846 #define HEAVY_CLIP_CTRL__PRE_EMP_HT40_ENABLE__VERIFY(src) \
53847 (!((((u_int32_t)(src)\
53860 #define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__READ(src) \
53861 (((u_int32_t)(src)\
53863 #define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__WRITE(src) \
53864 (((u_int32_t)(src)\
53866 #define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__MODIFY(dst, src) \
53868 ~0x0003fc00U) | (((u_int32_t)(src) <<\
53870 #define HEAVY_CLIP_CTRL__HEAVY_CLIP_FACTOR_XR__VERIFY(src) \
53871 (!((((u_int32_t)(src)\
53891 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__READ(src) \
53892 (u_int32_t)(src)\
53894 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__WRITE(src) \
53895 ((u_int32_t)(src)\
53897 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__MODIFY(dst, src) \
53899 ~0x000000ffU) | ((u_int32_t)(src) &\
53901 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_0__VERIFY(src) \
53902 (!(((u_int32_t)(src)\
53909 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__READ(src) \
53910 (((u_int32_t)(src)\
53912 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__WRITE(src) \
53913 (((u_int32_t)(src)\
53915 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__MODIFY(dst, src) \
53917 ~0x0000ff00U) | (((u_int32_t)(src) <<\
53919 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_1__VERIFY(src) \
53920 (!((((u_int32_t)(src)\
53927 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__READ(src) \
53928 (((u_int32_t)(src)\
53930 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__WRITE(src) \
53931 (((u_int32_t)(src)\
53933 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__MODIFY(dst, src) \
53935 ~0x00ff0000U) | (((u_int32_t)(src) <<\
53937 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_2__VERIFY(src) \
53938 (!((((u_int32_t)(src)\
53945 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__READ(src) \
53946 (((u_int32_t)(src)\
53948 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__WRITE(src) \
53949 (((u_int32_t)(src)\
53951 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__MODIFY(dst, src) \
53953 ~0xff000000U) | (((u_int32_t)(src) <<\
53955 #define HEAVY_CLIP_20__HEAVY_CLIP_FACTOR_3__VERIFY(src) \
53956 (!((((u_int32_t)(src)\
53976 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__READ(src) \
53977 (u_int32_t)(src)\
53979 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__WRITE(src) \
53980 ((u_int32_t)(src)\
53982 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__MODIFY(dst, src) \
53984 ~0x000000ffU) | ((u_int32_t)(src) &\
53986 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_4__VERIFY(src) \
53987 (!(((u_int32_t)(src)\
53994 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__READ(src) \
53995 (((u_int32_t)(src)\
53997 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__WRITE(src) \
53998 (((u_int32_t)(src)\
54000 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__MODIFY(dst, src) \
54002 ~0x0000ff00U) | (((u_int32_t)(src) <<\
54004 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_5__VERIFY(src) \
54005 (!((((u_int32_t)(src)\
54012 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__READ(src) \
54013 (((u_int32_t)(src)\
54015 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__WRITE(src) \
54016 (((u_int32_t)(src)\
54018 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__MODIFY(dst, src) \
54020 ~0x00ff0000U) | (((u_int32_t)(src) <<\
54022 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_6__VERIFY(src) \
54023 (!((((u_int32_t)(src)\
54030 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__READ(src) \
54031 (((u_int32_t)(src)\
54033 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__WRITE(src) \
54034 (((u_int32_t)(src)\
54036 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__MODIFY(dst, src) \
54038 ~0xff000000U) | (((u_int32_t)(src) <<\
54040 #define HEAVY_CLIP_40__HEAVY_CLIP_FACTOR_7__VERIFY(src) \
54041 (!((((u_int32_t)(src)\
54061 #define ILLEGAL_TX_RATE__ILLEGAL_TX_RATE__READ(src) \
54062 (u_int32_t)(src)\
54087 #define POWERTX_RATE1__POWERTX_0__READ(src) (u_int32_t)(src) & 0x0000003fU
54088 #define POWERTX_RATE1__POWERTX_0__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
54089 #define POWERTX_RATE1__POWERTX_0__MODIFY(dst, src) \
54091 ~0x0000003fU) | ((u_int32_t)(src) &\
54093 #define POWERTX_RATE1__POWERTX_0__VERIFY(src) \
54094 (!(((u_int32_t)(src)\
54101 #define POWERTX_RATE1__POWERTX_1__READ(src) \
54102 (((u_int32_t)(src)\
54104 #define POWERTX_RATE1__POWERTX_1__WRITE(src) \
54105 (((u_int32_t)(src)\
54107 #define POWERTX_RATE1__POWERTX_1__MODIFY(dst, src) \
54109 ~0x00003f00U) | (((u_int32_t)(src) <<\
54111 #define POWERTX_RATE1__POWERTX_1__VERIFY(src) \
54112 (!((((u_int32_t)(src)\
54119 #define POWERTX_RATE1__POWERTX_2__READ(src) \
54120 (((u_int32_t)(src)\
54122 #define POWERTX_RATE1__POWERTX_2__WRITE(src) \
54123 (((u_int32_t)(src)\
54125 #define POWERTX_RATE1__POWERTX_2__MODIFY(dst, src) \
54127 ~0x003f0000U) | (((u_int32_t)(src) <<\
54129 #define POWERTX_RATE1__POWERTX_2__VERIFY(src) \
54130 (!((((u_int32_t)(src)\
54137 #define POWERTX_RATE1__POWERTX_3__READ(src) \
54138 (((u_int32_t)(src)\
54140 #define POWERTX_RATE1__POWERTX_3__WRITE(src) \
54141 (((u_int32_t)(src)\
54143 #define POWERTX_RATE1__POWERTX_3__MODIFY(dst, src) \
54145 ~0x3f000000U) | (((u_int32_t)(src) <<\
54147 #define POWERTX_RATE1__POWERTX_3__VERIFY(src) \
54148 (!((((u_int32_t)(src)\
54168 #define POWERTX_RATE2__POWERTX_4__READ(src) (u_int32_t)(src) & 0x0000003fU
54169 #define POWERTX_RATE2__POWERTX_4__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
54170 #define POWERTX_RATE2__POWERTX_4__MODIFY(dst, src) \
54172 ~0x0000003fU) | ((u_int32_t)(src) &\
54174 #define POWERTX_RATE2__POWERTX_4__VERIFY(src) \
54175 (!(((u_int32_t)(src)\
54182 #define POWERTX_RATE2__POWERTX_5__READ(src) \
54183 (((u_int32_t)(src)\
54185 #define POWERTX_RATE2__POWERTX_5__WRITE(src) \
54186 (((u_int32_t)(src)\
54188 #define POWERTX_RATE2__POWERTX_5__MODIFY(dst, src) \
54190 ~0x00003f00U) | (((u_int32_t)(src) <<\
54192 #define POWERTX_RATE2__POWERTX_5__VERIFY(src) \
54193 (!((((u_int32_t)(src)\
54200 #define POWERTX_RATE2__POWERTX_6__READ(src) \
54201 (((u_int32_t)(src)\
54203 #define POWERTX_RATE2__POWERTX_6__WRITE(src) \
54204 (((u_int32_t)(src)\
54206 #define POWERTX_RATE2__POWERTX_6__MODIFY(dst, src) \
54208 ~0x003f0000U) | (((u_int32_t)(src) <<\
54210 #define POWERTX_RATE2__POWERTX_6__VERIFY(src) \
54211 (!((((u_int32_t)(src)\
54218 #define POWERTX_RATE2__POWERTX_7__READ(src) \
54219 (((u_int32_t)(src)\
54221 #define POWERTX_RATE2__POWERTX_7__WRITE(src) \
54222 (((u_int32_t)(src)\
54224 #define POWERTX_RATE2__POWERTX_7__MODIFY(dst, src) \
54226 ~0x3f000000U) | (((u_int32_t)(src) <<\
54228 #define POWERTX_RATE2__POWERTX_7__VERIFY(src) \
54229 (!((((u_int32_t)(src)\
54249 #define POWERTX_RATE3__POWERTX_1L__READ(src) (u_int32_t)(src) & 0x0000003fU
54250 #define POWERTX_RATE3__POWERTX_1L__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
54251 #define POWERTX_RATE3__POWERTX_1L__MODIFY(dst, src) \
54253 ~0x0000003fU) | ((u_int32_t)(src) &\
54255 #define POWERTX_RATE3__POWERTX_1L__VERIFY(src) \
54256 (!(((u_int32_t)(src)\
54263 #define POWERTX_RATE3__POWERTX_2L__READ(src) \
54264 (((u_int32_t)(src)\
54266 #define POWERTX_RATE3__POWERTX_2L__WRITE(src) \
54267 (((u_int32_t)(src)\
54269 #define POWERTX_RATE3__POWERTX_2L__MODIFY(dst, src) \
54271 ~0x003f0000U) | (((u_int32_t)(src) <<\
54273 #define POWERTX_RATE3__POWERTX_2L__VERIFY(src) \
54274 (!((((u_int32_t)(src)\
54281 #define POWERTX_RATE3__POWERTX_2S__READ(src) \
54282 (((u_int32_t)(src)\
54284 #define POWERTX_RATE3__POWERTX_2S__WRITE(src) \
54285 (((u_int32_t)(src)\
54287 #define POWERTX_RATE3__POWERTX_2S__MODIFY(dst, src) \
54289 ~0x3f000000U) | (((u_int32_t)(src) <<\
54291 #define POWERTX_RATE3__POWERTX_2S__VERIFY(src) \
54292 (!((((u_int32_t)(src)\
54312 #define POWERTX_RATE4__POWERTX_55L__READ(src) (u_int32_t)(src) & 0x0000003fU
54313 #define POWERTX_RATE4__POWERTX_55L__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
54314 #define POWERTX_RATE4__POWERTX_55L__MODIFY(dst, src) \
54316 ~0x0000003fU) | ((u_int32_t)(src) &\
54318 #define POWERTX_RATE4__POWERTX_55L__VERIFY(src) \
54319 (!(((u_int32_t)(src)\
54326 #define POWERTX_RATE4__POWERTX_55S__READ(src) \
54327 (((u_int32_t)(src)\
54329 #define POWERTX_RATE4__POWERTX_55S__WRITE(src) \
54330 (((u_int32_t)(src)\
54332 #define POWERTX_RATE4__POWERTX_55S__MODIFY(dst, src) \
54334 ~0x00003f00U) | (((u_int32_t)(src) <<\
54336 #define POWERTX_RATE4__POWERTX_55S__VERIFY(src) \
54337 (!((((u_int32_t)(src)\
54344 #define POWERTX_RATE4__POWERTX_11L__READ(src) \
54345 (((u_int32_t)(src)\
54347 #define POWERTX_RATE4__POWERTX_11L__WRITE(src) \
54348 (((u_int32_t)(src)\
54350 #define POWERTX_RATE4__POWERTX_11L__MODIFY(dst, src) \
54352 ~0x003f0000U) | (((u_int32_t)(src) <<\
54354 #define POWERTX_RATE4__POWERTX_11L__VERIFY(src) \
54355 (!((((u_int32_t)(src)\
54362 #define POWERTX_RATE4__POWERTX_11S__READ(src) \
54363 (((u_int32_t)(src)\
54365 #define POWERTX_RATE4__POWERTX_11S__WRITE(src) \
54366 (((u_int32_t)(src)\
54368 #define POWERTX_RATE4__POWERTX_11S__MODIFY(dst, src) \
54370 ~0x3f000000U) | (((u_int32_t)(src) <<\
54372 #define POWERTX_RATE4__POWERTX_11S__VERIFY(src) \
54373 (!((((u_int32_t)(src)\
54393 #define POWERTX_RATE5__POWERTXHT20_0__READ(src) (u_int32_t)(src) & 0x0000003fU
54394 #define POWERTX_RATE5__POWERTXHT20_0__WRITE(src) \
54395 ((u_int32_t)(src)\
54397 #define POWERTX_RATE5__POWERTXHT20_0__MODIFY(dst, src) \
54399 ~0x0000003fU) | ((u_int32_t)(src) &\
54401 #define POWERTX_RATE5__POWERTXHT20_0__VERIFY(src) \
54402 (!(((u_int32_t)(src)\
54409 #define POWERTX_RATE5__POWERTXHT20_1__READ(src) \
54410 (((u_int32_t)(src)\
54412 #define POWERTX_RATE5__POWERTXHT20_1__WRITE(src) \
54413 (((u_int32_t)(src)\
54415 #define POWERTX_RATE5__POWERTXHT20_1__MODIFY(dst, src) \
54417 ~0x00003f00U) | (((u_int32_t)(src) <<\
54419 #define POWERTX_RATE5__POWERTXHT20_1__VERIFY(src) \
54420 (!((((u_int32_t)(src)\
54427 #define POWERTX_RATE5__POWERTXHT20_2__READ(src) \
54428 (((u_int32_t)(src)\
54430 #define POWERTX_RATE5__POWERTXHT20_2__WRITE(src) \
54431 (((u_int32_t)(src)\
54433 #define POWERTX_RATE5__POWERTXHT20_2__MODIFY(dst, src) \
54435 ~0x003f0000U) | (((u_int32_t)(src) <<\
54437 #define POWERTX_RATE5__POWERTXHT20_2__VERIFY(src) \
54438 (!((((u_int32_t)(src)\
54445 #define POWERTX_RATE5__POWERTXHT20_3__READ(src) \
54446 (((u_int32_t)(src)\
54448 #define POWERTX_RATE5__POWERTXHT20_3__WRITE(src) \
54449 (((u_int32_t)(src)\
54451 #define POWERTX_RATE5__POWERTXHT20_3__MODIFY(dst, src) \
54453 ~0x3f000000U) | (((u_int32_t)(src) <<\
54455 #define POWERTX_RATE5__POWERTXHT20_3__VERIFY(src) \
54456 (!((((u_int32_t)(src)\
54476 #define POWERTX_RATE6__POWERTXHT20_4__READ(src) (u_int32_t)(src) & 0x0000003fU
54477 #define POWERTX_RATE6__POWERTXHT20_4__WRITE(src) \
54478 ((u_int32_t)(src)\
54480 #define POWERTX_RATE6__POWERTXHT20_4__MODIFY(dst, src) \
54482 ~0x0000003fU) | ((u_int32_t)(src) &\
54484 #define POWERTX_RATE6__POWERTXHT20_4__VERIFY(src) \
54485 (!(((u_int32_t)(src)\
54492 #define POWERTX_RATE6__POWERTXHT20_5__READ(src) \
54493 (((u_int32_t)(src)\
54495 #define POWERTX_RATE6__POWERTXHT20_5__WRITE(src) \
54496 (((u_int32_t)(src)\
54498 #define POWERTX_RATE6__POWERTXHT20_5__MODIFY(dst, src) \
54500 ~0x00003f00U) | (((u_int32_t)(src) <<\
54502 #define POWERTX_RATE6__POWERTXHT20_5__VERIFY(src) \
54503 (!((((u_int32_t)(src)\
54510 #define POWERTX_RATE6__POWERTXHT20_6__READ(src) \
54511 (((u_int32_t)(src)\
54513 #define POWERTX_RATE6__POWERTXHT20_6__WRITE(src) \
54514 (((u_int32_t)(src)\
54516 #define POWERTX_RATE6__POWERTXHT20_6__MODIFY(dst, src) \
54518 ~0x003f0000U) | (((u_int32_t)(src) <<\
54520 #define POWERTX_RATE6__POWERTXHT20_6__VERIFY(src) \
54521 (!((((u_int32_t)(src)\
54528 #define POWERTX_RATE6__POWERTXHT20_7__READ(src) \
54529 (((u_int32_t)(src)\
54531 #define POWERTX_RATE6__POWERTXHT20_7__WRITE(src) \
54532 (((u_int32_t)(src)\
54534 #define POWERTX_RATE6__POWERTXHT20_7__MODIFY(dst, src) \
54536 ~0x3f000000U) | (((u_int32_t)(src) <<\
54538 #define POWERTX_RATE6__POWERTXHT20_7__VERIFY(src) \
54539 (!((((u_int32_t)(src)\
54559 #define POWERTX_RATE7__POWERTXHT40_0__READ(src) (u_int32_t)(src) & 0x0000003fU
54560 #define POWERTX_RATE7__POWERTXHT40_0__WRITE(src) \
54561 ((u_int32_t)(src)\
54563 #define POWERTX_RATE7__POWERTXHT40_0__MODIFY(dst, src) \
54565 ~0x0000003fU) | ((u_int32_t)(src) &\
54567 #define POWERTX_RATE7__POWERTXHT40_0__VERIFY(src) \
54568 (!(((u_int32_t)(src)\
54575 #define POWERTX_RATE7__POWERTXHT40_1__READ(src) \
54576 (((u_int32_t)(src)\
54578 #define POWERTX_RATE7__POWERTXHT40_1__WRITE(src) \
54579 (((u_int32_t)(src)\
54581 #define POWERTX_RATE7__POWERTXHT40_1__MODIFY(dst, src) \
54583 ~0x00003f00U) | (((u_int32_t)(src) <<\
54585 #define POWERTX_RATE7__POWERTXHT40_1__VERIFY(src) \
54586 (!((((u_int32_t)(src)\
54593 #define POWERTX_RATE7__POWERTXHT40_2__READ(src) \
54594 (((u_int32_t)(src)\
54596 #define POWERTX_RATE7__POWERTXHT40_2__WRITE(src) \
54597 (((u_int32_t)(src)\
54599 #define POWERTX_RATE7__POWERTXHT40_2__MODIFY(dst, src) \
54601 ~0x003f0000U) | (((u_int32_t)(src) <<\
54603 #define POWERTX_RATE7__POWERTXHT40_2__VERIFY(src) \
54604 (!((((u_int32_t)(src)\
54611 #define POWERTX_RATE7__POWERTXHT40_3__READ(src) \
54612 (((u_int32_t)(src)\
54614 #define POWERTX_RATE7__POWERTXHT40_3__WRITE(src) \
54615 (((u_int32_t)(src)\
54617 #define POWERTX_RATE7__POWERTXHT40_3__MODIFY(dst, src) \
54619 ~0x3f000000U) | (((u_int32_t)(src) <<\
54621 #define POWERTX_RATE7__POWERTXHT40_3__VERIFY(src) \
54622 (!((((u_int32_t)(src)\
54642 #define POWERTX_RATE8__POWERTXHT40_4__READ(src) (u_int32_t)(src) & 0x0000003fU
54643 #define POWERTX_RATE8__POWERTXHT40_4__WRITE(src) \
54644 ((u_int32_t)(src)\
54646 #define POWERTX_RATE8__POWERTXHT40_4__MODIFY(dst, src) \
54648 ~0x0000003fU) | ((u_int32_t)(src) &\
54650 #define POWERTX_RATE8__POWERTXHT40_4__VERIFY(src) \
54651 (!(((u_int32_t)(src)\
54658 #define POWERTX_RATE8__POWERTXHT40_5__READ(src) \
54659 (((u_int32_t)(src)\
54661 #define POWERTX_RATE8__POWERTXHT40_5__WRITE(src) \
54662 (((u_int32_t)(src)\
54664 #define POWERTX_RATE8__POWERTXHT40_5__MODIFY(dst, src) \
54666 ~0x00003f00U) | (((u_int32_t)(src) <<\
54668 #define POWERTX_RATE8__POWERTXHT40_5__VERIFY(src) \
54669 (!((((u_int32_t)(src)\
54676 #define POWERTX_RATE8__POWERTXHT40_6__READ(src) \
54677 (((u_int32_t)(src)\
54679 #define POWERTX_RATE8__POWERTXHT40_6__WRITE(src) \
54680 (((u_int32_t)(src)\
54682 #define POWERTX_RATE8__POWERTXHT40_6__MODIFY(dst, src) \
54684 ~0x003f0000U) | (((u_int32_t)(src) <<\
54686 #define POWERTX_RATE8__POWERTXHT40_6__VERIFY(src) \
54687 (!((((u_int32_t)(src)\
54694 #define POWERTX_RATE8__POWERTXHT40_7__READ(src) \
54695 (((u_int32_t)(src)\
54697 #define POWERTX_RATE8__POWERTXHT40_7__WRITE(src) \
54698 (((u_int32_t)(src)\
54700 #define POWERTX_RATE8__POWERTXHT40_7__MODIFY(dst, src) \
54702 ~0x3f000000U) | (((u_int32_t)(src) <<\
54704 #define POWERTX_RATE8__POWERTXHT40_7__VERIFY(src) \
54705 (!((((u_int32_t)(src)\
54725 #define POWERTX_RATE9__POWERTX_DUP40_CCK__READ(src) \
54726 (u_int32_t)(src)\
54728 #define POWERTX_RATE9__POWERTX_DUP40_CCK__WRITE(src) \
54729 ((u_int32_t)(src)\
54731 #define POWERTX_RATE9__POWERTX_DUP40_CCK__MODIFY(dst, src) \
54733 ~0x0000003fU) | ((u_int32_t)(src) &\
54735 #define POWERTX_RATE9__POWERTX_DUP40_CCK__VERIFY(src) \
54736 (!(((u_int32_t)(src)\
54743 #define POWERTX_RATE9__POWERTX_DUP40_OFDM__READ(src) \
54744 (((u_int32_t)(src)\
54746 #define POWERTX_RATE9__POWERTX_DUP40_OFDM__WRITE(src) \
54747 (((u_int32_t)(src)\
54749 #define POWERTX_RATE9__POWERTX_DUP40_OFDM__MODIFY(dst, src) \
54751 ~0x00003f00U) | (((u_int32_t)(src) <<\
54753 #define POWERTX_RATE9__POWERTX_DUP40_OFDM__VERIFY(src) \
54754 (!((((u_int32_t)(src)\
54761 #define POWERTX_RATE9__POWERTX_EXT20_CCK__READ(src) \
54762 (((u_int32_t)(src)\
54764 #define POWERTX_RATE9__POWERTX_EXT20_CCK__WRITE(src) \
54765 (((u_int32_t)(src)\
54767 #define POWERTX_RATE9__POWERTX_EXT20_CCK__MODIFY(dst, src) \
54769 ~0x003f0000U) | (((u_int32_t)(src) <<\
54771 #define POWERTX_RATE9__POWERTX_EXT20_CCK__VERIFY(src) \
54772 (!((((u_int32_t)(src)\
54779 #define POWERTX_RATE9__POWERTX_EXT20_OFDM__READ(src) \
54780 (((u_int32_t)(src)\
54782 #define POWERTX_RATE9__POWERTX_EXT20_OFDM__WRITE(src) \
54783 (((u_int32_t)(src)\
54785 #define POWERTX_RATE9__POWERTX_EXT20_OFDM__MODIFY(dst, src) \
54787 ~0x3f000000U) | (((u_int32_t)(src) <<\
54789 #define POWERTX_RATE9__POWERTX_EXT20_OFDM__VERIFY(src) \
54790 (!((((u_int32_t)(src)\
54810 #define POWERTX_RATE10__POWERTXHT20_8__READ(src) (u_int32_t)(src) & 0x0000003fU
54811 #define POWERTX_RATE10__POWERTXHT20_8__WRITE(src) \
54812 ((u_int32_t)(src)\
54814 #define POWERTX_RATE10__POWERTXHT20_8__MODIFY(dst, src) \
54816 ~0x0000003fU) | ((u_int32_t)(src) &\
54818 #define POWERTX_RATE10__POWERTXHT20_8__VERIFY(src) \
54819 (!(((u_int32_t)(src)\
54826 #define POWERTX_RATE10__POWERTXHT20_9__READ(src) \
54827 (((u_int32_t)(src)\
54829 #define POWERTX_RATE10__POWERTXHT20_9__WRITE(src) \
54830 (((u_int32_t)(src)\
54832 #define POWERTX_RATE10__POWERTXHT20_9__MODIFY(dst, src) \
54834 ~0x00003f00U) | (((u_int32_t)(src) <<\
54836 #define POWERTX_RATE10__POWERTXHT20_9__VERIFY(src) \
54837 (!((((u_int32_t)(src)\
54844 #define POWERTX_RATE10__POWERTXHT20_10__READ(src) \
54845 (((u_int32_t)(src)\
54847 #define POWERTX_RATE10__POWERTXHT20_10__WRITE(src) \
54848 (((u_int32_t)(src)\
54850 #define POWERTX_RATE10__POWERTXHT20_10__MODIFY(dst, src) \
54852 ~0x003f0000U) | (((u_int32_t)(src) <<\
54854 #define POWERTX_RATE10__POWERTXHT20_10__VERIFY(src) \
54855 (!((((u_int32_t)(src)\
54862 #define POWERTX_RATE10__POWERTXHT20_11__READ(src) \
54863 (((u_int32_t)(src)\
54865 #define POWERTX_RATE10__POWERTXHT20_11__WRITE(src) \
54866 (((u_int32_t)(src)\
54868 #define POWERTX_RATE10__POWERTXHT20_11__MODIFY(dst, src) \
54870 ~0x3f000000U) | (((u_int32_t)(src) <<\
54872 #define POWERTX_RATE10__POWERTXHT20_11__VERIFY(src) \
54873 (!((((u_int32_t)(src)\
54893 #define POWERTX_RATE11__POWERTXHT20_12__READ(src) \
54894 (u_int32_t)(src)\
54896 #define POWERTX_RATE11__POWERTXHT20_12__WRITE(src) \
54897 ((u_int32_t)(src)\
54899 #define POWERTX_RATE11__POWERTXHT20_12__MODIFY(dst, src) \
54901 ~0x0000003fU) | ((u_int32_t)(src) &\
54903 #define POWERTX_RATE11__POWERTXHT20_12__VERIFY(src) \
54904 (!(((u_int32_t)(src)\
54911 #define POWERTX_RATE11__POWERTXHT20_13__READ(src) \
54912 (((u_int32_t)(src)\
54914 #define POWERTX_RATE11__POWERTXHT20_13__WRITE(src) \
54915 (((u_int32_t)(src)\
54917 #define POWERTX_RATE11__POWERTXHT20_13__MODIFY(dst, src) \
54919 ~0x00003f00U) | (((u_int32_t)(src) <<\
54921 #define POWERTX_RATE11__POWERTXHT20_13__VERIFY(src) \
54922 (!((((u_int32_t)(src)\
54929 #define POWERTX_RATE11__POWERTXHT40_12__READ(src) \
54930 (((u_int32_t)(src)\
54932 #define POWERTX_RATE11__POWERTXHT40_12__WRITE(src) \
54933 (((u_int32_t)(src)\
54935 #define POWERTX_RATE11__POWERTXHT40_12__MODIFY(dst, src) \
54937 ~0x003f0000U) | (((u_int32_t)(src) <<\
54939 #define POWERTX_RATE11__POWERTXHT40_12__VERIFY(src) \
54940 (!((((u_int32_t)(src)\
54947 #define POWERTX_RATE11__POWERTXHT40_13__READ(src) \
54948 (((u_int32_t)(src)\
54950 #define POWERTX_RATE11__POWERTXHT40_13__WRITE(src) \
54951 (((u_int32_t)(src)\
54953 #define POWERTX_RATE11__POWERTXHT40_13__MODIFY(dst, src) \
54955 ~0x3f000000U) | (((u_int32_t)(src) <<\
54957 #define POWERTX_RATE11__POWERTXHT40_13__VERIFY(src) \
54958 (!((((u_int32_t)(src)\
54978 #define POWERTX_RATE12__POWERTXHT40_8__READ(src) (u_int32_t)(src) & 0x0000003fU
54979 #define POWERTX_RATE12__POWERTXHT40_8__WRITE(src) \
54980 ((u_int32_t)(src)\
54982 #define POWERTX_RATE12__POWERTXHT40_8__MODIFY(dst, src) \
54984 ~0x0000003fU) | ((u_int32_t)(src) &\
54986 #define POWERTX_RATE12__POWERTXHT40_8__VERIFY(src) \
54987 (!(((u_int32_t)(src)\
54994 #define POWERTX_RATE12__POWERTXHT40_9__READ(src) \
54995 (((u_int32_t)(src)\
54997 #define POWERTX_RATE12__POWERTXHT40_9__WRITE(src) \
54998 (((u_int32_t)(src)\
55000 #define POWERTX_RATE12__POWERTXHT40_9__MODIFY(dst, src) \
55002 ~0x00003f00U) | (((u_int32_t)(src) <<\
55004 #define POWERTX_RATE12__POWERTXHT40_9__VERIFY(src) \
55005 (!((((u_int32_t)(src)\
55012 #define POWERTX_RATE12__POWERTXHT40_10__READ(src) \
55013 (((u_int32_t)(src)\
55015 #define POWERTX_RATE12__POWERTXHT40_10__WRITE(src) \
55016 (((u_int32_t)(src)\
55018 #define POWERTX_RATE12__POWERTXHT40_10__MODIFY(dst, src) \
55020 ~0x003f0000U) | (((u_int32_t)(src) <<\
55022 #define POWERTX_RATE12__POWERTXHT40_10__VERIFY(src) \
55023 (!((((u_int32_t)(src)\
55030 #define POWERTX_RATE12__POWERTXHT40_11__READ(src) \
55031 (((u_int32_t)(src)\
55033 #define POWERTX_RATE12__POWERTXHT40_11__WRITE(src) \
55034 (((u_int32_t)(src)\
55036 #define POWERTX_RATE12__POWERTXHT40_11__MODIFY(dst, src) \
55038 ~0x3f000000U) | (((u_int32_t)(src) <<\
55040 #define POWERTX_RATE12__POWERTXHT40_11__VERIFY(src) \
55041 (!((((u_int32_t)(src)\
55061 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__READ(src) \
55062 (((u_int32_t)(src)\
55064 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__WRITE(src) \
55065 (((u_int32_t)(src)\
55067 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__MODIFY(dst, src) \
55069 ~0x00000040U) | (((u_int32_t)(src) <<\
55071 #define POWERTX_MAX__USE_PER_PACKET_POWERTX_MAX__VERIFY(src) \
55072 (!((((u_int32_t)(src)\
55098 #define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__READ(src) \
55099 (u_int32_t)(src)\
55101 #define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__WRITE(src) \
55102 ((u_int32_t)(src)\
55104 #define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__MODIFY(dst, src) \
55106 ~0x0000003fU) | ((u_int32_t)(src) &\
55108 #define POWERTX_SUB__POWERTX_SUB_FOR_2CHAIN__VERIFY(src) \
55109 (!(((u_int32_t)(src)\
55116 #define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__READ(src) \
55117 (((u_int32_t)(src)\
55119 #define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__WRITE(src) \
55120 (((u_int32_t)(src)\
55122 #define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__MODIFY(dst, src) \
55124 ~0x00000fc0U) | (((u_int32_t)(src) <<\
55126 #define POWERTX_SUB__POWERTX_SUB_FOR_3CHAIN__VERIFY(src) \
55127 (!((((u_int32_t)(src)\
55147 #define TPC_1__FORCE_DAC_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U
55148 #define TPC_1__FORCE_DAC_GAIN__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
55149 #define TPC_1__FORCE_DAC_GAIN__MODIFY(dst, src) \
55151 ~0x00000001U) | ((u_int32_t)(src) &\
55153 #define TPC_1__FORCE_DAC_GAIN__VERIFY(src) \
55154 (!(((u_int32_t)(src)\
55167 #define TPC_1__FORCED_DAC_GAIN__READ(src) \
55168 (((u_int32_t)(src)\
55170 #define TPC_1__FORCED_DAC_GAIN__WRITE(src) \
55171 (((u_int32_t)(src)\
55173 #define TPC_1__FORCED_DAC_GAIN__MODIFY(dst, src) \
55175 ~0x0000003eU) | (((u_int32_t)(src) <<\
55177 #define TPC_1__FORCED_DAC_GAIN__VERIFY(src) \
55178 (!((((u_int32_t)(src)\
55185 #define TPC_1__PD_DC_OFFSET_TARGET__READ(src) \
55186 (((u_int32_t)(src)\
55188 #define TPC_1__PD_DC_OFFSET_TARGET__WRITE(src) \
55189 (((u_int32_t)(src)\
55191 #define TPC_1__PD_DC_OFFSET_TARGET__MODIFY(dst, src) \
55193 ~0x00003fc0U) | (((u_int32_t)(src) <<\
55195 #define TPC_1__PD_DC_OFFSET_TARGET__VERIFY(src) \
55196 (!((((u_int32_t)(src)\
55203 #define TPC_1__NUM_PD_GAIN__READ(src) (((u_int32_t)(src) & 0x0000c000U) >> 14)
55204 #define TPC_1__NUM_PD_GAIN__WRITE(src) (((u_int32_t)(src) << 14) & 0x0000c000U)
55205 #define TPC_1__NUM_PD_GAIN__MODIFY(dst, src) \
55207 ~0x0000c000U) | (((u_int32_t)(src) <<\
55209 #define TPC_1__NUM_PD_GAIN__VERIFY(src) \
55210 (!((((u_int32_t)(src)\
55217 #define TPC_1__PD_GAIN_SETTING1__READ(src) \
55218 (((u_int32_t)(src)\
55220 #define TPC_1__PD_GAIN_SETTING1__WRITE(src) \
55221 (((u_int32_t)(src)\
55223 #define TPC_1__PD_GAIN_SETTING1__MODIFY(dst, src) \
55225 ~0x00030000U) | (((u_int32_t)(src) <<\
55227 #define TPC_1__PD_GAIN_SETTING1__VERIFY(src) \
55228 (!((((u_int32_t)(src)\
55235 #define TPC_1__PD_GAIN_SETTING2__READ(src) \
55236 (((u_int32_t)(src)\
55238 #define TPC_1__PD_GAIN_SETTING2__WRITE(src) \
55239 (((u_int32_t)(src)\
55241 #define TPC_1__PD_GAIN_SETTING2__MODIFY(dst, src) \
55243 ~0x000c0000U) | (((u_int32_t)(src) <<\
55245 #define TPC_1__PD_GAIN_SETTING2__VERIFY(src) \
55246 (!((((u_int32_t)(src)\
55253 #define TPC_1__PD_GAIN_SETTING3__READ(src) \
55254 (((u_int32_t)(src)\
55256 #define TPC_1__PD_GAIN_SETTING3__WRITE(src) \
55257 (((u_int32_t)(src)\
55259 #define TPC_1__PD_GAIN_SETTING3__MODIFY(dst, src) \
55261 ~0x00300000U) | (((u_int32_t)(src) <<\
55263 #define TPC_1__PD_GAIN_SETTING3__VERIFY(src) \
55264 (!((((u_int32_t)(src)\
55271 #define TPC_1__ENABLE_PD_CALIBRATE__READ(src) \
55272 (((u_int32_t)(src)\
55274 #define TPC_1__ENABLE_PD_CALIBRATE__WRITE(src) \
55275 (((u_int32_t)(src)\
55277 #define TPC_1__ENABLE_PD_CALIBRATE__MODIFY(dst, src) \
55279 ~0x00400000U) | (((u_int32_t)(src) <<\
55281 #define TPC_1__ENABLE_PD_CALIBRATE__VERIFY(src) \
55282 (!((((u_int32_t)(src)\
55295 #define TPC_1__PD_CALIBRATE_WAIT__READ(src) \
55296 (((u_int32_t)(src)\
55298 #define TPC_1__PD_CALIBRATE_WAIT__WRITE(src) \
55299 (((u_int32_t)(src)\
55301 #define TPC_1__PD_CALIBRATE_WAIT__MODIFY(dst, src) \
55303 ~0x1f800000U) | (((u_int32_t)(src) <<\
55305 #define TPC_1__PD_CALIBRATE_WAIT__VERIFY(src) \
55306 (!((((u_int32_t)(src)\
55313 #define TPC_1__FORCE_PDADC_GAIN__READ(src) \
55314 (((u_int32_t)(src)\
55316 #define TPC_1__FORCE_PDADC_GAIN__WRITE(src) \
55317 (((u_int32_t)(src)\
55319 #define TPC_1__FORCE_PDADC_GAIN__MODIFY(dst, src) \
55321 ~0x20000000U) | (((u_int32_t)(src) <<\
55323 #define TPC_1__FORCE_PDADC_GAIN__VERIFY(src) \
55324 (!((((u_int32_t)(src)\
55337 #define TPC_1__FORCED_PDADC_GAIN__READ(src) \
55338 (((u_int32_t)(src)\
55340 #define TPC_1__FORCED_PDADC_GAIN__WRITE(src) \
55341 (((u_int32_t)(src)\
55343 #define TPC_1__FORCED_PDADC_GAIN__MODIFY(dst, src) \
55345 ~0xc0000000U) | (((u_int32_t)(src) <<\
55347 #define TPC_1__FORCED_PDADC_GAIN__VERIFY(src) \
55348 (!((((u_int32_t)(src)\
55368 #define TPC_2__TX_FRAME_TO_PDADC_ON__READ(src) (u_int32_t)(src) & 0x000000ffU
55369 #define TPC_2__TX_FRAME_TO_PDADC_ON__WRITE(src) \
55370 ((u_int32_t)(src)\
55372 #define TPC_2__TX_FRAME_TO_PDADC_ON__MODIFY(dst, src) \
55374 ~0x000000ffU) | ((u_int32_t)(src) &\
55376 #define TPC_2__TX_FRAME_TO_PDADC_ON__VERIFY(src) \
55377 (!(((u_int32_t)(src)\
55384 #define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__READ(src) \
55385 (((u_int32_t)(src)\
55387 #define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__WRITE(src) \
55388 (((u_int32_t)(src)\
55390 #define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__MODIFY(dst, src) \
55392 ~0x0000ff00U) | (((u_int32_t)(src) <<\
55394 #define TPC_2__TX_FRAME_TO_PD_ACC_OFDM__VERIFY(src) \
55395 (!((((u_int32_t)(src)\
55402 #define TPC_2__TX_FRAME_TO_PD_ACC_CCK__READ(src) \
55403 (((u_int32_t)(src)\
55405 #define TPC_2__TX_FRAME_TO_PD_ACC_CCK__WRITE(src) \
55406 (((u_int32_t)(src)\
55408 #define TPC_2__TX_FRAME_TO_PD_ACC_CCK__MODIFY(dst, src) \
55410 ~0x00ff0000U) | (((u_int32_t)(src) <<\
55412 #define TPC_2__TX_FRAME_TO_PD_ACC_CCK__VERIFY(src) \
55413 (!((((u_int32_t)(src)\
55433 #define TPC_3__TX_END_TO_PDADC_ON__READ(src) (u_int32_t)(src) & 0x000000ffU
55434 #define TPC_3__TX_END_TO_PDADC_ON__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
55435 #define TPC_3__TX_END_TO_PDADC_ON__MODIFY(dst, src) \
55437 ~0x000000ffU) | ((u_int32_t)(src) &\
55439 #define TPC_3__TX_END_TO_PDADC_ON__VERIFY(src) \
55440 (!(((u_int32_t)(src)\
55447 #define TPC_3__TX_END_TO_PD_ACC_ON__READ(src) \
55448 (((u_int32_t)(src)\
55450 #define TPC_3__TX_END_TO_PD_ACC_ON__WRITE(src) \
55451 (((u_int32_t)(src)\
55453 #define TPC_3__TX_END_TO_PD_ACC_ON__MODIFY(dst, src) \
55455 ~0x0000ff00U) | (((u_int32_t)(src) <<\
55457 #define TPC_3__TX_END_TO_PD_ACC_ON__VERIFY(src) \
55458 (!((((u_int32_t)(src)\
55465 #define TPC_3__PD_ACC_WINDOW_DC_OFF__READ(src) \
55466 (((u_int32_t)(src)\
55468 #define TPC_3__PD_ACC_WINDOW_DC_OFF__WRITE(src) \
55469 (((u_int32_t)(src)\
55471 #define TPC_3__PD_ACC_WINDOW_DC_OFF__MODIFY(dst, src) \
55473 ~0x00070000U) | (((u_int32_t)(src) <<\
55475 #define TPC_3__PD_ACC_WINDOW_DC_OFF__VERIFY(src) \
55476 (!((((u_int32_t)(src)\
55483 #define TPC_3__PD_ACC_WINDOW_CAL__READ(src) \
55484 (((u_int32_t)(src)\
55486 #define TPC_3__PD_ACC_WINDOW_CAL__WRITE(src) \
55487 (((u_int32_t)(src)\
55489 #define TPC_3__PD_ACC_WINDOW_CAL__MODIFY(dst, src) \
55491 ~0x00380000U) | (((u_int32_t)(src) <<\
55493 #define TPC_3__PD_ACC_WINDOW_CAL__VERIFY(src) \
55494 (!((((u_int32_t)(src)\
55501 #define TPC_3__PD_ACC_WINDOW_OFDM__READ(src) \
55502 (((u_int32_t)(src)\
55504 #define TPC_3__PD_ACC_WINDOW_OFDM__WRITE(src) \
55505 (((u_int32_t)(src)\
55507 #define TPC_3__PD_ACC_WINDOW_OFDM__MODIFY(dst, src) \
55509 ~0x01c00000U) | (((u_int32_t)(src) <<\
55511 #define TPC_3__PD_ACC_WINDOW_OFDM__VERIFY(src) \
55512 (!((((u_int32_t)(src)\
55519 #define TPC_3__PD_ACC_WINDOW_CCK__READ(src) \
55520 (((u_int32_t)(src)\
55522 #define TPC_3__PD_ACC_WINDOW_CCK__WRITE(src) \
55523 (((u_int32_t)(src)\
55525 #define TPC_3__PD_ACC_WINDOW_CCK__MODIFY(dst, src) \
55527 ~0x0e000000U) | (((u_int32_t)(src) <<\
55529 #define TPC_3__PD_ACC_WINDOW_CCK__VERIFY(src) \
55530 (!((((u_int32_t)(src)\
55537 #define TPC_3__TPC_CLK_GATE_ENABLE__READ(src) \
55538 (((u_int32_t)(src)\
55540 #define TPC_3__TPC_CLK_GATE_ENABLE__WRITE(src) \
55541 (((u_int32_t)(src)\
55543 #define TPC_3__TPC_CLK_GATE_ENABLE__MODIFY(dst, src) \
55545 ~0x80000000U) | (((u_int32_t)(src) <<\
55547 #define TPC_3__TPC_CLK_GATE_ENABLE__VERIFY(src) \
55548 (!((((u_int32_t)(src)\
55574 #define TPC_4_B0__PD_AVG_VALID_0__READ(src) (u_int32_t)(src) & 0x00000001U
55586 #define TPC_4_B0__PD_AVG_OUT_0__READ(src) \
55587 (((u_int32_t)(src)\
55594 #define TPC_4_B0__DAC_GAIN_0__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9)
55600 #define TPC_4_B0__TX_GAIN_SETTING_0__READ(src) \
55601 (((u_int32_t)(src)\
55608 #define TPC_4_B0__RATE_SENT_0__READ(src) \
55609 (((u_int32_t)(src)\
55616 #define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__READ(src) \
55617 (((u_int32_t)(src)\
55619 #define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__WRITE(src) \
55620 (((u_int32_t)(src)\
55622 #define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__MODIFY(dst, src) \
55624 ~0x7e000000U) | (((u_int32_t)(src) <<\
55626 #define TPC_4_B0__ERROR_EST_UPDATE_POWER_THRESH__VERIFY(src) \
55627 (!((((u_int32_t)(src)\
55647 #define TPC_5_B0__PD_GAIN_OVERLAP__READ(src) (u_int32_t)(src) & 0x0000000fU
55648 #define TPC_5_B0__PD_GAIN_OVERLAP__WRITE(src) ((u_int32_t)(src) & 0x0000000fU)
55649 #define TPC_5_B0__PD_GAIN_OVERLAP__MODIFY(dst, src) \
55651 ~0x0000000fU) | ((u_int32_t)(src) &\
55653 #define TPC_5_B0__PD_GAIN_OVERLAP__VERIFY(src) \
55654 (!(((u_int32_t)(src)\
55661 #define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__READ(src) \
55662 (((u_int32_t)(src)\
55664 #define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__WRITE(src) \
55665 (((u_int32_t)(src)\
55667 #define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__MODIFY(dst, src) \
55669 ~0x000003f0U) | (((u_int32_t)(src) <<\
55671 #define TPC_5_B0__PD_GAIN_BOUNDARY_1_0__VERIFY(src) \
55672 (!((((u_int32_t)(src)\
55679 #define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__READ(src) \
55680 (((u_int32_t)(src)\
55682 #define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__WRITE(src) \
55683 (((u_int32_t)(src)\
55685 #define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__MODIFY(dst, src) \
55687 ~0x0000fc00U) | (((u_int32_t)(src) <<\
55689 #define TPC_5_B0__PD_GAIN_BOUNDARY_2_0__VERIFY(src) \
55690 (!((((u_int32_t)(src)\
55697 #define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__READ(src) \
55698 (((u_int32_t)(src)\
55700 #define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__WRITE(src) \
55701 (((u_int32_t)(src)\
55703 #define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__MODIFY(dst, src) \
55705 ~0x003f0000U) | (((u_int32_t)(src) <<\
55707 #define TPC_5_B0__PD_GAIN_BOUNDARY_3_0__VERIFY(src) \
55708 (!((((u_int32_t)(src)\
55715 #define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__READ(src) \
55716 (((u_int32_t)(src)\
55718 #define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__WRITE(src) \
55719 (((u_int32_t)(src)\
55721 #define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__MODIFY(dst, src) \
55723 ~0x0fc00000U) | (((u_int32_t)(src) <<\
55725 #define TPC_5_B0__PD_GAIN_BOUNDARY_4_0__VERIFY(src) \
55726 (!((((u_int32_t)(src)\
55746 #define TPC_6_B0__PD_DAC_SETTING_1_0__READ(src) (u_int32_t)(src) & 0x0000003fU
55747 #define TPC_6_B0__PD_DAC_SETTING_1_0__WRITE(src) \
55748 ((u_int32_t)(src)\
55750 #define TPC_6_B0__PD_DAC_SETTING_1_0__MODIFY(dst, src) \
55752 ~0x0000003fU) | ((u_int32_t)(src) &\
55754 #define TPC_6_B0__PD_DAC_SETTING_1_0__VERIFY(src) \
55755 (!(((u_int32_t)(src)\
55762 #define TPC_6_B0__PD_DAC_SETTING_2_0__READ(src) \
55763 (((u_int32_t)(src)\
55765 #define TPC_6_B0__PD_DAC_SETTING_2_0__WRITE(src) \
55766 (((u_int32_t)(src)\
55768 #define TPC_6_B0__PD_DAC_SETTING_2_0__MODIFY(dst, src) \
55770 ~0x00000fc0U) | (((u_int32_t)(src) <<\
55772 #define TPC_6_B0__PD_DAC_SETTING_2_0__VERIFY(src) \
55773 (!((((u_int32_t)(src)\
55780 #define TPC_6_B0__PD_DAC_SETTING_3_0__READ(src) \
55781 (((u_int32_t)(src)\
55783 #define TPC_6_B0__PD_DAC_SETTING_3_0__WRITE(src) \
55784 (((u_int32_t)(src)\
55786 #define TPC_6_B0__PD_DAC_SETTING_3_0__MODIFY(dst, src) \
55788 ~0x0003f000U) | (((u_int32_t)(src) <<\
55790 #define TPC_6_B0__PD_DAC_SETTING_3_0__VERIFY(src) \
55791 (!((((u_int32_t)(src)\
55798 #define TPC_6_B0__PD_DAC_SETTING_4_0__READ(src) \
55799 (((u_int32_t)(src)\
55801 #define TPC_6_B0__PD_DAC_SETTING_4_0__WRITE(src) \
55802 (((u_int32_t)(src)\
55804 #define TPC_6_B0__PD_DAC_SETTING_4_0__MODIFY(dst, src) \
55806 ~0x00fc0000U) | (((u_int32_t)(src) <<\
55808 #define TPC_6_B0__PD_DAC_SETTING_4_0__VERIFY(src) \
55809 (!((((u_int32_t)(src)\
55816 #define TPC_6_B0__ERROR_EST_MODE__READ(src) \
55817 (((u_int32_t)(src)\
55819 #define TPC_6_B0__ERROR_EST_MODE__WRITE(src) \
55820 (((u_int32_t)(src)\
55822 #define TPC_6_B0__ERROR_EST_MODE__MODIFY(dst, src) \
55824 ~0x03000000U) | (((u_int32_t)(src) <<\
55826 #define TPC_6_B0__ERROR_EST_MODE__VERIFY(src) \
55827 (!((((u_int32_t)(src)\
55834 #define TPC_6_B0__ERROR_EST_FILTER_COEFF__READ(src) \
55835 (((u_int32_t)(src)\
55837 #define TPC_6_B0__ERROR_EST_FILTER_COEFF__WRITE(src) \
55838 (((u_int32_t)(src)\
55840 #define TPC_6_B0__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
55842 ~0x1c000000U) | (((u_int32_t)(src) <<\
55844 #define TPC_6_B0__ERROR_EST_FILTER_COEFF__VERIFY(src) \
55845 (!((((u_int32_t)(src)\
55865 #define TPC_7__TX_GAIN_TABLE_MAX__READ(src) (u_int32_t)(src) & 0x0000003fU
55866 #define TPC_7__TX_GAIN_TABLE_MAX__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
55867 #define TPC_7__TX_GAIN_TABLE_MAX__MODIFY(dst, src) \
55869 ~0x0000003fU) | ((u_int32_t)(src) &\
55871 #define TPC_7__TX_GAIN_TABLE_MAX__VERIFY(src) \
55872 (!(((u_int32_t)(src)\
55879 #define TPC_7__INIT_TX_GAIN_SETTING__READ(src) \
55880 (((u_int32_t)(src)\
55882 #define TPC_7__INIT_TX_GAIN_SETTING__WRITE(src) \
55883 (((u_int32_t)(src)\
55885 #define TPC_7__INIT_TX_GAIN_SETTING__MODIFY(dst, src) \
55887 ~0x00000fc0U) | (((u_int32_t)(src) <<\
55889 #define TPC_7__INIT_TX_GAIN_SETTING__VERIFY(src) \
55890 (!((((u_int32_t)(src)\
55897 #define TPC_7__EN_CL_GAIN_MOD__READ(src) \
55898 (((u_int32_t)(src)\
55900 #define TPC_7__EN_CL_GAIN_MOD__WRITE(src) \
55901 (((u_int32_t)(src)\
55903 #define TPC_7__EN_CL_GAIN_MOD__MODIFY(dst, src) \
55905 ~0x00001000U) | (((u_int32_t)(src) <<\
55907 #define TPC_7__EN_CL_GAIN_MOD__VERIFY(src) \
55908 (!((((u_int32_t)(src)\
55921 #define TPC_7__USE_TX_PD_IN_XPA__READ(src) \
55922 (((u_int32_t)(src)\
55924 #define TPC_7__USE_TX_PD_IN_XPA__WRITE(src) \
55925 (((u_int32_t)(src)\
55927 #define TPC_7__USE_TX_PD_IN_XPA__MODIFY(dst, src) \
55929 ~0x00002000U) | (((u_int32_t)(src) <<\
55931 #define TPC_7__USE_TX_PD_IN_XPA__VERIFY(src) \
55932 (!((((u_int32_t)(src)\
55945 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__READ(src) \
55946 (((u_int32_t)(src)\
55948 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__WRITE(src) \
55949 (((u_int32_t)(src)\
55951 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__MODIFY(dst, src) \
55953 ~0x00004000U) | (((u_int32_t)(src) <<\
55955 #define TPC_7__EXTEND_TX_FRAME_FOR_TPC__VERIFY(src) \
55956 (!((((u_int32_t)(src)\
55969 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__READ(src) \
55970 (((u_int32_t)(src)\
55972 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__WRITE(src) \
55973 (((u_int32_t)(src)\
55975 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__MODIFY(dst, src) \
55977 ~0x00008000U) | (((u_int32_t)(src) <<\
55979 #define TPC_7__USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET__VERIFY(src) \
55980 (!((((u_int32_t)(src)\
56006 #define TPC_8__DESIRED_SCALE_0__READ(src) (u_int32_t)(src) & 0x0000001fU
56007 #define TPC_8__DESIRED_SCALE_0__WRITE(src) ((u_int32_t)(src) & 0x0000001fU)
56008 #define TPC_8__DESIRED_SCALE_0__MODIFY(dst, src) \
56010 ~0x0000001fU) | ((u_int32_t)(src) &\
56012 #define TPC_8__DESIRED_SCALE_0__VERIFY(src) \
56013 (!(((u_int32_t)(src)\
56020 #define TPC_8__DESIRED_SCALE_1__READ(src) \
56021 (((u_int32_t)(src)\
56023 #define TPC_8__DESIRED_SCALE_1__WRITE(src) \
56024 (((u_int32_t)(src)\
56026 #define TPC_8__DESIRED_SCALE_1__MODIFY(dst, src) \
56028 ~0x000003e0U) | (((u_int32_t)(src) <<\
56030 #define TPC_8__DESIRED_SCALE_1__VERIFY(src) \
56031 (!((((u_int32_t)(src)\
56038 #define TPC_8__DESIRED_SCALE_2__READ(src) \
56039 (((u_int32_t)(src)\
56041 #define TPC_8__DESIRED_SCALE_2__WRITE(src) \
56042 (((u_int32_t)(src)\
56044 #define TPC_8__DESIRED_SCALE_2__MODIFY(dst, src) \
56046 ~0x00007c00U) | (((u_int32_t)(src) <<\
56048 #define TPC_8__DESIRED_SCALE_2__VERIFY(src) \
56049 (!((((u_int32_t)(src)\
56056 #define TPC_8__DESIRED_SCALE_3__READ(src) \
56057 (((u_int32_t)(src)\
56059 #define TPC_8__DESIRED_SCALE_3__WRITE(src) \
56060 (((u_int32_t)(src)\
56062 #define TPC_8__DESIRED_SCALE_3__MODIFY(dst, src) \
56064 ~0x000f8000U) | (((u_int32_t)(src) <<\
56066 #define TPC_8__DESIRED_SCALE_3__VERIFY(src) \
56067 (!((((u_int32_t)(src)\
56074 #define TPC_8__DESIRED_SCALE_4__READ(src) \
56075 (((u_int32_t)(src)\
56077 #define TPC_8__DESIRED_SCALE_4__WRITE(src) \
56078 (((u_int32_t)(src)\
56080 #define TPC_8__DESIRED_SCALE_4__MODIFY(dst, src) \
56082 ~0x01f00000U) | (((u_int32_t)(src) <<\
56084 #define TPC_8__DESIRED_SCALE_4__VERIFY(src) \
56085 (!((((u_int32_t)(src)\
56092 #define TPC_8__DESIRED_SCALE_5__READ(src) \
56093 (((u_int32_t)(src)\
56095 #define TPC_8__DESIRED_SCALE_5__WRITE(src) \
56096 (((u_int32_t)(src)\
56098 #define TPC_8__DESIRED_SCALE_5__MODIFY(dst, src) \
56100 ~0x3e000000U) | (((u_int32_t)(src) <<\
56102 #define TPC_8__DESIRED_SCALE_5__VERIFY(src) \
56103 (!((((u_int32_t)(src)\
56123 #define TPC_9__DESIRED_SCALE_6__READ(src) (u_int32_t)(src) & 0x0000001fU
56124 #define TPC_9__DESIRED_SCALE_6__WRITE(src) ((u_int32_t)(src) & 0x0000001fU)
56125 #define TPC_9__DESIRED_SCALE_6__MODIFY(dst, src) \
56127 ~0x0000001fU) | ((u_int32_t)(src) &\
56129 #define TPC_9__DESIRED_SCALE_6__VERIFY(src) \
56130 (!(((u_int32_t)(src)\
56137 #define TPC_9__DESIRED_SCALE_7__READ(src) \
56138 (((u_int32_t)(src)\
56140 #define TPC_9__DESIRED_SCALE_7__WRITE(src) \
56141 (((u_int32_t)(src)\
56143 #define TPC_9__DESIRED_SCALE_7__MODIFY(dst, src) \
56145 ~0x000003e0U) | (((u_int32_t)(src) <<\
56147 #define TPC_9__DESIRED_SCALE_7__VERIFY(src) \
56148 (!((((u_int32_t)(src)\
56155 #define TPC_9__DESIRED_SCALE_CCK__READ(src) \
56156 (((u_int32_t)(src)\
56158 #define TPC_9__DESIRED_SCALE_CCK__WRITE(src) \
56159 (((u_int32_t)(src)\
56161 #define TPC_9__DESIRED_SCALE_CCK__MODIFY(dst, src) \
56163 ~0x00007c00U) | (((u_int32_t)(src) <<\
56165 #define TPC_9__DESIRED_SCALE_CCK__VERIFY(src) \
56166 (!((((u_int32_t)(src)\
56173 #define TPC_9__EN_PD_DC_OFFSET_THR__READ(src) \
56174 (((u_int32_t)(src)\
56176 #define TPC_9__EN_PD_DC_OFFSET_THR__WRITE(src) \
56177 (((u_int32_t)(src)\
56179 #define TPC_9__EN_PD_DC_OFFSET_THR__MODIFY(dst, src) \
56181 ~0x00100000U) | (((u_int32_t)(src) <<\
56183 #define TPC_9__EN_PD_DC_OFFSET_THR__VERIFY(src) \
56184 (!((((u_int32_t)(src)\
56197 #define TPC_9__PD_DC_OFFSET_THR__READ(src) \
56198 (((u_int32_t)(src)\
56200 #define TPC_9__PD_DC_OFFSET_THR__WRITE(src) \
56201 (((u_int32_t)(src)\
56203 #define TPC_9__PD_DC_OFFSET_THR__MODIFY(dst, src) \
56205 ~0x07e00000U) | (((u_int32_t)(src) <<\
56207 #define TPC_9__PD_DC_OFFSET_THR__VERIFY(src) \
56208 (!((((u_int32_t)(src)\
56215 #define TPC_9__WAIT_CALTX_SETTLE__READ(src) \
56216 (((u_int32_t)(src)\
56218 #define TPC_9__WAIT_CALTX_SETTLE__WRITE(src) \
56219 (((u_int32_t)(src)\
56221 #define TPC_9__WAIT_CALTX_SETTLE__MODIFY(dst, src) \
56223 ~0x78000000U) | (((u_int32_t)(src) <<\
56225 #define TPC_9__WAIT_CALTX_SETTLE__VERIFY(src) \
56226 (!((((u_int32_t)(src)\
56233 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__READ(src) \
56234 (((u_int32_t)(src)\
56236 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__WRITE(src) \
56237 (((u_int32_t)(src)\
56239 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__MODIFY(dst, src) \
56241 ~0x80000000U) | (((u_int32_t)(src) <<\
56243 #define TPC_9__DISABLE_PDADC_RESIDUAL_DC_REMOVAL__VERIFY(src) \
56244 (!((((u_int32_t)(src)\
56270 #define TPC_10__DESIRED_SCALE_HT20_0__READ(src) (u_int32_t)(src) & 0x0000001fU
56271 #define TPC_10__DESIRED_SCALE_HT20_0__WRITE(src) \
56272 ((u_int32_t)(src)\
56274 #define TPC_10__DESIRED_SCALE_HT20_0__MODIFY(dst, src) \
56276 ~0x0000001fU) | ((u_int32_t)(src) &\
56278 #define TPC_10__DESIRED_SCALE_HT20_0__VERIFY(src) \
56279 (!(((u_int32_t)(src)\
56286 #define TPC_10__DESIRED_SCALE_HT20_1__READ(src) \
56287 (((u_int32_t)(src)\
56289 #define TPC_10__DESIRED_SCALE_HT20_1__WRITE(src) \
56290 (((u_int32_t)(src)\
56292 #define TPC_10__DESIRED_SCALE_HT20_1__MODIFY(dst, src) \
56294 ~0x000003e0U) | (((u_int32_t)(src) <<\
56296 #define TPC_10__DESIRED_SCALE_HT20_1__VERIFY(src) \
56297 (!((((u_int32_t)(src)\
56304 #define TPC_10__DESIRED_SCALE_HT20_2__READ(src) \
56305 (((u_int32_t)(src)\
56307 #define TPC_10__DESIRED_SCALE_HT20_2__WRITE(src) \
56308 (((u_int32_t)(src)\
56310 #define TPC_10__DESIRED_SCALE_HT20_2__MODIFY(dst, src) \
56312 ~0x00007c00U) | (((u_int32_t)(src) <<\
56314 #define TPC_10__DESIRED_SCALE_HT20_2__VERIFY(src) \
56315 (!((((u_int32_t)(src)\
56322 #define TPC_10__DESIRED_SCALE_HT20_3__READ(src) \
56323 (((u_int32_t)(src)\
56325 #define TPC_10__DESIRED_SCALE_HT20_3__WRITE(src) \
56326 (((u_int32_t)(src)\
56328 #define TPC_10__DESIRED_SCALE_HT20_3__MODIFY(dst, src) \
56330 ~0x000f8000U) | (((u_int32_t)(src) <<\
56332 #define TPC_10__DESIRED_SCALE_HT20_3__VERIFY(src) \
56333 (!((((u_int32_t)(src)\
56340 #define TPC_10__DESIRED_SCALE_HT20_4__READ(src) \
56341 (((u_int32_t)(src)\
56343 #define TPC_10__DESIRED_SCALE_HT20_4__WRITE(src) \
56344 (((u_int32_t)(src)\
56346 #define TPC_10__DESIRED_SCALE_HT20_4__MODIFY(dst, src) \
56348 ~0x01f00000U) | (((u_int32_t)(src) <<\
56350 #define TPC_10__DESIRED_SCALE_HT20_4__VERIFY(src) \
56351 (!((((u_int32_t)(src)\
56358 #define TPC_10__DESIRED_SCALE_HT20_5__READ(src) \
56359 (((u_int32_t)(src)\
56361 #define TPC_10__DESIRED_SCALE_HT20_5__WRITE(src) \
56362 (((u_int32_t)(src)\
56364 #define TPC_10__DESIRED_SCALE_HT20_5__MODIFY(dst, src) \
56366 ~0x3e000000U) | (((u_int32_t)(src) <<\
56368 #define TPC_10__DESIRED_SCALE_HT20_5__VERIFY(src) \
56369 (!((((u_int32_t)(src)\
56389 #define TPC_11_B0__DESIRED_SCALE_HT20_6__READ(src) \
56390 (u_int32_t)(src)\
56392 #define TPC_11_B0__DESIRED_SCALE_HT20_6__WRITE(src) \
56393 ((u_int32_t)(src)\
56395 #define TPC_11_B0__DESIRED_SCALE_HT20_6__MODIFY(dst, src) \
56397 ~0x0000001fU) | ((u_int32_t)(src) &\
56399 #define TPC_11_B0__DESIRED_SCALE_HT20_6__VERIFY(src) \
56400 (!(((u_int32_t)(src)\
56407 #define TPC_11_B0__DESIRED_SCALE_HT20_7__READ(src) \
56408 (((u_int32_t)(src)\
56410 #define TPC_11_B0__DESIRED_SCALE_HT20_7__WRITE(src) \
56411 (((u_int32_t)(src)\
56413 #define TPC_11_B0__DESIRED_SCALE_HT20_7__MODIFY(dst, src) \
56415 ~0x000003e0U) | (((u_int32_t)(src) <<\
56417 #define TPC_11_B0__DESIRED_SCALE_HT20_7__VERIFY(src) \
56418 (!((((u_int32_t)(src)\
56425 #define TPC_11_B0__OLPC_GAIN_DELTA_0__READ(src) \
56426 (((u_int32_t)(src)\
56428 #define TPC_11_B0__OLPC_GAIN_DELTA_0__WRITE(src) \
56429 (((u_int32_t)(src)\
56431 #define TPC_11_B0__OLPC_GAIN_DELTA_0__MODIFY(dst, src) \
56433 ~0x00ff0000U) | (((u_int32_t)(src) <<\
56435 #define TPC_11_B0__OLPC_GAIN_DELTA_0__VERIFY(src) \
56436 (!((((u_int32_t)(src)\
56443 #define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__READ(src) \
56444 (((u_int32_t)(src)\
56446 #define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__WRITE(src) \
56447 (((u_int32_t)(src)\
56449 #define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__MODIFY(dst, src) \
56451 ~0xff000000U) | (((u_int32_t)(src) <<\
56453 #define TPC_11_B0__OLPC_GAIN_DELTA_0_PAL_ON__VERIFY(src) \
56454 (!((((u_int32_t)(src)\
56474 #define TPC_12__DESIRED_SCALE_HT40_0__READ(src) (u_int32_t)(src) & 0x0000001fU
56475 #define TPC_12__DESIRED_SCALE_HT40_0__WRITE(src) \
56476 ((u_int32_t)(src)\
56478 #define TPC_12__DESIRED_SCALE_HT40_0__MODIFY(dst, src) \
56480 ~0x0000001fU) | ((u_int32_t)(src) &\
56482 #define TPC_12__DESIRED_SCALE_HT40_0__VERIFY(src) \
56483 (!(((u_int32_t)(src)\
56490 #define TPC_12__DESIRED_SCALE_HT40_1__READ(src) \
56491 (((u_int32_t)(src)\
56493 #define TPC_12__DESIRED_SCALE_HT40_1__WRITE(src) \
56494 (((u_int32_t)(src)\
56496 #define TPC_12__DESIRED_SCALE_HT40_1__MODIFY(dst, src) \
56498 ~0x000003e0U) | (((u_int32_t)(src) <<\
56500 #define TPC_12__DESIRED_SCALE_HT40_1__VERIFY(src) \
56501 (!((((u_int32_t)(src)\
56508 #define TPC_12__DESIRED_SCALE_HT40_2__READ(src) \
56509 (((u_int32_t)(src)\
56511 #define TPC_12__DESIRED_SCALE_HT40_2__WRITE(src) \
56512 (((u_int32_t)(src)\
56514 #define TPC_12__DESIRED_SCALE_HT40_2__MODIFY(dst, src) \
56516 ~0x00007c00U) | (((u_int32_t)(src) <<\
56518 #define TPC_12__DESIRED_SCALE_HT40_2__VERIFY(src) \
56519 (!((((u_int32_t)(src)\
56526 #define TPC_12__DESIRED_SCALE_HT40_3__READ(src) \
56527 (((u_int32_t)(src)\
56529 #define TPC_12__DESIRED_SCALE_HT40_3__WRITE(src) \
56530 (((u_int32_t)(src)\
56532 #define TPC_12__DESIRED_SCALE_HT40_3__MODIFY(dst, src) \
56534 ~0x000f8000U) | (((u_int32_t)(src) <<\
56536 #define TPC_12__DESIRED_SCALE_HT40_3__VERIFY(src) \
56537 (!((((u_int32_t)(src)\
56544 #define TPC_12__DESIRED_SCALE_HT40_4__READ(src) \
56545 (((u_int32_t)(src)\
56547 #define TPC_12__DESIRED_SCALE_HT40_4__WRITE(src) \
56548 (((u_int32_t)(src)\
56550 #define TPC_12__DESIRED_SCALE_HT40_4__MODIFY(dst, src) \
56552 ~0x01f00000U) | (((u_int32_t)(src) <<\
56554 #define TPC_12__DESIRED_SCALE_HT40_4__VERIFY(src) \
56555 (!((((u_int32_t)(src)\
56562 #define TPC_12__DESIRED_SCALE_HT40_5__READ(src) \
56563 (((u_int32_t)(src)\
56565 #define TPC_12__DESIRED_SCALE_HT40_5__WRITE(src) \
56566 (((u_int32_t)(src)\
56568 #define TPC_12__DESIRED_SCALE_HT40_5__MODIFY(dst, src) \
56570 ~0x3e000000U) | (((u_int32_t)(src) <<\
56572 #define TPC_12__DESIRED_SCALE_HT40_5__VERIFY(src) \
56573 (!((((u_int32_t)(src)\
56593 #define TPC_13__DESIRED_SCALE_HT40_6__READ(src) (u_int32_t)(src) & 0x0000001fU
56594 #define TPC_13__DESIRED_SCALE_HT40_6__WRITE(src) \
56595 ((u_int32_t)(src)\
56597 #define TPC_13__DESIRED_SCALE_HT40_6__MODIFY(dst, src) \
56599 ~0x0000001fU) | ((u_int32_t)(src) &\
56601 #define TPC_13__DESIRED_SCALE_HT40_6__VERIFY(src) \
56602 (!(((u_int32_t)(src)\
56609 #define TPC_13__DESIRED_SCALE_HT40_7__READ(src) \
56610 (((u_int32_t)(src)\
56612 #define TPC_13__DESIRED_SCALE_HT40_7__WRITE(src) \
56613 (((u_int32_t)(src)\
56615 #define TPC_13__DESIRED_SCALE_HT40_7__MODIFY(dst, src) \
56617 ~0x000003e0U) | (((u_int32_t)(src) <<\
56619 #define TPC_13__DESIRED_SCALE_HT40_7__VERIFY(src) \
56620 (!((((u_int32_t)(src)\
56640 #define TPC_14__DESIRED_SCALE_HT20_8__READ(src) (u_int32_t)(src) & 0x0000001fU
56641 #define TPC_14__DESIRED_SCALE_HT20_8__WRITE(src) \
56642 ((u_int32_t)(src)\
56644 #define TPC_14__DESIRED_SCALE_HT20_8__MODIFY(dst, src) \
56646 ~0x0000001fU) | ((u_int32_t)(src) &\
56648 #define TPC_14__DESIRED_SCALE_HT20_8__VERIFY(src) \
56649 (!(((u_int32_t)(src)\
56656 #define TPC_14__DESIRED_SCALE_HT20_9__READ(src) \
56657 (((u_int32_t)(src)\
56659 #define TPC_14__DESIRED_SCALE_HT20_9__WRITE(src) \
56660 (((u_int32_t)(src)\
56662 #define TPC_14__DESIRED_SCALE_HT20_9__MODIFY(dst, src) \
56664 ~0x000003e0U) | (((u_int32_t)(src) <<\
56666 #define TPC_14__DESIRED_SCALE_HT20_9__VERIFY(src) \
56667 (!((((u_int32_t)(src)\
56674 #define TPC_14__DESIRED_SCALE_HT20_10__READ(src) \
56675 (((u_int32_t)(src)\
56677 #define TPC_14__DESIRED_SCALE_HT20_10__WRITE(src) \
56678 (((u_int32_t)(src)\
56680 #define TPC_14__DESIRED_SCALE_HT20_10__MODIFY(dst, src) \
56682 ~0x00007c00U) | (((u_int32_t)(src) <<\
56684 #define TPC_14__DESIRED_SCALE_HT20_10__VERIFY(src) \
56685 (!((((u_int32_t)(src)\
56692 #define TPC_14__DESIRED_SCALE_HT20_11__READ(src) \
56693 (((u_int32_t)(src)\
56695 #define TPC_14__DESIRED_SCALE_HT20_11__WRITE(src) \
56696 (((u_int32_t)(src)\
56698 #define TPC_14__DESIRED_SCALE_HT20_11__MODIFY(dst, src) \
56700 ~0x000f8000U) | (((u_int32_t)(src) <<\
56702 #define TPC_14__DESIRED_SCALE_HT20_11__VERIFY(src) \
56703 (!((((u_int32_t)(src)\
56710 #define TPC_14__DESIRED_SCALE_HT20_12__READ(src) \
56711 (((u_int32_t)(src)\
56713 #define TPC_14__DESIRED_SCALE_HT20_12__WRITE(src) \
56714 (((u_int32_t)(src)\
56716 #define TPC_14__DESIRED_SCALE_HT20_12__MODIFY(dst, src) \
56718 ~0x01f00000U) | (((u_int32_t)(src) <<\
56720 #define TPC_14__DESIRED_SCALE_HT20_12__VERIFY(src) \
56721 (!((((u_int32_t)(src)\
56728 #define TPC_14__DESIRED_SCALE_HT20_13__READ(src) \
56729 (((u_int32_t)(src)\
56731 #define TPC_14__DESIRED_SCALE_HT20_13__WRITE(src) \
56732 (((u_int32_t)(src)\
56734 #define TPC_14__DESIRED_SCALE_HT20_13__MODIFY(dst, src) \
56736 ~0x3e000000U) | (((u_int32_t)(src) <<\
56738 #define TPC_14__DESIRED_SCALE_HT20_13__VERIFY(src) \
56739 (!((((u_int32_t)(src)\
56759 #define TPC_15__DESIRED_SCALE_HT40_8__READ(src) (u_int32_t)(src) & 0x0000001fU
56760 #define TPC_15__DESIRED_SCALE_HT40_8__WRITE(src) \
56761 ((u_int32_t)(src)\
56763 #define TPC_15__DESIRED_SCALE_HT40_8__MODIFY(dst, src) \
56765 ~0x0000001fU) | ((u_int32_t)(src) &\
56767 #define TPC_15__DESIRED_SCALE_HT40_8__VERIFY(src) \
56768 (!(((u_int32_t)(src)\
56775 #define TPC_15__DESIRED_SCALE_HT40_9__READ(src) \
56776 (((u_int32_t)(src)\
56778 #define TPC_15__DESIRED_SCALE_HT40_9__WRITE(src) \
56779 (((u_int32_t)(src)\
56781 #define TPC_15__DESIRED_SCALE_HT40_9__MODIFY(dst, src) \
56783 ~0x000003e0U) | (((u_int32_t)(src) <<\
56785 #define TPC_15__DESIRED_SCALE_HT40_9__VERIFY(src) \
56786 (!((((u_int32_t)(src)\
56793 #define TPC_15__DESIRED_SCALE_HT40_10__READ(src) \
56794 (((u_int32_t)(src)\
56796 #define TPC_15__DESIRED_SCALE_HT40_10__WRITE(src) \
56797 (((u_int32_t)(src)\
56799 #define TPC_15__DESIRED_SCALE_HT40_10__MODIFY(dst, src) \
56801 ~0x00007c00U) | (((u_int32_t)(src) <<\
56803 #define TPC_15__DESIRED_SCALE_HT40_10__VERIFY(src) \
56804 (!((((u_int32_t)(src)\
56811 #define TPC_15__DESIRED_SCALE_HT40_11__READ(src) \
56812 (((u_int32_t)(src)\
56814 #define TPC_15__DESIRED_SCALE_HT40_11__WRITE(src) \
56815 (((u_int32_t)(src)\
56817 #define TPC_15__DESIRED_SCALE_HT40_11__MODIFY(dst, src) \
56819 ~0x000f8000U) | (((u_int32_t)(src) <<\
56821 #define TPC_15__DESIRED_SCALE_HT40_11__VERIFY(src) \
56822 (!((((u_int32_t)(src)\
56829 #define TPC_15__DESIRED_SCALE_HT40_12__READ(src) \
56830 (((u_int32_t)(src)\
56832 #define TPC_15__DESIRED_SCALE_HT40_12__WRITE(src) \
56833 (((u_int32_t)(src)\
56835 #define TPC_15__DESIRED_SCALE_HT40_12__MODIFY(dst, src) \
56837 ~0x01f00000U) | (((u_int32_t)(src) <<\
56839 #define TPC_15__DESIRED_SCALE_HT40_12__VERIFY(src) \
56840 (!((((u_int32_t)(src)\
56847 #define TPC_15__DESIRED_SCALE_HT40_13__READ(src) \
56848 (((u_int32_t)(src)\
56850 #define TPC_15__DESIRED_SCALE_HT40_13__WRITE(src) \
56851 (((u_int32_t)(src)\
56853 #define TPC_15__DESIRED_SCALE_HT40_13__MODIFY(dst, src) \
56855 ~0x3e000000U) | (((u_int32_t)(src) <<\
56857 #define TPC_15__DESIRED_SCALE_HT40_13__VERIFY(src) \
56858 (!((((u_int32_t)(src)\
56878 #define TPC_16__PDADC_PAR_CORR_CCK__READ(src) \
56879 (((u_int32_t)(src)\
56881 #define TPC_16__PDADC_PAR_CORR_CCK__WRITE(src) \
56882 (((u_int32_t)(src)\
56884 #define TPC_16__PDADC_PAR_CORR_CCK__MODIFY(dst, src) \
56886 ~0x00003f00U) | (((u_int32_t)(src) <<\
56888 #define TPC_16__PDADC_PAR_CORR_CCK__VERIFY(src) \
56889 (!((((u_int32_t)(src)\
56896 #define TPC_16__PDADC_PAR_CORR_OFDM__READ(src) \
56897 (((u_int32_t)(src)\
56899 #define TPC_16__PDADC_PAR_CORR_OFDM__WRITE(src) \
56900 (((u_int32_t)(src)\
56902 #define TPC_16__PDADC_PAR_CORR_OFDM__MODIFY(dst, src) \
56904 ~0x003f0000U) | (((u_int32_t)(src) <<\
56906 #define TPC_16__PDADC_PAR_CORR_OFDM__VERIFY(src) \
56907 (!((((u_int32_t)(src)\
56914 #define TPC_16__PDADC_PAR_CORR_HT40__READ(src) \
56915 (((u_int32_t)(src)\
56917 #define TPC_16__PDADC_PAR_CORR_HT40__WRITE(src) \
56918 (((u_int32_t)(src)\
56920 #define TPC_16__PDADC_PAR_CORR_HT40__MODIFY(dst, src) \
56922 ~0x3f000000U) | (((u_int32_t)(src) <<\
56924 #define TPC_16__PDADC_PAR_CORR_HT40__VERIFY(src) \
56925 (!((((u_int32_t)(src)\
56945 #define TPC_17__ENABLE_PAL__READ(src) (u_int32_t)(src) & 0x00000001U
56946 #define TPC_17__ENABLE_PAL__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
56947 #define TPC_17__ENABLE_PAL__MODIFY(dst, src) \
56949 ~0x00000001U) | ((u_int32_t)(src) &\
56951 #define TPC_17__ENABLE_PAL__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
56963 #define TPC_17__ENABLE_PAL_CCK__READ(src) \
56964 (((u_int32_t)(src)\
56966 #define TPC_17__ENABLE_PAL_CCK__WRITE(src) \
56967 (((u_int32_t)(src)\
56969 #define TPC_17__ENABLE_PAL_CCK__MODIFY(dst, src) \
56971 ~0x00000002U) | (((u_int32_t)(src) <<\
56973 #define TPC_17__ENABLE_PAL_CCK__VERIFY(src) \
56974 (!((((u_int32_t)(src)\
56987 #define TPC_17__ENABLE_PAL_OFDM_20__READ(src) \
56988 (((u_int32_t)(src)\
56990 #define TPC_17__ENABLE_PAL_OFDM_20__WRITE(src) \
56991 (((u_int32_t)(src)\
56993 #define TPC_17__ENABLE_PAL_OFDM_20__MODIFY(dst, src) \
56995 ~0x00000004U) | (((u_int32_t)(src) <<\
56997 #define TPC_17__ENABLE_PAL_OFDM_20__VERIFY(src) \
56998 (!((((u_int32_t)(src)\
57011 #define TPC_17__ENABLE_PAL_OFDM_40__READ(src) \
57012 (((u_int32_t)(src)\
57014 #define TPC_17__ENABLE_PAL_OFDM_40__WRITE(src) \
57015 (((u_int32_t)(src)\
57017 #define TPC_17__ENABLE_PAL_OFDM_40__MODIFY(dst, src) \
57019 ~0x00000008U) | (((u_int32_t)(src) <<\
57021 #define TPC_17__ENABLE_PAL_OFDM_40__VERIFY(src) \
57022 (!((((u_int32_t)(src)\
57035 #define TPC_17__PAL_POWER_THRESHOLD__READ(src) \
57036 (((u_int32_t)(src)\
57038 #define TPC_17__PAL_POWER_THRESHOLD__WRITE(src) \
57039 (((u_int32_t)(src)\
57041 #define TPC_17__PAL_POWER_THRESHOLD__MODIFY(dst, src) \
57043 ~0x000003f0U) | (((u_int32_t)(src) <<\
57045 #define TPC_17__PAL_POWER_THRESHOLD__VERIFY(src) \
57046 (!((((u_int32_t)(src)\
57053 #define TPC_17__FORCE_PAL_LOCKED__READ(src) \
57054 (((u_int32_t)(src)\
57056 #define TPC_17__FORCE_PAL_LOCKED__WRITE(src) \
57057 (((u_int32_t)(src)\
57059 #define TPC_17__FORCE_PAL_LOCKED__MODIFY(dst, src) \
57061 ~0x00000400U) | (((u_int32_t)(src) <<\
57063 #define TPC_17__FORCE_PAL_LOCKED__VERIFY(src) \
57064 (!((((u_int32_t)(src)\
57077 #define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__READ(src) \
57078 (((u_int32_t)(src)\
57080 #define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__WRITE(src) \
57081 (((u_int32_t)(src)\
57083 #define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__MODIFY(dst, src) \
57085 ~0x0001f800U) | (((u_int32_t)(src) <<\
57087 #define TPC_17__INIT_TX_GAIN_SETTING_PAL_ON__VERIFY(src) \
57088 (!((((u_int32_t)(src)\
57108 #define TPC_18__THERM_CAL_VALUE__READ(src) (u_int32_t)(src) & 0x000000ffU
57109 #define TPC_18__THERM_CAL_VALUE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
57110 #define TPC_18__THERM_CAL_VALUE__MODIFY(dst, src) \
57112 ~0x000000ffU) | ((u_int32_t)(src) &\
57114 #define TPC_18__THERM_CAL_VALUE__VERIFY(src) \
57115 (!(((u_int32_t)(src)\
57122 #define TPC_18__VOLT_CAL_VALUE__READ(src) \
57123 (((u_int32_t)(src)\
57125 #define TPC_18__VOLT_CAL_VALUE__WRITE(src) \
57126 (((u_int32_t)(src)\
57128 #define TPC_18__VOLT_CAL_VALUE__MODIFY(dst, src) \
57130 ~0x0000ff00U) | (((u_int32_t)(src) <<\
57132 #define TPC_18__VOLT_CAL_VALUE__VERIFY(src) \
57133 (!((((u_int32_t)(src)\
57140 #define TPC_18__USE_LEGACY_TPC__READ(src) \
57141 (((u_int32_t)(src)\
57143 #define TPC_18__USE_LEGACY_TPC__WRITE(src) \
57144 (((u_int32_t)(src)\
57146 #define TPC_18__USE_LEGACY_TPC__MODIFY(dst, src) \
57148 ~0x00010000U) | (((u_int32_t)(src) <<\
57150 #define TPC_18__USE_LEGACY_TPC__VERIFY(src) \
57151 (!((((u_int32_t)(src)\
57164 #define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__READ(src) \
57165 (((u_int32_t)(src)\
57167 #define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__WRITE(src) \
57168 (((u_int32_t)(src)\
57170 #define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__MODIFY(dst, src) \
57172 ~0x007e0000U) | (((u_int32_t)(src) <<\
57174 #define TPC_18__MIN_POWER_THERM_VOLT_GAIN_CORR__VERIFY(src) \
57175 (!((((u_int32_t)(src)\
57195 #define TPC_19__ALPHA_THERM__READ(src) (u_int32_t)(src) & 0x000000ffU
57196 #define TPC_19__ALPHA_THERM__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
57197 #define TPC_19__ALPHA_THERM__MODIFY(dst, src) \
57199 ~0x000000ffU) | ((u_int32_t)(src) &\
57201 #define TPC_19__ALPHA_THERM__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
57207 #define TPC_19__ALPHA_THERM_PAL_ON__READ(src) \
57208 (((u_int32_t)(src)\
57210 #define TPC_19__ALPHA_THERM_PAL_ON__WRITE(src) \
57211 (((u_int32_t)(src)\
57213 #define TPC_19__ALPHA_THERM_PAL_ON__MODIFY(dst, src) \
57215 ~0x0000ff00U) | (((u_int32_t)(src) <<\
57217 #define TPC_19__ALPHA_THERM_PAL_ON__VERIFY(src) \
57218 (!((((u_int32_t)(src)\
57225 #define TPC_19__ALPHA_VOLT__READ(src) (((u_int32_t)(src) & 0x001f0000U) >> 16)
57226 #define TPC_19__ALPHA_VOLT__WRITE(src) (((u_int32_t)(src) << 16) & 0x001f0000U)
57227 #define TPC_19__ALPHA_VOLT__MODIFY(dst, src) \
57229 ~0x001f0000U) | (((u_int32_t)(src) <<\
57231 #define TPC_19__ALPHA_VOLT__VERIFY(src) \
57232 (!((((u_int32_t)(src)\
57239 #define TPC_19__ALPHA_VOLT_PAL_ON__READ(src) \
57240 (((u_int32_t)(src)\
57242 #define TPC_19__ALPHA_VOLT_PAL_ON__WRITE(src) \
57243 (((u_int32_t)(src)\
57245 #define TPC_19__ALPHA_VOLT_PAL_ON__MODIFY(dst, src) \
57247 ~0x03e00000U) | (((u_int32_t)(src) <<\
57249 #define TPC_19__ALPHA_VOLT_PAL_ON__VERIFY(src) \
57250 (!((((u_int32_t)(src)\
57270 #define TPC_20__ENABLE_PAL_MCS_0__READ(src) (u_int32_t)(src) & 0x00000001U
57271 #define TPC_20__ENABLE_PAL_MCS_0__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
57272 #define TPC_20__ENABLE_PAL_MCS_0__MODIFY(dst, src) \
57274 ~0x00000001U) | ((u_int32_t)(src) &\
57276 #define TPC_20__ENABLE_PAL_MCS_0__VERIFY(src) \
57277 (!(((u_int32_t)(src)\
57290 #define TPC_20__ENABLE_PAL_MCS_1__READ(src) \
57291 (((u_int32_t)(src)\
57293 #define TPC_20__ENABLE_PAL_MCS_1__WRITE(src) \
57294 (((u_int32_t)(src)\
57296 #define TPC_20__ENABLE_PAL_MCS_1__MODIFY(dst, src) \
57298 ~0x00000002U) | (((u_int32_t)(src) <<\
57300 #define TPC_20__ENABLE_PAL_MCS_1__VERIFY(src) \
57301 (!((((u_int32_t)(src)\
57314 #define TPC_20__ENABLE_PAL_MCS_2__READ(src) \
57315 (((u_int32_t)(src)\
57317 #define TPC_20__ENABLE_PAL_MCS_2__WRITE(src) \
57318 (((u_int32_t)(src)\
57320 #define TPC_20__ENABLE_PAL_MCS_2__MODIFY(dst, src) \
57322 ~0x00000004U) | (((u_int32_t)(src) <<\
57324 #define TPC_20__ENABLE_PAL_MCS_2__VERIFY(src) \
57325 (!((((u_int32_t)(src)\
57338 #define TPC_20__ENABLE_PAL_MCS_3__READ(src) \
57339 (((u_int32_t)(src)\
57341 #define TPC_20__ENABLE_PAL_MCS_3__WRITE(src) \
57342 (((u_int32_t)(src)\
57344 #define TPC_20__ENABLE_PAL_MCS_3__MODIFY(dst, src) \
57346 ~0x00000008U) | (((u_int32_t)(src) <<\
57348 #define TPC_20__ENABLE_PAL_MCS_3__VERIFY(src) \
57349 (!((((u_int32_t)(src)\
57362 #define TPC_20__ENABLE_PAL_MCS_4__READ(src) \
57363 (((u_int32_t)(src)\
57365 #define TPC_20__ENABLE_PAL_MCS_4__WRITE(src) \
57366 (((u_int32_t)(src)\
57368 #define TPC_20__ENABLE_PAL_MCS_4__MODIFY(dst, src) \
57370 ~0x00000010U) | (((u_int32_t)(src) <<\
57372 #define TPC_20__ENABLE_PAL_MCS_4__VERIFY(src) \
57373 (!((((u_int32_t)(src)\
57386 #define TPC_20__ENABLE_PAL_MCS_5__READ(src) \
57387 (((u_int32_t)(src)\
57389 #define TPC_20__ENABLE_PAL_MCS_5__WRITE(src) \
57390 (((u_int32_t)(src)\
57392 #define TPC_20__ENABLE_PAL_MCS_5__MODIFY(dst, src) \
57394 ~0x00000020U) | (((u_int32_t)(src) <<\
57396 #define TPC_20__ENABLE_PAL_MCS_5__VERIFY(src) \
57397 (!((((u_int32_t)(src)\
57410 #define TPC_20__ENABLE_PAL_MCS_6__READ(src) \
57411 (((u_int32_t)(src)\
57413 #define TPC_20__ENABLE_PAL_MCS_6__WRITE(src) \
57414 (((u_int32_t)(src)\
57416 #define TPC_20__ENABLE_PAL_MCS_6__MODIFY(dst, src) \
57418 ~0x00000040U) | (((u_int32_t)(src) <<\
57420 #define TPC_20__ENABLE_PAL_MCS_6__VERIFY(src) \
57421 (!((((u_int32_t)(src)\
57434 #define TPC_20__ENABLE_PAL_MCS_7__READ(src) \
57435 (((u_int32_t)(src)\
57437 #define TPC_20__ENABLE_PAL_MCS_7__WRITE(src) \
57438 (((u_int32_t)(src)\
57440 #define TPC_20__ENABLE_PAL_MCS_7__MODIFY(dst, src) \
57442 ~0x00000080U) | (((u_int32_t)(src) <<\
57444 #define TPC_20__ENABLE_PAL_MCS_7__VERIFY(src) \
57445 (!((((u_int32_t)(src)\
57458 #define TPC_20__ENABLE_PAL_MCS_8__READ(src) \
57459 (((u_int32_t)(src)\
57461 #define TPC_20__ENABLE_PAL_MCS_8__WRITE(src) \
57462 (((u_int32_t)(src)\
57464 #define TPC_20__ENABLE_PAL_MCS_8__MODIFY(dst, src) \
57466 ~0x00000100U) | (((u_int32_t)(src) <<\
57468 #define TPC_20__ENABLE_PAL_MCS_8__VERIFY(src) \
57469 (!((((u_int32_t)(src)\
57482 #define TPC_20__ENABLE_PAL_MCS_9__READ(src) \
57483 (((u_int32_t)(src)\
57485 #define TPC_20__ENABLE_PAL_MCS_9__WRITE(src) \
57486 (((u_int32_t)(src)\
57488 #define TPC_20__ENABLE_PAL_MCS_9__MODIFY(dst, src) \
57490 ~0x00000200U) | (((u_int32_t)(src) <<\
57492 #define TPC_20__ENABLE_PAL_MCS_9__VERIFY(src) \
57493 (!((((u_int32_t)(src)\
57506 #define TPC_20__ENABLE_PAL_MCS_10__READ(src) \
57507 (((u_int32_t)(src)\
57509 #define TPC_20__ENABLE_PAL_MCS_10__WRITE(src) \
57510 (((u_int32_t)(src)\
57512 #define TPC_20__ENABLE_PAL_MCS_10__MODIFY(dst, src) \
57514 ~0x00000400U) | (((u_int32_t)(src) <<\
57516 #define TPC_20__ENABLE_PAL_MCS_10__VERIFY(src) \
57517 (!((((u_int32_t)(src)\
57530 #define TPC_20__ENABLE_PAL_MCS_11__READ(src) \
57531 (((u_int32_t)(src)\
57533 #define TPC_20__ENABLE_PAL_MCS_11__WRITE(src) \
57534 (((u_int32_t)(src)\
57536 #define TPC_20__ENABLE_PAL_MCS_11__MODIFY(dst, src) \
57538 ~0x00000800U) | (((u_int32_t)(src) <<\
57540 #define TPC_20__ENABLE_PAL_MCS_11__VERIFY(src) \
57541 (!((((u_int32_t)(src)\
57554 #define TPC_20__ENABLE_PAL_MCS_12__READ(src) \
57555 (((u_int32_t)(src)\
57557 #define TPC_20__ENABLE_PAL_MCS_12__WRITE(src) \
57558 (((u_int32_t)(src)\
57560 #define TPC_20__ENABLE_PAL_MCS_12__MODIFY(dst, src) \
57562 ~0x00001000U) | (((u_int32_t)(src) <<\
57564 #define TPC_20__ENABLE_PAL_MCS_12__VERIFY(src) \
57565 (!((((u_int32_t)(src)\
57578 #define TPC_20__ENABLE_PAL_MCS_13__READ(src) \
57579 (((u_int32_t)(src)\
57581 #define TPC_20__ENABLE_PAL_MCS_13__WRITE(src) \
57582 (((u_int32_t)(src)\
57584 #define TPC_20__ENABLE_PAL_MCS_13__MODIFY(dst, src) \
57586 ~0x00002000U) | (((u_int32_t)(src) <<\
57588 #define TPC_20__ENABLE_PAL_MCS_13__VERIFY(src) \
57589 (!((((u_int32_t)(src)\
57602 #define TPC_20__ENABLE_PAL_MCS_14__READ(src) \
57603 (((u_int32_t)(src)\
57605 #define TPC_20__ENABLE_PAL_MCS_14__WRITE(src) \
57606 (((u_int32_t)(src)\
57608 #define TPC_20__ENABLE_PAL_MCS_14__MODIFY(dst, src) \
57610 ~0x00004000U) | (((u_int32_t)(src) <<\
57612 #define TPC_20__ENABLE_PAL_MCS_14__VERIFY(src) \
57613 (!((((u_int32_t)(src)\
57626 #define TPC_20__ENABLE_PAL_MCS_15__READ(src) \
57627 (((u_int32_t)(src)\
57629 #define TPC_20__ENABLE_PAL_MCS_15__WRITE(src) \
57630 (((u_int32_t)(src)\
57632 #define TPC_20__ENABLE_PAL_MCS_15__MODIFY(dst, src) \
57634 ~0x00008000U) | (((u_int32_t)(src) <<\
57636 #define TPC_20__ENABLE_PAL_MCS_15__VERIFY(src) \
57637 (!((((u_int32_t)(src)\
57650 #define TPC_20__ENABLE_PAL_MCS_16__READ(src) \
57651 (((u_int32_t)(src)\
57653 #define TPC_20__ENABLE_PAL_MCS_16__WRITE(src) \
57654 (((u_int32_t)(src)\
57656 #define TPC_20__ENABLE_PAL_MCS_16__MODIFY(dst, src) \
57658 ~0x00010000U) | (((u_int32_t)(src) <<\
57660 #define TPC_20__ENABLE_PAL_MCS_16__VERIFY(src) \
57661 (!((((u_int32_t)(src)\
57674 #define TPC_20__ENABLE_PAL_MCS_17__READ(src) \
57675 (((u_int32_t)(src)\
57677 #define TPC_20__ENABLE_PAL_MCS_17__WRITE(src) \
57678 (((u_int32_t)(src)\
57680 #define TPC_20__ENABLE_PAL_MCS_17__MODIFY(dst, src) \
57682 ~0x00020000U) | (((u_int32_t)(src) <<\
57684 #define TPC_20__ENABLE_PAL_MCS_17__VERIFY(src) \
57685 (!((((u_int32_t)(src)\
57698 #define TPC_20__ENABLE_PAL_MCS_18__READ(src) \
57699 (((u_int32_t)(src)\
57701 #define TPC_20__ENABLE_PAL_MCS_18__WRITE(src) \
57702 (((u_int32_t)(src)\
57704 #define TPC_20__ENABLE_PAL_MCS_18__MODIFY(dst, src) \
57706 ~0x00040000U) | (((u_int32_t)(src) <<\
57708 #define TPC_20__ENABLE_PAL_MCS_18__VERIFY(src) \
57709 (!((((u_int32_t)(src)\
57722 #define TPC_20__ENABLE_PAL_MCS_19__READ(src) \
57723 (((u_int32_t)(src)\
57725 #define TPC_20__ENABLE_PAL_MCS_19__WRITE(src) \
57726 (((u_int32_t)(src)\
57728 #define TPC_20__ENABLE_PAL_MCS_19__MODIFY(dst, src) \
57730 ~0x00080000U) | (((u_int32_t)(src) <<\
57732 #define TPC_20__ENABLE_PAL_MCS_19__VERIFY(src) \
57733 (!((((u_int32_t)(src)\
57746 #define TPC_20__ENABLE_PAL_MCS_20__READ(src) \
57747 (((u_int32_t)(src)\
57749 #define TPC_20__ENABLE_PAL_MCS_20__WRITE(src) \
57750 (((u_int32_t)(src)\
57752 #define TPC_20__ENABLE_PAL_MCS_20__MODIFY(dst, src) \
57754 ~0x00100000U) | (((u_int32_t)(src) <<\
57756 #define TPC_20__ENABLE_PAL_MCS_20__VERIFY(src) \
57757 (!((((u_int32_t)(src)\
57770 #define TPC_20__ENABLE_PAL_MCS_21__READ(src) \
57771 (((u_int32_t)(src)\
57773 #define TPC_20__ENABLE_PAL_MCS_21__WRITE(src) \
57774 (((u_int32_t)(src)\
57776 #define TPC_20__ENABLE_PAL_MCS_21__MODIFY(dst, src) \
57778 ~0x00200000U) | (((u_int32_t)(src) <<\
57780 #define TPC_20__ENABLE_PAL_MCS_21__VERIFY(src) \
57781 (!((((u_int32_t)(src)\
57794 #define TPC_20__ENABLE_PAL_MCS_22__READ(src) \
57795 (((u_int32_t)(src)\
57797 #define TPC_20__ENABLE_PAL_MCS_22__WRITE(src) \
57798 (((u_int32_t)(src)\
57800 #define TPC_20__ENABLE_PAL_MCS_22__MODIFY(dst, src) \
57802 ~0x00400000U) | (((u_int32_t)(src) <<\
57804 #define TPC_20__ENABLE_PAL_MCS_22__VERIFY(src) \
57805 (!((((u_int32_t)(src)\
57818 #define TPC_20__ENABLE_PAL_MCS_23__READ(src) \
57819 (((u_int32_t)(src)\
57821 #define TPC_20__ENABLE_PAL_MCS_23__WRITE(src) \
57822 (((u_int32_t)(src)\
57824 #define TPC_20__ENABLE_PAL_MCS_23__MODIFY(dst, src) \
57826 ~0x00800000U) | (((u_int32_t)(src) <<\
57828 #define TPC_20__ENABLE_PAL_MCS_23__VERIFY(src) \
57829 (!((((u_int32_t)(src)\
57855 #define THERM_ADC_1__INIT_THERM_SETTING__READ(src) \
57856 (u_int32_t)(src)\
57858 #define THERM_ADC_1__INIT_THERM_SETTING__WRITE(src) \
57859 ((u_int32_t)(src)\
57861 #define THERM_ADC_1__INIT_THERM_SETTING__MODIFY(dst, src) \
57863 ~0x000000ffU) | ((u_int32_t)(src) &\
57865 #define THERM_ADC_1__INIT_THERM_SETTING__VERIFY(src) \
57866 (!(((u_int32_t)(src)\
57873 #define THERM_ADC_1__INIT_VOLT_SETTING__READ(src) \
57874 (((u_int32_t)(src)\
57876 #define THERM_ADC_1__INIT_VOLT_SETTING__WRITE(src) \
57877 (((u_int32_t)(src)\
57879 #define THERM_ADC_1__INIT_VOLT_SETTING__MODIFY(dst, src) \
57881 ~0x0000ff00U) | (((u_int32_t)(src) <<\
57883 #define THERM_ADC_1__INIT_VOLT_SETTING__VERIFY(src) \
57884 (!((((u_int32_t)(src)\
57891 #define THERM_ADC_1__INIT_ATB_SETTING__READ(src) \
57892 (((u_int32_t)(src)\
57894 #define THERM_ADC_1__INIT_ATB_SETTING__WRITE(src) \
57895 (((u_int32_t)(src)\
57897 #define THERM_ADC_1__INIT_ATB_SETTING__MODIFY(dst, src) \
57899 ~0x00ff0000U) | (((u_int32_t)(src) <<\
57901 #define THERM_ADC_1__INIT_ATB_SETTING__VERIFY(src) \
57902 (!((((u_int32_t)(src)\
57909 #define THERM_ADC_1__SAMPLES_CNT_CODING__READ(src) \
57910 (((u_int32_t)(src)\
57912 #define THERM_ADC_1__SAMPLES_CNT_CODING__WRITE(src) \
57913 (((u_int32_t)(src)\
57915 #define THERM_ADC_1__SAMPLES_CNT_CODING__MODIFY(dst, src) \
57917 ~0x03000000U) | (((u_int32_t)(src) <<\
57919 #define THERM_ADC_1__SAMPLES_CNT_CODING__VERIFY(src) \
57920 (!((((u_int32_t)(src)\
57927 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__READ(src) \
57928 (((u_int32_t)(src)\
57930 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__WRITE(src) \
57931 (((u_int32_t)(src)\
57933 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__MODIFY(dst, src) \
57935 ~0x04000000U) | (((u_int32_t)(src) <<\
57937 #define THERM_ADC_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET__VERIFY(src) \
57938 (!((((u_int32_t)(src)\
57951 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__READ(src) \
57952 (((u_int32_t)(src)\
57954 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__WRITE(src) \
57955 (((u_int32_t)(src)\
57957 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__MODIFY(dst, src) \
57959 ~0x08000000U) | (((u_int32_t)(src) <<\
57961 #define THERM_ADC_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS__VERIFY(src) \
57962 (!((((u_int32_t)(src)\
57988 #define THERM_ADC_2__MEASURE_THERM_FREQ__READ(src) \
57989 (u_int32_t)(src)\
57991 #define THERM_ADC_2__MEASURE_THERM_FREQ__WRITE(src) \
57992 ((u_int32_t)(src)\
57994 #define THERM_ADC_2__MEASURE_THERM_FREQ__MODIFY(dst, src) \
57996 ~0x00000fffU) | ((u_int32_t)(src) &\
57998 #define THERM_ADC_2__MEASURE_THERM_FREQ__VERIFY(src) \
57999 (!(((u_int32_t)(src)\
58006 #define THERM_ADC_2__MEASURE_VOLT_FREQ__READ(src) \
58007 (((u_int32_t)(src)\
58009 #define THERM_ADC_2__MEASURE_VOLT_FREQ__WRITE(src) \
58010 (((u_int32_t)(src)\
58012 #define THERM_ADC_2__MEASURE_VOLT_FREQ__MODIFY(dst, src) \
58014 ~0x003ff000U) | (((u_int32_t)(src) <<\
58016 #define THERM_ADC_2__MEASURE_VOLT_FREQ__VERIFY(src) \
58017 (!((((u_int32_t)(src)\
58024 #define THERM_ADC_2__MEASURE_ATB_FREQ__READ(src) \
58025 (((u_int32_t)(src)\
58027 #define THERM_ADC_2__MEASURE_ATB_FREQ__WRITE(src) \
58028 (((u_int32_t)(src)\
58030 #define THERM_ADC_2__MEASURE_ATB_FREQ__MODIFY(dst, src) \
58032 ~0xffc00000U) | (((u_int32_t)(src) <<\
58034 #define THERM_ADC_2__MEASURE_ATB_FREQ__VERIFY(src) \
58035 (!((((u_int32_t)(src)\
58055 #define THERM_ADC_3__THERM_ADC_OFFSET__READ(src) (u_int32_t)(src) & 0x000000ffU
58056 #define THERM_ADC_3__THERM_ADC_OFFSET__WRITE(src) \
58057 ((u_int32_t)(src)\
58059 #define THERM_ADC_3__THERM_ADC_OFFSET__MODIFY(dst, src) \
58061 ~0x000000ffU) | ((u_int32_t)(src) &\
58063 #define THERM_ADC_3__THERM_ADC_OFFSET__VERIFY(src) \
58064 (!(((u_int32_t)(src)\
58071 #define THERM_ADC_3__THERM_ADC_SCALED_GAIN__READ(src) \
58072 (((u_int32_t)(src)\
58074 #define THERM_ADC_3__THERM_ADC_SCALED_GAIN__WRITE(src) \
58075 (((u_int32_t)(src)\
58077 #define THERM_ADC_3__THERM_ADC_SCALED_GAIN__MODIFY(dst, src) \
58079 ~0x0001ff00U) | (((u_int32_t)(src) <<\
58081 #define THERM_ADC_3__THERM_ADC_SCALED_GAIN__VERIFY(src) \
58082 (!((((u_int32_t)(src)\
58089 #define THERM_ADC_3__ADC_INTERVAL__READ(src) \
58090 (((u_int32_t)(src)\
58092 #define THERM_ADC_3__ADC_INTERVAL__WRITE(src) \
58093 (((u_int32_t)(src)\
58095 #define THERM_ADC_3__ADC_INTERVAL__MODIFY(dst, src) \
58097 ~0x3ffe0000U) | (((u_int32_t)(src) <<\
58099 #define THERM_ADC_3__ADC_INTERVAL__VERIFY(src) \
58100 (!((((u_int32_t)(src)\
58120 #define THERM_ADC_4__LATEST_THERM_VALUE__READ(src) \
58121 (u_int32_t)(src)\
58128 #define THERM_ADC_4__LATEST_VOLT_VALUE__READ(src) \
58129 (((u_int32_t)(src)\
58136 #define THERM_ADC_4__LATEST_ATB_VALUE__READ(src) \
58137 (((u_int32_t)(src)\
58156 #define TX_FORCED_GAIN__FORCE_TX_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U
58157 #define TX_FORCED_GAIN__FORCE_TX_GAIN__WRITE(src) \
58158 ((u_int32_t)(src)\
58160 #define TX_FORCED_GAIN__FORCE_TX_GAIN__MODIFY(dst, src) \
58162 ~0x00000001U) | ((u_int32_t)(src) &\
58164 #define TX_FORCED_GAIN__FORCE_TX_GAIN__VERIFY(src) \
58165 (!(((u_int32_t)(src)\
58178 #define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__READ(src) \
58179 (((u_int32_t)(src)\
58181 #define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__WRITE(src) \
58182 (((u_int32_t)(src)\
58184 #define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__MODIFY(dst, src) \
58186 ~0x0000000eU) | (((u_int32_t)(src) <<\
58188 #define TX_FORCED_GAIN__FORCED_TXBB1DBGAIN__VERIFY(src) \
58189 (!((((u_int32_t)(src)\
58196 #define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__READ(src) \
58197 (((u_int32_t)(src)\
58199 #define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__WRITE(src) \
58200 (((u_int32_t)(src)\
58202 #define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__MODIFY(dst, src) \
58204 ~0x00000030U) | (((u_int32_t)(src) <<\
58206 #define TX_FORCED_GAIN__FORCED_TXBB6DBGAIN__VERIFY(src) \
58207 (!((((u_int32_t)(src)\
58214 #define TX_FORCED_GAIN__FORCED_TXMXRGAIN__READ(src) \
58215 (((u_int32_t)(src)\
58217 #define TX_FORCED_GAIN__FORCED_TXMXRGAIN__WRITE(src) \
58218 (((u_int32_t)(src)\
58220 #define TX_FORCED_GAIN__FORCED_TXMXRGAIN__MODIFY(dst, src) \
58222 ~0x000003c0U) | (((u_int32_t)(src) <<\
58224 #define TX_FORCED_GAIN__FORCED_TXMXRGAIN__VERIFY(src) \
58225 (!((((u_int32_t)(src)\
58232 #define TX_FORCED_GAIN__FORCED_PADRVGNA__READ(src) \
58233 (((u_int32_t)(src)\
58235 #define TX_FORCED_GAIN__FORCED_PADRVGNA__WRITE(src) \
58236 (((u_int32_t)(src)\
58238 #define TX_FORCED_GAIN__FORCED_PADRVGNA__MODIFY(dst, src) \
58240 ~0x00003c00U) | (((u_int32_t)(src) <<\
58242 #define TX_FORCED_GAIN__FORCED_PADRVGNA__VERIFY(src) \
58243 (!((((u_int32_t)(src)\
58250 #define TX_FORCED_GAIN__FORCED_PADRVGNB__READ(src) \
58251 (((u_int32_t)(src)\
58253 #define TX_FORCED_GAIN__FORCED_PADRVGNB__WRITE(src) \
58254 (((u_int32_t)(src)\
58256 #define TX_FORCED_GAIN__FORCED_PADRVGNB__MODIFY(dst, src) \
58258 ~0x0003c000U) | (((u_int32_t)(src) <<\
58260 #define TX_FORCED_GAIN__FORCED_PADRVGNB__VERIFY(src) \
58261 (!((((u_int32_t)(src)\
58268 #define TX_FORCED_GAIN__FORCED_PADRVGNC__READ(src) \
58269 (((u_int32_t)(src)\
58271 #define TX_FORCED_GAIN__FORCED_PADRVGNC__WRITE(src) \
58272 (((u_int32_t)(src)\
58274 #define TX_FORCED_GAIN__FORCED_PADRVGNC__MODIFY(dst, src) \
58276 ~0x003c0000U) | (((u_int32_t)(src) <<\
58278 #define TX_FORCED_GAIN__FORCED_PADRVGNC__VERIFY(src) \
58279 (!((((u_int32_t)(src)\
58286 #define TX_FORCED_GAIN__FORCED_PADRVGND__READ(src) \
58287 (((u_int32_t)(src)\
58289 #define TX_FORCED_GAIN__FORCED_PADRVGND__WRITE(src) \
58290 (((u_int32_t)(src)\
58292 #define TX_FORCED_GAIN__FORCED_PADRVGND__MODIFY(dst, src) \
58294 ~0x00c00000U) | (((u_int32_t)(src) <<\
58296 #define TX_FORCED_GAIN__FORCED_PADRVGND__VERIFY(src) \
58297 (!((((u_int32_t)(src)\
58304 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__READ(src) \
58305 (((u_int32_t)(src)\
58307 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__WRITE(src) \
58308 (((u_int32_t)(src)\
58310 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__MODIFY(dst, src) \
58312 ~0x01000000U) | (((u_int32_t)(src) <<\
58314 #define TX_FORCED_GAIN__FORCED_ENABLE_PAL__VERIFY(src) \
58315 (!((((u_int32_t)(src)\
58341 #define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58342 #define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
58344 ~0xffffffffU) | ((u_int32_t)(src) &\
58346 #define PDADC_TAB__TAB_ENTRY__VERIFY(src) \
58347 (!(((u_int32_t)(src)\
58366 #define TX_GAIN_TAB_1__TG_TABLE1__READ(src) (u_int32_t)(src) & 0xffffffffU
58367 #define TX_GAIN_TAB_1__TG_TABLE1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58368 #define TX_GAIN_TAB_1__TG_TABLE1__MODIFY(dst, src) \
58370 ~0xffffffffU) | ((u_int32_t)(src) &\
58372 #define TX_GAIN_TAB_1__TG_TABLE1__VERIFY(src) \
58373 (!(((u_int32_t)(src)\
58393 #define TX_GAIN_TAB_2__TG_TABLE2__READ(src) (u_int32_t)(src) & 0xffffffffU
58394 #define TX_GAIN_TAB_2__TG_TABLE2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58395 #define TX_GAIN_TAB_2__TG_TABLE2__MODIFY(dst, src) \
58397 ~0xffffffffU) | ((u_int32_t)(src) &\
58399 #define TX_GAIN_TAB_2__TG_TABLE2__VERIFY(src) \
58400 (!(((u_int32_t)(src)\
58420 #define TX_GAIN_TAB_3__TG_TABLE3__READ(src) (u_int32_t)(src) & 0xffffffffU
58421 #define TX_GAIN_TAB_3__TG_TABLE3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58422 #define TX_GAIN_TAB_3__TG_TABLE3__MODIFY(dst, src) \
58424 ~0xffffffffU) | ((u_int32_t)(src) &\
58426 #define TX_GAIN_TAB_3__TG_TABLE3__VERIFY(src) \
58427 (!(((u_int32_t)(src)\
58447 #define TX_GAIN_TAB_4__TG_TABLE4__READ(src) (u_int32_t)(src) & 0xffffffffU
58448 #define TX_GAIN_TAB_4__TG_TABLE4__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58449 #define TX_GAIN_TAB_4__TG_TABLE4__MODIFY(dst, src) \
58451 ~0xffffffffU) | ((u_int32_t)(src) &\
58453 #define TX_GAIN_TAB_4__TG_TABLE4__VERIFY(src) \
58454 (!(((u_int32_t)(src)\
58474 #define TX_GAIN_TAB_5__TG_TABLE5__READ(src) (u_int32_t)(src) & 0xffffffffU
58475 #define TX_GAIN_TAB_5__TG_TABLE5__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58476 #define TX_GAIN_TAB_5__TG_TABLE5__MODIFY(dst, src) \
58478 ~0xffffffffU) | ((u_int32_t)(src) &\
58480 #define TX_GAIN_TAB_5__TG_TABLE5__VERIFY(src) \
58481 (!(((u_int32_t)(src)\
58501 #define TX_GAIN_TAB_6__TG_TABLE6__READ(src) (u_int32_t)(src) & 0xffffffffU
58502 #define TX_GAIN_TAB_6__TG_TABLE6__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58503 #define TX_GAIN_TAB_6__TG_TABLE6__MODIFY(dst, src) \
58505 ~0xffffffffU) | ((u_int32_t)(src) &\
58507 #define TX_GAIN_TAB_6__TG_TABLE6__VERIFY(src) \
58508 (!(((u_int32_t)(src)\
58528 #define TX_GAIN_TAB_7__TG_TABLE7__READ(src) (u_int32_t)(src) & 0xffffffffU
58529 #define TX_GAIN_TAB_7__TG_TABLE7__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58530 #define TX_GAIN_TAB_7__TG_TABLE7__MODIFY(dst, src) \
58532 ~0xffffffffU) | ((u_int32_t)(src) &\
58534 #define TX_GAIN_TAB_7__TG_TABLE7__VERIFY(src) \
58535 (!(((u_int32_t)(src)\
58555 #define TX_GAIN_TAB_8__TG_TABLE8__READ(src) (u_int32_t)(src) & 0xffffffffU
58556 #define TX_GAIN_TAB_8__TG_TABLE8__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58557 #define TX_GAIN_TAB_8__TG_TABLE8__MODIFY(dst, src) \
58559 ~0xffffffffU) | ((u_int32_t)(src) &\
58561 #define TX_GAIN_TAB_8__TG_TABLE8__VERIFY(src) \
58562 (!(((u_int32_t)(src)\
58582 #define TX_GAIN_TAB_9__TG_TABLE9__READ(src) (u_int32_t)(src) & 0xffffffffU
58583 #define TX_GAIN_TAB_9__TG_TABLE9__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58584 #define TX_GAIN_TAB_9__TG_TABLE9__MODIFY(dst, src) \
58586 ~0xffffffffU) | ((u_int32_t)(src) &\
58588 #define TX_GAIN_TAB_9__TG_TABLE9__VERIFY(src) \
58589 (!(((u_int32_t)(src)\
58609 #define TX_GAIN_TAB_10__TG_TABLE10__READ(src) (u_int32_t)(src) & 0xffffffffU
58610 #define TX_GAIN_TAB_10__TG_TABLE10__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58611 #define TX_GAIN_TAB_10__TG_TABLE10__MODIFY(dst, src) \
58613 ~0xffffffffU) | ((u_int32_t)(src) &\
58615 #define TX_GAIN_TAB_10__TG_TABLE10__VERIFY(src) \
58616 (!(((u_int32_t)(src)\
58636 #define TX_GAIN_TAB_11__TG_TABLE11__READ(src) (u_int32_t)(src) & 0xffffffffU
58637 #define TX_GAIN_TAB_11__TG_TABLE11__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58638 #define TX_GAIN_TAB_11__TG_TABLE11__MODIFY(dst, src) \
58640 ~0xffffffffU) | ((u_int32_t)(src) &\
58642 #define TX_GAIN_TAB_11__TG_TABLE11__VERIFY(src) \
58643 (!(((u_int32_t)(src)\
58663 #define TX_GAIN_TAB_12__TG_TABLE12__READ(src) (u_int32_t)(src) & 0xffffffffU
58664 #define TX_GAIN_TAB_12__TG_TABLE12__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58665 #define TX_GAIN_TAB_12__TG_TABLE12__MODIFY(dst, src) \
58667 ~0xffffffffU) | ((u_int32_t)(src) &\
58669 #define TX_GAIN_TAB_12__TG_TABLE12__VERIFY(src) \
58670 (!(((u_int32_t)(src)\
58690 #define TX_GAIN_TAB_13__TG_TABLE13__READ(src) (u_int32_t)(src) & 0xffffffffU
58691 #define TX_GAIN_TAB_13__TG_TABLE13__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58692 #define TX_GAIN_TAB_13__TG_TABLE13__MODIFY(dst, src) \
58694 ~0xffffffffU) | ((u_int32_t)(src) &\
58696 #define TX_GAIN_TAB_13__TG_TABLE13__VERIFY(src) \
58697 (!(((u_int32_t)(src)\
58717 #define TX_GAIN_TAB_14__TG_TABLE14__READ(src) (u_int32_t)(src) & 0xffffffffU
58718 #define TX_GAIN_TAB_14__TG_TABLE14__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58719 #define TX_GAIN_TAB_14__TG_TABLE14__MODIFY(dst, src) \
58721 ~0xffffffffU) | ((u_int32_t)(src) &\
58723 #define TX_GAIN_TAB_14__TG_TABLE14__VERIFY(src) \
58724 (!(((u_int32_t)(src)\
58744 #define TX_GAIN_TAB_15__TG_TABLE15__READ(src) (u_int32_t)(src) & 0xffffffffU
58745 #define TX_GAIN_TAB_15__TG_TABLE15__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58746 #define TX_GAIN_TAB_15__TG_TABLE15__MODIFY(dst, src) \
58748 ~0xffffffffU) | ((u_int32_t)(src) &\
58750 #define TX_GAIN_TAB_15__TG_TABLE15__VERIFY(src) \
58751 (!(((u_int32_t)(src)\
58771 #define TX_GAIN_TAB_16__TG_TABLE16__READ(src) (u_int32_t)(src) & 0xffffffffU
58772 #define TX_GAIN_TAB_16__TG_TABLE16__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58773 #define TX_GAIN_TAB_16__TG_TABLE16__MODIFY(dst, src) \
58775 ~0xffffffffU) | ((u_int32_t)(src) &\
58777 #define TX_GAIN_TAB_16__TG_TABLE16__VERIFY(src) \
58778 (!(((u_int32_t)(src)\
58798 #define TX_GAIN_TAB_17__TG_TABLE17__READ(src) (u_int32_t)(src) & 0xffffffffU
58799 #define TX_GAIN_TAB_17__TG_TABLE17__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58800 #define TX_GAIN_TAB_17__TG_TABLE17__MODIFY(dst, src) \
58802 ~0xffffffffU) | ((u_int32_t)(src) &\
58804 #define TX_GAIN_TAB_17__TG_TABLE17__VERIFY(src) \
58805 (!(((u_int32_t)(src)\
58825 #define TX_GAIN_TAB_18__TG_TABLE18__READ(src) (u_int32_t)(src) & 0xffffffffU
58826 #define TX_GAIN_TAB_18__TG_TABLE18__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58827 #define TX_GAIN_TAB_18__TG_TABLE18__MODIFY(dst, src) \
58829 ~0xffffffffU) | ((u_int32_t)(src) &\
58831 #define TX_GAIN_TAB_18__TG_TABLE18__VERIFY(src) \
58832 (!(((u_int32_t)(src)\
58852 #define TX_GAIN_TAB_19__TG_TABLE19__READ(src) (u_int32_t)(src) & 0xffffffffU
58853 #define TX_GAIN_TAB_19__TG_TABLE19__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58854 #define TX_GAIN_TAB_19__TG_TABLE19__MODIFY(dst, src) \
58856 ~0xffffffffU) | ((u_int32_t)(src) &\
58858 #define TX_GAIN_TAB_19__TG_TABLE19__VERIFY(src) \
58859 (!(((u_int32_t)(src)\
58879 #define TX_GAIN_TAB_20__TG_TABLE20__READ(src) (u_int32_t)(src) & 0xffffffffU
58880 #define TX_GAIN_TAB_20__TG_TABLE20__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58881 #define TX_GAIN_TAB_20__TG_TABLE20__MODIFY(dst, src) \
58883 ~0xffffffffU) | ((u_int32_t)(src) &\
58885 #define TX_GAIN_TAB_20__TG_TABLE20__VERIFY(src) \
58886 (!(((u_int32_t)(src)\
58906 #define TX_GAIN_TAB_21__TG_TABLE21__READ(src) (u_int32_t)(src) & 0xffffffffU
58907 #define TX_GAIN_TAB_21__TG_TABLE21__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58908 #define TX_GAIN_TAB_21__TG_TABLE21__MODIFY(dst, src) \
58910 ~0xffffffffU) | ((u_int32_t)(src) &\
58912 #define TX_GAIN_TAB_21__TG_TABLE21__VERIFY(src) \
58913 (!(((u_int32_t)(src)\
58933 #define TX_GAIN_TAB_22__TG_TABLE22__READ(src) (u_int32_t)(src) & 0xffffffffU
58934 #define TX_GAIN_TAB_22__TG_TABLE22__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58935 #define TX_GAIN_TAB_22__TG_TABLE22__MODIFY(dst, src) \
58937 ~0xffffffffU) | ((u_int32_t)(src) &\
58939 #define TX_GAIN_TAB_22__TG_TABLE22__VERIFY(src) \
58940 (!(((u_int32_t)(src)\
58960 #define TX_GAIN_TAB_23__TG_TABLE23__READ(src) (u_int32_t)(src) & 0xffffffffU
58961 #define TX_GAIN_TAB_23__TG_TABLE23__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58962 #define TX_GAIN_TAB_23__TG_TABLE23__MODIFY(dst, src) \
58964 ~0xffffffffU) | ((u_int32_t)(src) &\
58966 #define TX_GAIN_TAB_23__TG_TABLE23__VERIFY(src) \
58967 (!(((u_int32_t)(src)\
58987 #define TX_GAIN_TAB_24__TG_TABLE24__READ(src) (u_int32_t)(src) & 0xffffffffU
58988 #define TX_GAIN_TAB_24__TG_TABLE24__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
58989 #define TX_GAIN_TAB_24__TG_TABLE24__MODIFY(dst, src) \
58991 ~0xffffffffU) | ((u_int32_t)(src) &\
58993 #define TX_GAIN_TAB_24__TG_TABLE24__VERIFY(src) \
58994 (!(((u_int32_t)(src)\
59014 #define TX_GAIN_TAB_25__TG_TABLE25__READ(src) (u_int32_t)(src) & 0xffffffffU
59015 #define TX_GAIN_TAB_25__TG_TABLE25__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
59016 #define TX_GAIN_TAB_25__TG_TABLE25__MODIFY(dst, src) \
59018 ~0xffffffffU) | ((u_int32_t)(src) &\
59020 #define TX_GAIN_TAB_25__TG_TABLE25__VERIFY(src) \
59021 (!(((u_int32_t)(src)\
59041 #define TX_GAIN_TAB_26__TG_TABLE26__READ(src) (u_int32_t)(src) & 0xffffffffU
59042 #define TX_GAIN_TAB_26__TG_TABLE26__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
59043 #define TX_GAIN_TAB_26__TG_TABLE26__MODIFY(dst, src) \
59045 ~0xffffffffU) | ((u_int32_t)(src) &\
59047 #define TX_GAIN_TAB_26__TG_TABLE26__VERIFY(src) \
59048 (!(((u_int32_t)(src)\
59068 #define TX_GAIN_TAB_27__TG_TABLE27__READ(src) (u_int32_t)(src) & 0xffffffffU
59069 #define TX_GAIN_TAB_27__TG_TABLE27__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
59070 #define TX_GAIN_TAB_27__TG_TABLE27__MODIFY(dst, src) \
59072 ~0xffffffffU) | ((u_int32_t)(src) &\
59074 #define TX_GAIN_TAB_27__TG_TABLE27__VERIFY(src) \
59075 (!(((u_int32_t)(src)\
59095 #define TX_GAIN_TAB_28__TG_TABLE28__READ(src) (u_int32_t)(src) & 0xffffffffU
59096 #define TX_GAIN_TAB_28__TG_TABLE28__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
59097 #define TX_GAIN_TAB_28__TG_TABLE28__MODIFY(dst, src) \
59099 ~0xffffffffU) | ((u_int32_t)(src) &\
59101 #define TX_GAIN_TAB_28__TG_TABLE28__VERIFY(src) \
59102 (!(((u_int32_t)(src)\
59122 #define TX_GAIN_TAB_29__TG_TABLE29__READ(src) (u_int32_t)(src) & 0xffffffffU
59123 #define TX_GAIN_TAB_29__TG_TABLE29__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
59124 #define TX_GAIN_TAB_29__TG_TABLE29__MODIFY(dst, src) \
59126 ~0xffffffffU) | ((u_int32_t)(src) &\
59128 #define TX_GAIN_TAB_29__TG_TABLE29__VERIFY(src) \
59129 (!(((u_int32_t)(src)\
59149 #define TX_GAIN_TAB_30__TG_TABLE30__READ(src) (u_int32_t)(src) & 0xffffffffU
59150 #define TX_GAIN_TAB_30__TG_TABLE30__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
59151 #define TX_GAIN_TAB_30__TG_TABLE30__MODIFY(dst, src) \
59153 ~0xffffffffU) | ((u_int32_t)(src) &\
59155 #define TX_GAIN_TAB_30__TG_TABLE30__VERIFY(src) \
59156 (!(((u_int32_t)(src)\
59176 #define TX_GAIN_TAB_31__TG_TABLE31__READ(src) (u_int32_t)(src) & 0xffffffffU
59177 #define TX_GAIN_TAB_31__TG_TABLE31__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
59178 #define TX_GAIN_TAB_31__TG_TABLE31__MODIFY(dst, src) \
59180 ~0xffffffffU) | ((u_int32_t)(src) &\
59182 #define TX_GAIN_TAB_31__TG_TABLE31__VERIFY(src) \
59183 (!(((u_int32_t)(src)\
59203 #define TX_GAIN_TAB_32__TG_TABLE32__READ(src) (u_int32_t)(src) & 0xffffffffU
59204 #define TX_GAIN_TAB_32__TG_TABLE32__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
59205 #define TX_GAIN_TAB_32__TG_TABLE32__MODIFY(dst, src) \
59207 ~0xffffffffU) | ((u_int32_t)(src) &\
59209 #define TX_GAIN_TAB_32__TG_TABLE32__VERIFY(src) \
59210 (!(((u_int32_t)(src)\
59230 #define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__READ(src) \
59231 (u_int32_t)(src)\
59233 #define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__WRITE(src) \
59234 ((u_int32_t)(src)\
59236 #define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__MODIFY(dst, src) \
59238 ~0xffffffffU) | ((u_int32_t)(src) &\
59240 #define TX_GAIN_TAB_PAL_1__TG_TABLE1_PAL_ON__VERIFY(src) \
59241 (!(((u_int32_t)(src)\
59261 #define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__READ(src) \
59262 (u_int32_t)(src)\
59264 #define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__WRITE(src) \
59265 ((u_int32_t)(src)\
59267 #define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__MODIFY(dst, src) \
59269 ~0xffffffffU) | ((u_int32_t)(src) &\
59271 #define TX_GAIN_TAB_PAL_2__TG_TABLE2_PAL_ON__VERIFY(src) \
59272 (!(((u_int32_t)(src)\
59292 #define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__READ(src) \
59293 (u_int32_t)(src)\
59295 #define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__WRITE(src) \
59296 ((u_int32_t)(src)\
59298 #define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__MODIFY(dst, src) \
59300 ~0xffffffffU) | ((u_int32_t)(src) &\
59302 #define TX_GAIN_TAB_PAL_3__TG_TABLE3_PAL_ON__VERIFY(src) \
59303 (!(((u_int32_t)(src)\
59323 #define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__READ(src) \
59324 (u_int32_t)(src)\
59326 #define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__WRITE(src) \
59327 ((u_int32_t)(src)\
59329 #define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__MODIFY(dst, src) \
59331 ~0xffffffffU) | ((u_int32_t)(src) &\
59333 #define TX_GAIN_TAB_PAL_4__TG_TABLE4_PAL_ON__VERIFY(src) \
59334 (!(((u_int32_t)(src)\
59354 #define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__READ(src) \
59355 (u_int32_t)(src)\
59357 #define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__WRITE(src) \
59358 ((u_int32_t)(src)\
59360 #define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__MODIFY(dst, src) \
59362 ~0xffffffffU) | ((u_int32_t)(src) &\
59364 #define TX_GAIN_TAB_PAL_5__TG_TABLE5_PAL_ON__VERIFY(src) \
59365 (!(((u_int32_t)(src)\
59385 #define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__READ(src) \
59386 (u_int32_t)(src)\
59388 #define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__WRITE(src) \
59389 ((u_int32_t)(src)\
59391 #define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__MODIFY(dst, src) \
59393 ~0xffffffffU) | ((u_int32_t)(src) &\
59395 #define TX_GAIN_TAB_PAL_6__TG_TABLE6_PAL_ON__VERIFY(src) \
59396 (!(((u_int32_t)(src)\
59416 #define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__READ(src) \
59417 (u_int32_t)(src)\
59419 #define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__WRITE(src) \
59420 ((u_int32_t)(src)\
59422 #define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__MODIFY(dst, src) \
59424 ~0xffffffffU) | ((u_int32_t)(src) &\
59426 #define TX_GAIN_TAB_PAL_7__TG_TABLE7_PAL_ON__VERIFY(src) \
59427 (!(((u_int32_t)(src)\
59447 #define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__READ(src) \
59448 (u_int32_t)(src)\
59450 #define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__WRITE(src) \
59451 ((u_int32_t)(src)\
59453 #define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__MODIFY(dst, src) \
59455 ~0xffffffffU) | ((u_int32_t)(src) &\
59457 #define TX_GAIN_TAB_PAL_8__TG_TABLE8_PAL_ON__VERIFY(src) \
59458 (!(((u_int32_t)(src)\
59478 #define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__READ(src) \
59479 (u_int32_t)(src)\
59481 #define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__WRITE(src) \
59482 ((u_int32_t)(src)\
59484 #define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__MODIFY(dst, src) \
59486 ~0xffffffffU) | ((u_int32_t)(src) &\
59488 #define TX_GAIN_TAB_PAL_9__TG_TABLE9_PAL_ON__VERIFY(src) \
59489 (!(((u_int32_t)(src)\
59509 #define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__READ(src) \
59510 (u_int32_t)(src)\
59512 #define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__WRITE(src) \
59513 ((u_int32_t)(src)\
59515 #define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__MODIFY(dst, src) \
59517 ~0xffffffffU) | ((u_int32_t)(src) &\
59519 #define TX_GAIN_TAB_PAL_10__TG_TABLE10_PAL_ON__VERIFY(src) \
59520 (!(((u_int32_t)(src)\
59540 #define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__READ(src) \
59541 (u_int32_t)(src)\
59543 #define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__WRITE(src) \
59544 ((u_int32_t)(src)\
59546 #define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__MODIFY(dst, src) \
59548 ~0xffffffffU) | ((u_int32_t)(src) &\
59550 #define TX_GAIN_TAB_PAL_11__TG_TABLE11_PAL_ON__VERIFY(src) \
59551 (!(((u_int32_t)(src)\
59571 #define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__READ(src) \
59572 (u_int32_t)(src)\
59574 #define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__WRITE(src) \
59575 ((u_int32_t)(src)\
59577 #define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__MODIFY(dst, src) \
59579 ~0xffffffffU) | ((u_int32_t)(src) &\
59581 #define TX_GAIN_TAB_PAL_12__TG_TABLE12_PAL_ON__VERIFY(src) \
59582 (!(((u_int32_t)(src)\
59602 #define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__READ(src) \
59603 (u_int32_t)(src)\
59605 #define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__WRITE(src) \
59606 ((u_int32_t)(src)\
59608 #define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__MODIFY(dst, src) \
59610 ~0xffffffffU) | ((u_int32_t)(src) &\
59612 #define TX_GAIN_TAB_PAL_13__TG_TABLE13_PAL_ON__VERIFY(src) \
59613 (!(((u_int32_t)(src)\
59633 #define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__READ(src) \
59634 (u_int32_t)(src)\
59636 #define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__WRITE(src) \
59637 ((u_int32_t)(src)\
59639 #define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__MODIFY(dst, src) \
59641 ~0xffffffffU) | ((u_int32_t)(src) &\
59643 #define TX_GAIN_TAB_PAL_14__TG_TABLE14_PAL_ON__VERIFY(src) \
59644 (!(((u_int32_t)(src)\
59664 #define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__READ(src) \
59665 (u_int32_t)(src)\
59667 #define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__WRITE(src) \
59668 ((u_int32_t)(src)\
59670 #define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__MODIFY(dst, src) \
59672 ~0xffffffffU) | ((u_int32_t)(src) &\
59674 #define TX_GAIN_TAB_PAL_15__TG_TABLE15_PAL_ON__VERIFY(src) \
59675 (!(((u_int32_t)(src)\
59695 #define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__READ(src) \
59696 (u_int32_t)(src)\
59698 #define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__WRITE(src) \
59699 ((u_int32_t)(src)\
59701 #define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__MODIFY(dst, src) \
59703 ~0xffffffffU) | ((u_int32_t)(src) &\
59705 #define TX_GAIN_TAB_PAL_16__TG_TABLE16_PAL_ON__VERIFY(src) \
59706 (!(((u_int32_t)(src)\
59726 #define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__READ(src) \
59727 (u_int32_t)(src)\
59729 #define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__WRITE(src) \
59730 ((u_int32_t)(src)\
59732 #define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__MODIFY(dst, src) \
59734 ~0xffffffffU) | ((u_int32_t)(src) &\
59736 #define TX_GAIN_TAB_PAL_17__TG_TABLE17_PAL_ON__VERIFY(src) \
59737 (!(((u_int32_t)(src)\
59757 #define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__READ(src) \
59758 (u_int32_t)(src)\
59760 #define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__WRITE(src) \
59761 ((u_int32_t)(src)\
59763 #define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__MODIFY(dst, src) \
59765 ~0xffffffffU) | ((u_int32_t)(src) &\
59767 #define TX_GAIN_TAB_PAL_18__TG_TABLE18_PAL_ON__VERIFY(src) \
59768 (!(((u_int32_t)(src)\
59788 #define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__READ(src) \
59789 (u_int32_t)(src)\
59791 #define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__WRITE(src) \
59792 ((u_int32_t)(src)\
59794 #define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__MODIFY(dst, src) \
59796 ~0xffffffffU) | ((u_int32_t)(src) &\
59798 #define TX_GAIN_TAB_PAL_19__TG_TABLE19_PAL_ON__VERIFY(src) \
59799 (!(((u_int32_t)(src)\
59819 #define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__READ(src) \
59820 (u_int32_t)(src)\
59822 #define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__WRITE(src) \
59823 ((u_int32_t)(src)\
59825 #define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__MODIFY(dst, src) \
59827 ~0xffffffffU) | ((u_int32_t)(src) &\
59829 #define TX_GAIN_TAB_PAL_20__TG_TABLE20_PAL_ON__VERIFY(src) \
59830 (!(((u_int32_t)(src)\
59850 #define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__READ(src) \
59851 (u_int32_t)(src)\
59853 #define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__WRITE(src) \
59854 ((u_int32_t)(src)\
59856 #define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__MODIFY(dst, src) \
59858 ~0xffffffffU) | ((u_int32_t)(src) &\
59860 #define TX_GAIN_TAB_PAL_21__TG_TABLE21_PAL_ON__VERIFY(src) \
59861 (!(((u_int32_t)(src)\
59881 #define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__READ(src) \
59882 (u_int32_t)(src)\
59884 #define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__WRITE(src) \
59885 ((u_int32_t)(src)\
59887 #define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__MODIFY(dst, src) \
59889 ~0xffffffffU) | ((u_int32_t)(src) &\
59891 #define TX_GAIN_TAB_PAL_22__TG_TABLE22_PAL_ON__VERIFY(src) \
59892 (!(((u_int32_t)(src)\
59912 #define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__READ(src) \
59913 (u_int32_t)(src)\
59915 #define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__WRITE(src) \
59916 ((u_int32_t)(src)\
59918 #define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__MODIFY(dst, src) \
59920 ~0xffffffffU) | ((u_int32_t)(src) &\
59922 #define TX_GAIN_TAB_PAL_23__TG_TABLE23_PAL_ON__VERIFY(src) \
59923 (!(((u_int32_t)(src)\
59943 #define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__READ(src) \
59944 (u_int32_t)(src)\
59946 #define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__WRITE(src) \
59947 ((u_int32_t)(src)\
59949 #define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__MODIFY(dst, src) \
59951 ~0xffffffffU) | ((u_int32_t)(src) &\
59953 #define TX_GAIN_TAB_PAL_24__TG_TABLE24_PAL_ON__VERIFY(src) \
59954 (!(((u_int32_t)(src)\
59974 #define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__READ(src) \
59975 (u_int32_t)(src)\
59977 #define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__WRITE(src) \
59978 ((u_int32_t)(src)\
59980 #define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__MODIFY(dst, src) \
59982 ~0xffffffffU) | ((u_int32_t)(src) &\
59984 #define TX_GAIN_TAB_PAL_25__TG_TABLE25_PAL_ON__VERIFY(src) \
59985 (!(((u_int32_t)(src)\
60005 #define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__READ(src) \
60006 (u_int32_t)(src)\
60008 #define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__WRITE(src) \
60009 ((u_int32_t)(src)\
60011 #define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__MODIFY(dst, src) \
60013 ~0xffffffffU) | ((u_int32_t)(src) &\
60015 #define TX_GAIN_TAB_PAL_26__TG_TABLE26_PAL_ON__VERIFY(src) \
60016 (!(((u_int32_t)(src)\
60036 #define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__READ(src) \
60037 (u_int32_t)(src)\
60039 #define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__WRITE(src) \
60040 ((u_int32_t)(src)\
60042 #define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__MODIFY(dst, src) \
60044 ~0xffffffffU) | ((u_int32_t)(src) &\
60046 #define TX_GAIN_TAB_PAL_27__TG_TABLE27_PAL_ON__VERIFY(src) \
60047 (!(((u_int32_t)(src)\
60067 #define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__READ(src) \
60068 (u_int32_t)(src)\
60070 #define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__WRITE(src) \
60071 ((u_int32_t)(src)\
60073 #define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__MODIFY(dst, src) \
60075 ~0xffffffffU) | ((u_int32_t)(src) &\
60077 #define TX_GAIN_TAB_PAL_28__TG_TABLE28_PAL_ON__VERIFY(src) \
60078 (!(((u_int32_t)(src)\
60098 #define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__READ(src) \
60099 (u_int32_t)(src)\
60101 #define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__WRITE(src) \
60102 ((u_int32_t)(src)\
60104 #define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__MODIFY(dst, src) \
60106 ~0xffffffffU) | ((u_int32_t)(src) &\
60108 #define TX_GAIN_TAB_PAL_29__TG_TABLE29_PAL_ON__VERIFY(src) \
60109 (!(((u_int32_t)(src)\
60129 #define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__READ(src) \
60130 (u_int32_t)(src)\
60132 #define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__WRITE(src) \
60133 ((u_int32_t)(src)\
60135 #define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__MODIFY(dst, src) \
60137 ~0xffffffffU) | ((u_int32_t)(src) &\
60139 #define TX_GAIN_TAB_PAL_30__TG_TABLE30_PAL_ON__VERIFY(src) \
60140 (!(((u_int32_t)(src)\
60160 #define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__READ(src) \
60161 (u_int32_t)(src)\
60163 #define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__WRITE(src) \
60164 ((u_int32_t)(src)\
60166 #define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__MODIFY(dst, src) \
60168 ~0xffffffffU) | ((u_int32_t)(src) &\
60170 #define TX_GAIN_TAB_PAL_31__TG_TABLE31_PAL_ON__VERIFY(src) \
60171 (!(((u_int32_t)(src)\
60191 #define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__READ(src) \
60192 (u_int32_t)(src)\
60194 #define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__WRITE(src) \
60195 ((u_int32_t)(src)\
60197 #define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__MODIFY(dst, src) \
60199 ~0xffffffffU) | ((u_int32_t)(src) &\
60201 #define TX_GAIN_TAB_PAL_32__TG_TABLE32_PAL_ON__VERIFY(src) \
60202 (!(((u_int32_t)(src)\
60222 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__READ(src) \
60223 (u_int32_t)(src)\
60225 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__WRITE(src) \
60226 ((u_int32_t)(src)\
60228 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__MODIFY(dst, src) \
60230 ~0x00003fffU) | ((u_int32_t)(src) &\
60232 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_0__VERIFY(src) \
60233 (!(((u_int32_t)(src)\
60240 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__READ(src) \
60241 (((u_int32_t)(src)\
60243 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__WRITE(src) \
60244 (((u_int32_t)(src)\
60246 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__MODIFY(dst, src) \
60248 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60250 #define CALTX_GAIN_SET_0__CALTX_GAIN_SET_1__VERIFY(src) \
60251 (!((((u_int32_t)(src)\
60271 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__READ(src) \
60272 (u_int32_t)(src)\
60274 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__WRITE(src) \
60275 ((u_int32_t)(src)\
60277 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__MODIFY(dst, src) \
60279 ~0x00003fffU) | ((u_int32_t)(src) &\
60281 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_2__VERIFY(src) \
60282 (!(((u_int32_t)(src)\
60289 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__READ(src) \
60290 (((u_int32_t)(src)\
60292 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__WRITE(src) \
60293 (((u_int32_t)(src)\
60295 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__MODIFY(dst, src) \
60297 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60299 #define CALTX_GAIN_SET_2__CALTX_GAIN_SET_3__VERIFY(src) \
60300 (!((((u_int32_t)(src)\
60320 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__READ(src) \
60321 (u_int32_t)(src)\
60323 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__WRITE(src) \
60324 ((u_int32_t)(src)\
60326 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__MODIFY(dst, src) \
60328 ~0x00003fffU) | ((u_int32_t)(src) &\
60330 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_4__VERIFY(src) \
60331 (!(((u_int32_t)(src)\
60338 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__READ(src) \
60339 (((u_int32_t)(src)\
60341 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__WRITE(src) \
60342 (((u_int32_t)(src)\
60344 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__MODIFY(dst, src) \
60346 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60348 #define CALTX_GAIN_SET_4__CALTX_GAIN_SET_5__VERIFY(src) \
60349 (!((((u_int32_t)(src)\
60369 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__READ(src) \
60370 (u_int32_t)(src)\
60372 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__WRITE(src) \
60373 ((u_int32_t)(src)\
60375 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__MODIFY(dst, src) \
60377 ~0x00003fffU) | ((u_int32_t)(src) &\
60379 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_6__VERIFY(src) \
60380 (!(((u_int32_t)(src)\
60387 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__READ(src) \
60388 (((u_int32_t)(src)\
60390 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__WRITE(src) \
60391 (((u_int32_t)(src)\
60393 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__MODIFY(dst, src) \
60395 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60397 #define CALTX_GAIN_SET_6__CALTX_GAIN_SET_7__VERIFY(src) \
60398 (!((((u_int32_t)(src)\
60418 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__READ(src) \
60419 (u_int32_t)(src)\
60421 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__WRITE(src) \
60422 ((u_int32_t)(src)\
60424 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__MODIFY(dst, src) \
60426 ~0x00003fffU) | ((u_int32_t)(src) &\
60428 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_8__VERIFY(src) \
60429 (!(((u_int32_t)(src)\
60436 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__READ(src) \
60437 (((u_int32_t)(src)\
60439 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__WRITE(src) \
60440 (((u_int32_t)(src)\
60442 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__MODIFY(dst, src) \
60444 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60446 #define CALTX_GAIN_SET_8__CALTX_GAIN_SET_9__VERIFY(src) \
60447 (!((((u_int32_t)(src)\
60467 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__READ(src) \
60468 (u_int32_t)(src)\
60470 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__WRITE(src) \
60471 ((u_int32_t)(src)\
60473 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__MODIFY(dst, src) \
60475 ~0x00003fffU) | ((u_int32_t)(src) &\
60477 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_10__VERIFY(src) \
60478 (!(((u_int32_t)(src)\
60485 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__READ(src) \
60486 (((u_int32_t)(src)\
60488 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__WRITE(src) \
60489 (((u_int32_t)(src)\
60491 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__MODIFY(dst, src) \
60493 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60495 #define CALTX_GAIN_SET_10__CALTX_GAIN_SET_11__VERIFY(src) \
60496 (!((((u_int32_t)(src)\
60516 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__READ(src) \
60517 (u_int32_t)(src)\
60519 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__WRITE(src) \
60520 ((u_int32_t)(src)\
60522 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__MODIFY(dst, src) \
60524 ~0x00003fffU) | ((u_int32_t)(src) &\
60526 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_12__VERIFY(src) \
60527 (!(((u_int32_t)(src)\
60534 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__READ(src) \
60535 (((u_int32_t)(src)\
60537 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__WRITE(src) \
60538 (((u_int32_t)(src)\
60540 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__MODIFY(dst, src) \
60542 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60544 #define CALTX_GAIN_SET_12__CALTX_GAIN_SET_13__VERIFY(src) \
60545 (!((((u_int32_t)(src)\
60565 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__READ(src) \
60566 (u_int32_t)(src)\
60568 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__WRITE(src) \
60569 ((u_int32_t)(src)\
60571 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__MODIFY(dst, src) \
60573 ~0x00003fffU) | ((u_int32_t)(src) &\
60575 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_14__VERIFY(src) \
60576 (!(((u_int32_t)(src)\
60583 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__READ(src) \
60584 (((u_int32_t)(src)\
60586 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__WRITE(src) \
60587 (((u_int32_t)(src)\
60589 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__MODIFY(dst, src) \
60591 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60593 #define CALTX_GAIN_SET_14__CALTX_GAIN_SET_15__VERIFY(src) \
60594 (!((((u_int32_t)(src)\
60614 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__READ(src) \
60615 (u_int32_t)(src)\
60617 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__WRITE(src) \
60618 ((u_int32_t)(src)\
60620 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__MODIFY(dst, src) \
60622 ~0x00003fffU) | ((u_int32_t)(src) &\
60624 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_16__VERIFY(src) \
60625 (!(((u_int32_t)(src)\
60632 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__READ(src) \
60633 (((u_int32_t)(src)\
60635 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__WRITE(src) \
60636 (((u_int32_t)(src)\
60638 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__MODIFY(dst, src) \
60640 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60642 #define CALTX_GAIN_SET_16__CALTX_GAIN_SET_17__VERIFY(src) \
60643 (!((((u_int32_t)(src)\
60663 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__READ(src) \
60664 (u_int32_t)(src)\
60666 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__WRITE(src) \
60667 ((u_int32_t)(src)\
60669 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__MODIFY(dst, src) \
60671 ~0x00003fffU) | ((u_int32_t)(src) &\
60673 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_18__VERIFY(src) \
60674 (!(((u_int32_t)(src)\
60681 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__READ(src) \
60682 (((u_int32_t)(src)\
60684 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__WRITE(src) \
60685 (((u_int32_t)(src)\
60687 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__MODIFY(dst, src) \
60689 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60691 #define CALTX_GAIN_SET_18__CALTX_GAIN_SET_19__VERIFY(src) \
60692 (!((((u_int32_t)(src)\
60712 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__READ(src) \
60713 (u_int32_t)(src)\
60715 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__WRITE(src) \
60716 ((u_int32_t)(src)\
60718 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__MODIFY(dst, src) \
60720 ~0x00003fffU) | ((u_int32_t)(src) &\
60722 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_20__VERIFY(src) \
60723 (!(((u_int32_t)(src)\
60730 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__READ(src) \
60731 (((u_int32_t)(src)\
60733 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__WRITE(src) \
60734 (((u_int32_t)(src)\
60736 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__MODIFY(dst, src) \
60738 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60740 #define CALTX_GAIN_SET_20__CALTX_GAIN_SET_21__VERIFY(src) \
60741 (!((((u_int32_t)(src)\
60761 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__READ(src) \
60762 (u_int32_t)(src)\
60764 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__WRITE(src) \
60765 ((u_int32_t)(src)\
60767 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__MODIFY(dst, src) \
60769 ~0x00003fffU) | ((u_int32_t)(src) &\
60771 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_22__VERIFY(src) \
60772 (!(((u_int32_t)(src)\
60779 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__READ(src) \
60780 (((u_int32_t)(src)\
60782 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__WRITE(src) \
60783 (((u_int32_t)(src)\
60785 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__MODIFY(dst, src) \
60787 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60789 #define CALTX_GAIN_SET_22__CALTX_GAIN_SET_23__VERIFY(src) \
60790 (!((((u_int32_t)(src)\
60810 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__READ(src) \
60811 (u_int32_t)(src)\
60813 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__WRITE(src) \
60814 ((u_int32_t)(src)\
60816 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__MODIFY(dst, src) \
60818 ~0x00003fffU) | ((u_int32_t)(src) &\
60820 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_24__VERIFY(src) \
60821 (!(((u_int32_t)(src)\
60828 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__READ(src) \
60829 (((u_int32_t)(src)\
60831 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__WRITE(src) \
60832 (((u_int32_t)(src)\
60834 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__MODIFY(dst, src) \
60836 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60838 #define CALTX_GAIN_SET_24__CALTX_GAIN_SET_25__VERIFY(src) \
60839 (!((((u_int32_t)(src)\
60859 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__READ(src) \
60860 (u_int32_t)(src)\
60862 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__WRITE(src) \
60863 ((u_int32_t)(src)\
60865 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__MODIFY(dst, src) \
60867 ~0x00003fffU) | ((u_int32_t)(src) &\
60869 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_26__VERIFY(src) \
60870 (!(((u_int32_t)(src)\
60877 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__READ(src) \
60878 (((u_int32_t)(src)\
60880 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__WRITE(src) \
60881 (((u_int32_t)(src)\
60883 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__MODIFY(dst, src) \
60885 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60887 #define CALTX_GAIN_SET_26__CALTX_GAIN_SET_27__VERIFY(src) \
60888 (!((((u_int32_t)(src)\
60908 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__READ(src) \
60909 (u_int32_t)(src)\
60911 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__WRITE(src) \
60912 ((u_int32_t)(src)\
60914 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__MODIFY(dst, src) \
60916 ~0x00003fffU) | ((u_int32_t)(src) &\
60918 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_28__VERIFY(src) \
60919 (!(((u_int32_t)(src)\
60926 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__READ(src) \
60927 (((u_int32_t)(src)\
60929 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__WRITE(src) \
60930 (((u_int32_t)(src)\
60932 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__MODIFY(dst, src) \
60934 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60936 #define CALTX_GAIN_SET_28__CALTX_GAIN_SET_29__VERIFY(src) \
60937 (!((((u_int32_t)(src)\
60957 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__READ(src) \
60958 (u_int32_t)(src)\
60960 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__WRITE(src) \
60961 ((u_int32_t)(src)\
60963 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__MODIFY(dst, src) \
60965 ~0x00003fffU) | ((u_int32_t)(src) &\
60967 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_30__VERIFY(src) \
60968 (!(((u_int32_t)(src)\
60975 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__READ(src) \
60976 (((u_int32_t)(src)\
60978 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__WRITE(src) \
60979 (((u_int32_t)(src)\
60981 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__MODIFY(dst, src) \
60983 ~0x0fffc000U) | (((u_int32_t)(src) <<\
60985 #define CALTX_GAIN_SET_30__CALTX_GAIN_SET_31__VERIFY(src) \
60986 (!((((u_int32_t)(src)\
61007 #define TXIQCAL_START__DO_TX_IQCAL__READ(src) (u_int32_t)(src) & 0x00000001U
61008 #define TXIQCAL_START__DO_TX_IQCAL__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
61009 #define TXIQCAL_START__DO_TX_IQCAL__MODIFY(dst, src) \
61011 ~0x00000001U) | ((u_int32_t)(src) &\
61013 #define TXIQCAL_START__DO_TX_IQCAL__VERIFY(src) \
61014 (!(((u_int32_t)(src)\
61040 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__READ(src) \
61041 (u_int32_t)(src)\
61043 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__WRITE(src) \
61044 ((u_int32_t)(src)\
61046 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__MODIFY(dst, src) \
61048 ~0x00000001U) | ((u_int32_t)(src) &\
61050 #define TXIQCAL_CONTROL_0__IQC_TX_TABLE_SEL__VERIFY(src) \
61051 (!(((u_int32_t)(src)\
61064 #define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__READ(src) \
61065 (((u_int32_t)(src)\
61067 #define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__WRITE(src) \
61068 (((u_int32_t)(src)\
61070 #define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__MODIFY(dst, src) \
61072 ~0x0000007eU) | (((u_int32_t)(src) <<\
61074 #define TXIQCAL_CONTROL_0__BASE_TX_TONE_DB__VERIFY(src) \
61075 (!((((u_int32_t)(src)\
61082 #define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__READ(src) \
61083 (((u_int32_t)(src)\
61085 #define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__WRITE(src) \
61086 (((u_int32_t)(src)\
61088 #define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__MODIFY(dst, src) \
61090 ~0x00001f80U) | (((u_int32_t)(src) <<\
61092 #define TXIQCAL_CONTROL_0__MAX_TX_TONE_GAIN__VERIFY(src) \
61093 (!((((u_int32_t)(src)\
61100 #define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__READ(src) \
61101 (((u_int32_t)(src)\
61103 #define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__WRITE(src) \
61104 (((u_int32_t)(src)\
61106 #define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__MODIFY(dst, src) \
61108 ~0x0007e000U) | (((u_int32_t)(src) <<\
61110 #define TXIQCAL_CONTROL_0__MIN_TX_TONE_GAIN__VERIFY(src) \
61111 (!((((u_int32_t)(src)\
61118 #define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__READ(src) \
61119 (((u_int32_t)(src)\
61121 #define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__WRITE(src) \
61122 (((u_int32_t)(src)\
61124 #define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__MODIFY(dst, src) \
61126 ~0x00780000U) | (((u_int32_t)(src) <<\
61128 #define TXIQCAL_CONTROL_0__CALTXSHIFT_DELAY__VERIFY(src) \
61129 (!((((u_int32_t)(src)\
61136 #define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__READ(src) \
61137 (((u_int32_t)(src)\
61139 #define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__WRITE(src) \
61140 (((u_int32_t)(src)\
61142 #define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__MODIFY(dst, src) \
61144 ~0x3f800000U) | (((u_int32_t)(src) <<\
61146 #define TXIQCAL_CONTROL_0__LOOPBACK_DELAY__VERIFY(src) \
61147 (!((((u_int32_t)(src)\
61154 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__READ(src) \
61155 (((u_int32_t)(src)\
61157 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__WRITE(src) \
61158 (((u_int32_t)(src)\
61160 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__MODIFY(dst, src) \
61162 ~0x40000000U) | (((u_int32_t)(src) <<\
61164 #define TXIQCAL_CONTROL_0__ENABLE_COMBINED_CARR_IQ_CAL__VERIFY(src) \
61165 (!((((u_int32_t)(src)\
61191 #define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__READ(src) \
61192 (u_int32_t)(src)\
61194 #define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__WRITE(src) \
61195 ((u_int32_t)(src)\
61197 #define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__MODIFY(dst, src) \
61199 ~0x0000003fU) | ((u_int32_t)(src) &\
61201 #define TXIQCAL_CONTROL_1__RX_INIT_GAIN_DB__VERIFY(src) \
61202 (!(((u_int32_t)(src)\
61209 #define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__READ(src) \
61210 (((u_int32_t)(src)\
61212 #define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__WRITE(src) \
61213 (((u_int32_t)(src)\
61215 #define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__MODIFY(dst, src) \
61217 ~0x00000fc0U) | (((u_int32_t)(src) <<\
61219 #define TXIQCAL_CONTROL_1__MAX_RX_GAIN_DB__VERIFY(src) \
61220 (!((((u_int32_t)(src)\
61227 #define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__READ(src) \
61228 (((u_int32_t)(src)\
61230 #define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__WRITE(src) \
61231 (((u_int32_t)(src)\
61233 #define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__MODIFY(dst, src) \
61235 ~0x0003f000U) | (((u_int32_t)(src) <<\
61237 #define TXIQCAL_CONTROL_1__MIN_RX_GAIN_DB__VERIFY(src) \
61238 (!((((u_int32_t)(src)\
61245 #define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__READ(src) \
61246 (((u_int32_t)(src)\
61248 #define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__WRITE(src) \
61249 (((u_int32_t)(src)\
61251 #define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__MODIFY(dst, src) \
61253 ~0x01fc0000U) | (((u_int32_t)(src) <<\
61255 #define TXIQCAL_CONTROL_1__IQCORR_I_Q_COFF_DELPT__VERIFY(src) \
61256 (!((((u_int32_t)(src)\
61276 #define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__READ(src) \
61277 (u_int32_t)(src)\
61279 #define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__WRITE(src) \
61280 ((u_int32_t)(src)\
61282 #define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__MODIFY(dst, src) \
61284 ~0x0000000fU) | ((u_int32_t)(src) &\
61286 #define TXIQCAL_CONTROL_2__IQC_FORCED_PAGAIN__VERIFY(src) \
61287 (!(((u_int32_t)(src)\
61294 #define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__READ(src) \
61295 (((u_int32_t)(src)\
61297 #define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__WRITE(src) \
61298 (((u_int32_t)(src)\
61300 #define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__MODIFY(dst, src) \
61302 ~0x000001f0U) | (((u_int32_t)(src) <<\
61304 #define TXIQCAL_CONTROL_2__IQCAL_MIN_TX_GAIN__VERIFY(src) \
61305 (!((((u_int32_t)(src)\
61312 #define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__READ(src) \
61313 (((u_int32_t)(src)\
61315 #define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__WRITE(src) \
61316 (((u_int32_t)(src)\
61318 #define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__MODIFY(dst, src) \
61320 ~0x00003e00U) | (((u_int32_t)(src) <<\
61322 #define TXIQCAL_CONTROL_2__IQCAL_MAX_TX_GAIN__VERIFY(src) \
61323 (!((((u_int32_t)(src)\
61343 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__READ(src) \
61344 (u_int32_t)(src)\
61346 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__WRITE(src) \
61347 ((u_int32_t)(src)\
61349 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__MODIFY(dst, src) \
61351 ~0x00003fffU) | ((u_int32_t)(src) &\
61353 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_0_0__VERIFY(src) \
61354 (!(((u_int32_t)(src)\
61361 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__READ(src) \
61362 (((u_int32_t)(src)\
61364 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__WRITE(src) \
61365 (((u_int32_t)(src)\
61367 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__MODIFY(dst, src) \
61369 ~0x0fffc000U) | (((u_int32_t)(src) <<\
61371 #define TXIQ_CORR_COEFF_01_B0__IQC_COEFF_TABLE_1_0__VERIFY(src) \
61372 (!((((u_int32_t)(src)\
61392 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__READ(src) \
61393 (u_int32_t)(src)\
61395 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__WRITE(src) \
61396 ((u_int32_t)(src)\
61398 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__MODIFY(dst, src) \
61400 ~0x00003fffU) | ((u_int32_t)(src) &\
61402 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_2_0__VERIFY(src) \
61403 (!(((u_int32_t)(src)\
61410 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__READ(src) \
61411 (((u_int32_t)(src)\
61413 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__WRITE(src) \
61414 (((u_int32_t)(src)\
61416 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__MODIFY(dst, src) \
61418 ~0x0fffc000U) | (((u_int32_t)(src) <<\
61420 #define TXIQ_CORR_COEFF_23_B0__IQC_COEFF_TABLE_3_0__VERIFY(src) \
61421 (!((((u_int32_t)(src)\
61441 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__READ(src) \
61442 (u_int32_t)(src)\
61444 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__WRITE(src) \
61445 ((u_int32_t)(src)\
61447 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__MODIFY(dst, src) \
61449 ~0x00003fffU) | ((u_int32_t)(src) &\
61451 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_4_0__VERIFY(src) \
61452 (!(((u_int32_t)(src)\
61459 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__READ(src) \
61460 (((u_int32_t)(src)\
61462 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__WRITE(src) \
61463 (((u_int32_t)(src)\
61465 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__MODIFY(dst, src) \
61467 ~0x0fffc000U) | (((u_int32_t)(src) <<\
61469 #define TXIQ_CORR_COEFF_45_B0__IQC_COEFF_TABLE_5_0__VERIFY(src) \
61470 (!((((u_int32_t)(src)\
61490 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__READ(src) \
61491 (u_int32_t)(src)\
61493 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__WRITE(src) \
61494 ((u_int32_t)(src)\
61496 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__MODIFY(dst, src) \
61498 ~0x00003fffU) | ((u_int32_t)(src) &\
61500 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_6_0__VERIFY(src) \
61501 (!(((u_int32_t)(src)\
61508 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__READ(src) \
61509 (((u_int32_t)(src)\
61511 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__WRITE(src) \
61512 (((u_int32_t)(src)\
61514 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__MODIFY(dst, src) \
61516 ~0x0fffc000U) | (((u_int32_t)(src) <<\
61518 #define TXIQ_CORR_COEFF_67_B0__IQC_COEFF_TABLE_7_0__VERIFY(src) \
61519 (!((((u_int32_t)(src)\
61539 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__READ(src) \
61540 (u_int32_t)(src)\
61542 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__WRITE(src) \
61543 ((u_int32_t)(src)\
61545 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__MODIFY(dst, src) \
61547 ~0x00003fffU) | ((u_int32_t)(src) &\
61549 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_8_0__VERIFY(src) \
61550 (!(((u_int32_t)(src)\
61557 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__READ(src) \
61558 (((u_int32_t)(src)\
61560 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__WRITE(src) \
61561 (((u_int32_t)(src)\
61563 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__MODIFY(dst, src) \
61565 ~0x0fffc000U) | (((u_int32_t)(src) <<\
61567 #define TXIQ_CORR_COEFF_89_B0__IQC_COEFF_TABLE_9_0__VERIFY(src) \
61568 (!((((u_int32_t)(src)\
61588 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__READ(src) \
61589 (u_int32_t)(src)\
61591 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__WRITE(src) \
61592 ((u_int32_t)(src)\
61594 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__MODIFY(dst, src) \
61596 ~0x00003fffU) | ((u_int32_t)(src) &\
61598 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_A_0__VERIFY(src) \
61599 (!(((u_int32_t)(src)\
61606 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__READ(src) \
61607 (((u_int32_t)(src)\
61609 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__WRITE(src) \
61610 (((u_int32_t)(src)\
61612 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__MODIFY(dst, src) \
61614 ~0x0fffc000U) | (((u_int32_t)(src) <<\
61616 #define TXIQ_CORR_COEFF_AB_B0__IQC_COEFF_TABLE_B_0__VERIFY(src) \
61617 (!((((u_int32_t)(src)\
61637 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__READ(src) \
61638 (u_int32_t)(src)\
61640 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__WRITE(src) \
61641 ((u_int32_t)(src)\
61643 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__MODIFY(dst, src) \
61645 ~0x00003fffU) | ((u_int32_t)(src) &\
61647 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_C_0__VERIFY(src) \
61648 (!(((u_int32_t)(src)\
61655 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__READ(src) \
61656 (((u_int32_t)(src)\
61658 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__WRITE(src) \
61659 (((u_int32_t)(src)\
61661 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__MODIFY(dst, src) \
61663 ~0x0fffc000U) | (((u_int32_t)(src) <<\
61665 #define TXIQ_CORR_COEFF_CD_B0__IQC_COEFF_TABLE_D_0__VERIFY(src) \
61666 (!((((u_int32_t)(src)\
61686 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__READ(src) \
61687 (u_int32_t)(src)\
61689 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__WRITE(src) \
61690 ((u_int32_t)(src)\
61692 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__MODIFY(dst, src) \
61694 ~0x00003fffU) | ((u_int32_t)(src) &\
61696 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_E_0__VERIFY(src) \
61697 (!(((u_int32_t)(src)\
61704 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__READ(src) \
61705 (((u_int32_t)(src)\
61707 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__WRITE(src) \
61708 (((u_int32_t)(src)\
61710 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__MODIFY(dst, src) \
61712 ~0x0fffc000U) | (((u_int32_t)(src) <<\
61714 #define TXIQ_CORR_COEFF_EF_B0__IQC_COEFF_TABLE_F_0__VERIFY(src) \
61715 (!((((u_int32_t)(src)\
61735 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__READ(src) \
61736 (u_int32_t)(src)\
61738 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__WRITE(src) \
61739 ((u_int32_t)(src)\
61741 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__MODIFY(dst, src) \
61743 ~0x000000ffU) | ((u_int32_t)(src) &\
61745 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_0__VERIFY(src) \
61746 (!(((u_int32_t)(src)\
61753 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__READ(src) \
61754 (((u_int32_t)(src)\
61756 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__WRITE(src) \
61757 (((u_int32_t)(src)\
61759 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__MODIFY(dst, src) \
61761 ~0x0000ff00U) | (((u_int32_t)(src) <<\
61763 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_1__VERIFY(src) \
61764 (!((((u_int32_t)(src)\
61771 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__READ(src) \
61772 (((u_int32_t)(src)\
61774 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__WRITE(src) \
61775 (((u_int32_t)(src)\
61777 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__MODIFY(dst, src) \
61779 ~0x00ff0000U) | (((u_int32_t)(src) <<\
61781 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_2__VERIFY(src) \
61782 (!((((u_int32_t)(src)\
61789 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__READ(src) \
61790 (((u_int32_t)(src)\
61792 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__WRITE(src) \
61793 (((u_int32_t)(src)\
61795 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__MODIFY(dst, src) \
61797 ~0xff000000U) | (((u_int32_t)(src) <<\
61799 #define CAL_RXBB_GAIN_TBL_0__TXCAL_RX_BB_GAIN_TABLE_3__VERIFY(src) \
61800 (!((((u_int32_t)(src)\
61820 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__READ(src) \
61821 (u_int32_t)(src)\
61823 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__WRITE(src) \
61824 ((u_int32_t)(src)\
61826 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__MODIFY(dst, src) \
61828 ~0x000000ffU) | ((u_int32_t)(src) &\
61830 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_4__VERIFY(src) \
61831 (!(((u_int32_t)(src)\
61838 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__READ(src) \
61839 (((u_int32_t)(src)\
61841 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__WRITE(src) \
61842 (((u_int32_t)(src)\
61844 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__MODIFY(dst, src) \
61846 ~0x0000ff00U) | (((u_int32_t)(src) <<\
61848 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_5__VERIFY(src) \
61849 (!((((u_int32_t)(src)\
61856 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__READ(src) \
61857 (((u_int32_t)(src)\
61859 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__WRITE(src) \
61860 (((u_int32_t)(src)\
61862 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__MODIFY(dst, src) \
61864 ~0x00ff0000U) | (((u_int32_t)(src) <<\
61866 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_6__VERIFY(src) \
61867 (!((((u_int32_t)(src)\
61874 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__READ(src) \
61875 (((u_int32_t)(src)\
61877 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__WRITE(src) \
61878 (((u_int32_t)(src)\
61880 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__MODIFY(dst, src) \
61882 ~0xff000000U) | (((u_int32_t)(src) <<\
61884 #define CAL_RXBB_GAIN_TBL_4__TXCAL_RX_BB_GAIN_TABLE_7__VERIFY(src) \
61885 (!((((u_int32_t)(src)\
61905 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__READ(src) \
61906 (u_int32_t)(src)\
61908 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__WRITE(src) \
61909 ((u_int32_t)(src)\
61911 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__MODIFY(dst, src) \
61913 ~0x000000ffU) | ((u_int32_t)(src) &\
61915 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_8__VERIFY(src) \
61916 (!(((u_int32_t)(src)\
61923 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__READ(src) \
61924 (((u_int32_t)(src)\
61926 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__WRITE(src) \
61927 (((u_int32_t)(src)\
61929 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__MODIFY(dst, src) \
61931 ~0x0000ff00U) | (((u_int32_t)(src) <<\
61933 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_9__VERIFY(src) \
61934 (!((((u_int32_t)(src)\
61941 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__READ(src) \
61942 (((u_int32_t)(src)\
61944 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__WRITE(src) \
61945 (((u_int32_t)(src)\
61947 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__MODIFY(dst, src) \
61949 ~0x00ff0000U) | (((u_int32_t)(src) <<\
61951 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_10__VERIFY(src) \
61952 (!((((u_int32_t)(src)\
61959 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__READ(src) \
61960 (((u_int32_t)(src)\
61962 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__WRITE(src) \
61963 (((u_int32_t)(src)\
61965 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__MODIFY(dst, src) \
61967 ~0xff000000U) | (((u_int32_t)(src) <<\
61969 #define CAL_RXBB_GAIN_TBL_8__TXCAL_RX_BB_GAIN_TABLE_11__VERIFY(src) \
61970 (!((((u_int32_t)(src)\
61990 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__READ(src) \
61991 (u_int32_t)(src)\
61993 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__WRITE(src) \
61994 ((u_int32_t)(src)\
61996 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__MODIFY(dst, src) \
61998 ~0x000000ffU) | ((u_int32_t)(src) &\
62000 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_12__VERIFY(src) \
62001 (!(((u_int32_t)(src)\
62008 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__READ(src) \
62009 (((u_int32_t)(src)\
62011 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__WRITE(src) \
62012 (((u_int32_t)(src)\
62014 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__MODIFY(dst, src) \
62016 ~0x0000ff00U) | (((u_int32_t)(src) <<\
62018 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_13__VERIFY(src) \
62019 (!((((u_int32_t)(src)\
62026 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__READ(src) \
62027 (((u_int32_t)(src)\
62029 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__WRITE(src) \
62030 (((u_int32_t)(src)\
62032 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__MODIFY(dst, src) \
62034 ~0x00ff0000U) | (((u_int32_t)(src) <<\
62036 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_14__VERIFY(src) \
62037 (!((((u_int32_t)(src)\
62044 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__READ(src) \
62045 (((u_int32_t)(src)\
62047 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__WRITE(src) \
62048 (((u_int32_t)(src)\
62050 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__MODIFY(dst, src) \
62052 ~0xff000000U) | (((u_int32_t)(src) <<\
62054 #define CAL_RXBB_GAIN_TBL_12__TXCAL_RX_BB_GAIN_TABLE_15__VERIFY(src) \
62055 (!((((u_int32_t)(src)\
62075 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__READ(src) \
62076 (u_int32_t)(src)\
62078 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__WRITE(src) \
62079 ((u_int32_t)(src)\
62081 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__MODIFY(dst, src) \
62083 ~0x000000ffU) | ((u_int32_t)(src) &\
62085 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_16__VERIFY(src) \
62086 (!(((u_int32_t)(src)\
62093 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__READ(src) \
62094 (((u_int32_t)(src)\
62096 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__WRITE(src) \
62097 (((u_int32_t)(src)\
62099 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__MODIFY(dst, src) \
62101 ~0x0000ff00U) | (((u_int32_t)(src) <<\
62103 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_17__VERIFY(src) \
62104 (!((((u_int32_t)(src)\
62111 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__READ(src) \
62112 (((u_int32_t)(src)\
62114 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__WRITE(src) \
62115 (((u_int32_t)(src)\
62117 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__MODIFY(dst, src) \
62119 ~0x00ff0000U) | (((u_int32_t)(src) <<\
62121 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_18__VERIFY(src) \
62122 (!((((u_int32_t)(src)\
62129 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__READ(src) \
62130 (((u_int32_t)(src)\
62132 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__WRITE(src) \
62133 (((u_int32_t)(src)\
62135 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__MODIFY(dst, src) \
62137 ~0xff000000U) | (((u_int32_t)(src) <<\
62139 #define CAL_RXBB_GAIN_TBL_16__TXCAL_RX_BB_GAIN_TABLE_19__VERIFY(src) \
62140 (!((((u_int32_t)(src)\
62160 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__READ(src) \
62161 (u_int32_t)(src)\
62163 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__WRITE(src) \
62164 ((u_int32_t)(src)\
62166 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__MODIFY(dst, src) \
62168 ~0x000000ffU) | ((u_int32_t)(src) &\
62170 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_20__VERIFY(src) \
62171 (!(((u_int32_t)(src)\
62178 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__READ(src) \
62179 (((u_int32_t)(src)\
62181 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__WRITE(src) \
62182 (((u_int32_t)(src)\
62184 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__MODIFY(dst, src) \
62186 ~0x0000ff00U) | (((u_int32_t)(src) <<\
62188 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_21__VERIFY(src) \
62189 (!((((u_int32_t)(src)\
62196 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__READ(src) \
62197 (((u_int32_t)(src)\
62199 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__WRITE(src) \
62200 (((u_int32_t)(src)\
62202 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__MODIFY(dst, src) \
62204 ~0x00ff0000U) | (((u_int32_t)(src) <<\
62206 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_22__VERIFY(src) \
62207 (!((((u_int32_t)(src)\
62214 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__READ(src) \
62215 (((u_int32_t)(src)\
62217 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__WRITE(src) \
62218 (((u_int32_t)(src)\
62220 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__MODIFY(dst, src) \
62222 ~0xff000000U) | (((u_int32_t)(src) <<\
62224 #define CAL_RXBB_GAIN_TBL_20__TXCAL_RX_BB_GAIN_TABLE_23__VERIFY(src) \
62225 (!((((u_int32_t)(src)\
62245 #define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__READ(src) \
62246 (u_int32_t)(src)\
62248 #define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__WRITE(src) \
62249 ((u_int32_t)(src)\
62251 #define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__MODIFY(dst, src) \
62253 ~0x000000ffU) | ((u_int32_t)(src) &\
62255 #define CAL_RXBB_GAIN_TBL_24__TXCAL_RX_BB_GAIN_TABLE_24__VERIFY(src) \
62256 (!(((u_int32_t)(src)\
62276 #define TXIQCAL_STATUS_B0__TXIQCAL_FAILED_0__READ(src) \
62277 (u_int32_t)(src)\
62290 #define TXIQCAL_STATUS_B0__CALIBRATED_GAINS_0__READ(src) \
62291 (((u_int32_t)(src)\
62298 #define TXIQCAL_STATUS_B0__TONE_GAIN_USED_0__READ(src) \
62299 (((u_int32_t)(src)\
62306 #define TXIQCAL_STATUS_B0__RX_GAIN_USED_0__READ(src) \
62307 (((u_int32_t)(src)\
62314 #define TXIQCAL_STATUS_B0__LAST_MEAS_ADDR_0__READ(src) \
62315 (((u_int32_t)(src)\
62334 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__READ(src) \
62335 (u_int32_t)(src)\
62337 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__WRITE(src) \
62338 ((u_int32_t)(src)\
62340 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__MODIFY(dst, src) \
62342 ~0x00000001U) | ((u_int32_t)(src) &\
62344 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TRAIN_ENABLE__VERIFY(src) \
62345 (!(((u_int32_t)(src)\
62358 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__READ(src) \
62359 (((u_int32_t)(src)\
62361 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__WRITE(src) \
62362 (((u_int32_t)(src)\
62364 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__MODIFY(dst, src) \
62366 ~0x000000feU) | (((u_int32_t)(src) <<\
62368 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_AGC2_SETTLING__VERIFY(src) \
62369 (!((((u_int32_t)(src)\
62376 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__READ(src) \
62377 (((u_int32_t)(src)\
62379 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__WRITE(src) \
62380 (((u_int32_t)(src)\
62382 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__MODIFY(dst, src) \
62384 ~0x00000100U) | (((u_int32_t)(src) <<\
62386 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_IQCORR_ENABLE__VERIFY(src) \
62387 (!((((u_int32_t)(src)\
62400 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__READ(src) \
62401 (((u_int32_t)(src)\
62403 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__WRITE(src) \
62404 (((u_int32_t)(src)\
62406 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__MODIFY(dst, src) \
62408 ~0x00000200U) | (((u_int32_t)(src) <<\
62410 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_RX_BB_GAIN_FORCE__VERIFY(src) \
62411 (!((((u_int32_t)(src)\
62424 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__READ(src) \
62425 (((u_int32_t)(src)\
62427 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__WRITE(src) \
62428 (((u_int32_t)(src)\
62430 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__MODIFY(dst, src) \
62432 ~0x00000400U) | (((u_int32_t)(src) <<\
62434 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_TX_GAIN_FORCE__VERIFY(src) \
62435 (!((((u_int32_t)(src)\
62448 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__READ(src) \
62449 (((u_int32_t)(src)\
62451 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__WRITE(src) \
62452 (((u_int32_t)(src)\
62454 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__MODIFY(dst, src) \
62456 ~0x00000800U) | (((u_int32_t)(src) <<\
62458 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_ENABLE__VERIFY(src) \
62459 (!((((u_int32_t)(src)\
62472 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__READ(src) \
62473 (((u_int32_t)(src)\
62475 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__WRITE(src) \
62476 (((u_int32_t)(src)\
62478 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__MODIFY(dst, src) \
62480 ~0x0007f000U) | (((u_int32_t)(src) <<\
62482 #define PAPRD_TRAINER_CNTL1__CF_PAPRD_LB_SKIP__VERIFY(src) \
62483 (!((((u_int32_t)(src)\
62503 #define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__READ(src) \
62504 (u_int32_t)(src)\
62506 #define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__WRITE(src) \
62507 ((u_int32_t)(src)\
62509 #define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__MODIFY(dst, src) \
62511 ~0xffffffffU) | ((u_int32_t)(src) &\
62513 #define PAPRD_TRAINER_CNTL2__CF_PAPRD_INIT_RX_BB_GAIN__VERIFY(src) \
62514 (!(((u_int32_t)(src)\
62534 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__READ(src) \
62535 (u_int32_t)(src)\
62537 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__WRITE(src) \
62538 ((u_int32_t)(src)\
62540 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__MODIFY(dst, src) \
62542 ~0x0000003fU) | ((u_int32_t)(src) &\
62544 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_ADC_DESIRED_SIZE__VERIFY(src) \
62545 (!(((u_int32_t)(src)\
62552 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__READ(src) \
62553 (((u_int32_t)(src)\
62555 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__WRITE(src) \
62556 (((u_int32_t)(src)\
62558 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__MODIFY(dst, src) \
62560 ~0x00000fc0U) | (((u_int32_t)(src) <<\
62562 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_QUICK_DROP__VERIFY(src) \
62563 (!((((u_int32_t)(src)\
62570 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__READ(src) \
62571 (((u_int32_t)(src)\
62573 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__WRITE(src) \
62574 (((u_int32_t)(src)\
62576 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__MODIFY(dst, src) \
62578 ~0x0001f000U) | (((u_int32_t)(src) <<\
62580 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_MIN_LOOPBACK_DEL__VERIFY(src) \
62581 (!((((u_int32_t)(src)\
62588 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__READ(src) \
62589 (((u_int32_t)(src)\
62591 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__WRITE(src) \
62592 (((u_int32_t)(src)\
62594 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__MODIFY(dst, src) \
62596 ~0x000e0000U) | (((u_int32_t)(src) <<\
62598 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_NUM_CORR_STAGES__VERIFY(src) \
62599 (!((((u_int32_t)(src)\
62606 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__READ(src) \
62607 (((u_int32_t)(src)\
62609 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__WRITE(src) \
62610 (((u_int32_t)(src)\
62612 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__MODIFY(dst, src) \
62614 ~0x00f00000U) | (((u_int32_t)(src) <<\
62616 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_COARSE_CORR_LEN__VERIFY(src) \
62617 (!((((u_int32_t)(src)\
62624 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__READ(src) \
62625 (((u_int32_t)(src)\
62627 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__WRITE(src) \
62628 (((u_int32_t)(src)\
62630 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__MODIFY(dst, src) \
62632 ~0x0f000000U) | (((u_int32_t)(src) <<\
62634 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_FINE_CORR_LEN__VERIFY(src) \
62635 (!((((u_int32_t)(src)\
62642 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__READ(src) \
62643 (((u_int32_t)(src)\
62645 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__WRITE(src) \
62646 (((u_int32_t)(src)\
62648 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__MODIFY(dst, src) \
62650 ~0x10000000U) | (((u_int32_t)(src) <<\
62652 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_REUSE_CORR__VERIFY(src) \
62653 (!((((u_int32_t)(src)\
62666 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__READ(src) \
62667 (((u_int32_t)(src)\
62669 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__WRITE(src) \
62670 (((u_int32_t)(src)\
62672 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__MODIFY(dst, src) \
62674 ~0x20000000U) | (((u_int32_t)(src) <<\
62676 #define PAPRD_TRAINER_CNTL3__CF_PAPRD_BBTXMIX_DISABLE__VERIFY(src) \
62677 (!((((u_int32_t)(src)\
62703 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__READ(src) \
62704 (u_int32_t)(src)\
62706 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__WRITE(src) \
62707 ((u_int32_t)(src)\
62709 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__MODIFY(dst, src) \
62711 ~0x00000fffU) | ((u_int32_t)(src) &\
62713 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_MIN_CORR__VERIFY(src) \
62714 (!(((u_int32_t)(src)\
62721 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__READ(src) \
62722 (((u_int32_t)(src)\
62724 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__WRITE(src) \
62725 (((u_int32_t)(src)\
62727 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__MODIFY(dst, src) \
62729 ~0x0000f000U) | (((u_int32_t)(src) <<\
62731 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_SAFETY_DELTA__VERIFY(src) \
62732 (!((((u_int32_t)(src)\
62739 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__READ(src) \
62740 (((u_int32_t)(src)\
62742 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__WRITE(src) \
62743 (((u_int32_t)(src)\
62745 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__MODIFY(dst, src) \
62747 ~0x03ff0000U) | (((u_int32_t)(src) <<\
62749 #define PAPRD_TRAINER_CNTL4__CF_PAPRD_NUM_TRAIN_SAMPLES__VERIFY(src) \
62750 (!((((u_int32_t)(src)\
62770 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__READ(src) \
62771 (u_int32_t)(src)\
62773 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__WRITE(src) \
62774 ((u_int32_t)(src)\
62776 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__MODIFY(dst, src) \
62778 ~0x00000001U) | ((u_int32_t)(src) &\
62780 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_DONE__VERIFY(src) \
62781 (!(((u_int32_t)(src)\
62794 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_INCOMPLETE__READ(src) \
62795 (((u_int32_t)(src)\
62808 #define PAPRD_TRAINER_STAT1__PAPRD_CORR_ERR__READ(src) \
62809 (((u_int32_t)(src)\
62822 #define PAPRD_TRAINER_STAT1__PAPRD_TRAIN_ACTIVE__READ(src) \
62823 (((u_int32_t)(src)\
62836 #define PAPRD_TRAINER_STAT1__PAPRD_RX_GAIN_IDX__READ(src) \
62837 (((u_int32_t)(src)\
62844 #define PAPRD_TRAINER_STAT1__PAPRD_AGC2_PWR__READ(src) \
62845 (((u_int32_t)(src)\
62865 #define PAPRD_TRAINER_STAT2__PAPRD_FINE_VAL__READ(src) \
62866 (u_int32_t)(src)\
62873 #define PAPRD_TRAINER_STAT2__PAPRD_COARSE_IDX__READ(src) \
62874 (((u_int32_t)(src)\
62881 #define PAPRD_TRAINER_STAT2__PAPRD_FINE_IDX__READ(src) \
62882 (((u_int32_t)(src)\
62901 #define PAPRD_TRAINER_STAT3__PAPRD_TRAIN_SAMPLES_CNT__READ(src) \
62902 (u_int32_t)(src)\
62921 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__READ(src) \
62922 (u_int32_t)(src)\
62924 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__WRITE(src) \
62925 ((u_int32_t)(src)\
62927 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__MODIFY(dst, src) \
62929 ~0x00000007U) | ((u_int32_t)(src) &\
62931 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_1__VERIFY(src) \
62932 (!(((u_int32_t)(src)\
62939 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__READ(src) \
62940 (((u_int32_t)(src)\
62942 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__WRITE(src) \
62943 (((u_int32_t)(src)\
62945 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__MODIFY(dst, src) \
62947 ~0x00000008U) | (((u_int32_t)(src) <<\
62949 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_DET_HANG__VERIFY(src) \
62950 (!((((u_int32_t)(src)\
62963 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__READ(src) \
62964 (((u_int32_t)(src)\
62966 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__WRITE(src) \
62967 (((u_int32_t)(src)\
62969 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__MODIFY(dst, src) \
62971 ~0x000000f0U) | (((u_int32_t)(src) <<\
62973 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_2__VERIFY(src) \
62974 (!((((u_int32_t)(src)\
62981 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__READ(src) \
62982 (((u_int32_t)(src)\
62984 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__WRITE(src) \
62985 (((u_int32_t)(src)\
62987 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__MODIFY(dst, src) \
62989 ~0x00000f00U) | (((u_int32_t)(src) <<\
62991 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_3__VERIFY(src) \
62992 (!((((u_int32_t)(src)\
62999 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__READ(src) \
63000 (((u_int32_t)(src)\
63002 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__WRITE(src) \
63003 (((u_int32_t)(src)\
63005 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__MODIFY(dst, src) \
63007 ~0x0000f000U) | (((u_int32_t)(src) <<\
63009 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_4__VERIFY(src) \
63010 (!((((u_int32_t)(src)\
63017 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__READ(src) \
63018 (((u_int32_t)(src)\
63020 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__WRITE(src) \
63021 (((u_int32_t)(src)\
63023 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__MODIFY(dst, src) \
63025 ~0x000f0000U) | (((u_int32_t)(src) <<\
63027 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_5__VERIFY(src) \
63028 (!((((u_int32_t)(src)\
63035 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__READ(src) \
63036 (((u_int32_t)(src)\
63038 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__WRITE(src) \
63039 (((u_int32_t)(src)\
63041 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__MODIFY(dst, src) \
63043 ~0x00f00000U) | (((u_int32_t)(src) <<\
63045 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_6__VERIFY(src) \
63046 (!((((u_int32_t)(src)\
63053 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__READ(src) \
63054 (((u_int32_t)(src)\
63056 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__WRITE(src) \
63057 (((u_int32_t)(src)\
63059 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__MODIFY(dst, src) \
63061 ~0x0f000000U) | (((u_int32_t)(src) <<\
63063 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_7__VERIFY(src) \
63064 (!((((u_int32_t)(src)\
63071 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__READ(src) \
63072 (((u_int32_t)(src)\
63074 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__WRITE(src) \
63075 (((u_int32_t)(src)\
63077 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__MODIFY(dst, src) \
63079 ~0xf0000000U) | (((u_int32_t)(src) <<\
63081 #define PANIC_WATCHDOG_STATUS__PANIC_WATCHDOG_STATUS_8__VERIFY(src) \
63082 (!((((u_int32_t)(src)\
63102 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__READ(src) \
63103 (u_int32_t)(src)\
63105 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__WRITE(src) \
63106 ((u_int32_t)(src)\
63108 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__MODIFY(dst, src) \
63110 ~0x00000001U) | ((u_int32_t)(src) &\
63112 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_NON_IDLE__VERIFY(src) \
63113 (!(((u_int32_t)(src)\
63126 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__READ(src) \
63127 (((u_int32_t)(src)\
63129 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__WRITE(src) \
63130 (((u_int32_t)(src)\
63132 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__MODIFY(dst, src) \
63134 ~0x00000002U) | (((u_int32_t)(src) <<\
63136 #define PANIC_WATCHDOG_CTRL_1__ENABLE_PANIC_WATCHDOG_IDLE__VERIFY(src) \
63137 (!((((u_int32_t)(src)\
63150 #define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__READ(src) \
63151 (((u_int32_t)(src)\
63153 #define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__WRITE(src) \
63154 (((u_int32_t)(src)\
63156 #define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__MODIFY(dst, src) \
63158 ~0x0000fffcU) | (((u_int32_t)(src) <<\
63160 #define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_NON_IDLE_LIMIT__VERIFY(src) \
63161 (!((((u_int32_t)(src)\
63168 #define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__READ(src) \
63169 (((u_int32_t)(src)\
63171 #define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__WRITE(src) \
63172 (((u_int32_t)(src)\
63174 #define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__MODIFY(dst, src) \
63176 ~0xffff0000U) | (((u_int32_t)(src) <<\
63178 #define PANIC_WATCHDOG_CTRL_1__PANIC_WATCHDOG_IDLE_LIMIT__VERIFY(src) \
63179 (!((((u_int32_t)(src)\
63199 #define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__READ(src) \
63200 (u_int32_t)(src)\
63202 #define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__WRITE(src) \
63203 ((u_int32_t)(src)\
63205 #define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__MODIFY(dst, src) \
63207 ~0x00000001U) | ((u_int32_t)(src) &\
63209 #define PANIC_WATCHDOG_CTRL_2__FORCE_FAST_ADC_CLK__VERIFY(src) \
63210 (!(((u_int32_t)(src)\
63223 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__READ(src) \
63224 (((u_int32_t)(src)\
63226 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__WRITE(src) \
63227 (((u_int32_t)(src)\
63229 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__MODIFY(dst, src) \
63231 ~0x00000002U) | (((u_int32_t)(src) <<\
63233 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_RESET_ENA__VERIFY(src) \
63234 (!((((u_int32_t)(src)\
63247 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__READ(src) \
63248 (((u_int32_t)(src)\
63250 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__WRITE(src) \
63251 (((u_int32_t)(src)\
63253 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__MODIFY(dst, src) \
63255 ~0x00000004U) | (((u_int32_t)(src) <<\
63257 #define PANIC_WATCHDOG_CTRL_2__PANIC_WATCHDOG_IRQ_ENA__VERIFY(src) \
63258 (!((((u_int32_t)(src)\
63284 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__READ(src) \
63285 (u_int32_t)(src)\
63287 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__WRITE(src) \
63288 ((u_int32_t)(src)\
63290 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__MODIFY(dst, src) \
63292 ~0x00000001U) | ((u_int32_t)(src) &\
63294 #define BLUETOOTH_CNTL__BT_BREAK_CCK_EN__VERIFY(src) \
63295 (!(((u_int32_t)(src)\
63308 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__READ(src) \
63309 (((u_int32_t)(src)\
63311 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__WRITE(src) \
63312 (((u_int32_t)(src)\
63314 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__MODIFY(dst, src) \
63316 ~0x00000002U) | (((u_int32_t)(src) <<\
63318 #define BLUETOOTH_CNTL__BT_ANT_HALT_WLAN__VERIFY(src) \
63319 (!((((u_int32_t)(src)\
63345 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__READ(src) \
63346 (u_int32_t)(src)\
63348 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__WRITE(src) \
63349 ((u_int32_t)(src)\
63351 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__MODIFY(dst, src) \
63353 ~0x00000001U) | ((u_int32_t)(src) &\
63355 #define PHYONLY_WARM_RESET__PHYONLY_RST_WARM_L__VERIFY(src) \
63356 (!(((u_int32_t)(src)\
63382 #define PHYONLY_CONTROL__RX_DRAIN_RATE__READ(src) \
63383 (u_int32_t)(src)\
63385 #define PHYONLY_CONTROL__RX_DRAIN_RATE__WRITE(src) \
63386 ((u_int32_t)(src)\
63388 #define PHYONLY_CONTROL__RX_DRAIN_RATE__MODIFY(dst, src) \
63390 ~0x00000001U) | ((u_int32_t)(src) &\
63392 #define PHYONLY_CONTROL__RX_DRAIN_RATE__VERIFY(src) \
63393 (!(((u_int32_t)(src)\
63406 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__READ(src) \
63407 (((u_int32_t)(src)\
63409 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__WRITE(src) \
63410 (((u_int32_t)(src)\
63412 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__MODIFY(dst, src) \
63414 ~0x00000002U) | (((u_int32_t)(src) <<\
63416 #define PHYONLY_CONTROL__LATE_TX_SIGNAL_SYMBOL__VERIFY(src) \
63417 (!((((u_int32_t)(src)\
63430 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__READ(src) \
63431 (((u_int32_t)(src)\
63433 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__WRITE(src) \
63434 (((u_int32_t)(src)\
63436 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__MODIFY(dst, src) \
63438 ~0x00000004U) | (((u_int32_t)(src) <<\
63440 #define PHYONLY_CONTROL__GENERATE_SCRAMBLER__VERIFY(src) \
63441 (!((((u_int32_t)(src)\
63454 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__READ(src) \
63455 (((u_int32_t)(src)\
63457 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__WRITE(src) \
63458 (((u_int32_t)(src)\
63460 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__MODIFY(dst, src) \
63462 ~0x00000008U) | (((u_int32_t)(src) <<\
63464 #define PHYONLY_CONTROL__TX_ANTENNA_SELECT__VERIFY(src) \
63465 (!((((u_int32_t)(src)\
63478 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__READ(src) \
63479 (((u_int32_t)(src)\
63481 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__WRITE(src) \
63482 (((u_int32_t)(src)\
63484 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__MODIFY(dst, src) \
63486 ~0x00000010U) | (((u_int32_t)(src) <<\
63488 #define PHYONLY_CONTROL__STATIC_TX_ANTENNA__VERIFY(src) \
63489 (!((((u_int32_t)(src)\
63502 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__READ(src) \
63503 (((u_int32_t)(src)\
63505 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__WRITE(src) \
63506 (((u_int32_t)(src)\
63508 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__MODIFY(dst, src) \
63510 ~0x00000020U) | (((u_int32_t)(src) <<\
63512 #define PHYONLY_CONTROL__RX_ANTENNA_SELECT__VERIFY(src) \
63513 (!((((u_int32_t)(src)\
63526 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__READ(src) \
63527 (((u_int32_t)(src)\
63529 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__WRITE(src) \
63530 (((u_int32_t)(src)\
63532 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__MODIFY(dst, src) \
63534 ~0x00000040U) | (((u_int32_t)(src) <<\
63536 #define PHYONLY_CONTROL__STATIC_RX_ANTENNA__VERIFY(src) \
63537 (!((((u_int32_t)(src)\
63550 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__READ(src) \
63551 (((u_int32_t)(src)\
63553 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__WRITE(src) \
63554 (((u_int32_t)(src)\
63556 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__MODIFY(dst, src) \
63558 ~0x00000080U) | (((u_int32_t)(src) <<\
63560 #define PHYONLY_CONTROL__EN_LOW_FREQ_SLEEP__VERIFY(src) \
63561 (!((((u_int32_t)(src)\
63587 #define ECO_CTRL__ECO_CTRL__READ(src) (u_int32_t)(src) & 0x000000ffU
63588 #define ECO_CTRL__ECO_CTRL__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
63589 #define ECO_CTRL__ECO_CTRL__MODIFY(dst, src) \
63591 ~0x000000ffU) | ((u_int32_t)(src) &\
63593 #define ECO_CTRL__ECO_CTRL__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
63612 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U
63632 #define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__READ(src) \
63633 (u_int32_t)(src)\
63635 #define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__WRITE(src) \
63636 ((u_int32_t)(src)\
63638 #define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__MODIFY(dst, src) \
63640 ~0x000001ffU) | ((u_int32_t)(src) &\
63642 #define EXT_CHAN_PWR_THR_2_B1__CF_MAXCCAPWR_EXT_1__VERIFY(src) \
63643 (!(((u_int32_t)(src)\
63650 #define EXT_CHAN_PWR_THR_2_B1__MINCCAPWR_EXT_1__READ(src) \
63651 (((u_int32_t)(src)\
63671 #define SPUR_REPORT_B1__SPUR_EST_I_1__READ(src) (u_int32_t)(src) & 0x000000ffU
63677 #define SPUR_REPORT_B1__SPUR_EST_Q_1__READ(src) \
63678 (((u_int32_t)(src)\
63685 #define SPUR_REPORT_B1__POWER_WITH_SPUR_REMOVED_1__READ(src) \
63686 (((u_int32_t)(src)\
63705 #define IQ_ADC_MEAS_0_B1__GAIN_DC_IQ_CAL_MEAS_0_1__READ(src) \
63706 (u_int32_t)(src)\
63725 #define IQ_ADC_MEAS_1_B1__GAIN_DC_IQ_CAL_MEAS_1_1__READ(src) \
63726 (u_int32_t)(src)\
63745 #define IQ_ADC_MEAS_2_B1__GAIN_DC_IQ_CAL_MEAS_2_1__READ(src) \
63746 (u_int32_t)(src)\
63765 #define IQ_ADC_MEAS_3_B1__GAIN_DC_IQ_CAL_MEAS_3_1__READ(src) \
63766 (u_int32_t)(src)\
63785 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__READ(src) \
63786 (u_int32_t)(src)\
63788 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__WRITE(src) \
63789 ((u_int32_t)(src)\
63791 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__MODIFY(dst, src) \
63793 ~0x00000001U) | ((u_int32_t)(src) &\
63795 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ENABLE_1__VERIFY(src) \
63796 (!(((u_int32_t)(src)\
63809 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__READ(src) \
63810 (((u_int32_t)(src)\
63812 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__WRITE(src) \
63813 (((u_int32_t)(src)\
63815 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__MODIFY(dst, src) \
63817 ~0x0000007eU) | (((u_int32_t)(src) <<\
63819 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_BIAS_1__VERIFY(src) \
63820 (!((((u_int32_t)(src)\
63827 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__READ(src) \
63828 (((u_int32_t)(src)\
63830 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__WRITE(src) \
63831 (((u_int32_t)(src)\
63833 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__MODIFY(dst, src) \
63835 ~0x0001ff80U) | (((u_int32_t)(src) <<\
63837 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_INIT_1__VERIFY(src) \
63838 (!((((u_int32_t)(src)\
63845 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__READ(src) \
63846 (((u_int32_t)(src)\
63848 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__WRITE(src) \
63849 (((u_int32_t)(src)\
63851 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__MODIFY(dst, src) \
63853 ~0x01fe0000U) | (((u_int32_t)(src) <<\
63855 #define TX_PHASE_RAMP_B1__CF_PHASE_RAMP_ALPHA_1__VERIFY(src) \
63856 (!((((u_int32_t)(src)\
63876 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__READ(src) \
63877 (u_int32_t)(src)\
63879 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__WRITE(src) \
63880 ((u_int32_t)(src)\
63882 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__MODIFY(dst, src) \
63884 ~0x0000003fU) | ((u_int32_t)(src) &\
63886 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_Q_COEFF_1__VERIFY(src) \
63887 (!(((u_int32_t)(src)\
63894 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__READ(src) \
63895 (((u_int32_t)(src)\
63897 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__WRITE(src) \
63898 (((u_int32_t)(src)\
63900 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__MODIFY(dst, src) \
63902 ~0x00000fc0U) | (((u_int32_t)(src) <<\
63904 #define ADC_GAIN_DC_CORR_B1__ADC_GAIN_CORR_I_COEFF_1__VERIFY(src) \
63905 (!((((u_int32_t)(src)\
63912 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__READ(src) \
63913 (((u_int32_t)(src)\
63915 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__WRITE(src) \
63916 (((u_int32_t)(src)\
63918 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__MODIFY(dst, src) \
63920 ~0x001ff000U) | (((u_int32_t)(src) <<\
63922 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_Q_COEFF_1__VERIFY(src) \
63923 (!((((u_int32_t)(src)\
63930 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__READ(src) \
63931 (((u_int32_t)(src)\
63933 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__WRITE(src) \
63934 (((u_int32_t)(src)\
63936 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__MODIFY(dst, src) \
63938 ~0x3fe00000U) | (((u_int32_t)(src) <<\
63940 #define ADC_GAIN_DC_CORR_B1__ADC_DC_CORR_I_COEFF_1__VERIFY(src) \
63941 (!((((u_int32_t)(src)\
63961 #define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__READ(src) \
63962 (u_int32_t)(src)\
63964 #define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__WRITE(src) \
63965 ((u_int32_t)(src)\
63967 #define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \
63969 ~0x0000007fU) | ((u_int32_t)(src) &\
63971 #define RX_IQ_CORR_B1__RX_IQCORR_Q_Q_COFF_1__VERIFY(src) \
63972 (!(((u_int32_t)(src)\
63979 #define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__READ(src) \
63980 (((u_int32_t)(src)\
63982 #define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__WRITE(src) \
63983 (((u_int32_t)(src)\
63985 #define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \
63987 ~0x00003f80U) | (((u_int32_t)(src) <<\
63989 #define RX_IQ_CORR_B1__RX_IQCORR_Q_I_COFF_1__VERIFY(src) \
63990 (!((((u_int32_t)(src)\
63997 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__READ(src) \
63998 (((u_int32_t)(src)\
64000 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__WRITE(src) \
64001 (((u_int32_t)(src)\
64003 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__MODIFY(dst, src) \
64005 ~0x003f8000U) | (((u_int32_t)(src) <<\
64007 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_Q_COFF_1__VERIFY(src) \
64008 (!((((u_int32_t)(src)\
64015 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__READ(src) \
64016 (((u_int32_t)(src)\
64018 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__WRITE(src) \
64019 (((u_int32_t)(src)\
64021 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__MODIFY(dst, src) \
64023 ~0x1fc00000U) | (((u_int32_t)(src) <<\
64025 #define RX_IQ_CORR_B1__LOOPBACK_IQCORR_Q_I_COFF_1__VERIFY(src) \
64026 (!((((u_int32_t)(src)\
64046 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__READ(src) \
64047 (u_int32_t)(src)\
64049 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__WRITE(src) \
64050 ((u_int32_t)(src)\
64052 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__MODIFY(dst, src) \
64054 ~0x00000001U) | ((u_int32_t)(src) &\
64056 #define PAPRD_CTRL0_B1__PAPRD_ENABLE_1__VERIFY(src) \
64057 (!(((u_int32_t)(src)\
64070 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__READ(src) \
64071 (((u_int32_t)(src)\
64073 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__WRITE(src) \
64074 (((u_int32_t)(src)\
64076 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__MODIFY(dst, src) \
64078 ~0x00000002U) | (((u_int32_t)(src) <<\
64080 #define PAPRD_CTRL0_B1__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_1__VERIFY(src) \
64081 (!((((u_int32_t)(src)\
64094 #define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__READ(src) \
64095 (((u_int32_t)(src)\
64097 #define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__WRITE(src) \
64098 (((u_int32_t)(src)\
64100 #define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__MODIFY(dst, src) \
64102 ~0x07fffffcU) | (((u_int32_t)(src) <<\
64104 #define PAPRD_CTRL0_B1__PAPRD_VALID_GAIN_1__VERIFY(src) \
64105 (!((((u_int32_t)(src)\
64112 #define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__READ(src) \
64113 (((u_int32_t)(src)\
64115 #define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__WRITE(src) \
64116 (((u_int32_t)(src)\
64118 #define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__MODIFY(dst, src) \
64120 ~0xf8000000U) | (((u_int32_t)(src) <<\
64122 #define PAPRD_CTRL0_B1__PAPRD_MAG_THRSH_1__VERIFY(src) \
64123 (!((((u_int32_t)(src)\
64143 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__READ(src) \
64144 (u_int32_t)(src)\
64146 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__WRITE(src) \
64147 ((u_int32_t)(src)\
64149 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__MODIFY(dst, src) \
64151 ~0x00000001U) | ((u_int32_t)(src) &\
64153 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_SCALING_ENABLE_1__VERIFY(src) \
64154 (!(((u_int32_t)(src)\
64167 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__READ(src) \
64168 (((u_int32_t)(src)\
64170 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__WRITE(src) \
64171 (((u_int32_t)(src)\
64173 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__MODIFY(dst, src) \
64175 ~0x00000002U) | (((u_int32_t)(src) <<\
64177 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2AM_ENABLE_1__VERIFY(src) \
64178 (!((((u_int32_t)(src)\
64191 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__READ(src) \
64192 (((u_int32_t)(src)\
64194 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__WRITE(src) \
64195 (((u_int32_t)(src)\
64197 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__MODIFY(dst, src) \
64199 ~0x00000004U) | (((u_int32_t)(src) <<\
64201 #define PAPRD_CTRL1_B1__PAPRD_ADAPTIVE_AM2PM_ENABLE_1__VERIFY(src) \
64202 (!((((u_int32_t)(src)\
64215 #define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__READ(src) \
64216 (((u_int32_t)(src)\
64218 #define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__WRITE(src) \
64219 (((u_int32_t)(src)\
64221 #define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__MODIFY(dst, src) \
64223 ~0x000001f8U) | (((u_int32_t)(src) <<\
64225 #define PAPRD_CTRL1_B1__PAPRD_POWER_AT_AM2AM_CAL_1__VERIFY(src) \
64226 (!((((u_int32_t)(src)\
64233 #define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__READ(src) \
64234 (((u_int32_t)(src)\
64236 #define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__WRITE(src) \
64237 (((u_int32_t)(src)\
64239 #define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__MODIFY(dst, src) \
64241 ~0x0001fe00U) | (((u_int32_t)(src) <<\
64243 #define PAPRD_CTRL1_B1__PA_GAIN_SCALE_FACTOR_1__VERIFY(src) \
64244 (!((((u_int32_t)(src)\
64251 #define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__READ(src) \
64252 (((u_int32_t)(src)\
64254 #define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__WRITE(src) \
64255 (((u_int32_t)(src)\
64257 #define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__MODIFY(dst, src) \
64259 ~0x07fe0000U) | (((u_int32_t)(src) <<\
64261 #define PAPRD_CTRL1_B1__PAPRD_MAG_SCALE_FACTOR_1__VERIFY(src) \
64262 (!((((u_int32_t)(src)\
64269 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__READ(src) \
64270 (((u_int32_t)(src)\
64272 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__WRITE(src) \
64273 (((u_int32_t)(src)\
64275 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__MODIFY(dst, src) \
64277 ~0x08000000U) | (((u_int32_t)(src) <<\
64279 #define PAPRD_CTRL1_B1__PAPRD_TRAINER_IANDQ_SEL_1__VERIFY(src) \
64280 (!((((u_int32_t)(src)\
64306 #define PA_GAIN123_B1__PA_GAIN1_1__READ(src) (u_int32_t)(src) & 0x000003ffU
64307 #define PA_GAIN123_B1__PA_GAIN1_1__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
64308 #define PA_GAIN123_B1__PA_GAIN1_1__MODIFY(dst, src) \
64310 ~0x000003ffU) | ((u_int32_t)(src) &\
64312 #define PA_GAIN123_B1__PA_GAIN1_1__VERIFY(src) \
64313 (!(((u_int32_t)(src)\
64320 #define PA_GAIN123_B1__PA_GAIN2_1__READ(src) \
64321 (((u_int32_t)(src)\
64323 #define PA_GAIN123_B1__PA_GAIN2_1__WRITE(src) \
64324 (((u_int32_t)(src)\
64326 #define PA_GAIN123_B1__PA_GAIN2_1__MODIFY(dst, src) \
64328 ~0x000ffc00U) | (((u_int32_t)(src) <<\
64330 #define PA_GAIN123_B1__PA_GAIN2_1__VERIFY(src) \
64331 (!((((u_int32_t)(src)\
64338 #define PA_GAIN123_B1__PA_GAIN3_1__READ(src) \
64339 (((u_int32_t)(src)\
64341 #define PA_GAIN123_B1__PA_GAIN3_1__WRITE(src) \
64342 (((u_int32_t)(src)\
64344 #define PA_GAIN123_B1__PA_GAIN3_1__MODIFY(dst, src) \
64346 ~0x3ff00000U) | (((u_int32_t)(src) <<\
64348 #define PA_GAIN123_B1__PA_GAIN3_1__VERIFY(src) \
64349 (!((((u_int32_t)(src)\
64369 #define PA_GAIN45_B1__PA_GAIN4_1__READ(src) (u_int32_t)(src) & 0x000003ffU
64370 #define PA_GAIN45_B1__PA_GAIN4_1__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
64371 #define PA_GAIN45_B1__PA_GAIN4_1__MODIFY(dst, src) \
64373 ~0x000003ffU) | ((u_int32_t)(src) &\
64375 #define PA_GAIN45_B1__PA_GAIN4_1__VERIFY(src) \
64376 (!(((u_int32_t)(src)\
64383 #define PA_GAIN45_B1__PA_GAIN5_1__READ(src) \
64384 (((u_int32_t)(src)\
64386 #define PA_GAIN45_B1__PA_GAIN5_1__WRITE(src) \
64387 (((u_int32_t)(src)\
64389 #define PA_GAIN45_B1__PA_GAIN5_1__MODIFY(dst, src) \
64391 ~0x000ffc00U) | (((u_int32_t)(src) <<\
64393 #define PA_GAIN45_B1__PA_GAIN5_1__VERIFY(src) \
64394 (!((((u_int32_t)(src)\
64401 #define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__READ(src) \
64402 (((u_int32_t)(src)\
64404 #define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__WRITE(src) \
64405 (((u_int32_t)(src)\
64407 #define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__MODIFY(dst, src) \
64409 ~0x01f00000U) | (((u_int32_t)(src) <<\
64411 #define PA_GAIN45_B1__PAPRD_ADAPTIVE_TABLE_VALID_1__VERIFY(src) \
64412 (!((((u_int32_t)(src)\
64432 #define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__READ(src) \
64433 (u_int32_t)(src)\
64435 #define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__WRITE(src) \
64436 ((u_int32_t)(src)\
64438 #define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__MODIFY(dst, src) \
64440 ~0x0003ffffU) | ((u_int32_t)(src) &\
64442 #define PAPRD_PRE_POST_SCALE_0_B1__PAPRD_PRE_POST_SCALING_0_1__VERIFY(src) \
64443 (!(((u_int32_t)(src)\
64463 #define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__READ(src) \
64464 (u_int32_t)(src)\
64466 #define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__WRITE(src) \
64467 ((u_int32_t)(src)\
64469 #define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__MODIFY(dst, src) \
64471 ~0x0003ffffU) | ((u_int32_t)(src) &\
64473 #define PAPRD_PRE_POST_SCALE_1_B1__PAPRD_PRE_POST_SCALING_1_1__VERIFY(src) \
64474 (!(((u_int32_t)(src)\
64494 #define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__READ(src) \
64495 (u_int32_t)(src)\
64497 #define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__WRITE(src) \
64498 ((u_int32_t)(src)\
64500 #define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__MODIFY(dst, src) \
64502 ~0x0003ffffU) | ((u_int32_t)(src) &\
64504 #define PAPRD_PRE_POST_SCALE_2_B1__PAPRD_PRE_POST_SCALING_2_1__VERIFY(src) \
64505 (!(((u_int32_t)(src)\
64525 #define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__READ(src) \
64526 (u_int32_t)(src)\
64528 #define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__WRITE(src) \
64529 ((u_int32_t)(src)\
64531 #define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__MODIFY(dst, src) \
64533 ~0x0003ffffU) | ((u_int32_t)(src) &\
64535 #define PAPRD_PRE_POST_SCALE_3_B1__PAPRD_PRE_POST_SCALING_3_1__VERIFY(src) \
64536 (!(((u_int32_t)(src)\
64556 #define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__READ(src) \
64557 (u_int32_t)(src)\
64559 #define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__WRITE(src) \
64560 ((u_int32_t)(src)\
64562 #define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__MODIFY(dst, src) \
64564 ~0x0003ffffU) | ((u_int32_t)(src) &\
64566 #define PAPRD_PRE_POST_SCALE_4_B1__PAPRD_PRE_POST_SCALING_4_1__VERIFY(src) \
64567 (!(((u_int32_t)(src)\
64587 #define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__READ(src) \
64588 (u_int32_t)(src)\
64590 #define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__WRITE(src) \
64591 ((u_int32_t)(src)\
64593 #define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__MODIFY(dst, src) \
64595 ~0x0003ffffU) | ((u_int32_t)(src) &\
64597 #define PAPRD_PRE_POST_SCALE_5_B1__PAPRD_PRE_POST_SCALING_5_1__VERIFY(src) \
64598 (!(((u_int32_t)(src)\
64618 #define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__READ(src) \
64619 (u_int32_t)(src)\
64621 #define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__WRITE(src) \
64622 ((u_int32_t)(src)\
64624 #define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__MODIFY(dst, src) \
64626 ~0x0003ffffU) | ((u_int32_t)(src) &\
64628 #define PAPRD_PRE_POST_SCALE_6_B1__PAPRD_PRE_POST_SCALING_6_1__VERIFY(src) \
64629 (!(((u_int32_t)(src)\
64649 #define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__READ(src) \
64650 (u_int32_t)(src)\
64652 #define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__WRITE(src) \
64653 ((u_int32_t)(src)\
64655 #define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__MODIFY(dst, src) \
64657 ~0x0003ffffU) | ((u_int32_t)(src) &\
64659 #define PAPRD_PRE_POST_SCALE_7_B1__PAPRD_PRE_POST_SCALING_7_1__VERIFY(src) \
64660 (!(((u_int32_t)(src)\
64680 #define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU
64681 #define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU)
64682 #define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
64684 ~0x003fffffU) | ((u_int32_t)(src) &\
64686 #define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \
64687 (!(((u_int32_t)(src)\
64707 #define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \
64708 (u_int32_t)(src)\
64727 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U
64747 #define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__READ(src) \
64748 (u_int32_t)(src)\
64750 #define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__WRITE(src) \
64751 ((u_int32_t)(src)\
64753 #define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__MODIFY(dst, src) \
64755 ~0x000000ffU) | ((u_int32_t)(src) &\
64757 #define GAIN_FORCE_MAX_GAINS_B1__RF_GAIN_F_1__VERIFY(src) \
64758 (!(((u_int32_t)(src)\
64765 #define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__READ(src) \
64766 (((u_int32_t)(src)\
64768 #define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__WRITE(src) \
64769 (((u_int32_t)(src)\
64771 #define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__MODIFY(dst, src) \
64773 ~0x0000ff00U) | (((u_int32_t)(src) <<\
64775 #define GAIN_FORCE_MAX_GAINS_B1__MB_GAIN_F_1__VERIFY(src) \
64776 (!((((u_int32_t)(src)\
64783 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__READ(src) \
64784 (((u_int32_t)(src)\
64786 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__WRITE(src) \
64787 (((u_int32_t)(src)\
64789 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__MODIFY(dst, src) \
64791 ~0x00010000U) | (((u_int32_t)(src) <<\
64793 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_SW_F_1__VERIFY(src) \
64794 (!((((u_int32_t)(src)\
64807 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__READ(src) \
64808 (((u_int32_t)(src)\
64810 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__WRITE(src) \
64811 (((u_int32_t)(src)\
64813 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__MODIFY(dst, src) \
64815 ~0x00020000U) | (((u_int32_t)(src) <<\
64817 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_SW_F_1__VERIFY(src) \
64818 (!((((u_int32_t)(src)\
64831 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__READ(src) \
64832 (((u_int32_t)(src)\
64834 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__WRITE(src) \
64835 (((u_int32_t)(src)\
64837 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__MODIFY(dst, src) \
64839 ~0x01fc0000U) | (((u_int32_t)(src) <<\
64841 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN1_HYST_MARGIN_1__VERIFY(src) \
64842 (!((((u_int32_t)(src)\
64849 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__READ(src) \
64850 (((u_int32_t)(src)\
64852 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__WRITE(src) \
64853 (((u_int32_t)(src)\
64855 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__MODIFY(dst, src) \
64857 ~0xfe000000U) | (((u_int32_t)(src) <<\
64859 #define GAIN_FORCE_MAX_GAINS_B1__XATTEN2_HYST_MARGIN_1__VERIFY(src) \
64860 (!((((u_int32_t)(src)\
64880 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__READ(src) \
64881 (u_int32_t)(src)\
64883 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__WRITE(src) \
64884 ((u_int32_t)(src)\
64886 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__MODIFY(dst, src) \
64888 ~0x0000003fU) | ((u_int32_t)(src) &\
64890 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_DB_1__VERIFY(src) \
64891 (!(((u_int32_t)(src)\
64898 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__READ(src) \
64899 (((u_int32_t)(src)\
64901 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__WRITE(src) \
64902 (((u_int32_t)(src)\
64904 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__MODIFY(dst, src) \
64906 ~0x00000fc0U) | (((u_int32_t)(src) <<\
64908 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_DB_1__VERIFY(src) \
64909 (!((((u_int32_t)(src)\
64916 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__READ(src) \
64917 (((u_int32_t)(src)\
64919 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__WRITE(src) \
64920 (((u_int32_t)(src)\
64922 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__MODIFY(dst, src) \
64924 ~0x0001f000U) | (((u_int32_t)(src) <<\
64926 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN1_MARGIN_1__VERIFY(src) \
64927 (!((((u_int32_t)(src)\
64934 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__READ(src) \
64935 (((u_int32_t)(src)\
64937 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__WRITE(src) \
64938 (((u_int32_t)(src)\
64940 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__MODIFY(dst, src) \
64942 ~0x003e0000U) | (((u_int32_t)(src) <<\
64944 #define EXT_ATTEN_SWITCH_CTL_B1__XATTEN2_MARGIN_1__VERIFY(src) \
64945 (!((((u_int32_t)(src)\
64952 #define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__READ(src) \
64953 (((u_int32_t)(src)\
64955 #define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__WRITE(src) \
64956 (((u_int32_t)(src)\
64958 #define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__MODIFY(dst, src) \
64960 ~0x07c00000U) | (((u_int32_t)(src) <<\
64962 #define EXT_ATTEN_SWITCH_CTL_B1__XLNA_GAIN_DB_1__VERIFY(src) \
64963 (!((((u_int32_t)(src)\
64983 #define CCA_B1__CF_MAXCCAPWR_1__READ(src) (u_int32_t)(src) & 0x000001ffU
64984 #define CCA_B1__CF_MAXCCAPWR_1__WRITE(src) ((u_int32_t)(src) & 0x000001ffU)
64985 #define CCA_B1__CF_MAXCCAPWR_1__MODIFY(dst, src) \
64987 ~0x000001ffU) | ((u_int32_t)(src) &\
64989 #define CCA_B1__CF_MAXCCAPWR_1__VERIFY(src) \
64990 (!(((u_int32_t)(src)\
64997 #define CCA_B1__MINCCAPWR_1__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20)
65016 #define CCA_CTRL_2_B1__MINCCAPWR_THR_1__READ(src) \
65017 (u_int32_t)(src)\
65019 #define CCA_CTRL_2_B1__MINCCAPWR_THR_1__WRITE(src) \
65020 ((u_int32_t)(src)\
65022 #define CCA_CTRL_2_B1__MINCCAPWR_THR_1__MODIFY(dst, src) \
65024 ~0x000001ffU) | ((u_int32_t)(src) &\
65026 #define CCA_CTRL_2_B1__MINCCAPWR_THR_1__VERIFY(src) \
65027 (!(((u_int32_t)(src)\
65034 #define CCA_CTRL_2_B1__NF_GAIN_COMP_1__READ(src) \
65035 (((u_int32_t)(src)\
65037 #define CCA_CTRL_2_B1__NF_GAIN_COMP_1__WRITE(src) \
65038 (((u_int32_t)(src)\
65040 #define CCA_CTRL_2_B1__NF_GAIN_COMP_1__MODIFY(dst, src) \
65042 ~0x0003fc00U) | (((u_int32_t)(src) <<\
65044 #define CCA_CTRL_2_B1__NF_GAIN_COMP_1__VERIFY(src) \
65045 (!((((u_int32_t)(src)\
65065 #define RSSI_B1__RSSI_1__READ(src) (u_int32_t)(src) & 0x000000ffU
65071 #define RSSI_B1__RSSI_EXT_1__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
65089 #define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_I_1_CCK__READ(src) \
65090 (u_int32_t)(src)\
65097 #define SPUR_EST_CCK_REPORT_B1__SPUR_EST_SD_Q_1_CCK__READ(src) \
65098 (((u_int32_t)(src)\
65105 #define SPUR_EST_CCK_REPORT_B1__SPUR_EST_I_1_CCK__READ(src) \
65106 (((u_int32_t)(src)\
65113 #define SPUR_EST_CCK_REPORT_B1__SPUR_EST_Q_1_CCK__READ(src) \
65114 (((u_int32_t)(src)\
65133 #define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C1_RES_I_1__READ(src) \
65134 (u_int32_t)(src)\
65141 #define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C2_RES_I_1__READ(src) \
65142 (((u_int32_t)(src)\
65149 #define AGC_DIG_DC_STATUS_I_B1__DIG_DC_C3_RES_I_1__READ(src) \
65150 (((u_int32_t)(src)\
65169 #define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C1_RES_Q_1__READ(src) \
65170 (u_int32_t)(src)\
65177 #define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C2_RES_Q_1__READ(src) \
65178 (((u_int32_t)(src)\
65185 #define AGC_DIG_DC_STATUS_Q_B1__DIG_DC_C3_RES_Q_1__READ(src) \
65186 (((u_int32_t)(src)\
65205 #define RX_OCGAIN2__GAIN_ENTRY2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
65206 #define RX_OCGAIN2__GAIN_ENTRY2__MODIFY(dst, src) \
65208 ~0xffffffffU) | ((u_int32_t)(src) &\
65210 #define RX_OCGAIN2__GAIN_ENTRY2__VERIFY(src) \
65211 (!(((u_int32_t)(src)\
65230 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U
65250 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__READ(src) \
65251 (u_int32_t)(src)\
65253 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__WRITE(src) \
65254 ((u_int32_t)(src)\
65256 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__MODIFY(dst, src) \
65258 ~0x00000003U) | ((u_int32_t)(src) &\
65260 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_IDLE_1__VERIFY(src) \
65261 (!(((u_int32_t)(src)\
65268 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__READ(src) \
65269 (((u_int32_t)(src)\
65271 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__WRITE(src) \
65272 (((u_int32_t)(src)\
65274 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__MODIFY(dst, src) \
65276 ~0x0000000cU) | (((u_int32_t)(src) <<\
65278 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_T_1__VERIFY(src) \
65279 (!((((u_int32_t)(src)\
65286 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__READ(src) \
65287 (((u_int32_t)(src)\
65289 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__WRITE(src) \
65290 (((u_int32_t)(src)\
65292 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__MODIFY(dst, src) \
65294 ~0x00000030U) | (((u_int32_t)(src) <<\
65296 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_R_1__VERIFY(src) \
65297 (!((((u_int32_t)(src)\
65304 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__READ(src) \
65305 (((u_int32_t)(src)\
65307 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__WRITE(src) \
65308 (((u_int32_t)(src)\
65310 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__MODIFY(dst, src) \
65312 ~0x000000c0U) | (((u_int32_t)(src) <<\
65314 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX1_1__VERIFY(src) \
65315 (!((((u_int32_t)(src)\
65322 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__READ(src) \
65323 (((u_int32_t)(src)\
65325 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__WRITE(src) \
65326 (((u_int32_t)(src)\
65328 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__MODIFY(dst, src) \
65330 ~0x00000300U) | (((u_int32_t)(src) <<\
65332 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_RX12_1__VERIFY(src) \
65333 (!((((u_int32_t)(src)\
65340 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__READ(src) \
65341 (((u_int32_t)(src)\
65343 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__WRITE(src) \
65344 (((u_int32_t)(src)\
65346 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__MODIFY(dst, src) \
65348 ~0x00000c00U) | (((u_int32_t)(src) <<\
65350 #define SWITCH_TABLE_CHN_B1__SWITCH_TABLE_B_1__VERIFY(src) \
65351 (!((((u_int32_t)(src)\
65371 #define FCAL_2_B1__FLC_SW_CAP_VAL_1__READ(src) \
65372 (((u_int32_t)(src)\
65374 #define FCAL_2_B1__FLC_SW_CAP_VAL_1__WRITE(src) \
65375 (((u_int32_t)(src)\
65377 #define FCAL_2_B1__FLC_SW_CAP_VAL_1__MODIFY(dst, src) \
65379 ~0x000000f8U) | (((u_int32_t)(src) <<\
65381 #define FCAL_2_B1__FLC_SW_CAP_VAL_1__VERIFY(src) \
65382 (!((((u_int32_t)(src)\
65389 #define FCAL_2_B1__FLC_CAP_VAL_STATUS_1__READ(src) \
65390 (((u_int32_t)(src)\
65410 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__READ(src) \
65411 (u_int32_t)(src)\
65413 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__WRITE(src) \
65414 ((u_int32_t)(src)\
65416 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__MODIFY(dst, src) \
65418 ~0x00000001U) | ((u_int32_t)(src) &\
65420 #define DFT_TONE_CTRL_B1__DFT_TONE_EN_1__VERIFY(src) \
65421 (!(((u_int32_t)(src)\
65434 #define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__READ(src) \
65435 (((u_int32_t)(src)\
65437 #define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__WRITE(src) \
65438 (((u_int32_t)(src)\
65440 #define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__MODIFY(dst, src) \
65442 ~0x0000000cU) | (((u_int32_t)(src) <<\
65444 #define DFT_TONE_CTRL_B1__DFT_TONE_AMP_SEL_1__VERIFY(src) \
65445 (!((((u_int32_t)(src)\
65452 #define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__READ(src) \
65453 (((u_int32_t)(src)\
65455 #define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__WRITE(src) \
65456 (((u_int32_t)(src)\
65458 #define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__MODIFY(dst, src) \
65460 ~0x00001ff0U) | (((u_int32_t)(src) <<\
65462 #define DFT_TONE_CTRL_B1__DFT_TONE_FREQ_ANG_1__VERIFY(src) \
65463 (!((((u_int32_t)(src)\
65483 #define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU
65484 #define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
65485 #define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
65487 ~0xffffffffU) | ((u_int32_t)(src) &\
65489 #define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
65508 #define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU
65509 #define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
65510 #define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
65512 ~0xffffffffU) | ((u_int32_t)(src) &\
65514 #define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
65533 #define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU
65534 #define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
65535 #define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
65537 ~0xffffffffU) | ((u_int32_t)(src) &\
65539 #define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
65558 #define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU
65559 #define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
65560 #define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
65562 ~0xffffffffU) | ((u_int32_t)(src) &\
65564 #define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
65583 #define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU
65584 #define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
65585 #define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
65587 ~0xffffffffU) | ((u_int32_t)(src) &\
65589 #define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \
65590 (!(((u_int32_t)(src)\
65610 #define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU
65611 #define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
65612 #define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
65614 ~0xffffffffU) | ((u_int32_t)(src) &\
65616 #define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \
65617 (!(((u_int32_t)(src)\
65637 #define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU
65638 #define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
65639 #define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
65641 ~0xffffffffU) | ((u_int32_t)(src) &\
65643 #define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \
65644 (!(((u_int32_t)(src)\
65664 #define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU
65665 #define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
65666 #define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
65668 ~0xffffffffU) | ((u_int32_t)(src) &\
65670 #define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \
65671 (!(((u_int32_t)(src)\
65691 #define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU
65692 #define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU)
65693 #define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
65695 ~0x0000001fU) | ((u_int32_t)(src) &\
65697 #define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))
65703 #define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \
65704 (((u_int32_t)(src)\
65706 #define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \
65707 (((u_int32_t)(src)\
65709 #define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
65711 ~0x0000ffe0U) | (((u_int32_t)(src) <<\
65713 #define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \
65714 (!((((u_int32_t)(src)\
65721 #define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \
65722 (((u_int32_t)(src)\
65724 #define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \
65725 (((u_int32_t)(src)\
65727 #define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
65729 ~0x07ff0000U) | (((u_int32_t)(src) <<\
65731 #define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \
65732 (!((((u_int32_t)(src)\
65739 #define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27)
65740 #define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U)
65741 #define CL_TAB__BB_GAIN__MODIFY(dst, src) \
65743 ~0x78000000U) | (((u_int32_t)(src) <<\
65745 #define CL_TAB__BB_GAIN__VERIFY(src) \
65746 (!((((u_int32_t)(src)\
65766 #define CHAN_INFO_GAIN_B1__CHAN_INFO_RSSI_1__READ(src) \
65767 (u_int32_t)(src)\
65774 #define CHAN_INFO_GAIN_B1__CHAN_INFO_RF_GAIN_1__READ(src) \
65775 (((u_int32_t)(src)\
65782 #define CHAN_INFO_GAIN_B1__CHAN_INFO_MB_GAIN_1__READ(src) \
65783 (((u_int32_t)(src)\
65790 #define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN1_SW_1__READ(src) \
65791 (((u_int32_t)(src)\
65804 #define CHAN_INFO_GAIN_B1__CHAN_INFO_XATTEN2_SW_1__READ(src) \
65805 (((u_int32_t)(src)\
65830 #define TPC_4_B1__PD_AVG_VALID_1__READ(src) (u_int32_t)(src) & 0x00000001U
65842 #define TPC_4_B1__PD_AVG_OUT_1__READ(src) \
65843 (((u_int32_t)(src)\
65850 #define TPC_4_B1__DAC_GAIN_1__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9)
65856 #define TPC_4_B1__TX_GAIN_SETTING_1__READ(src) \
65857 (((u_int32_t)(src)\
65864 #define TPC_4_B1__RATE_SENT_1__READ(src) \
65865 (((u_int32_t)(src)\
65884 #define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__READ(src) \
65885 (((u_int32_t)(src)\
65887 #define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__WRITE(src) \
65888 (((u_int32_t)(src)\
65890 #define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__MODIFY(dst, src) \
65892 ~0x000003f0U) | (((u_int32_t)(src) <<\
65894 #define TPC_5_B1__PD_GAIN_BOUNDARY_1_1__VERIFY(src) \
65895 (!((((u_int32_t)(src)\
65902 #define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__READ(src) \
65903 (((u_int32_t)(src)\
65905 #define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__WRITE(src) \
65906 (((u_int32_t)(src)\
65908 #define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__MODIFY(dst, src) \
65910 ~0x0000fc00U) | (((u_int32_t)(src) <<\
65912 #define TPC_5_B1__PD_GAIN_BOUNDARY_2_1__VERIFY(src) \
65913 (!((((u_int32_t)(src)\
65920 #define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__READ(src) \
65921 (((u_int32_t)(src)\
65923 #define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__WRITE(src) \
65924 (((u_int32_t)(src)\
65926 #define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__MODIFY(dst, src) \
65928 ~0x003f0000U) | (((u_int32_t)(src) <<\
65930 #define TPC_5_B1__PD_GAIN_BOUNDARY_3_1__VERIFY(src) \
65931 (!((((u_int32_t)(src)\
65938 #define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__READ(src) \
65939 (((u_int32_t)(src)\
65941 #define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__WRITE(src) \
65942 (((u_int32_t)(src)\
65944 #define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__MODIFY(dst, src) \
65946 ~0x0fc00000U) | (((u_int32_t)(src) <<\
65948 #define TPC_5_B1__PD_GAIN_BOUNDARY_4_1__VERIFY(src) \
65949 (!((((u_int32_t)(src)\
65969 #define TPC_6_B1__PD_DAC_SETTING_1_1__READ(src) (u_int32_t)(src) & 0x0000003fU
65970 #define TPC_6_B1__PD_DAC_SETTING_1_1__WRITE(src) \
65971 ((u_int32_t)(src)\
65973 #define TPC_6_B1__PD_DAC_SETTING_1_1__MODIFY(dst, src) \
65975 ~0x0000003fU) | ((u_int32_t)(src) &\
65977 #define TPC_6_B1__PD_DAC_SETTING_1_1__VERIFY(src) \
65978 (!(((u_int32_t)(src)\
65985 #define TPC_6_B1__PD_DAC_SETTING_2_1__READ(src) \
65986 (((u_int32_t)(src)\
65988 #define TPC_6_B1__PD_DAC_SETTING_2_1__WRITE(src) \
65989 (((u_int32_t)(src)\
65991 #define TPC_6_B1__PD_DAC_SETTING_2_1__MODIFY(dst, src) \
65993 ~0x00000fc0U) | (((u_int32_t)(src) <<\
65995 #define TPC_6_B1__PD_DAC_SETTING_2_1__VERIFY(src) \
65996 (!((((u_int32_t)(src)\
66003 #define TPC_6_B1__PD_DAC_SETTING_3_1__READ(src) \
66004 (((u_int32_t)(src)\
66006 #define TPC_6_B1__PD_DAC_SETTING_3_1__WRITE(src) \
66007 (((u_int32_t)(src)\
66009 #define TPC_6_B1__PD_DAC_SETTING_3_1__MODIFY(dst, src) \
66011 ~0x0003f000U) | (((u_int32_t)(src) <<\
66013 #define TPC_6_B1__PD_DAC_SETTING_3_1__VERIFY(src) \
66014 (!((((u_int32_t)(src)\
66021 #define TPC_6_B1__PD_DAC_SETTING_4_1__READ(src) \
66022 (((u_int32_t)(src)\
66024 #define TPC_6_B1__PD_DAC_SETTING_4_1__WRITE(src) \
66025 (((u_int32_t)(src)\
66027 #define TPC_6_B1__PD_DAC_SETTING_4_1__MODIFY(dst, src) \
66029 ~0x00fc0000U) | (((u_int32_t)(src) <<\
66031 #define TPC_6_B1__PD_DAC_SETTING_4_1__VERIFY(src) \
66032 (!((((u_int32_t)(src)\
66039 #define TPC_6_B1__ERROR_EST_MODE__READ(src) \
66040 (((u_int32_t)(src)\
66042 #define TPC_6_B1__ERROR_EST_MODE__WRITE(src) \
66043 (((u_int32_t)(src)\
66045 #define TPC_6_B1__ERROR_EST_MODE__MODIFY(dst, src) \
66047 ~0x03000000U) | (((u_int32_t)(src) <<\
66049 #define TPC_6_B1__ERROR_EST_MODE__VERIFY(src) \
66050 (!((((u_int32_t)(src)\
66057 #define TPC_6_B1__ERROR_EST_FILTER_COEFF__READ(src) \
66058 (((u_int32_t)(src)\
66060 #define TPC_6_B1__ERROR_EST_FILTER_COEFF__WRITE(src) \
66061 (((u_int32_t)(src)\
66063 #define TPC_6_B1__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
66065 ~0x1c000000U) | (((u_int32_t)(src) <<\
66067 #define TPC_6_B1__ERROR_EST_FILTER_COEFF__VERIFY(src) \
66068 (!((((u_int32_t)(src)\
66088 #define TPC_11_B1__OLPC_GAIN_DELTA_1__READ(src) \
66089 (((u_int32_t)(src)\
66091 #define TPC_11_B1__OLPC_GAIN_DELTA_1__WRITE(src) \
66092 (((u_int32_t)(src)\
66094 #define TPC_11_B1__OLPC_GAIN_DELTA_1__MODIFY(dst, src) \
66096 ~0x00ff0000U) | (((u_int32_t)(src) <<\
66098 #define TPC_11_B1__OLPC_GAIN_DELTA_1__VERIFY(src) \
66099 (!((((u_int32_t)(src)\
66106 #define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__READ(src) \
66107 (((u_int32_t)(src)\
66109 #define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__WRITE(src) \
66110 (((u_int32_t)(src)\
66112 #define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__MODIFY(dst, src) \
66114 ~0xff000000U) | (((u_int32_t)(src) <<\
66116 #define TPC_11_B1__OLPC_GAIN_DELTA_1_PAL_ON__VERIFY(src) \
66117 (!((((u_int32_t)(src)\
66137 #define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
66138 #define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
66140 ~0xffffffffU) | ((u_int32_t)(src) &\
66142 #define PDADC_TAB__TAB_ENTRY__VERIFY(src) \
66143 (!(((u_int32_t)(src)\
66162 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__READ(src) \
66163 (u_int32_t)(src)\
66165 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__WRITE(src) \
66166 ((u_int32_t)(src)\
66168 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__MODIFY(dst, src) \
66170 ~0x00003fffU) | ((u_int32_t)(src) &\
66172 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_0_1__VERIFY(src) \
66173 (!(((u_int32_t)(src)\
66180 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__READ(src) \
66181 (((u_int32_t)(src)\
66183 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__WRITE(src) \
66184 (((u_int32_t)(src)\
66186 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__MODIFY(dst, src) \
66188 ~0x0fffc000U) | (((u_int32_t)(src) <<\
66190 #define TXIQ_CORR_COEFF_01_B1__IQC_COEFF_TABLE_1_1__VERIFY(src) \
66191 (!((((u_int32_t)(src)\
66211 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__READ(src) \
66212 (u_int32_t)(src)\
66214 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__WRITE(src) \
66215 ((u_int32_t)(src)\
66217 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__MODIFY(dst, src) \
66219 ~0x00003fffU) | ((u_int32_t)(src) &\
66221 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_2_1__VERIFY(src) \
66222 (!(((u_int32_t)(src)\
66229 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__READ(src) \
66230 (((u_int32_t)(src)\
66232 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__WRITE(src) \
66233 (((u_int32_t)(src)\
66235 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__MODIFY(dst, src) \
66237 ~0x0fffc000U) | (((u_int32_t)(src) <<\
66239 #define TXIQ_CORR_COEFF_23_B1__IQC_COEFF_TABLE_3_1__VERIFY(src) \
66240 (!((((u_int32_t)(src)\
66260 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__READ(src) \
66261 (u_int32_t)(src)\
66263 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__WRITE(src) \
66264 ((u_int32_t)(src)\
66266 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__MODIFY(dst, src) \
66268 ~0x00003fffU) | ((u_int32_t)(src) &\
66270 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_4_1__VERIFY(src) \
66271 (!(((u_int32_t)(src)\
66278 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__READ(src) \
66279 (((u_int32_t)(src)\
66281 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__WRITE(src) \
66282 (((u_int32_t)(src)\
66284 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__MODIFY(dst, src) \
66286 ~0x0fffc000U) | (((u_int32_t)(src) <<\
66288 #define TXIQ_CORR_COEFF_45_B1__IQC_COEFF_TABLE_5_1__VERIFY(src) \
66289 (!((((u_int32_t)(src)\
66309 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__READ(src) \
66310 (u_int32_t)(src)\
66312 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__WRITE(src) \
66313 ((u_int32_t)(src)\
66315 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__MODIFY(dst, src) \
66317 ~0x00003fffU) | ((u_int32_t)(src) &\
66319 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_6_1__VERIFY(src) \
66320 (!(((u_int32_t)(src)\
66327 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__READ(src) \
66328 (((u_int32_t)(src)\
66330 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__WRITE(src) \
66331 (((u_int32_t)(src)\
66333 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__MODIFY(dst, src) \
66335 ~0x0fffc000U) | (((u_int32_t)(src) <<\
66337 #define TXIQ_CORR_COEFF_67_B1__IQC_COEFF_TABLE_7_1__VERIFY(src) \
66338 (!((((u_int32_t)(src)\
66358 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__READ(src) \
66359 (u_int32_t)(src)\
66361 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__WRITE(src) \
66362 ((u_int32_t)(src)\
66364 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__MODIFY(dst, src) \
66366 ~0x00003fffU) | ((u_int32_t)(src) &\
66368 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_8_1__VERIFY(src) \
66369 (!(((u_int32_t)(src)\
66376 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__READ(src) \
66377 (((u_int32_t)(src)\
66379 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__WRITE(src) \
66380 (((u_int32_t)(src)\
66382 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__MODIFY(dst, src) \
66384 ~0x0fffc000U) | (((u_int32_t)(src) <<\
66386 #define TXIQ_CORR_COEFF_89_B1__IQC_COEFF_TABLE_9_1__VERIFY(src) \
66387 (!((((u_int32_t)(src)\
66407 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__READ(src) \
66408 (u_int32_t)(src)\
66410 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__WRITE(src) \
66411 ((u_int32_t)(src)\
66413 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__MODIFY(dst, src) \
66415 ~0x00003fffU) | ((u_int32_t)(src) &\
66417 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_A_1__VERIFY(src) \
66418 (!(((u_int32_t)(src)\
66425 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__READ(src) \
66426 (((u_int32_t)(src)\
66428 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__WRITE(src) \
66429 (((u_int32_t)(src)\
66431 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__MODIFY(dst, src) \
66433 ~0x0fffc000U) | (((u_int32_t)(src) <<\
66435 #define TXIQ_CORR_COEFF_AB_B1__IQC_COEFF_TABLE_B_1__VERIFY(src) \
66436 (!((((u_int32_t)(src)\
66456 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__READ(src) \
66457 (u_int32_t)(src)\
66459 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__WRITE(src) \
66460 ((u_int32_t)(src)\
66462 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__MODIFY(dst, src) \
66464 ~0x00003fffU) | ((u_int32_t)(src) &\
66466 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_C_1__VERIFY(src) \
66467 (!(((u_int32_t)(src)\
66474 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__READ(src) \
66475 (((u_int32_t)(src)\
66477 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__WRITE(src) \
66478 (((u_int32_t)(src)\
66480 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__MODIFY(dst, src) \
66482 ~0x0fffc000U) | (((u_int32_t)(src) <<\
66484 #define TXIQ_CORR_COEFF_CD_B1__IQC_COEFF_TABLE_D_1__VERIFY(src) \
66485 (!((((u_int32_t)(src)\
66505 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__READ(src) \
66506 (u_int32_t)(src)\
66508 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__WRITE(src) \
66509 ((u_int32_t)(src)\
66511 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__MODIFY(dst, src) \
66513 ~0x00003fffU) | ((u_int32_t)(src) &\
66515 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_E_1__VERIFY(src) \
66516 (!(((u_int32_t)(src)\
66523 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__READ(src) \
66524 (((u_int32_t)(src)\
66526 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__WRITE(src) \
66527 (((u_int32_t)(src)\
66529 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__MODIFY(dst, src) \
66531 ~0x0fffc000U) | (((u_int32_t)(src) <<\
66533 #define TXIQ_CORR_COEFF_EF_B1__IQC_COEFF_TABLE_F_1__VERIFY(src) \
66534 (!((((u_int32_t)(src)\
66554 #define TXIQCAL_STATUS_B1__TXIQCAL_FAILED_1__READ(src) \
66555 (u_int32_t)(src)\
66568 #define TXIQCAL_STATUS_B1__CALIBRATED_GAINS_1__READ(src) \
66569 (((u_int32_t)(src)\
66576 #define TXIQCAL_STATUS_B1__TONE_GAIN_USED_1__READ(src) \
66577 (((u_int32_t)(src)\
66584 #define TXIQCAL_STATUS_B1__RX_GAIN_USED_1__READ(src) \
66585 (((u_int32_t)(src)\
66592 #define TXIQCAL_STATUS_B1__LAST_MEAS_ADDR_1__READ(src) \
66593 (((u_int32_t)(src)\
66615 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U
66635 #define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__READ(src) \
66636 (u_int32_t)(src)\
66638 #define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__WRITE(src) \
66639 ((u_int32_t)(src)\
66641 #define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__MODIFY(dst, src) \
66643 ~0x000001ffU) | ((u_int32_t)(src) &\
66645 #define EXT_CHAN_PWR_THR_2_B2__CF_MAXCCAPWR_EXT_2__VERIFY(src) \
66646 (!(((u_int32_t)(src)\
66653 #define EXT_CHAN_PWR_THR_2_B2__MINCCAPWR_EXT_2__READ(src) \
66654 (((u_int32_t)(src)\
66674 #define SPUR_REPORT_B2__SPUR_EST_I_2__READ(src) (u_int32_t)(src) & 0x000000ffU
66680 #define SPUR_REPORT_B2__SPUR_EST_Q_2__READ(src) \
66681 (((u_int32_t)(src)\
66688 #define SPUR_REPORT_B2__POWER_WITH_SPUR_REMOVED_2__READ(src) \
66689 (((u_int32_t)(src)\
66708 #define IQ_ADC_MEAS_0_B2__GAIN_DC_IQ_CAL_MEAS_0_2__READ(src) \
66709 (u_int32_t)(src)\
66728 #define IQ_ADC_MEAS_1_B2__GAIN_DC_IQ_CAL_MEAS_1_2__READ(src) \
66729 (u_int32_t)(src)\
66748 #define IQ_ADC_MEAS_2_B2__GAIN_DC_IQ_CAL_MEAS_2_2__READ(src) \
66749 (u_int32_t)(src)\
66768 #define IQ_ADC_MEAS_3_B2__GAIN_DC_IQ_CAL_MEAS_3_2__READ(src) \
66769 (u_int32_t)(src)\
66788 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__READ(src) \
66789 (u_int32_t)(src)\
66791 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__WRITE(src) \
66792 ((u_int32_t)(src)\
66794 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__MODIFY(dst, src) \
66796 ~0x00000001U) | ((u_int32_t)(src) &\
66798 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ENABLE_2__VERIFY(src) \
66799 (!(((u_int32_t)(src)\
66812 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__READ(src) \
66813 (((u_int32_t)(src)\
66815 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__WRITE(src) \
66816 (((u_int32_t)(src)\
66818 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__MODIFY(dst, src) \
66820 ~0x0000007eU) | (((u_int32_t)(src) <<\
66822 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_BIAS_2__VERIFY(src) \
66823 (!((((u_int32_t)(src)\
66830 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__READ(src) \
66831 (((u_int32_t)(src)\
66833 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__WRITE(src) \
66834 (((u_int32_t)(src)\
66836 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__MODIFY(dst, src) \
66838 ~0x0001ff80U) | (((u_int32_t)(src) <<\
66840 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_INIT_2__VERIFY(src) \
66841 (!((((u_int32_t)(src)\
66848 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__READ(src) \
66849 (((u_int32_t)(src)\
66851 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__WRITE(src) \
66852 (((u_int32_t)(src)\
66854 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__MODIFY(dst, src) \
66856 ~0x01fe0000U) | (((u_int32_t)(src) <<\
66858 #define TX_PHASE_RAMP_B2__CF_PHASE_RAMP_ALPHA_2__VERIFY(src) \
66859 (!((((u_int32_t)(src)\
66879 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__READ(src) \
66880 (u_int32_t)(src)\
66882 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__WRITE(src) \
66883 ((u_int32_t)(src)\
66885 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__MODIFY(dst, src) \
66887 ~0x0000003fU) | ((u_int32_t)(src) &\
66889 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_Q_COEFF_2__VERIFY(src) \
66890 (!(((u_int32_t)(src)\
66897 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__READ(src) \
66898 (((u_int32_t)(src)\
66900 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__WRITE(src) \
66901 (((u_int32_t)(src)\
66903 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__MODIFY(dst, src) \
66905 ~0x00000fc0U) | (((u_int32_t)(src) <<\
66907 #define ADC_GAIN_DC_CORR_B2__ADC_GAIN_CORR_I_COEFF_2__VERIFY(src) \
66908 (!((((u_int32_t)(src)\
66915 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__READ(src) \
66916 (((u_int32_t)(src)\
66918 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__WRITE(src) \
66919 (((u_int32_t)(src)\
66921 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__MODIFY(dst, src) \
66923 ~0x001ff000U) | (((u_int32_t)(src) <<\
66925 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_Q_COEFF_2__VERIFY(src) \
66926 (!((((u_int32_t)(src)\
66933 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__READ(src) \
66934 (((u_int32_t)(src)\
66936 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__WRITE(src) \
66937 (((u_int32_t)(src)\
66939 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__MODIFY(dst, src) \
66941 ~0x3fe00000U) | (((u_int32_t)(src) <<\
66943 #define ADC_GAIN_DC_CORR_B2__ADC_DC_CORR_I_COEFF_2__VERIFY(src) \
66944 (!((((u_int32_t)(src)\
66964 #define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__READ(src) \
66965 (u_int32_t)(src)\
66967 #define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__WRITE(src) \
66968 ((u_int32_t)(src)\
66970 #define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \
66972 ~0x0000007fU) | ((u_int32_t)(src) &\
66974 #define RX_IQ_CORR_B2__RX_IQCORR_Q_Q_COFF_2__VERIFY(src) \
66975 (!(((u_int32_t)(src)\
66982 #define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__READ(src) \
66983 (((u_int32_t)(src)\
66985 #define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__WRITE(src) \
66986 (((u_int32_t)(src)\
66988 #define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \
66990 ~0x00003f80U) | (((u_int32_t)(src) <<\
66992 #define RX_IQ_CORR_B2__RX_IQCORR_Q_I_COFF_2__VERIFY(src) \
66993 (!((((u_int32_t)(src)\
67000 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__READ(src) \
67001 (((u_int32_t)(src)\
67003 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__WRITE(src) \
67004 (((u_int32_t)(src)\
67006 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__MODIFY(dst, src) \
67008 ~0x003f8000U) | (((u_int32_t)(src) <<\
67010 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_Q_COFF_2__VERIFY(src) \
67011 (!((((u_int32_t)(src)\
67018 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__READ(src) \
67019 (((u_int32_t)(src)\
67021 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__WRITE(src) \
67022 (((u_int32_t)(src)\
67024 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__MODIFY(dst, src) \
67026 ~0x1fc00000U) | (((u_int32_t)(src) <<\
67028 #define RX_IQ_CORR_B2__LOOPBACK_IQCORR_Q_I_COFF_2__VERIFY(src) \
67029 (!((((u_int32_t)(src)\
67049 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__READ(src) \
67050 (u_int32_t)(src)\
67052 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__WRITE(src) \
67053 ((u_int32_t)(src)\
67055 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__MODIFY(dst, src) \
67057 ~0x00000001U) | ((u_int32_t)(src) &\
67059 #define PAPRD_CTRL0_B2__PAPRD_ENABLE_2__VERIFY(src) \
67060 (!(((u_int32_t)(src)\
67073 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__READ(src) \
67074 (((u_int32_t)(src)\
67076 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__WRITE(src) \
67077 (((u_int32_t)(src)\
67079 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__MODIFY(dst, src) \
67081 ~0x00000002U) | (((u_int32_t)(src) <<\
67083 #define PAPRD_CTRL0_B2__PAPRD_ADAPTIVE_USE_SINGLE_TABLE_2__VERIFY(src) \
67084 (!((((u_int32_t)(src)\
67097 #define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__READ(src) \
67098 (((u_int32_t)(src)\
67100 #define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__WRITE(src) \
67101 (((u_int32_t)(src)\
67103 #define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__MODIFY(dst, src) \
67105 ~0x07fffffcU) | (((u_int32_t)(src) <<\
67107 #define PAPRD_CTRL0_B2__PAPRD_VALID_GAIN_2__VERIFY(src) \
67108 (!((((u_int32_t)(src)\
67115 #define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__READ(src) \
67116 (((u_int32_t)(src)\
67118 #define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__WRITE(src) \
67119 (((u_int32_t)(src)\
67121 #define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__MODIFY(dst, src) \
67123 ~0xf8000000U) | (((u_int32_t)(src) <<\
67125 #define PAPRD_CTRL0_B2__PAPRD_MAG_THRSH_2__VERIFY(src) \
67126 (!((((u_int32_t)(src)\
67146 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__READ(src) \
67147 (u_int32_t)(src)\
67149 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__WRITE(src) \
67150 ((u_int32_t)(src)\
67152 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__MODIFY(dst, src) \
67154 ~0x00000001U) | ((u_int32_t)(src) &\
67156 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_SCALING_ENABLE_2__VERIFY(src) \
67157 (!(((u_int32_t)(src)\
67170 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__READ(src) \
67171 (((u_int32_t)(src)\
67173 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__WRITE(src) \
67174 (((u_int32_t)(src)\
67176 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__MODIFY(dst, src) \
67178 ~0x00000002U) | (((u_int32_t)(src) <<\
67180 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2AM_ENABLE_2__VERIFY(src) \
67181 (!((((u_int32_t)(src)\
67194 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__READ(src) \
67195 (((u_int32_t)(src)\
67197 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__WRITE(src) \
67198 (((u_int32_t)(src)\
67200 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__MODIFY(dst, src) \
67202 ~0x00000004U) | (((u_int32_t)(src) <<\
67204 #define PAPRD_CTRL1_B2__PAPRD_ADAPTIVE_AM2PM_ENABLE_2__VERIFY(src) \
67205 (!((((u_int32_t)(src)\
67218 #define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__READ(src) \
67219 (((u_int32_t)(src)\
67221 #define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__WRITE(src) \
67222 (((u_int32_t)(src)\
67224 #define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__MODIFY(dst, src) \
67226 ~0x000001f8U) | (((u_int32_t)(src) <<\
67228 #define PAPRD_CTRL1_B2__PAPRD_POWER_AT_AM2AM_CAL_2__VERIFY(src) \
67229 (!((((u_int32_t)(src)\
67236 #define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__READ(src) \
67237 (((u_int32_t)(src)\
67239 #define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__WRITE(src) \
67240 (((u_int32_t)(src)\
67242 #define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__MODIFY(dst, src) \
67244 ~0x0001fe00U) | (((u_int32_t)(src) <<\
67246 #define PAPRD_CTRL1_B2__PA_GAIN_SCALE_FACTOR_2__VERIFY(src) \
67247 (!((((u_int32_t)(src)\
67254 #define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__READ(src) \
67255 (((u_int32_t)(src)\
67257 #define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__WRITE(src) \
67258 (((u_int32_t)(src)\
67260 #define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__MODIFY(dst, src) \
67262 ~0x07fe0000U) | (((u_int32_t)(src) <<\
67264 #define PAPRD_CTRL1_B2__PAPRD_MAG_SCALE_FACTOR_2__VERIFY(src) \
67265 (!((((u_int32_t)(src)\
67272 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__READ(src) \
67273 (((u_int32_t)(src)\
67275 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__WRITE(src) \
67276 (((u_int32_t)(src)\
67278 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__MODIFY(dst, src) \
67280 ~0x08000000U) | (((u_int32_t)(src) <<\
67282 #define PAPRD_CTRL1_B2__PAPRD_TRAINER_IANDQ_SEL_2__VERIFY(src) \
67283 (!((((u_int32_t)(src)\
67309 #define PA_GAIN123_B2__PA_GAIN1_2__READ(src) (u_int32_t)(src) & 0x000003ffU
67310 #define PA_GAIN123_B2__PA_GAIN1_2__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
67311 #define PA_GAIN123_B2__PA_GAIN1_2__MODIFY(dst, src) \
67313 ~0x000003ffU) | ((u_int32_t)(src) &\
67315 #define PA_GAIN123_B2__PA_GAIN1_2__VERIFY(src) \
67316 (!(((u_int32_t)(src)\
67323 #define PA_GAIN123_B2__PA_GAIN2_2__READ(src) \
67324 (((u_int32_t)(src)\
67326 #define PA_GAIN123_B2__PA_GAIN2_2__WRITE(src) \
67327 (((u_int32_t)(src)\
67329 #define PA_GAIN123_B2__PA_GAIN2_2__MODIFY(dst, src) \
67331 ~0x000ffc00U) | (((u_int32_t)(src) <<\
67333 #define PA_GAIN123_B2__PA_GAIN2_2__VERIFY(src) \
67334 (!((((u_int32_t)(src)\
67341 #define PA_GAIN123_B2__PA_GAIN3_2__READ(src) \
67342 (((u_int32_t)(src)\
67344 #define PA_GAIN123_B2__PA_GAIN3_2__WRITE(src) \
67345 (((u_int32_t)(src)\
67347 #define PA_GAIN123_B2__PA_GAIN3_2__MODIFY(dst, src) \
67349 ~0x3ff00000U) | (((u_int32_t)(src) <<\
67351 #define PA_GAIN123_B2__PA_GAIN3_2__VERIFY(src) \
67352 (!((((u_int32_t)(src)\
67372 #define PA_GAIN45_B2__PA_GAIN4_2__READ(src) (u_int32_t)(src) & 0x000003ffU
67373 #define PA_GAIN45_B2__PA_GAIN4_2__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
67374 #define PA_GAIN45_B2__PA_GAIN4_2__MODIFY(dst, src) \
67376 ~0x000003ffU) | ((u_int32_t)(src) &\
67378 #define PA_GAIN45_B2__PA_GAIN4_2__VERIFY(src) \
67379 (!(((u_int32_t)(src)\
67386 #define PA_GAIN45_B2__PA_GAIN5_2__READ(src) \
67387 (((u_int32_t)(src)\
67389 #define PA_GAIN45_B2__PA_GAIN5_2__WRITE(src) \
67390 (((u_int32_t)(src)\
67392 #define PA_GAIN45_B2__PA_GAIN5_2__MODIFY(dst, src) \
67394 ~0x000ffc00U) | (((u_int32_t)(src) <<\
67396 #define PA_GAIN45_B2__PA_GAIN5_2__VERIFY(src) \
67397 (!((((u_int32_t)(src)\
67404 #define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__READ(src) \
67405 (((u_int32_t)(src)\
67407 #define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__WRITE(src) \
67408 (((u_int32_t)(src)\
67410 #define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__MODIFY(dst, src) \
67412 ~0x01f00000U) | (((u_int32_t)(src) <<\
67414 #define PA_GAIN45_B2__PAPRD_ADAPTIVE_TABLE_VALID_2__VERIFY(src) \
67415 (!((((u_int32_t)(src)\
67435 #define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__READ(src) \
67436 (u_int32_t)(src)\
67438 #define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__WRITE(src) \
67439 ((u_int32_t)(src)\
67441 #define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__MODIFY(dst, src) \
67443 ~0x0003ffffU) | ((u_int32_t)(src) &\
67445 #define PAPRD_PRE_POST_SCALE_0_B2__PAPRD_PRE_POST_SCALING_0_2__VERIFY(src) \
67446 (!(((u_int32_t)(src)\
67466 #define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__READ(src) \
67467 (u_int32_t)(src)\
67469 #define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__WRITE(src) \
67470 ((u_int32_t)(src)\
67472 #define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__MODIFY(dst, src) \
67474 ~0x0003ffffU) | ((u_int32_t)(src) &\
67476 #define PAPRD_PRE_POST_SCALE_1_B2__PAPRD_PRE_POST_SCALING_1_2__VERIFY(src) \
67477 (!(((u_int32_t)(src)\
67497 #define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__READ(src) \
67498 (u_int32_t)(src)\
67500 #define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__WRITE(src) \
67501 ((u_int32_t)(src)\
67503 #define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__MODIFY(dst, src) \
67505 ~0x0003ffffU) | ((u_int32_t)(src) &\
67507 #define PAPRD_PRE_POST_SCALE_2_B2__PAPRD_PRE_POST_SCALING_2_2__VERIFY(src) \
67508 (!(((u_int32_t)(src)\
67528 #define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__READ(src) \
67529 (u_int32_t)(src)\
67531 #define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__WRITE(src) \
67532 ((u_int32_t)(src)\
67534 #define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__MODIFY(dst, src) \
67536 ~0x0003ffffU) | ((u_int32_t)(src) &\
67538 #define PAPRD_PRE_POST_SCALE_3_B2__PAPRD_PRE_POST_SCALING_3_2__VERIFY(src) \
67539 (!(((u_int32_t)(src)\
67559 #define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__READ(src) \
67560 (u_int32_t)(src)\
67562 #define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__WRITE(src) \
67563 ((u_int32_t)(src)\
67565 #define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__MODIFY(dst, src) \
67567 ~0x0003ffffU) | ((u_int32_t)(src) &\
67569 #define PAPRD_PRE_POST_SCALE_4_B2__PAPRD_PRE_POST_SCALING_4_2__VERIFY(src) \
67570 (!(((u_int32_t)(src)\
67590 #define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__READ(src) \
67591 (u_int32_t)(src)\
67593 #define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__WRITE(src) \
67594 ((u_int32_t)(src)\
67596 #define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__MODIFY(dst, src) \
67598 ~0x0003ffffU) | ((u_int32_t)(src) &\
67600 #define PAPRD_PRE_POST_SCALE_5_B2__PAPRD_PRE_POST_SCALING_5_2__VERIFY(src) \
67601 (!(((u_int32_t)(src)\
67621 #define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__READ(src) \
67622 (u_int32_t)(src)\
67624 #define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__WRITE(src) \
67625 ((u_int32_t)(src)\
67627 #define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__MODIFY(dst, src) \
67629 ~0x0003ffffU) | ((u_int32_t)(src) &\
67631 #define PAPRD_PRE_POST_SCALE_6_B2__PAPRD_PRE_POST_SCALING_6_2__VERIFY(src) \
67632 (!(((u_int32_t)(src)\
67652 #define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__READ(src) \
67653 (u_int32_t)(src)\
67655 #define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__WRITE(src) \
67656 ((u_int32_t)(src)\
67658 #define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__MODIFY(dst, src) \
67660 ~0x0003ffffU) | ((u_int32_t)(src) &\
67662 #define PAPRD_PRE_POST_SCALE_7_B2__PAPRD_PRE_POST_SCALING_7_2__VERIFY(src) \
67663 (!(((u_int32_t)(src)\
67683 #define PAPRD_MEM_TAB__PAPRD_MEM__READ(src) (u_int32_t)(src) & 0x003fffffU
67684 #define PAPRD_MEM_TAB__PAPRD_MEM__WRITE(src) ((u_int32_t)(src) & 0x003fffffU)
67685 #define PAPRD_MEM_TAB__PAPRD_MEM__MODIFY(dst, src) \
67687 ~0x003fffffU) | ((u_int32_t)(src) &\
67689 #define PAPRD_MEM_TAB__PAPRD_MEM__VERIFY(src) \
67690 (!(((u_int32_t)(src)\
67710 #define CHAN_INFO_CHAN_TAB__CHANINFO_WORD__READ(src) \
67711 (u_int32_t)(src)\
67730 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U
67750 #define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__READ(src) \
67751 (u_int32_t)(src)\
67753 #define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__WRITE(src) \
67754 ((u_int32_t)(src)\
67756 #define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__MODIFY(dst, src) \
67758 ~0x000000ffU) | ((u_int32_t)(src) &\
67760 #define GAIN_FORCE_MAX_GAINS_B2__RF_GAIN_F_2__VERIFY(src) \
67761 (!(((u_int32_t)(src)\
67768 #define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__READ(src) \
67769 (((u_int32_t)(src)\
67771 #define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__WRITE(src) \
67772 (((u_int32_t)(src)\
67774 #define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__MODIFY(dst, src) \
67776 ~0x0000ff00U) | (((u_int32_t)(src) <<\
67778 #define GAIN_FORCE_MAX_GAINS_B2__MB_GAIN_F_2__VERIFY(src) \
67779 (!((((u_int32_t)(src)\
67786 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__READ(src) \
67787 (((u_int32_t)(src)\
67789 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__WRITE(src) \
67790 (((u_int32_t)(src)\
67792 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__MODIFY(dst, src) \
67794 ~0x00010000U) | (((u_int32_t)(src) <<\
67796 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_SW_F_2__VERIFY(src) \
67797 (!((((u_int32_t)(src)\
67810 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__READ(src) \
67811 (((u_int32_t)(src)\
67813 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__WRITE(src) \
67814 (((u_int32_t)(src)\
67816 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__MODIFY(dst, src) \
67818 ~0x00020000U) | (((u_int32_t)(src) <<\
67820 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_SW_F_2__VERIFY(src) \
67821 (!((((u_int32_t)(src)\
67834 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__READ(src) \
67835 (((u_int32_t)(src)\
67837 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__WRITE(src) \
67838 (((u_int32_t)(src)\
67840 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__MODIFY(dst, src) \
67842 ~0x01fc0000U) | (((u_int32_t)(src) <<\
67844 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN1_HYST_MARGIN_2__VERIFY(src) \
67845 (!((((u_int32_t)(src)\
67852 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__READ(src) \
67853 (((u_int32_t)(src)\
67855 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__WRITE(src) \
67856 (((u_int32_t)(src)\
67858 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__MODIFY(dst, src) \
67860 ~0xfe000000U) | (((u_int32_t)(src) <<\
67862 #define GAIN_FORCE_MAX_GAINS_B2__XATTEN2_HYST_MARGIN_2__VERIFY(src) \
67863 (!((((u_int32_t)(src)\
67883 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__READ(src) \
67884 (u_int32_t)(src)\
67886 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__WRITE(src) \
67887 ((u_int32_t)(src)\
67889 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__MODIFY(dst, src) \
67891 ~0x0000003fU) | ((u_int32_t)(src) &\
67893 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_DB_2__VERIFY(src) \
67894 (!(((u_int32_t)(src)\
67901 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__READ(src) \
67902 (((u_int32_t)(src)\
67904 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__WRITE(src) \
67905 (((u_int32_t)(src)\
67907 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__MODIFY(dst, src) \
67909 ~0x00000fc0U) | (((u_int32_t)(src) <<\
67911 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_DB_2__VERIFY(src) \
67912 (!((((u_int32_t)(src)\
67919 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__READ(src) \
67920 (((u_int32_t)(src)\
67922 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__WRITE(src) \
67923 (((u_int32_t)(src)\
67925 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__MODIFY(dst, src) \
67927 ~0x0001f000U) | (((u_int32_t)(src) <<\
67929 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN1_MARGIN_2__VERIFY(src) \
67930 (!((((u_int32_t)(src)\
67937 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__READ(src) \
67938 (((u_int32_t)(src)\
67940 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__WRITE(src) \
67941 (((u_int32_t)(src)\
67943 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__MODIFY(dst, src) \
67945 ~0x003e0000U) | (((u_int32_t)(src) <<\
67947 #define EXT_ATTEN_SWITCH_CTL_B2__XATTEN2_MARGIN_2__VERIFY(src) \
67948 (!((((u_int32_t)(src)\
67955 #define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__READ(src) \
67956 (((u_int32_t)(src)\
67958 #define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__WRITE(src) \
67959 (((u_int32_t)(src)\
67961 #define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__MODIFY(dst, src) \
67963 ~0x07c00000U) | (((u_int32_t)(src) <<\
67965 #define EXT_ATTEN_SWITCH_CTL_B2__XLNA_GAIN_DB_2__VERIFY(src) \
67966 (!((((u_int32_t)(src)\
67986 #define CCA_B2__CF_MAXCCAPWR_2__READ(src) (u_int32_t)(src) & 0x000001ffU
67987 #define CCA_B2__CF_MAXCCAPWR_2__WRITE(src) ((u_int32_t)(src) & 0x000001ffU)
67988 #define CCA_B2__CF_MAXCCAPWR_2__MODIFY(dst, src) \
67990 ~0x000001ffU) | ((u_int32_t)(src) &\
67992 #define CCA_B2__CF_MAXCCAPWR_2__VERIFY(src) \
67993 (!(((u_int32_t)(src)\
68000 #define CCA_B2__MINCCAPWR_2__READ(src) (((u_int32_t)(src) & 0x1ff00000U) >> 20)
68019 #define CCA_CTRL_2_B2__MINCCAPWR_THR_2__READ(src) \
68020 (u_int32_t)(src)\
68022 #define CCA_CTRL_2_B2__MINCCAPWR_THR_2__WRITE(src) \
68023 ((u_int32_t)(src)\
68025 #define CCA_CTRL_2_B2__MINCCAPWR_THR_2__MODIFY(dst, src) \
68027 ~0x000001ffU) | ((u_int32_t)(src) &\
68029 #define CCA_CTRL_2_B2__MINCCAPWR_THR_2__VERIFY(src) \
68030 (!(((u_int32_t)(src)\
68037 #define CCA_CTRL_2_B2__NF_GAIN_COMP_2__READ(src) \
68038 (((u_int32_t)(src)\
68040 #define CCA_CTRL_2_B2__NF_GAIN_COMP_2__WRITE(src) \
68041 (((u_int32_t)(src)\
68043 #define CCA_CTRL_2_B2__NF_GAIN_COMP_2__MODIFY(dst, src) \
68045 ~0x0003fc00U) | (((u_int32_t)(src) <<\
68047 #define CCA_CTRL_2_B2__NF_GAIN_COMP_2__VERIFY(src) \
68048 (!((((u_int32_t)(src)\
68068 #define RSSI_B2__RSSI_2__READ(src) (u_int32_t)(src) & 0x000000ffU
68074 #define RSSI_B2__RSSI_EXT_2__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
68092 #define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C1_RES_I_2__READ(src) \
68093 (u_int32_t)(src)\
68100 #define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C2_RES_I_2__READ(src) \
68101 (((u_int32_t)(src)\
68108 #define AGC_DIG_DC_STATUS_I_B2__DIG_DC_C3_RES_I_2__READ(src) \
68109 (((u_int32_t)(src)\
68128 #define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C1_RES_Q_2__READ(src) \
68129 (u_int32_t)(src)\
68136 #define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C2_RES_Q_2__READ(src) \
68137 (((u_int32_t)(src)\
68144 #define AGC_DIG_DC_STATUS_Q_B2__DIG_DC_C3_RES_Q_2__READ(src) \
68145 (((u_int32_t)(src)\
68164 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U
68184 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__READ(src) \
68185 (u_int32_t)(src)\
68187 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__WRITE(src) \
68188 ((u_int32_t)(src)\
68190 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__MODIFY(dst, src) \
68192 ~0x00000003U) | ((u_int32_t)(src) &\
68194 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_IDLE_2__VERIFY(src) \
68195 (!(((u_int32_t)(src)\
68202 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__READ(src) \
68203 (((u_int32_t)(src)\
68205 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__WRITE(src) \
68206 (((u_int32_t)(src)\
68208 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__MODIFY(dst, src) \
68210 ~0x0000000cU) | (((u_int32_t)(src) <<\
68212 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_T_2__VERIFY(src) \
68213 (!((((u_int32_t)(src)\
68220 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__READ(src) \
68221 (((u_int32_t)(src)\
68223 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__WRITE(src) \
68224 (((u_int32_t)(src)\
68226 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__MODIFY(dst, src) \
68228 ~0x00000030U) | (((u_int32_t)(src) <<\
68230 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_R_2__VERIFY(src) \
68231 (!((((u_int32_t)(src)\
68238 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__READ(src) \
68239 (((u_int32_t)(src)\
68241 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__WRITE(src) \
68242 (((u_int32_t)(src)\
68244 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__MODIFY(dst, src) \
68246 ~0x000000c0U) | (((u_int32_t)(src) <<\
68248 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX1_2__VERIFY(src) \
68249 (!((((u_int32_t)(src)\
68256 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__READ(src) \
68257 (((u_int32_t)(src)\
68259 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__WRITE(src) \
68260 (((u_int32_t)(src)\
68262 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__MODIFY(dst, src) \
68264 ~0x00000300U) | (((u_int32_t)(src) <<\
68266 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_RX12_2__VERIFY(src) \
68267 (!((((u_int32_t)(src)\
68274 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__READ(src) \
68275 (((u_int32_t)(src)\
68277 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__WRITE(src) \
68278 (((u_int32_t)(src)\
68280 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__MODIFY(dst, src) \
68282 ~0x00000c00U) | (((u_int32_t)(src) <<\
68284 #define SWITCH_TABLE_CHN_B2__SWITCH_TABLE_B_2__VERIFY(src) \
68285 (!((((u_int32_t)(src)\
68305 #define FCAL_2_B2__FLC_SW_CAP_VAL_2__READ(src) \
68306 (((u_int32_t)(src)\
68308 #define FCAL_2_B2__FLC_SW_CAP_VAL_2__WRITE(src) \
68309 (((u_int32_t)(src)\
68311 #define FCAL_2_B2__FLC_SW_CAP_VAL_2__MODIFY(dst, src) \
68313 ~0x000000f8U) | (((u_int32_t)(src) <<\
68315 #define FCAL_2_B2__FLC_SW_CAP_VAL_2__VERIFY(src) \
68316 (!((((u_int32_t)(src)\
68323 #define FCAL_2_B2__FLC_CAP_VAL_STATUS_2__READ(src) \
68324 (((u_int32_t)(src)\
68344 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__READ(src) \
68345 (u_int32_t)(src)\
68347 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__WRITE(src) \
68348 ((u_int32_t)(src)\
68350 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__MODIFY(dst, src) \
68352 ~0x00000001U) | ((u_int32_t)(src) &\
68354 #define DFT_TONE_CTRL_B2__DFT_TONE_EN_2__VERIFY(src) \
68355 (!(((u_int32_t)(src)\
68368 #define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__READ(src) \
68369 (((u_int32_t)(src)\
68371 #define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__WRITE(src) \
68372 (((u_int32_t)(src)\
68374 #define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__MODIFY(dst, src) \
68376 ~0x0000000cU) | (((u_int32_t)(src) <<\
68378 #define DFT_TONE_CTRL_B2__DFT_TONE_AMP_SEL_2__VERIFY(src) \
68379 (!((((u_int32_t)(src)\
68386 #define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__READ(src) \
68387 (((u_int32_t)(src)\
68389 #define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__WRITE(src) \
68390 (((u_int32_t)(src)\
68392 #define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__MODIFY(dst, src) \
68394 ~0x00001ff0U) | (((u_int32_t)(src) <<\
68396 #define DFT_TONE_CTRL_B2__DFT_TONE_FREQ_ANG_2__VERIFY(src) \
68397 (!((((u_int32_t)(src)\
68417 #define CL_MAP_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU
68418 #define CL_MAP_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
68419 #define CL_MAP_0__CL_MAP_0__MODIFY(dst, src) \
68421 ~0xffffffffU) | ((u_int32_t)(src) &\
68423 #define CL_MAP_0__CL_MAP_0__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
68442 #define CL_MAP_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU
68443 #define CL_MAP_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
68444 #define CL_MAP_1__CL_MAP_1__MODIFY(dst, src) \
68446 ~0xffffffffU) | ((u_int32_t)(src) &\
68448 #define CL_MAP_1__CL_MAP_1__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
68467 #define CL_MAP_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU
68468 #define CL_MAP_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
68469 #define CL_MAP_2__CL_MAP_2__MODIFY(dst, src) \
68471 ~0xffffffffU) | ((u_int32_t)(src) &\
68473 #define CL_MAP_2__CL_MAP_2__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
68492 #define CL_MAP_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU
68493 #define CL_MAP_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
68494 #define CL_MAP_3__CL_MAP_3__MODIFY(dst, src) \
68496 ~0xffffffffU) | ((u_int32_t)(src) &\
68498 #define CL_MAP_3__CL_MAP_3__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
68517 #define CL_MAP_PAL_0__CL_MAP_0__READ(src) (u_int32_t)(src) & 0xffffffffU
68518 #define CL_MAP_PAL_0__CL_MAP_0__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
68519 #define CL_MAP_PAL_0__CL_MAP_0__MODIFY(dst, src) \
68521 ~0xffffffffU) | ((u_int32_t)(src) &\
68523 #define CL_MAP_PAL_0__CL_MAP_0__VERIFY(src) \
68524 (!(((u_int32_t)(src)\
68544 #define CL_MAP_PAL_1__CL_MAP_1__READ(src) (u_int32_t)(src) & 0xffffffffU
68545 #define CL_MAP_PAL_1__CL_MAP_1__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
68546 #define CL_MAP_PAL_1__CL_MAP_1__MODIFY(dst, src) \
68548 ~0xffffffffU) | ((u_int32_t)(src) &\
68550 #define CL_MAP_PAL_1__CL_MAP_1__VERIFY(src) \
68551 (!(((u_int32_t)(src)\
68571 #define CL_MAP_PAL_2__CL_MAP_2__READ(src) (u_int32_t)(src) & 0xffffffffU
68572 #define CL_MAP_PAL_2__CL_MAP_2__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
68573 #define CL_MAP_PAL_2__CL_MAP_2__MODIFY(dst, src) \
68575 ~0xffffffffU) | ((u_int32_t)(src) &\
68577 #define CL_MAP_PAL_2__CL_MAP_2__VERIFY(src) \
68578 (!(((u_int32_t)(src)\
68598 #define CL_MAP_PAL_3__CL_MAP_3__READ(src) (u_int32_t)(src) & 0xffffffffU
68599 #define CL_MAP_PAL_3__CL_MAP_3__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
68600 #define CL_MAP_PAL_3__CL_MAP_3__MODIFY(dst, src) \
68602 ~0xffffffffU) | ((u_int32_t)(src) &\
68604 #define CL_MAP_PAL_3__CL_MAP_3__VERIFY(src) \
68605 (!(((u_int32_t)(src)\
68625 #define CL_TAB__CL_GAIN_MOD__READ(src) (u_int32_t)(src) & 0x0000001fU
68626 #define CL_TAB__CL_GAIN_MOD__WRITE(src) ((u_int32_t)(src) & 0x0000001fU)
68627 #define CL_TAB__CL_GAIN_MOD__MODIFY(dst, src) \
68629 ~0x0000001fU) | ((u_int32_t)(src) &\
68631 #define CL_TAB__CL_GAIN_MOD__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))
68637 #define CL_TAB__CARR_LK_DC_ADD_Q__READ(src) \
68638 (((u_int32_t)(src)\
68640 #define CL_TAB__CARR_LK_DC_ADD_Q__WRITE(src) \
68641 (((u_int32_t)(src)\
68643 #define CL_TAB__CARR_LK_DC_ADD_Q__MODIFY(dst, src) \
68645 ~0x0000ffe0U) | (((u_int32_t)(src) <<\
68647 #define CL_TAB__CARR_LK_DC_ADD_Q__VERIFY(src) \
68648 (!((((u_int32_t)(src)\
68655 #define CL_TAB__CARR_LK_DC_ADD_I__READ(src) \
68656 (((u_int32_t)(src)\
68658 #define CL_TAB__CARR_LK_DC_ADD_I__WRITE(src) \
68659 (((u_int32_t)(src)\
68661 #define CL_TAB__CARR_LK_DC_ADD_I__MODIFY(dst, src) \
68663 ~0x07ff0000U) | (((u_int32_t)(src) <<\
68665 #define CL_TAB__CARR_LK_DC_ADD_I__VERIFY(src) \
68666 (!((((u_int32_t)(src)\
68673 #define CL_TAB__BB_GAIN__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27)
68674 #define CL_TAB__BB_GAIN__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U)
68675 #define CL_TAB__BB_GAIN__MODIFY(dst, src) \
68677 ~0x78000000U) | (((u_int32_t)(src) <<\
68679 #define CL_TAB__BB_GAIN__VERIFY(src) \
68680 (!((((u_int32_t)(src)\
68700 #define CHAN_INFO_GAIN_B2__CHAN_INFO_RSSI_2__READ(src) \
68701 (u_int32_t)(src)\
68708 #define CHAN_INFO_GAIN_B2__CHAN_INFO_RF_GAIN_2__READ(src) \
68709 (((u_int32_t)(src)\
68716 #define CHAN_INFO_GAIN_B2__CHAN_INFO_MB_GAIN_2__READ(src) \
68717 (((u_int32_t)(src)\
68724 #define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN1_SW_2__READ(src) \
68725 (((u_int32_t)(src)\
68738 #define CHAN_INFO_GAIN_B2__CHAN_INFO_XATTEN2_SW_2__READ(src) \
68739 (((u_int32_t)(src)\
68764 #define TPC_4_B2__PD_AVG_VALID_2__READ(src) (u_int32_t)(src) & 0x00000001U
68776 #define TPC_4_B2__PD_AVG_OUT_2__READ(src) \
68777 (((u_int32_t)(src)\
68784 #define TPC_4_B2__DAC_GAIN_2__READ(src) (((u_int32_t)(src) & 0x00003e00U) >> 9)
68790 #define TPC_4_B2__TX_GAIN_SETTING_2__READ(src) \
68791 (((u_int32_t)(src)\
68798 #define TPC_4_B2__RATE_SENT_2__READ(src) \
68799 (((u_int32_t)(src)\
68818 #define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__READ(src) \
68819 (((u_int32_t)(src)\
68821 #define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__WRITE(src) \
68822 (((u_int32_t)(src)\
68824 #define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__MODIFY(dst, src) \
68826 ~0x000003f0U) | (((u_int32_t)(src) <<\
68828 #define TPC_5_B2__PD_GAIN_BOUNDARY_1_2__VERIFY(src) \
68829 (!((((u_int32_t)(src)\
68836 #define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__READ(src) \
68837 (((u_int32_t)(src)\
68839 #define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__WRITE(src) \
68840 (((u_int32_t)(src)\
68842 #define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__MODIFY(dst, src) \
68844 ~0x0000fc00U) | (((u_int32_t)(src) <<\
68846 #define TPC_5_B2__PD_GAIN_BOUNDARY_2_2__VERIFY(src) \
68847 (!((((u_int32_t)(src)\
68854 #define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__READ(src) \
68855 (((u_int32_t)(src)\
68857 #define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__WRITE(src) \
68858 (((u_int32_t)(src)\
68860 #define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__MODIFY(dst, src) \
68862 ~0x003f0000U) | (((u_int32_t)(src) <<\
68864 #define TPC_5_B2__PD_GAIN_BOUNDARY_3_2__VERIFY(src) \
68865 (!((((u_int32_t)(src)\
68872 #define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__READ(src) \
68873 (((u_int32_t)(src)\
68875 #define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__WRITE(src) \
68876 (((u_int32_t)(src)\
68878 #define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__MODIFY(dst, src) \
68880 ~0x0fc00000U) | (((u_int32_t)(src) <<\
68882 #define TPC_5_B2__PD_GAIN_BOUNDARY_4_2__VERIFY(src) \
68883 (!((((u_int32_t)(src)\
68903 #define TPC_6_B2__PD_DAC_SETTING_1_2__READ(src) (u_int32_t)(src) & 0x0000003fU
68904 #define TPC_6_B2__PD_DAC_SETTING_1_2__WRITE(src) \
68905 ((u_int32_t)(src)\
68907 #define TPC_6_B2__PD_DAC_SETTING_1_2__MODIFY(dst, src) \
68909 ~0x0000003fU) | ((u_int32_t)(src) &\
68911 #define TPC_6_B2__PD_DAC_SETTING_1_2__VERIFY(src) \
68912 (!(((u_int32_t)(src)\
68919 #define TPC_6_B2__PD_DAC_SETTING_2_2__READ(src) \
68920 (((u_int32_t)(src)\
68922 #define TPC_6_B2__PD_DAC_SETTING_2_2__WRITE(src) \
68923 (((u_int32_t)(src)\
68925 #define TPC_6_B2__PD_DAC_SETTING_2_2__MODIFY(dst, src) \
68927 ~0x00000fc0U) | (((u_int32_t)(src) <<\
68929 #define TPC_6_B2__PD_DAC_SETTING_2_2__VERIFY(src) \
68930 (!((((u_int32_t)(src)\
68937 #define TPC_6_B2__PD_DAC_SETTING_3_2__READ(src) \
68938 (((u_int32_t)(src)\
68940 #define TPC_6_B2__PD_DAC_SETTING_3_2__WRITE(src) \
68941 (((u_int32_t)(src)\
68943 #define TPC_6_B2__PD_DAC_SETTING_3_2__MODIFY(dst, src) \
68945 ~0x0003f000U) | (((u_int32_t)(src) <<\
68947 #define TPC_6_B2__PD_DAC_SETTING_3_2__VERIFY(src) \
68948 (!((((u_int32_t)(src)\
68955 #define TPC_6_B2__PD_DAC_SETTING_4_2__READ(src) \
68956 (((u_int32_t)(src)\
68958 #define TPC_6_B2__PD_DAC_SETTING_4_2__WRITE(src) \
68959 (((u_int32_t)(src)\
68961 #define TPC_6_B2__PD_DAC_SETTING_4_2__MODIFY(dst, src) \
68963 ~0x00fc0000U) | (((u_int32_t)(src) <<\
68965 #define TPC_6_B2__PD_DAC_SETTING_4_2__VERIFY(src) \
68966 (!((((u_int32_t)(src)\
68973 #define TPC_6_B2__ERROR_EST_MODE__READ(src) \
68974 (((u_int32_t)(src)\
68976 #define TPC_6_B2__ERROR_EST_MODE__WRITE(src) \
68977 (((u_int32_t)(src)\
68979 #define TPC_6_B2__ERROR_EST_MODE__MODIFY(dst, src) \
68981 ~0x03000000U) | (((u_int32_t)(src) <<\
68983 #define TPC_6_B2__ERROR_EST_MODE__VERIFY(src) \
68984 (!((((u_int32_t)(src)\
68991 #define TPC_6_B2__ERROR_EST_FILTER_COEFF__READ(src) \
68992 (((u_int32_t)(src)\
68994 #define TPC_6_B2__ERROR_EST_FILTER_COEFF__WRITE(src) \
68995 (((u_int32_t)(src)\
68997 #define TPC_6_B2__ERROR_EST_FILTER_COEFF__MODIFY(dst, src) \
68999 ~0x1c000000U) | (((u_int32_t)(src) <<\
69001 #define TPC_6_B2__ERROR_EST_FILTER_COEFF__VERIFY(src) \
69002 (!((((u_int32_t)(src)\
69022 #define TPC_11_B2__OLPC_GAIN_DELTA_2__READ(src) \
69023 (((u_int32_t)(src)\
69025 #define TPC_11_B2__OLPC_GAIN_DELTA_2__WRITE(src) \
69026 (((u_int32_t)(src)\
69028 #define TPC_11_B2__OLPC_GAIN_DELTA_2__MODIFY(dst, src) \
69030 ~0x00ff0000U) | (((u_int32_t)(src) <<\
69032 #define TPC_11_B2__OLPC_GAIN_DELTA_2__VERIFY(src) \
69033 (!((((u_int32_t)(src)\
69040 #define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__READ(src) \
69041 (((u_int32_t)(src)\
69043 #define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__WRITE(src) \
69044 (((u_int32_t)(src)\
69046 #define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__MODIFY(dst, src) \
69048 ~0xff000000U) | (((u_int32_t)(src) <<\
69050 #define TPC_11_B2__OLPC_GAIN_DELTA_2_PAL_ON__VERIFY(src) \
69051 (!((((u_int32_t)(src)\
69071 #define PDADC_TAB__TAB_ENTRY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
69072 #define PDADC_TAB__TAB_ENTRY__MODIFY(dst, src) \
69074 ~0xffffffffU) | ((u_int32_t)(src) &\
69076 #define PDADC_TAB__TAB_ENTRY__VERIFY(src) \
69077 (!(((u_int32_t)(src)\
69096 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__READ(src) \
69097 (u_int32_t)(src)\
69099 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__WRITE(src) \
69100 ((u_int32_t)(src)\
69102 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__MODIFY(dst, src) \
69104 ~0x00003fffU) | ((u_int32_t)(src) &\
69106 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_0_2__VERIFY(src) \
69107 (!(((u_int32_t)(src)\
69114 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__READ(src) \
69115 (((u_int32_t)(src)\
69117 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__WRITE(src) \
69118 (((u_int32_t)(src)\
69120 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__MODIFY(dst, src) \
69122 ~0x0fffc000U) | (((u_int32_t)(src) <<\
69124 #define TXIQ_CORR_COEFF_01_B2__IQC_COEFF_TABLE_1_2__VERIFY(src) \
69125 (!((((u_int32_t)(src)\
69145 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__READ(src) \
69146 (u_int32_t)(src)\
69148 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__WRITE(src) \
69149 ((u_int32_t)(src)\
69151 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__MODIFY(dst, src) \
69153 ~0x00003fffU) | ((u_int32_t)(src) &\
69155 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_2_2__VERIFY(src) \
69156 (!(((u_int32_t)(src)\
69163 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__READ(src) \
69164 (((u_int32_t)(src)\
69166 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__WRITE(src) \
69167 (((u_int32_t)(src)\
69169 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__MODIFY(dst, src) \
69171 ~0x0fffc000U) | (((u_int32_t)(src) <<\
69173 #define TXIQ_CORR_COEFF_23_B2__IQC_COEFF_TABLE_3_2__VERIFY(src) \
69174 (!((((u_int32_t)(src)\
69194 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__READ(src) \
69195 (u_int32_t)(src)\
69197 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__WRITE(src) \
69198 ((u_int32_t)(src)\
69200 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__MODIFY(dst, src) \
69202 ~0x00003fffU) | ((u_int32_t)(src) &\
69204 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_4_2__VERIFY(src) \
69205 (!(((u_int32_t)(src)\
69212 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__READ(src) \
69213 (((u_int32_t)(src)\
69215 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__WRITE(src) \
69216 (((u_int32_t)(src)\
69218 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__MODIFY(dst, src) \
69220 ~0x0fffc000U) | (((u_int32_t)(src) <<\
69222 #define TXIQ_CORR_COEFF_45_B2__IQC_COEFF_TABLE_5_2__VERIFY(src) \
69223 (!((((u_int32_t)(src)\
69243 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__READ(src) \
69244 (u_int32_t)(src)\
69246 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__WRITE(src) \
69247 ((u_int32_t)(src)\
69249 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__MODIFY(dst, src) \
69251 ~0x00003fffU) | ((u_int32_t)(src) &\
69253 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_6_2__VERIFY(src) \
69254 (!(((u_int32_t)(src)\
69261 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__READ(src) \
69262 (((u_int32_t)(src)\
69264 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__WRITE(src) \
69265 (((u_int32_t)(src)\
69267 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__MODIFY(dst, src) \
69269 ~0x0fffc000U) | (((u_int32_t)(src) <<\
69271 #define TXIQ_CORR_COEFF_67_B2__IQC_COEFF_TABLE_7_2__VERIFY(src) \
69272 (!((((u_int32_t)(src)\
69292 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__READ(src) \
69293 (u_int32_t)(src)\
69295 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__WRITE(src) \
69296 ((u_int32_t)(src)\
69298 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__MODIFY(dst, src) \
69300 ~0x00003fffU) | ((u_int32_t)(src) &\
69302 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_8_2__VERIFY(src) \
69303 (!(((u_int32_t)(src)\
69310 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__READ(src) \
69311 (((u_int32_t)(src)\
69313 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__WRITE(src) \
69314 (((u_int32_t)(src)\
69316 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__MODIFY(dst, src) \
69318 ~0x0fffc000U) | (((u_int32_t)(src) <<\
69320 #define TXIQ_CORR_COEFF_89_B2__IQC_COEFF_TABLE_9_2__VERIFY(src) \
69321 (!((((u_int32_t)(src)\
69341 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__READ(src) \
69342 (u_int32_t)(src)\
69344 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__WRITE(src) \
69345 ((u_int32_t)(src)\
69347 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__MODIFY(dst, src) \
69349 ~0x00003fffU) | ((u_int32_t)(src) &\
69351 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_A_2__VERIFY(src) \
69352 (!(((u_int32_t)(src)\
69359 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__READ(src) \
69360 (((u_int32_t)(src)\
69362 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__WRITE(src) \
69363 (((u_int32_t)(src)\
69365 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__MODIFY(dst, src) \
69367 ~0x0fffc000U) | (((u_int32_t)(src) <<\
69369 #define TXIQ_CORR_COEFF_AB_B2__IQC_COEFF_TABLE_B_2__VERIFY(src) \
69370 (!((((u_int32_t)(src)\
69390 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__READ(src) \
69391 (u_int32_t)(src)\
69393 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__WRITE(src) \
69394 ((u_int32_t)(src)\
69396 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__MODIFY(dst, src) \
69398 ~0x00003fffU) | ((u_int32_t)(src) &\
69400 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_C_2__VERIFY(src) \
69401 (!(((u_int32_t)(src)\
69408 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__READ(src) \
69409 (((u_int32_t)(src)\
69411 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__WRITE(src) \
69412 (((u_int32_t)(src)\
69414 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__MODIFY(dst, src) \
69416 ~0x0fffc000U) | (((u_int32_t)(src) <<\
69418 #define TXIQ_CORR_COEFF_CD_B2__IQC_COEFF_TABLE_D_2__VERIFY(src) \
69419 (!((((u_int32_t)(src)\
69439 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__READ(src) \
69440 (u_int32_t)(src)\
69442 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__WRITE(src) \
69443 ((u_int32_t)(src)\
69445 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__MODIFY(dst, src) \
69447 ~0x00003fffU) | ((u_int32_t)(src) &\
69449 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_E_2__VERIFY(src) \
69450 (!(((u_int32_t)(src)\
69457 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__READ(src) \
69458 (((u_int32_t)(src)\
69460 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__WRITE(src) \
69461 (((u_int32_t)(src)\
69463 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__MODIFY(dst, src) \
69465 ~0x0fffc000U) | (((u_int32_t)(src) <<\
69467 #define TXIQ_CORR_COEFF_EF_B2__IQC_COEFF_TABLE_F_2__VERIFY(src) \
69468 (!((((u_int32_t)(src)\
69488 #define TXIQCAL_STATUS_B2__TXIQCAL_FAILED_2__READ(src) \
69489 (u_int32_t)(src)\
69502 #define TXIQCAL_STATUS_B2__CALIBRATED_GAINS_2__READ(src) \
69503 (((u_int32_t)(src)\
69510 #define TXIQCAL_STATUS_B2__TONE_GAIN_USED_2__READ(src) \
69511 (((u_int32_t)(src)\
69518 #define TXIQCAL_STATUS_B2__RX_GAIN_USED_2__READ(src) \
69519 (((u_int32_t)(src)\
69526 #define TXIQCAL_STATUS_B2__LAST_MEAS_ADDR_2__READ(src) \
69527 (((u_int32_t)(src)\
69549 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U
69569 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U
69589 #define RSSI_B3__RSSI_3__READ(src) (u_int32_t)(src) & 0x000000ffU
69595 #define RSSI_B3__RSSI_EXT_3__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
69613 #define DUMMY__DUMMY__READ(src) (u_int32_t)(src) & 0x00000001U
69647 #define TXBF_DBG__MODE__READ(src) (u_int32_t)(src) & 0x00000003U
69648 #define TXBF_DBG__MODE__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
69649 #define TXBF_DBG__MODE__MODIFY(dst, src) \
69651 ~0x00000003U) | ((u_int32_t)(src) &\
69653 #define TXBF_DBG__MODE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
69659 #define TXBF_DBG__CLIENT_TABLE__READ(src) \
69660 (((u_int32_t)(src)\
69662 #define TXBF_DBG__CLIENT_TABLE__WRITE(src) \
69663 (((u_int32_t)(src)\
69665 #define TXBF_DBG__CLIENT_TABLE__MODIFY(dst, src) \
69667 ~0x0003fffcU) | (((u_int32_t)(src) <<\
69669 #define TXBF_DBG__CLIENT_TABLE__VERIFY(src) \
69670 (!((((u_int32_t)(src)\
69677 #define TXBF_DBG__SW_WR_V_DONE__READ(src) \
69678 (((u_int32_t)(src)\
69680 #define TXBF_DBG__SW_WR_V_DONE__WRITE(src) \
69681 (((u_int32_t)(src)\
69683 #define TXBF_DBG__SW_WR_V_DONE__MODIFY(dst, src) \
69685 ~0x00040000U) | (((u_int32_t)(src) <<\
69687 #define TXBF_DBG__SW_WR_V_DONE__VERIFY(src) \
69688 (!((((u_int32_t)(src)\
69701 #define TXBF_DBG__DBG_IM__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19)
69702 #define TXBF_DBG__DBG_IM__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U)
69703 #define TXBF_DBG__DBG_IM__MODIFY(dst, src) \
69705 ~0x00080000U) | (((u_int32_t)(src) <<\
69707 #define TXBF_DBG__DBG_IM__VERIFY(src) \
69708 (!((((u_int32_t)(src)\
69721 #define TXBF_DBG__DBG_BW__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20)
69722 #define TXBF_DBG__DBG_BW__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U)
69723 #define TXBF_DBG__DBG_BW__MODIFY(dst, src) \
69725 ~0x00100000U) | (((u_int32_t)(src) <<\
69727 #define TXBF_DBG__DBG_BW__VERIFY(src) \
69728 (!((((u_int32_t)(src)\
69741 #define TXBF_DBG__CLK_CNTL__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U)
69742 #define TXBF_DBG__CLK_CNTL__MODIFY(dst, src) \
69744 ~0x00200000U) | (((u_int32_t)(src) <<\
69746 #define TXBF_DBG__CLK_CNTL__VERIFY(src) \
69747 (!((((u_int32_t)(src)\
69760 #define TXBF_DBG__REGULAR_SOUNDING__READ(src) \
69761 (((u_int32_t)(src)\
69763 #define TXBF_DBG__REGULAR_SOUNDING__WRITE(src) \
69764 (((u_int32_t)(src)\
69766 #define TXBF_DBG__REGULAR_SOUNDING__MODIFY(dst, src) \
69768 ~0x00400000U) | (((u_int32_t)(src) <<\
69770 #define TXBF_DBG__REGULAR_SOUNDING__VERIFY(src) \
69771 (!((((u_int32_t)(src)\
69784 #define TXBF_DBG__DBG_NO_WALSH__READ(src) \
69785 (((u_int32_t)(src)\
69787 #define TXBF_DBG__DBG_NO_WALSH__WRITE(src) \
69788 (((u_int32_t)(src)\
69790 #define TXBF_DBG__DBG_NO_WALSH__MODIFY(dst, src) \
69792 ~0x00800000U) | (((u_int32_t)(src) <<\
69794 #define TXBF_DBG__DBG_NO_WALSH__VERIFY(src) \
69795 (!((((u_int32_t)(src)\
69808 #define TXBF_DBG__DBG_NO_CSD__READ(src) \
69809 (((u_int32_t)(src)\
69811 #define TXBF_DBG__DBG_NO_CSD__WRITE(src) \
69812 (((u_int32_t)(src)\
69814 #define TXBF_DBG__DBG_NO_CSD__MODIFY(dst, src) \
69816 ~0x01000000U) | (((u_int32_t)(src) <<\
69818 #define TXBF_DBG__DBG_NO_CSD__VERIFY(src) \
69819 (!((((u_int32_t)(src)\
69845 #define TXBF__CB_TX__READ(src) (u_int32_t)(src) & 0x00000003U
69846 #define TXBF__CB_TX__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
69847 #define TXBF__CB_TX__MODIFY(dst, src) \
69849 ~0x00000003U) | ((u_int32_t)(src) &\
69851 #define TXBF__CB_TX__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
69857 #define TXBF__NB_TX__READ(src) (((u_int32_t)(src) & 0x0000000cU) >> 2)
69858 #define TXBF__NB_TX__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000000cU)
69859 #define TXBF__NB_TX__MODIFY(dst, src) \
69861 ~0x0000000cU) | (((u_int32_t)(src) <<\
69863 #define TXBF__NB_TX__VERIFY(src) (!((((u_int32_t)(src) << 2) & ~0x0000000cU)))
69869 #define TXBF__NG_RPT_TX__READ(src) (((u_int32_t)(src) & 0x00000030U) >> 4)
69870 #define TXBF__NG_RPT_TX__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000030U)
69871 #define TXBF__NG_RPT_TX__MODIFY(dst, src) \
69873 ~0x00000030U) | (((u_int32_t)(src) <<\
69875 #define TXBF__NG_RPT_TX__VERIFY(src) \
69876 (!((((u_int32_t)(src)\
69883 #define TXBF__NG_CVCACHE__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6)
69884 #define TXBF__NG_CVCACHE__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U)
69885 #define TXBF__NG_CVCACHE__MODIFY(dst, src) \
69887 ~0x000000c0U) | (((u_int32_t)(src) <<\
69889 #define TXBF__NG_CVCACHE__VERIFY(src) \
69890 (!((((u_int32_t)(src)\
69897 #define TXBF__TXCV_BFWEIGHT_METHOD__READ(src) \
69898 (((u_int32_t)(src)\
69900 #define TXBF__TXCV_BFWEIGHT_METHOD__WRITE(src) \
69901 (((u_int32_t)(src)\
69903 #define TXBF__TXCV_BFWEIGHT_METHOD__MODIFY(dst, src) \
69905 ~0x00000600U) | (((u_int32_t)(src) <<\
69907 #define TXBF__TXCV_BFWEIGHT_METHOD__VERIFY(src) \
69908 (!((((u_int32_t)(src)\
69915 #define TXBF__RLR_EN__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
69916 #define TXBF__RLR_EN__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U)
69917 #define TXBF__RLR_EN__MODIFY(dst, src) \
69919 ~0x00000800U) | (((u_int32_t)(src) <<\
69921 #define TXBF__RLR_EN__VERIFY(src) \
69922 (!((((u_int32_t)(src)\
69935 #define TXBF__RC_20_U_DONE__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12)
69936 #define TXBF__RC_20_U_DONE__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U)
69937 #define TXBF__RC_20_U_DONE__MODIFY(dst, src) \
69939 ~0x00001000U) | (((u_int32_t)(src) <<\
69941 #define TXBF__RC_20_U_DONE__VERIFY(src) \
69942 (!((((u_int32_t)(src)\
69955 #define TXBF__RC_20_L_DONE__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13)
69956 #define TXBF__RC_20_L_DONE__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U)
69957 #define TXBF__RC_20_L_DONE__MODIFY(dst, src) \
69959 ~0x00002000U) | (((u_int32_t)(src) <<\
69961 #define TXBF__RC_20_L_DONE__VERIFY(src) \
69962 (!((((u_int32_t)(src)\
69975 #define TXBF__RC_40_DONE__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14)
69976 #define TXBF__RC_40_DONE__WRITE(src) (((u_int32_t)(src) << 14) & 0x00004000U)
69977 #define TXBF__RC_40_DONE__MODIFY(dst, src) \
69979 ~0x00004000U) | (((u_int32_t)(src) <<\
69981 #define TXBF__RC_40_DONE__VERIFY(src) \
69982 (!((((u_int32_t)(src)\
70008 #define TXBF_TIMER__TIMEOUT__READ(src) (u_int32_t)(src) & 0x000000ffU
70009 #define TXBF_TIMER__TIMEOUT__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
70010 #define TXBF_TIMER__TIMEOUT__MODIFY(dst, src) \
70012 ~0x000000ffU) | ((u_int32_t)(src) &\
70014 #define TXBF_TIMER__TIMEOUT__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
70020 #define TXBF_TIMER__ATIMEOUT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
70021 #define TXBF_TIMER__ATIMEOUT__WRITE(src) \
70022 (((u_int32_t)(src)\
70024 #define TXBF_TIMER__ATIMEOUT__MODIFY(dst, src) \
70026 ~0x0000ff00U) | (((u_int32_t)(src) <<\
70028 #define TXBF_TIMER__ATIMEOUT__VERIFY(src) \
70029 (!((((u_int32_t)(src)\
70049 #define TXBF_SW__LRU_ACK__READ(src) (u_int32_t)(src) & 0x00000001U
70050 #define TXBF_SW__LRU_ACK__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
70051 #define TXBF_SW__LRU_ACK__MODIFY(dst, src) \
70053 ~0x00000001U) | ((u_int32_t)(src) &\
70055 #define TXBF_SW__LRU_ACK__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
70067 #define TXBF_SW__LRU_ADDR__READ(src) (((u_int32_t)(src) & 0x000003feU) >> 1)
70073 #define TXBF_SW__LRU_EN__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
70074 #define TXBF_SW__LRU_EN__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U)
70075 #define TXBF_SW__LRU_EN__MODIFY(dst, src) \
70077 ~0x00000800U) | (((u_int32_t)(src) <<\
70079 #define TXBF_SW__LRU_EN__VERIFY(src) \
70080 (!((((u_int32_t)(src)\
70093 #define TXBF_SW__DEST_IDX__READ(src) (((u_int32_t)(src) & 0x0007f000U) >> 12)
70094 #define TXBF_SW__DEST_IDX__WRITE(src) (((u_int32_t)(src) << 12) & 0x0007f000U)
70095 #define TXBF_SW__DEST_IDX__MODIFY(dst, src) \
70097 ~0x0007f000U) | (((u_int32_t)(src) <<\
70099 #define TXBF_SW__DEST_IDX__VERIFY(src) \
70100 (!((((u_int32_t)(src)\
70107 #define TXBF_SW__LRU_WR_ACK__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19)
70108 #define TXBF_SW__LRU_WR_ACK__WRITE(src) \
70109 (((u_int32_t)(src)\
70111 #define TXBF_SW__LRU_WR_ACK__MODIFY(dst, src) \
70113 ~0x00080000U) | (((u_int32_t)(src) <<\
70115 #define TXBF_SW__LRU_WR_ACK__VERIFY(src) \
70116 (!((((u_int32_t)(src)\
70129 #define TXBF_SW__LRU_RD_ACK__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20)
70130 #define TXBF_SW__LRU_RD_ACK__WRITE(src) \
70131 (((u_int32_t)(src)\
70133 #define TXBF_SW__LRU_RD_ACK__MODIFY(dst, src) \
70135 ~0x00100000U) | (((u_int32_t)(src) <<\
70137 #define TXBF_SW__LRU_RD_ACK__VERIFY(src) \
70138 (!((((u_int32_t)(src)\
70151 #define TXBF_SW__WALSH_CSD_MODE__READ(src) \
70152 (((u_int32_t)(src)\
70154 #define TXBF_SW__WALSH_CSD_MODE__WRITE(src) \
70155 (((u_int32_t)(src)\
70157 #define TXBF_SW__WALSH_CSD_MODE__MODIFY(dst, src) \
70159 ~0x00200000U) | (((u_int32_t)(src) <<\
70161 #define TXBF_SW__WALSH_CSD_MODE__VERIFY(src) \
70162 (!((((u_int32_t)(src)\
70175 #define TXBF_SW__CONDITION_NUMBER__READ(src) \
70176 (((u_int32_t)(src)\
70178 #define TXBF_SW__CONDITION_NUMBER__WRITE(src) \
70179 (((u_int32_t)(src)\
70181 #define TXBF_SW__CONDITION_NUMBER__MODIFY(dst, src) \
70183 ~0x07c00000U) | (((u_int32_t)(src) <<\
70185 #define TXBF_SW__CONDITION_NUMBER__VERIFY(src) \
70186 (!((((u_int32_t)(src)\
70206 #define TXBF_SM__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU
70224 #define TXBF1_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU
70242 #define TXBF2_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU
70260 #define TXBF3_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU
70278 #define TXBF4_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU
70296 #define TXBF5_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU
70314 #define TXBF6_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU
70332 #define TXBF7_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU
70350 #define TXBF8_CNTL__OBS__READ(src) (u_int32_t)(src) & 0xffffffffU
70368 #define RC0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
70369 #define RC0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
70370 #define RC0__DATA__MODIFY(dst, src) \
70372 ~0xffffffffU) | ((u_int32_t)(src) &\
70374 #define RC0__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
70393 #define RC1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
70394 #define RC1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
70395 #define RC1__DATA__MODIFY(dst, src) \
70397 ~0xffffffffU) | ((u_int32_t)(src) &\
70399 #define RC1__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
70418 #define SVD_MEM0__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
70419 #define SVD_MEM0__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
70420 #define SVD_MEM0__DATA__MODIFY(dst, src) \
70422 ~0xffffffffU) | ((u_int32_t)(src) &\
70424 #define SVD_MEM0__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
70443 #define SVD_MEM1__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
70444 #define SVD_MEM1__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
70445 #define SVD_MEM1__DATA__MODIFY(dst, src) \
70447 ~0xffffffffU) | ((u_int32_t)(src) &\
70449 #define SVD_MEM1__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
70468 #define SVD_MEM2__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
70469 #define SVD_MEM2__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
70470 #define SVD_MEM2__DATA__MODIFY(dst, src) \
70472 ~0xffffffffU) | ((u_int32_t)(src) &\
70474 #define SVD_MEM2__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
70493 #define SVD_MEM3__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
70494 #define SVD_MEM3__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
70495 #define SVD_MEM3__DATA__MODIFY(dst, src) \
70497 ~0xffffffffU) | ((u_int32_t)(src) &\
70499 #define SVD_MEM3__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
70518 #define SVD_MEM4__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
70519 #define SVD_MEM4__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
70520 #define SVD_MEM4__DATA__MODIFY(dst, src) \
70522 ~0xffffffffU) | ((u_int32_t)(src) &\
70524 #define SVD_MEM4__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
70543 #define CVCACHE__DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
70544 #define CVCACHE__DATA__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
70545 #define CVCACHE__DATA__MODIFY(dst, src) \
70547 ~0xffffffffU) | ((u_int32_t)(src) &\
70549 #define CVCACHE__DATA__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
70568 #define OTP_MEM__OTP_MEM__READ(src) (u_int32_t)(src) & 0xffffffffU
70569 #define OTP_MEM__OTP_MEM__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
70570 #define OTP_MEM__OTP_MEM__MODIFY(dst, src) \
70572 ~0xffffffffU) | ((u_int32_t)(src) &\
70574 #define OTP_MEM__OTP_MEM__VERIFY(src) (!(((u_int32_t)(src) & ~0xffffffffU)))
70593 #define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__READ(src) \
70594 (u_int32_t)(src)\
70596 #define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__WRITE(src) \
70597 ((u_int32_t)(src)\
70599 #define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__MODIFY(dst, src) \
70601 ~0xffffffffU) | ((u_int32_t)(src) &\
70603 #define OTP_INTF0__EFUSE_WR_ENABLE_REG_V__VERIFY(src) \
70604 (!(((u_int32_t)(src)\
70624 #define OTP_INTF1__BITMASK_WR_REG_V__READ(src) (u_int32_t)(src) & 0xffffffffU
70625 #define OTP_INTF1__BITMASK_WR_REG_V__WRITE(src) \
70626 ((u_int32_t)(src)\
70628 #define OTP_INTF1__BITMASK_WR_REG_V__MODIFY(dst, src) \
70630 ~0xffffffffU) | ((u_int32_t)(src) &\
70632 #define OTP_INTF1__BITMASK_WR_REG_V__VERIFY(src) \
70633 (!(((u_int32_t)(src)\
70653 #define OTP_INTF2__PG_STROBE_PW_REG_V__READ(src) (u_int32_t)(src) & 0xffffffffU
70654 #define OTP_INTF2__PG_STROBE_PW_REG_V__WRITE(src) \
70655 ((u_int32_t)(src)\
70657 #define OTP_INTF2__PG_STROBE_PW_REG_V__MODIFY(dst, src) \
70659 ~0xffffffffU) | ((u_int32_t)(src) &\
70661 #define OTP_INTF2__PG_STROBE_PW_REG_V__VERIFY(src) \
70662 (!(((u_int32_t)(src)\
70682 #define OTP_INTF3__RD_STROBE_PW_REG_V__READ(src) (u_int32_t)(src) & 0xffffffffU
70683 #define OTP_INTF3__RD_STROBE_PW_REG_V__WRITE(src) \
70684 ((u_int32_t)(src)\
70686 #define OTP_INTF3__RD_STROBE_PW_REG_V__MODIFY(dst, src) \
70688 ~0xffffffffU) | ((u_int32_t)(src) &\
70690 #define OTP_INTF3__RD_STROBE_PW_REG_V__VERIFY(src) \
70691 (!(((u_int32_t)(src)\
70711 #define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__READ(src) \
70712 (u_int32_t)(src)\
70714 #define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__WRITE(src) \
70715 ((u_int32_t)(src)\
70717 #define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__MODIFY(dst, src) \
70719 ~0xffffffffU) | ((u_int32_t)(src) &\
70721 #define OTP_INTF4__VDDQ_SETTLE_TIME_REG_V__VERIFY(src) \
70722 (!(((u_int32_t)(src)\
70742 #define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__READ(src) \
70743 (u_int32_t)(src)\
70745 #define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__WRITE(src) \
70746 ((u_int32_t)(src)\
70748 #define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__MODIFY(dst, src) \
70750 ~0x00000001U) | ((u_int32_t)(src) &\
70752 #define OTP_INTF5__EFUSE_INT_ENABLE_REG_V__VERIFY(src) \
70753 (!(((u_int32_t)(src)\
70779 #define OTP_STATUS0__OTP_SM_BUSY__READ(src) (u_int32_t)(src) & 0x00000001U
70791 #define OTP_STATUS0__EFUSE_ACCESS_BUSY__READ(src) \
70792 (((u_int32_t)(src)\
70805 #define OTP_STATUS0__EFUSE_READ_DATA_VALID__READ(src) \
70806 (((u_int32_t)(src)\
70831 #define OTP_STATUS1__EFUSE_READ_DATA__READ(src) (u_int32_t)(src) & 0xffffffffU
70849 #define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__READ(src) \
70850 (u_int32_t)(src)\
70852 #define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__WRITE(src) \
70853 ((u_int32_t)(src)\
70855 #define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__MODIFY(dst, src) \
70857 ~0xffffffffU) | ((u_int32_t)(src) &\
70859 #define OTP_INTF6__BACK_TO_BACK_ACCESS_DELAY__VERIFY(src) \
70860 (!(((u_int32_t)(src)\
70880 #define OTP_LDO_CONTROL__ENABLE__READ(src) (u_int32_t)(src) & 0x00000001U
70881 #define OTP_LDO_CONTROL__ENABLE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
70882 #define OTP_LDO_CONTROL__ENABLE__MODIFY(dst, src) \
70884 ~0x00000001U) | ((u_int32_t)(src) &\
70886 #define OTP_LDO_CONTROL__ENABLE__VERIFY(src) \
70887 (!(((u_int32_t)(src)\
70913 #define OTP_LDO_POWER_GOOD__DELAY__READ(src) (u_int32_t)(src) & 0x00000fffU
70914 #define OTP_LDO_POWER_GOOD__DELAY__WRITE(src) ((u_int32_t)(src) & 0x00000fffU)
70915 #define OTP_LDO_POWER_GOOD__DELAY__MODIFY(dst, src) \
70917 ~0x00000fffU) | ((u_int32_t)(src) &\
70919 #define OTP_LDO_POWER_GOOD__DELAY__VERIFY(src) \
70920 (!(((u_int32_t)(src)\
70940 #define OTP_LDO_STATUS__POWER_ON__READ(src) (u_int32_t)(src) & 0x00000001U
70964 #define OTP_VDDQ_HOLD_TIME__DELAY__READ(src) (u_int32_t)(src) & 0xffffffffU
70965 #define OTP_VDDQ_HOLD_TIME__DELAY__WRITE(src) ((u_int32_t)(src) & 0xffffffffU)
70966 #define OTP_VDDQ_HOLD_TIME__DELAY__MODIFY(dst, src) \
70968 ~0xffffffffU) | ((u_int32_t)(src) &\
70970 #define OTP_VDDQ_HOLD_TIME__DELAY__VERIFY(src) \
70971 (!(((u_int32_t)(src)\
70991 #define OTP_PGENB_SETUP_HOLD_TIME__DELAY__READ(src) \
70992 (u_int32_t)(src)\
70994 #define OTP_PGENB_SETUP_HOLD_TIME__DELAY__WRITE(src) \
70995 ((u_int32_t)(src)\
70997 #define OTP_PGENB_SETUP_HOLD_TIME__DELAY__MODIFY(dst, src) \
70999 ~0xffffffffU) | ((u_int32_t)(src) &\
71001 #define OTP_PGENB_SETUP_HOLD_TIME__DELAY__VERIFY(src) \
71002 (!(((u_int32_t)(src)\
71022 #define OTP_STROBE_PULSE_INTERVAL__DELAY__READ(src) \
71023 (u_int32_t)(src)\
71025 #define OTP_STROBE_PULSE_INTERVAL__DELAY__WRITE(src) \
71026 ((u_int32_t)(src)\
71028 #define OTP_STROBE_PULSE_INTERVAL__DELAY__MODIFY(dst, src) \
71030 ~0xffffffffU) | ((u_int32_t)(src) &\
71032 #define OTP_STROBE_PULSE_INTERVAL__DELAY__VERIFY(src) \
71033 (!(((u_int32_t)(src)\
71053 #define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__READ(src) \
71054 (u_int32_t)(src)\
71056 #define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__WRITE(src) \
71057 ((u_int32_t)(src)\
71059 #define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__MODIFY(dst, src) \
71061 ~0xffffffffU) | ((u_int32_t)(src) &\
71063 #define OTP_CSB_ADDR_LOAD_SETUP_HOLD__DELAY__VERIFY(src) \
71064 (!(((u_int32_t)(src)\
71084 #define RXRF_BIAS1__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U
71085 #define RXRF_BIAS1__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
71086 #define RXRF_BIAS1__SPARE__MODIFY(dst, src) \
71088 ~0x00000001U) | ((u_int32_t)(src) &\
71090 #define RXRF_BIAS1__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
71102 #define RXRF_BIAS1__PWD_IR25SPARE__READ(src) \
71103 (((u_int32_t)(src)\
71105 #define RXRF_BIAS1__PWD_IR25SPARE__WRITE(src) \
71106 (((u_int32_t)(src)\
71108 #define RXRF_BIAS1__PWD_IR25SPARE__MODIFY(dst, src) \
71110 ~0x0000000eU) | (((u_int32_t)(src) <<\
71112 #define RXRF_BIAS1__PWD_IR25SPARE__VERIFY(src) \
71113 (!((((u_int32_t)(src)\
71120 #define RXRF_BIAS1__PWD_IR25LO18__READ(src) \
71121 (((u_int32_t)(src)\
71123 #define RXRF_BIAS1__PWD_IR25LO18__WRITE(src) \
71124 (((u_int32_t)(src)\
71126 #define RXRF_BIAS1__PWD_IR25LO18__MODIFY(dst, src) \
71128 ~0x00000070U) | (((u_int32_t)(src) <<\
71130 #define RXRF_BIAS1__PWD_IR25LO18__VERIFY(src) \
71131 (!((((u_int32_t)(src)\
71138 #define RXRF_BIAS1__PWD_IC25LO36__READ(src) \
71139 (((u_int32_t)(src)\
71141 #define RXRF_BIAS1__PWD_IC25LO36__WRITE(src) \
71142 (((u_int32_t)(src)\
71144 #define RXRF_BIAS1__PWD_IC25LO36__MODIFY(dst, src) \
71146 ~0x00000380U) | (((u_int32_t)(src) <<\
71148 #define RXRF_BIAS1__PWD_IC25LO36__VERIFY(src) \
71149 (!((((u_int32_t)(src)\
71156 #define RXRF_BIAS1__PWD_IC25MXR2_5GH__READ(src) \
71157 (((u_int32_t)(src)\
71159 #define RXRF_BIAS1__PWD_IC25MXR2_5GH__WRITE(src) \
71160 (((u_int32_t)(src)\
71162 #define RXRF_BIAS1__PWD_IC25MXR2_5GH__MODIFY(dst, src) \
71164 ~0x00001c00U) | (((u_int32_t)(src) <<\
71166 #define RXRF_BIAS1__PWD_IC25MXR2_5GH__VERIFY(src) \
71167 (!((((u_int32_t)(src)\
71174 #define RXRF_BIAS1__PWD_IC25MXR5GH__READ(src) \
71175 (((u_int32_t)(src)\
71177 #define RXRF_BIAS1__PWD_IC25MXR5GH__WRITE(src) \
71178 (((u_int32_t)(src)\
71180 #define RXRF_BIAS1__PWD_IC25MXR5GH__MODIFY(dst, src) \
71182 ~0x0000e000U) | (((u_int32_t)(src) <<\
71184 #define RXRF_BIAS1__PWD_IC25MXR5GH__VERIFY(src) \
71185 (!((((u_int32_t)(src)\
71192 #define RXRF_BIAS1__PWD_IC25VGA5G__READ(src) \
71193 (((u_int32_t)(src)\
71195 #define RXRF_BIAS1__PWD_IC25VGA5G__WRITE(src) \
71196 (((u_int32_t)(src)\
71198 #define RXRF_BIAS1__PWD_IC25VGA5G__MODIFY(dst, src) \
71200 ~0x00070000U) | (((u_int32_t)(src) <<\
71202 #define RXRF_BIAS1__PWD_IC25VGA5G__VERIFY(src) \
71203 (!((((u_int32_t)(src)\
71210 #define RXRF_BIAS1__PWD_IC75LNA5G__READ(src) \
71211 (((u_int32_t)(src)\
71213 #define RXRF_BIAS1__PWD_IC75LNA5G__WRITE(src) \
71214 (((u_int32_t)(src)\
71216 #define RXRF_BIAS1__PWD_IC75LNA5G__MODIFY(dst, src) \
71218 ~0x00380000U) | (((u_int32_t)(src) <<\
71220 #define RXRF_BIAS1__PWD_IC75LNA5G__VERIFY(src) \
71221 (!((((u_int32_t)(src)\
71228 #define RXRF_BIAS1__PWD_IR25LO24__READ(src) \
71229 (((u_int32_t)(src)\
71231 #define RXRF_BIAS1__PWD_IR25LO24__WRITE(src) \
71232 (((u_int32_t)(src)\
71234 #define RXRF_BIAS1__PWD_IR25LO24__MODIFY(dst, src) \
71236 ~0x01c00000U) | (((u_int32_t)(src) <<\
71238 #define RXRF_BIAS1__PWD_IR25LO24__VERIFY(src) \
71239 (!((((u_int32_t)(src)\
71246 #define RXRF_BIAS1__PWD_IC25MXR2GH__READ(src) \
71247 (((u_int32_t)(src)\
71249 #define RXRF_BIAS1__PWD_IC25MXR2GH__WRITE(src) \
71250 (((u_int32_t)(src)\
71252 #define RXRF_BIAS1__PWD_IC25MXR2GH__MODIFY(dst, src) \
71254 ~0x0e000000U) | (((u_int32_t)(src) <<\
71256 #define RXRF_BIAS1__PWD_IC25MXR2GH__VERIFY(src) \
71257 (!((((u_int32_t)(src)\
71264 #define RXRF_BIAS1__PWD_IC75LNA2G__READ(src) \
71265 (((u_int32_t)(src)\
71267 #define RXRF_BIAS1__PWD_IC75LNA2G__WRITE(src) \
71268 (((u_int32_t)(src)\
71270 #define RXRF_BIAS1__PWD_IC75LNA2G__MODIFY(dst, src) \
71272 ~0x70000000U) | (((u_int32_t)(src) <<\
71274 #define RXRF_BIAS1__PWD_IC75LNA2G__VERIFY(src) \
71275 (!((((u_int32_t)(src)\
71282 #define RXRF_BIAS1__PWD_BIAS__READ(src) \
71283 (((u_int32_t)(src)\
71285 #define RXRF_BIAS1__PWD_BIAS__WRITE(src) \
71286 (((u_int32_t)(src)\
71288 #define RXRF_BIAS1__PWD_BIAS__MODIFY(dst, src) \
71290 ~0x80000000U) | (((u_int32_t)(src) <<\
71292 #define RXRF_BIAS1__PWD_BIAS__VERIFY(src) \
71293 (!((((u_int32_t)(src)\
71319 #define RXRF_BIAS2__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U
71320 #define RXRF_BIAS2__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
71321 #define RXRF_BIAS2__SPARE__MODIFY(dst, src) \
71323 ~0x00000001U) | ((u_int32_t)(src) &\
71325 #define RXRF_BIAS2__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
71337 #define RXRF_BIAS2__PKEN__READ(src) (((u_int32_t)(src) & 0x0000000eU) >> 1)
71338 #define RXRF_BIAS2__PKEN__WRITE(src) (((u_int32_t)(src) << 1) & 0x0000000eU)
71339 #define RXRF_BIAS2__PKEN__MODIFY(dst, src) \
71341 ~0x0000000eU) | (((u_int32_t)(src) <<\
71343 #define RXRF_BIAS2__PKEN__VERIFY(src) \
71344 (!((((u_int32_t)(src)\
71351 #define RXRF_BIAS2__VCMVALUE__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4)
71352 #define RXRF_BIAS2__VCMVALUE__WRITE(src) \
71353 (((u_int32_t)(src)\
71355 #define RXRF_BIAS2__VCMVALUE__MODIFY(dst, src) \
71357 ~0x00000070U) | (((u_int32_t)(src) <<\
71359 #define RXRF_BIAS2__VCMVALUE__VERIFY(src) \
71360 (!((((u_int32_t)(src)\
71367 #define RXRF_BIAS2__PWD_VCMBUF__READ(src) \
71368 (((u_int32_t)(src)\
71370 #define RXRF_BIAS2__PWD_VCMBUF__WRITE(src) \
71371 (((u_int32_t)(src)\
71373 #define RXRF_BIAS2__PWD_VCMBUF__MODIFY(dst, src) \
71375 ~0x00000080U) | (((u_int32_t)(src) <<\
71377 #define RXRF_BIAS2__PWD_VCMBUF__VERIFY(src) \
71378 (!((((u_int32_t)(src)\
71391 #define RXRF_BIAS2__PWD_IR25SPAREH__READ(src) \
71392 (((u_int32_t)(src)\
71394 #define RXRF_BIAS2__PWD_IR25SPAREH__WRITE(src) \
71395 (((u_int32_t)(src)\
71397 #define RXRF_BIAS2__PWD_IR25SPAREH__MODIFY(dst, src) \
71399 ~0x00000700U) | (((u_int32_t)(src) <<\
71401 #define RXRF_BIAS2__PWD_IR25SPAREH__VERIFY(src) \
71402 (!((((u_int32_t)(src)\
71409 #define RXRF_BIAS2__PWD_IR25SPARE__READ(src) \
71410 (((u_int32_t)(src)\
71412 #define RXRF_BIAS2__PWD_IR25SPARE__WRITE(src) \
71413 (((u_int32_t)(src)\
71415 #define RXRF_BIAS2__PWD_IR25SPARE__MODIFY(dst, src) \
71417 ~0x00003800U) | (((u_int32_t)(src) <<\
71419 #define RXRF_BIAS2__PWD_IR25SPARE__VERIFY(src) \
71420 (!((((u_int32_t)(src)\
71427 #define RXRF_BIAS2__PWD_IC25LNABUF__READ(src) \
71428 (((u_int32_t)(src)\
71430 #define RXRF_BIAS2__PWD_IC25LNABUF__WRITE(src) \
71431 (((u_int32_t)(src)\
71433 #define RXRF_BIAS2__PWD_IC25LNABUF__MODIFY(dst, src) \
71435 ~0x0001c000U) | (((u_int32_t)(src) <<\
71437 #define RXRF_BIAS2__PWD_IC25LNABUF__VERIFY(src) \
71438 (!((((u_int32_t)(src)\
71445 #define RXRF_BIAS2__PWD_IR25AGCH__READ(src) \
71446 (((u_int32_t)(src)\
71448 #define RXRF_BIAS2__PWD_IR25AGCH__WRITE(src) \
71449 (((u_int32_t)(src)\
71451 #define RXRF_BIAS2__PWD_IR25AGCH__MODIFY(dst, src) \
71453 ~0x000e0000U) | (((u_int32_t)(src) <<\
71455 #define RXRF_BIAS2__PWD_IR25AGCH__VERIFY(src) \
71456 (!((((u_int32_t)(src)\
71463 #define RXRF_BIAS2__PWD_IR25AGC__READ(src) \
71464 (((u_int32_t)(src)\
71466 #define RXRF_BIAS2__PWD_IR25AGC__WRITE(src) \
71467 (((u_int32_t)(src)\
71469 #define RXRF_BIAS2__PWD_IR25AGC__MODIFY(dst, src) \
71471 ~0x00700000U) | (((u_int32_t)(src) <<\
71473 #define RXRF_BIAS2__PWD_IR25AGC__VERIFY(src) \
71474 (!((((u_int32_t)(src)\
71481 #define RXRF_BIAS2__PWD_IC25AGC__READ(src) \
71482 (((u_int32_t)(src)\
71484 #define RXRF_BIAS2__PWD_IC25AGC__WRITE(src) \
71485 (((u_int32_t)(src)\
71487 #define RXRF_BIAS2__PWD_IC25AGC__MODIFY(dst, src) \
71489 ~0x03800000U) | (((u_int32_t)(src) <<\
71491 #define RXRF_BIAS2__PWD_IC25AGC__VERIFY(src) \
71492 (!((((u_int32_t)(src)\
71499 #define RXRF_BIAS2__PWD_IC25VCMBUF__READ(src) \
71500 (((u_int32_t)(src)\
71502 #define RXRF_BIAS2__PWD_IC25VCMBUF__WRITE(src) \
71503 (((u_int32_t)(src)\
71505 #define RXRF_BIAS2__PWD_IC25VCMBUF__MODIFY(dst, src) \
71507 ~0x1c000000U) | (((u_int32_t)(src) <<\
71509 #define RXRF_BIAS2__PWD_IC25VCMBUF__VERIFY(src) \
71510 (!((((u_int32_t)(src)\
71517 #define RXRF_BIAS2__PWD_IR25VCM__READ(src) \
71518 (((u_int32_t)(src)\
71520 #define RXRF_BIAS2__PWD_IR25VCM__WRITE(src) \
71521 (((u_int32_t)(src)\
71523 #define RXRF_BIAS2__PWD_IR25VCM__MODIFY(dst, src) \
71525 ~0xe0000000U) | (((u_int32_t)(src) <<\
71527 #define RXRF_BIAS2__PWD_IR25VCM__VERIFY(src) \
71528 (!((((u_int32_t)(src)\
71548 #define RXRF_GAINSTAGES__SPARE__READ(src) (u_int32_t)(src) & 0x00000001U
71549 #define RXRF_GAINSTAGES__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
71550 #define RXRF_GAINSTAGES__SPARE__MODIFY(dst, src) \
71552 ~0x00000001U) | ((u_int32_t)(src) &\
71554 #define RXRF_GAINSTAGES__SPARE__VERIFY(src) \
71555 (!(((u_int32_t)(src)\
71568 #define RXRF_GAINSTAGES__LNAON_CALDC__READ(src) \
71569 (((u_int32_t)(src)\
71571 #define RXRF_GAINSTAGES__LNAON_CALDC__WRITE(src) \
71572 (((u_int32_t)(src)\
71574 #define RXRF_GAINSTAGES__LNAON_CALDC__MODIFY(dst, src) \
71576 ~0x00000002U) | (((u_int32_t)(src) <<\
71578 #define RXRF_GAINSTAGES__LNAON_CALDC__VERIFY(src) \
71579 (!((((u_int32_t)(src)\
71592 #define RXRF_GAINSTAGES__VGA5G_CAP__READ(src) \
71593 (((u_int32_t)(src)\
71595 #define RXRF_GAINSTAGES__VGA5G_CAP__WRITE(src) \
71596 (((u_int32_t)(src)\
71598 #define RXRF_GAINSTAGES__VGA5G_CAP__MODIFY(dst, src) \
71600 ~0x0000000cU) | (((u_int32_t)(src) <<\
71602 #define RXRF_GAINSTAGES__VGA5G_CAP__VERIFY(src) \
71603 (!((((u_int32_t)(src)\
71610 #define RXRF_GAINSTAGES__LNA5G_CAP__READ(src) \
71611 (((u_int32_t)(src)\
71613 #define RXRF_GAINSTAGES__LNA5G_CAP__WRITE(src) \
71614 (((u_int32_t)(src)\
71616 #define RXRF_GAINSTAGES__LNA5G_CAP__MODIFY(dst, src) \
71618 ~0x00000030U) | (((u_int32_t)(src) <<\
71620 #define RXRF_GAINSTAGES__LNA5G_CAP__VERIFY(src) \
71621 (!((((u_int32_t)(src)\
71628 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__READ(src) \
71629 (((u_int32_t)(src)\
71631 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__WRITE(src) \
71632 (((u_int32_t)(src)\
71634 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__MODIFY(dst, src) \
71636 ~0x00000040U) | (((u_int32_t)(src) <<\
71638 #define RXRF_GAINSTAGES__LNA5G_SHORTINP__VERIFY(src) \
71639 (!((((u_int32_t)(src)\
71652 #define RXRF_GAINSTAGES__PWD_LO5G__READ(src) \
71653 (((u_int32_t)(src)\
71655 #define RXRF_GAINSTAGES__PWD_LO5G__WRITE(src) \
71656 (((u_int32_t)(src)\
71658 #define RXRF_GAINSTAGES__PWD_LO5G__MODIFY(dst, src) \
71660 ~0x00000080U) | (((u_int32_t)(src) <<\
71662 #define RXRF_GAINSTAGES__PWD_LO5G__VERIFY(src) \
71663 (!((((u_int32_t)(src)\
71676 #define RXRF_GAINSTAGES__PWD_VGA5G__READ(src) \
71677 (((u_int32_t)(src)\
71679 #define RXRF_GAINSTAGES__PWD_VGA5G__WRITE(src) \
71680 (((u_int32_t)(src)\
71682 #define RXRF_GAINSTAGES__PWD_VGA5G__MODIFY(dst, src) \
71684 ~0x00000100U) | (((u_int32_t)(src) <<\
71686 #define RXRF_GAINSTAGES__PWD_VGA5G__VERIFY(src) \
71687 (!((((u_int32_t)(src)\
71700 #define RXRF_GAINSTAGES__PWD_MXR5G__READ(src) \
71701 (((u_int32_t)(src)\
71703 #define RXRF_GAINSTAGES__PWD_MXR5G__WRITE(src) \
71704 (((u_int32_t)(src)\
71706 #define RXRF_GAINSTAGES__PWD_MXR5G__MODIFY(dst, src) \
71708 ~0x00000200U) | (((u_int32_t)(src) <<\
71710 #define RXRF_GAINSTAGES__PWD_MXR5G__VERIFY(src) \
71711 (!((((u_int32_t)(src)\
71724 #define RXRF_GAINSTAGES__PWD_LNA5G__READ(src) \
71725 (((u_int32_t)(src)\
71727 #define RXRF_GAINSTAGES__PWD_LNA5G__WRITE(src) \
71728 (((u_int32_t)(src)\
71730 #define RXRF_GAINSTAGES__PWD_LNA5G__MODIFY(dst, src) \
71732 ~0x00000400U) | (((u_int32_t)(src) <<\
71734 #define RXRF_GAINSTAGES__PWD_LNA5G__VERIFY(src) \
71735 (!((((u_int32_t)(src)\
71748 #define RXRF_GAINSTAGES__LNA2G_CAP__READ(src) \
71749 (((u_int32_t)(src)\
71751 #define RXRF_GAINSTAGES__LNA2G_CAP__WRITE(src) \
71752 (((u_int32_t)(src)\
71754 #define RXRF_GAINSTAGES__LNA2G_CAP__MODIFY(dst, src) \
71756 ~0x00001800U) | (((u_int32_t)(src) <<\
71758 #define RXRF_GAINSTAGES__LNA2G_CAP__VERIFY(src) \
71759 (!((((u_int32_t)(src)\
71766 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__READ(src) \
71767 (((u_int32_t)(src)\
71769 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__WRITE(src) \
71770 (((u_int32_t)(src)\
71772 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__MODIFY(dst, src) \
71774 ~0x00002000U) | (((u_int32_t)(src) <<\
71776 #define RXRF_GAINSTAGES__LNA2G_SHORTINP__VERIFY(src) \
71777 (!((((u_int32_t)(src)\
71790 #define RXRF_GAINSTAGES__LNA2G_LP__READ(src) \
71791 (((u_int32_t)(src)\
71793 #define RXRF_GAINSTAGES__LNA2G_LP__WRITE(src) \
71794 (((u_int32_t)(src)\
71796 #define RXRF_GAINSTAGES__LNA2G_LP__MODIFY(dst, src) \
71798 ~0x00004000U) | (((u_int32_t)(src) <<\
71800 #define RXRF_GAINSTAGES__LNA2G_LP__VERIFY(src) \
71801 (!((((u_int32_t)(src)\
71814 #define RXRF_GAINSTAGES__PWD_LO2G__READ(src) \
71815 (((u_int32_t)(src)\
71817 #define RXRF_GAINSTAGES__PWD_LO2G__WRITE(src) \
71818 (((u_int32_t)(src)\
71820 #define RXRF_GAINSTAGES__PWD_LO2G__MODIFY(dst, src) \
71822 ~0x00008000U) | (((u_int32_t)(src) <<\
71824 #define RXRF_GAINSTAGES__PWD_LO2G__VERIFY(src) \
71825 (!((((u_int32_t)(src)\
71838 #define RXRF_GAINSTAGES__PWD_MXR2G__READ(src) \
71839 (((u_int32_t)(src)\
71841 #define RXRF_GAINSTAGES__PWD_MXR2G__WRITE(src) \
71842 (((u_int32_t)(src)\
71844 #define RXRF_GAINSTAGES__PWD_MXR2G__MODIFY(dst, src) \
71846 ~0x00010000U) | (((u_int32_t)(src) <<\
71848 #define RXRF_GAINSTAGES__PWD_MXR2G__VERIFY(src) \
71849 (!((((u_int32_t)(src)\
71862 #define RXRF_GAINSTAGES__PWD_LNA2G__READ(src) \
71863 (((u_int32_t)(src)\
71865 #define RXRF_GAINSTAGES__PWD_LNA2G__WRITE(src) \
71866 (((u_int32_t)(src)\
71868 #define RXRF_GAINSTAGES__PWD_LNA2G__MODIFY(dst, src) \
71870 ~0x00020000U) | (((u_int32_t)(src) <<\
71872 #define RXRF_GAINSTAGES__PWD_LNA2G__VERIFY(src) \
71873 (!((((u_int32_t)(src)\
71886 #define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__READ(src) \
71887 (((u_int32_t)(src)\
71889 #define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__WRITE(src) \
71890 (((u_int32_t)(src)\
71892 #define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__MODIFY(dst, src) \
71894 ~0x000c0000U) | (((u_int32_t)(src) <<\
71896 #define RXRF_GAINSTAGES__MXR5G_GAIN_OVR__VERIFY(src) \
71897 (!((((u_int32_t)(src)\
71904 #define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__READ(src) \
71905 (((u_int32_t)(src)\
71907 #define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__WRITE(src) \
71908 (((u_int32_t)(src)\
71910 #define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__MODIFY(dst, src) \
71912 ~0x00700000U) | (((u_int32_t)(src) <<\
71914 #define RXRF_GAINSTAGES__VGA5G_GAIN_OVR__VERIFY(src) \
71915 (!((((u_int32_t)(src)\
71922 #define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__READ(src) \
71923 (((u_int32_t)(src)\
71925 #define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__WRITE(src) \
71926 (((u_int32_t)(src)\
71928 #define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__MODIFY(dst, src) \
71930 ~0x03800000U) | (((u_int32_t)(src) <<\
71932 #define RXRF_GAINSTAGES__LNA5G_GAIN_OVR__VERIFY(src) \
71933 (!((((u_int32_t)(src)\
71940 #define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__READ(src) \
71941 (((u_int32_t)(src)\
71943 #define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__WRITE(src) \
71944 (((u_int32_t)(src)\
71946 #define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__MODIFY(dst, src) \
71948 ~0x0c000000U) | (((u_int32_t)(src) <<\
71950 #define RXRF_GAINSTAGES__MXR2G_GAIN_OVR__VERIFY(src) \
71951 (!((((u_int32_t)(src)\
71958 #define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__READ(src) \
71959 (((u_int32_t)(src)\
71961 #define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__WRITE(src) \
71962 (((u_int32_t)(src)\
71964 #define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__MODIFY(dst, src) \
71966 ~0x70000000U) | (((u_int32_t)(src) <<\
71968 #define RXRF_GAINSTAGES__LNA2G_GAIN_OVR__VERIFY(src) \
71969 (!((((u_int32_t)(src)\
71976 #define RXRF_GAINSTAGES__RX_OVERRIDE__READ(src) \
71977 (((u_int32_t)(src)\
71979 #define RXRF_GAINSTAGES__RX_OVERRIDE__WRITE(src) \
71980 (((u_int32_t)(src)\
71982 #define RXRF_GAINSTAGES__RX_OVERRIDE__MODIFY(dst, src) \
71984 ~0x80000000U) | (((u_int32_t)(src) <<\
71986 #define RXRF_GAINSTAGES__RX_OVERRIDE__VERIFY(src) \
71987 (!((((u_int32_t)(src)\
72013 #define RXRF_AGC__RF5G_ON_DURING_CALPA__READ(src) \
72014 (u_int32_t)(src)\
72016 #define RXRF_AGC__RF5G_ON_DURING_CALPA__WRITE(src) \
72017 ((u_int32_t)(src)\
72019 #define RXRF_AGC__RF5G_ON_DURING_CALPA__MODIFY(dst, src) \
72021 ~0x00000001U) | ((u_int32_t)(src) &\
72023 #define RXRF_AGC__RF5G_ON_DURING_CALPA__VERIFY(src) \
72024 (!(((u_int32_t)(src)\
72037 #define RXRF_AGC__RF2G_ON_DURING_CALPA__READ(src) \
72038 (((u_int32_t)(src)\
72040 #define RXRF_AGC__RF2G_ON_DURING_CALPA__WRITE(src) \
72041 (((u_int32_t)(src)\
72043 #define RXRF_AGC__RF2G_ON_DURING_CALPA__MODIFY(dst, src) \
72045 ~0x00000002U) | (((u_int32_t)(src) <<\
72047 #define RXRF_AGC__RF2G_ON_DURING_CALPA__VERIFY(src) \
72048 (!((((u_int32_t)(src)\
72061 #define RXRF_AGC__AGC_OUT__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
72073 #define RXRF_AGC__LNABUFGAIN2X__READ(src) \
72074 (((u_int32_t)(src)\
72076 #define RXRF_AGC__LNABUFGAIN2X__WRITE(src) \
72077 (((u_int32_t)(src)\
72079 #define RXRF_AGC__LNABUFGAIN2X__MODIFY(dst, src) \
72081 ~0x00000008U) | (((u_int32_t)(src) <<\
72083 #define RXRF_AGC__LNABUFGAIN2X__VERIFY(src) \
72084 (!((((u_int32_t)(src)\
72097 #define RXRF_AGC__LNABUF_PWD_OVR__READ(src) \
72098 (((u_int32_t)(src)\
72100 #define RXRF_AGC__LNABUF_PWD_OVR__WRITE(src) \
72101 (((u_int32_t)(src)\
72103 #define RXRF_AGC__LNABUF_PWD_OVR__MODIFY(dst, src) \
72105 ~0x00000010U) | (((u_int32_t)(src) <<\
72107 #define RXRF_AGC__LNABUF_PWD_OVR__VERIFY(src) \
72108 (!((((u_int32_t)(src)\
72121 #define RXRF_AGC__PWD_LNABUF__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
72122 #define RXRF_AGC__PWD_LNABUF__WRITE(src) \
72123 (((u_int32_t)(src)\
72125 #define RXRF_AGC__PWD_LNABUF__MODIFY(dst, src) \
72127 ~0x00000020U) | (((u_int32_t)(src) <<\
72129 #define RXRF_AGC__PWD_LNABUF__VERIFY(src) \
72130 (!((((u_int32_t)(src)\
72143 #define RXRF_AGC__AGC_FALL_CTRL__READ(src) \
72144 (((u_int32_t)(src)\
72146 #define RXRF_AGC__AGC_FALL_CTRL__WRITE(src) \
72147 (((u_int32_t)(src)\
72149 #define RXRF_AGC__AGC_FALL_CTRL__MODIFY(dst, src) \
72151 ~0x000001c0U) | (((u_int32_t)(src) <<\
72153 #define RXRF_AGC__AGC_FALL_CTRL__VERIFY(src) \
72154 (!((((u_int32_t)(src)\
72161 #define RXRF_AGC__AGC5G_CALDAC_OVR__READ(src) \
72162 (((u_int32_t)(src)\
72164 #define RXRF_AGC__AGC5G_CALDAC_OVR__WRITE(src) \
72165 (((u_int32_t)(src)\
72167 #define RXRF_AGC__AGC5G_CALDAC_OVR__MODIFY(dst, src) \
72169 ~0x00007e00U) | (((u_int32_t)(src) <<\
72171 #define RXRF_AGC__AGC5G_CALDAC_OVR__VERIFY(src) \
72172 (!((((u_int32_t)(src)\
72179 #define RXRF_AGC__AGC5G_DBDAC_OVR__READ(src) \
72180 (((u_int32_t)(src)\
72182 #define RXRF_AGC__AGC5G_DBDAC_OVR__WRITE(src) \
72183 (((u_int32_t)(src)\
72185 #define RXRF_AGC__AGC5G_DBDAC_OVR__MODIFY(dst, src) \
72187 ~0x00078000U) | (((u_int32_t)(src) <<\
72189 #define RXRF_AGC__AGC5G_DBDAC_OVR__VERIFY(src) \
72190 (!((((u_int32_t)(src)\
72197 #define RXRF_AGC__AGC2G_CALDAC_OVR__READ(src) \
72198 (((u_int32_t)(src)\
72200 #define RXRF_AGC__AGC2G_CALDAC_OVR__WRITE(src) \
72201 (((u_int32_t)(src)\
72203 #define RXRF_AGC__AGC2G_CALDAC_OVR__MODIFY(dst, src) \
72205 ~0x01f80000U) | (((u_int32_t)(src) <<\
72207 #define RXRF_AGC__AGC2G_CALDAC_OVR__VERIFY(src) \
72208 (!((((u_int32_t)(src)\
72215 #define RXRF_AGC__AGC2G_DBDAC_OVR__READ(src) \
72216 (((u_int32_t)(src)\
72218 #define RXRF_AGC__AGC2G_DBDAC_OVR__WRITE(src) \
72219 (((u_int32_t)(src)\
72221 #define RXRF_AGC__AGC2G_DBDAC_OVR__MODIFY(dst, src) \
72223 ~0x1e000000U) | (((u_int32_t)(src) <<\
72225 #define RXRF_AGC__AGC2G_DBDAC_OVR__VERIFY(src) \
72226 (!((((u_int32_t)(src)\
72233 #define RXRF_AGC__AGC_CAL_OVR__READ(src) \
72234 (((u_int32_t)(src)\
72236 #define RXRF_AGC__AGC_CAL_OVR__WRITE(src) \
72237 (((u_int32_t)(src)\
72239 #define RXRF_AGC__AGC_CAL_OVR__MODIFY(dst, src) \
72241 ~0x20000000U) | (((u_int32_t)(src) <<\
72243 #define RXRF_AGC__AGC_CAL_OVR__VERIFY(src) \
72244 (!((((u_int32_t)(src)\
72257 #define RXRF_AGC__AGC_ON_OVR__READ(src) \
72258 (((u_int32_t)(src)\
72260 #define RXRF_AGC__AGC_ON_OVR__WRITE(src) \
72261 (((u_int32_t)(src)\
72263 #define RXRF_AGC__AGC_ON_OVR__MODIFY(dst, src) \
72265 ~0x40000000U) | (((u_int32_t)(src) <<\
72267 #define RXRF_AGC__AGC_ON_OVR__VERIFY(src) \
72268 (!((((u_int32_t)(src)\
72281 #define RXRF_AGC__AGC_OVERRIDE__READ(src) \
72282 (((u_int32_t)(src)\
72284 #define RXRF_AGC__AGC_OVERRIDE__WRITE(src) \
72285 (((u_int32_t)(src)\
72287 #define RXRF_AGC__AGC_OVERRIDE__MODIFY(dst, src) \
72289 ~0x80000000U) | (((u_int32_t)(src) <<\
72291 #define RXRF_AGC__AGC_OVERRIDE__VERIFY(src) \
72292 (!((((u_int32_t)(src)\
72318 #define TXRF1__PDLOBUF5G__READ(src) (u_int32_t)(src) & 0x00000001U
72319 #define TXRF1__PDLOBUF5G__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
72320 #define TXRF1__PDLOBUF5G__MODIFY(dst, src) \
72322 ~0x00000001U) | ((u_int32_t)(src) &\
72324 #define TXRF1__PDLOBUF5G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
72336 #define TXRF1__PDLODIV5G__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
72337 #define TXRF1__PDLODIV5G__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
72338 #define TXRF1__PDLODIV5G__MODIFY(dst, src) \
72340 ~0x00000002U) | (((u_int32_t)(src) <<\
72342 #define TXRF1__PDLODIV5G__VERIFY(src) \
72343 (!((((u_int32_t)(src)\
72356 #define TXRF1__LOBUF5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
72357 #define TXRF1__LOBUF5GFORCED__WRITE(src) \
72358 (((u_int32_t)(src)\
72360 #define TXRF1__LOBUF5GFORCED__MODIFY(dst, src) \
72362 ~0x00000004U) | (((u_int32_t)(src) <<\
72364 #define TXRF1__LOBUF5GFORCED__VERIFY(src) \
72365 (!((((u_int32_t)(src)\
72378 #define TXRF1__LODIV5GFORCED__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
72379 #define TXRF1__LODIV5GFORCED__WRITE(src) \
72380 (((u_int32_t)(src)\
72382 #define TXRF1__LODIV5GFORCED__MODIFY(dst, src) \
72384 ~0x00000008U) | (((u_int32_t)(src) <<\
72386 #define TXRF1__LODIV5GFORCED__VERIFY(src) \
72387 (!((((u_int32_t)(src)\
72400 #define TXRF1__PADRV2GN5G__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4)
72401 #define TXRF1__PADRV2GN5G__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U)
72402 #define TXRF1__PADRV2GN5G__MODIFY(dst, src) \
72404 ~0x000000f0U) | (((u_int32_t)(src) <<\
72406 #define TXRF1__PADRV2GN5G__VERIFY(src) \
72407 (!((((u_int32_t)(src)\
72414 #define TXRF1__PADRV3GN5G__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8)
72415 #define TXRF1__PADRV3GN5G__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U)
72416 #define TXRF1__PADRV3GN5G__MODIFY(dst, src) \
72418 ~0x00000f00U) | (((u_int32_t)(src) <<\
72420 #define TXRF1__PADRV3GN5G__VERIFY(src) \
72421 (!((((u_int32_t)(src)\
72428 #define TXRF1__PADRV4GN5G__READ(src) (((u_int32_t)(src) & 0x0000f000U) >> 12)
72429 #define TXRF1__PADRV4GN5G__WRITE(src) (((u_int32_t)(src) << 12) & 0x0000f000U)
72430 #define TXRF1__PADRV4GN5G__MODIFY(dst, src) \
72432 ~0x0000f000U) | (((u_int32_t)(src) <<\
72434 #define TXRF1__PADRV4GN5G__VERIFY(src) \
72435 (!((((u_int32_t)(src)\
72442 #define TXRF1__LOCALTXGAIN5G__READ(src) \
72443 (((u_int32_t)(src)\
72445 #define TXRF1__LOCALTXGAIN5G__WRITE(src) \
72446 (((u_int32_t)(src)\
72448 #define TXRF1__LOCALTXGAIN5G__MODIFY(dst, src) \
72450 ~0x00010000U) | (((u_int32_t)(src) <<\
72452 #define TXRF1__LOCALTXGAIN5G__VERIFY(src) \
72453 (!((((u_int32_t)(src)\
72466 #define TXRF1__PDOUT2G__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17)
72467 #define TXRF1__PDOUT2G__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U)
72468 #define TXRF1__PDOUT2G__MODIFY(dst, src) \
72470 ~0x00020000U) | (((u_int32_t)(src) <<\
72472 #define TXRF1__PDOUT2G__VERIFY(src) \
72473 (!((((u_int32_t)(src)\
72486 #define TXRF1__PDDR2G__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18)
72487 #define TXRF1__PDDR2G__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U)
72488 #define TXRF1__PDDR2G__MODIFY(dst, src) \
72490 ~0x00040000U) | (((u_int32_t)(src) <<\
72492 #define TXRF1__PDDR2G__VERIFY(src) \
72493 (!((((u_int32_t)(src)\
72506 #define TXRF1__PDMXR2G__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19)
72507 #define TXRF1__PDMXR2G__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U)
72508 #define TXRF1__PDMXR2G__MODIFY(dst, src) \
72510 ~0x00080000U) | (((u_int32_t)(src) <<\
72512 #define TXRF1__PDMXR2G__VERIFY(src) \
72513 (!((((u_int32_t)(src)\
72526 #define TXRF1__PDLOBUF2G__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20)
72527 #define TXRF1__PDLOBUF2G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U)
72528 #define TXRF1__PDLOBUF2G__MODIFY(dst, src) \
72530 ~0x00100000U) | (((u_int32_t)(src) <<\
72532 #define TXRF1__PDLOBUF2G__VERIFY(src) \
72533 (!((((u_int32_t)(src)\
72546 #define TXRF1__PDLODIV2G__READ(src) (((u_int32_t)(src) & 0x00200000U) >> 21)
72547 #define TXRF1__PDLODIV2G__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U)
72548 #define TXRF1__PDLODIV2G__MODIFY(dst, src) \
72550 ~0x00200000U) | (((u_int32_t)(src) <<\
72552 #define TXRF1__PDLODIV2G__VERIFY(src) \
72553 (!((((u_int32_t)(src)\
72566 #define TXRF1__LOBUF2GFORCED__READ(src) \
72567 (((u_int32_t)(src)\
72569 #define TXRF1__LOBUF2GFORCED__WRITE(src) \
72570 (((u_int32_t)(src)\
72572 #define TXRF1__LOBUF2GFORCED__MODIFY(dst, src) \
72574 ~0x00400000U) | (((u_int32_t)(src) <<\
72576 #define TXRF1__LOBUF2GFORCED__VERIFY(src) \
72577 (!((((u_int32_t)(src)\
72590 #define TXRF1__LODIV2GFORCED__READ(src) \
72591 (((u_int32_t)(src)\
72593 #define TXRF1__LODIV2GFORCED__WRITE(src) \
72594 (((u_int32_t)(src)\
72596 #define TXRF1__LODIV2GFORCED__MODIFY(dst, src) \
72598 ~0x00800000U) | (((u_int32_t)(src) <<\
72600 #define TXRF1__LODIV2GFORCED__VERIFY(src) \
72601 (!((((u_int32_t)(src)\
72614 #define TXRF1__PADRVGN2G__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24)
72615 #define TXRF1__PADRVGN2G__WRITE(src) (((u_int32_t)(src) << 24) & 0x7f000000U)
72616 #define TXRF1__PADRVGN2G__MODIFY(dst, src) \
72618 ~0x7f000000U) | (((u_int32_t)(src) <<\
72620 #define TXRF1__PADRVGN2G__VERIFY(src) \
72621 (!((((u_int32_t)(src)\
72628 #define TXRF1__LOCALTXGAIN2G__READ(src) \
72629 (((u_int32_t)(src)\
72631 #define TXRF1__LOCALTXGAIN2G__WRITE(src) \
72632 (((u_int32_t)(src)\
72634 #define TXRF1__LOCALTXGAIN2G__MODIFY(dst, src) \
72636 ~0x80000000U) | (((u_int32_t)(src) <<\
72638 #define TXRF1__LOCALTXGAIN2G__VERIFY(src) \
72639 (!((((u_int32_t)(src)\
72665 #define TXRF2__D3B5G__READ(src) (u_int32_t)(src) & 0x00000007U
72666 #define TXRF2__D3B5G__WRITE(src) ((u_int32_t)(src) & 0x00000007U)
72667 #define TXRF2__D3B5G__MODIFY(dst, src) \
72669 ~0x00000007U) | ((u_int32_t)(src) &\
72671 #define TXRF2__D3B5G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U)))
72677 #define TXRF2__D4B5G__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3)
72678 #define TXRF2__D4B5G__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000038U)
72679 #define TXRF2__D4B5G__MODIFY(dst, src) \
72681 ~0x00000038U) | (((u_int32_t)(src) <<\
72683 #define TXRF2__D4B5G__VERIFY(src) (!((((u_int32_t)(src) << 3) & ~0x00000038U)))
72689 #define TXRF2__OCAS2G__READ(src) (((u_int32_t)(src) & 0x000001c0U) >> 6)
72690 #define TXRF2__OCAS2G__WRITE(src) (((u_int32_t)(src) << 6) & 0x000001c0U)
72691 #define TXRF2__OCAS2G__MODIFY(dst, src) \
72693 ~0x000001c0U) | (((u_int32_t)(src) <<\
72695 #define TXRF2__OCAS2G__VERIFY(src) \
72696 (!((((u_int32_t)(src)\
72703 #define TXRF2__DCAS2G__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9)
72704 #define TXRF2__DCAS2G__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U)
72705 #define TXRF2__DCAS2G__MODIFY(dst, src) \
72707 ~0x00000e00U) | (((u_int32_t)(src) <<\
72709 #define TXRF2__DCAS2G__VERIFY(src) \
72710 (!((((u_int32_t)(src)\
72717 #define TXRF2__OB2G_PALOFF__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12)
72718 #define TXRF2__OB2G_PALOFF__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U)
72719 #define TXRF2__OB2G_PALOFF__MODIFY(dst, src) \
72721 ~0x00007000U) | (((u_int32_t)(src) <<\
72723 #define TXRF2__OB2G_PALOFF__VERIFY(src) \
72724 (!((((u_int32_t)(src)\
72731 #define TXRF2__OB2G_QAM__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15)
72732 #define TXRF2__OB2G_QAM__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U)
72733 #define TXRF2__OB2G_QAM__MODIFY(dst, src) \
72735 ~0x00038000U) | (((u_int32_t)(src) <<\
72737 #define TXRF2__OB2G_QAM__VERIFY(src) \
72738 (!((((u_int32_t)(src)\
72745 #define TXRF2__OB2G_PSK__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18)
72746 #define TXRF2__OB2G_PSK__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U)
72747 #define TXRF2__OB2G_PSK__MODIFY(dst, src) \
72749 ~0x001c0000U) | (((u_int32_t)(src) <<\
72751 #define TXRF2__OB2G_PSK__VERIFY(src) \
72752 (!((((u_int32_t)(src)\
72759 #define TXRF2__OB2G_CCK__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21)
72760 #define TXRF2__OB2G_CCK__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U)
72761 #define TXRF2__OB2G_CCK__MODIFY(dst, src) \
72763 ~0x00e00000U) | (((u_int32_t)(src) <<\
72765 #define TXRF2__OB2G_CCK__VERIFY(src) \
72766 (!((((u_int32_t)(src)\
72773 #define TXRF2__DB2G__READ(src) (((u_int32_t)(src) & 0x07000000U) >> 24)
72774 #define TXRF2__DB2G__WRITE(src) (((u_int32_t)(src) << 24) & 0x07000000U)
72775 #define TXRF2__DB2G__MODIFY(dst, src) \
72777 ~0x07000000U) | (((u_int32_t)(src) <<\
72779 #define TXRF2__DB2G__VERIFY(src) (!((((u_int32_t)(src) << 24) & ~0x07000000U)))
72785 #define TXRF2__PDOUT5G__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27)
72786 #define TXRF2__PDOUT5G__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U)
72787 #define TXRF2__PDOUT5G__MODIFY(dst, src) \
72789 ~0x78000000U) | (((u_int32_t)(src) <<\
72791 #define TXRF2__PDOUT5G__VERIFY(src) \
72792 (!((((u_int32_t)(src)\
72799 #define TXRF2__PDMXR5G__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
72800 #define TXRF2__PDMXR5G__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U)
72801 #define TXRF2__PDMXR5G__MODIFY(dst, src) \
72803 ~0x80000000U) | (((u_int32_t)(src) <<\
72805 #define TXRF2__PDMXR5G__VERIFY(src) \
72806 (!((((u_int32_t)(src)\
72832 #define TXRF3__FILTR2G__READ(src) (u_int32_t)(src) & 0x00000003U
72833 #define TXRF3__FILTR2G__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
72834 #define TXRF3__FILTR2G__MODIFY(dst, src) \
72836 ~0x00000003U) | ((u_int32_t)(src) &\
72838 #define TXRF3__FILTR2G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
72844 #define TXRF3__PWDFB2_2G__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
72845 #define TXRF3__PWDFB2_2G__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
72846 #define TXRF3__PWDFB2_2G__MODIFY(dst, src) \
72848 ~0x00000004U) | (((u_int32_t)(src) <<\
72850 #define TXRF3__PWDFB2_2G__VERIFY(src) \
72851 (!((((u_int32_t)(src)\
72864 #define TXRF3__PWDFB1_2G__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
72865 #define TXRF3__PWDFB1_2G__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U)
72866 #define TXRF3__PWDFB1_2G__MODIFY(dst, src) \
72868 ~0x00000008U) | (((u_int32_t)(src) <<\
72870 #define TXRF3__PWDFB1_2G__VERIFY(src) \
72871 (!((((u_int32_t)(src)\
72884 #define TXRF3__PDFB2G__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4)
72885 #define TXRF3__PDFB2G__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U)
72886 #define TXRF3__PDFB2G__MODIFY(dst, src) \
72888 ~0x00000010U) | (((u_int32_t)(src) <<\
72890 #define TXRF3__PDFB2G__VERIFY(src) \
72891 (!((((u_int32_t)(src)\
72904 #define TXRF3__RDIV5G__READ(src) (((u_int32_t)(src) & 0x00000060U) >> 5)
72905 #define TXRF3__RDIV5G__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000060U)
72906 #define TXRF3__RDIV5G__MODIFY(dst, src) \
72908 ~0x00000060U) | (((u_int32_t)(src) <<\
72910 #define TXRF3__RDIV5G__VERIFY(src) \
72911 (!((((u_int32_t)(src)\
72918 #define TXRF3__CAPDIV5G__READ(src) (((u_int32_t)(src) & 0x00000380U) >> 7)
72919 #define TXRF3__CAPDIV5G__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000380U)
72920 #define TXRF3__CAPDIV5G__MODIFY(dst, src) \
72922 ~0x00000380U) | (((u_int32_t)(src) <<\
72924 #define TXRF3__CAPDIV5G__VERIFY(src) \
72925 (!((((u_int32_t)(src)\
72932 #define TXRF3__PDPREDIST5G__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
72933 #define TXRF3__PDPREDIST5G__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U)
72934 #define TXRF3__PDPREDIST5G__MODIFY(dst, src) \
72936 ~0x00000400U) | (((u_int32_t)(src) <<\
72938 #define TXRF3__PDPREDIST5G__VERIFY(src) \
72939 (!((((u_int32_t)(src)\
72952 #define TXRF3__RDIV2G__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11)
72953 #define TXRF3__RDIV2G__WRITE(src) (((u_int32_t)(src) << 11) & 0x00001800U)
72954 #define TXRF3__RDIV2G__MODIFY(dst, src) \
72956 ~0x00001800U) | (((u_int32_t)(src) <<\
72958 #define TXRF3__RDIV2G__VERIFY(src) \
72959 (!((((u_int32_t)(src)\
72966 #define TXRF3__PDPREDIST2G__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13)
72967 #define TXRF3__PDPREDIST2G__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U)
72968 #define TXRF3__PDPREDIST2G__MODIFY(dst, src) \
72970 ~0x00002000U) | (((u_int32_t)(src) <<\
72972 #define TXRF3__PDPREDIST2G__VERIFY(src) \
72973 (!((((u_int32_t)(src)\
72986 #define TXRF3__OCAS5G__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14)
72987 #define TXRF3__OCAS5G__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U)
72988 #define TXRF3__OCAS5G__MODIFY(dst, src) \
72990 ~0x0001c000U) | (((u_int32_t)(src) <<\
72992 #define TXRF3__OCAS5G__VERIFY(src) \
72993 (!((((u_int32_t)(src)\
73000 #define TXRF3__D2CAS5G__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17)
73001 #define TXRF3__D2CAS5G__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U)
73002 #define TXRF3__D2CAS5G__MODIFY(dst, src) \
73004 ~0x000e0000U) | (((u_int32_t)(src) <<\
73006 #define TXRF3__D2CAS5G__VERIFY(src) \
73007 (!((((u_int32_t)(src)\
73014 #define TXRF3__D3CAS5G__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20)
73015 #define TXRF3__D3CAS5G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U)
73016 #define TXRF3__D3CAS5G__MODIFY(dst, src) \
73018 ~0x00700000U) | (((u_int32_t)(src) <<\
73020 #define TXRF3__D3CAS5G__VERIFY(src) \
73021 (!((((u_int32_t)(src)\
73028 #define TXRF3__D4CAS5G__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23)
73029 #define TXRF3__D4CAS5G__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U)
73030 #define TXRF3__D4CAS5G__MODIFY(dst, src) \
73032 ~0x03800000U) | (((u_int32_t)(src) <<\
73034 #define TXRF3__D4CAS5G__VERIFY(src) \
73035 (!((((u_int32_t)(src)\
73042 #define TXRF3__OB5G__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26)
73043 #define TXRF3__OB5G__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U)
73044 #define TXRF3__OB5G__MODIFY(dst, src) \
73046 ~0x1c000000U) | (((u_int32_t)(src) <<\
73048 #define TXRF3__OB5G__VERIFY(src) (!((((u_int32_t)(src) << 26) & ~0x1c000000U)))
73054 #define TXRF3__D2B5G__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29)
73055 #define TXRF3__D2B5G__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U)
73056 #define TXRF3__D2B5G__MODIFY(dst, src) \
73058 ~0xe0000000U) | (((u_int32_t)(src) <<\
73060 #define TXRF3__D2B5G__VERIFY(src) \
73061 (!((((u_int32_t)(src)\
73081 #define TXRF4__PK1B2G_CCK__READ(src) (u_int32_t)(src) & 0x00000003U
73082 #define TXRF4__PK1B2G_CCK__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
73083 #define TXRF4__PK1B2G_CCK__MODIFY(dst, src) \
73085 ~0x00000003U) | ((u_int32_t)(src) &\
73087 #define TXRF4__PK1B2G_CCK__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
73093 #define TXRF4__MIOB2G_QAM__READ(src) (((u_int32_t)(src) & 0x0000001cU) >> 2)
73094 #define TXRF4__MIOB2G_QAM__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000001cU)
73095 #define TXRF4__MIOB2G_QAM__MODIFY(dst, src) \
73097 ~0x0000001cU) | (((u_int32_t)(src) <<\
73099 #define TXRF4__MIOB2G_QAM__VERIFY(src) \
73100 (!((((u_int32_t)(src)\
73107 #define TXRF4__MIOB2G_PSK__READ(src) (((u_int32_t)(src) & 0x000000e0U) >> 5)
73108 #define TXRF4__MIOB2G_PSK__WRITE(src) (((u_int32_t)(src) << 5) & 0x000000e0U)
73109 #define TXRF4__MIOB2G_PSK__MODIFY(dst, src) \
73111 ~0x000000e0U) | (((u_int32_t)(src) <<\
73113 #define TXRF4__MIOB2G_PSK__VERIFY(src) \
73114 (!((((u_int32_t)(src)\
73121 #define TXRF4__MIOB2G_CCK__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8)
73122 #define TXRF4__MIOB2G_CCK__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U)
73123 #define TXRF4__MIOB2G_CCK__MODIFY(dst, src) \
73125 ~0x00000700U) | (((u_int32_t)(src) <<\
73127 #define TXRF4__MIOB2G_CCK__VERIFY(src) \
73128 (!((((u_int32_t)(src)\
73135 #define TXRF4__COMP2G_QAM__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11)
73136 #define TXRF4__COMP2G_QAM__WRITE(src) (((u_int32_t)(src) << 11) & 0x00003800U)
73137 #define TXRF4__COMP2G_QAM__MODIFY(dst, src) \
73139 ~0x00003800U) | (((u_int32_t)(src) <<\
73141 #define TXRF4__COMP2G_QAM__VERIFY(src) \
73142 (!((((u_int32_t)(src)\
73149 #define TXRF4__COMP2G_PSK__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14)
73150 #define TXRF4__COMP2G_PSK__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U)
73151 #define TXRF4__COMP2G_PSK__MODIFY(dst, src) \
73153 ~0x0001c000U) | (((u_int32_t)(src) <<\
73155 #define TXRF4__COMP2G_PSK__VERIFY(src) \
73156 (!((((u_int32_t)(src)\
73163 #define TXRF4__COMP2G_CCK__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17)
73164 #define TXRF4__COMP2G_CCK__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U)
73165 #define TXRF4__COMP2G_CCK__MODIFY(dst, src) \
73167 ~0x000e0000U) | (((u_int32_t)(src) <<\
73169 #define TXRF4__COMP2G_CCK__VERIFY(src) \
73170 (!((((u_int32_t)(src)\
73177 #define TXRF4__AMP2B2G_QAM__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20)
73178 #define TXRF4__AMP2B2G_QAM__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U)
73179 #define TXRF4__AMP2B2G_QAM__MODIFY(dst, src) \
73181 ~0x00700000U) | (((u_int32_t)(src) <<\
73183 #define TXRF4__AMP2B2G_QAM__VERIFY(src) \
73184 (!((((u_int32_t)(src)\
73191 #define TXRF4__AMP2B2G_PSK__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23)
73192 #define TXRF4__AMP2B2G_PSK__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U)
73193 #define TXRF4__AMP2B2G_PSK__MODIFY(dst, src) \
73195 ~0x03800000U) | (((u_int32_t)(src) <<\
73197 #define TXRF4__AMP2B2G_PSK__VERIFY(src) \
73198 (!((((u_int32_t)(src)\
73205 #define TXRF4__AMP2B2G_CCK__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26)
73206 #define TXRF4__AMP2B2G_CCK__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U)
73207 #define TXRF4__AMP2B2G_CCK__MODIFY(dst, src) \
73209 ~0x1c000000U) | (((u_int32_t)(src) <<\
73211 #define TXRF4__AMP2B2G_CCK__VERIFY(src) \
73212 (!((((u_int32_t)(src)\
73219 #define TXRF4__AMP2CAS2G__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29)
73220 #define TXRF4__AMP2CAS2G__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U)
73221 #define TXRF4__AMP2CAS2G__MODIFY(dst, src) \
73223 ~0xe0000000U) | (((u_int32_t)(src) <<\
73225 #define TXRF4__AMP2CAS2G__VERIFY(src) \
73226 (!((((u_int32_t)(src)\
73246 #define TXRF5__TXMODPALONLY__READ(src) (u_int32_t)(src) & 0x00000001U
73247 #define TXRF5__TXMODPALONLY__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
73248 #define TXRF5__TXMODPALONLY__MODIFY(dst, src) \
73250 ~0x00000001U) | ((u_int32_t)(src) &\
73252 #define TXRF5__TXMODPALONLY__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
73264 #define TXRF5__PAL_LOCKED__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
73276 #define TXRF5__FBHI2G__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
73288 #define TXRF5__FBLO2G__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
73300 #define TXRF5__NOPALGAIN2G__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4)
73301 #define TXRF5__NOPALGAIN2G__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U)
73302 #define TXRF5__NOPALGAIN2G__MODIFY(dst, src) \
73304 ~0x00000010U) | (((u_int32_t)(src) <<\
73306 #define TXRF5__NOPALGAIN2G__VERIFY(src) \
73307 (!((((u_int32_t)(src)\
73320 #define TXRF5__ENPACAL2G__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
73321 #define TXRF5__ENPACAL2G__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
73322 #define TXRF5__ENPACAL2G__MODIFY(dst, src) \
73324 ~0x00000020U) | (((u_int32_t)(src) <<\
73326 #define TXRF5__ENPACAL2G__VERIFY(src) \
73327 (!((((u_int32_t)(src)\
73340 #define TXRF5__OFFSET2G__READ(src) (((u_int32_t)(src) & 0x00001fc0U) >> 6)
73341 #define TXRF5__OFFSET2G__WRITE(src) (((u_int32_t)(src) << 6) & 0x00001fc0U)
73342 #define TXRF5__OFFSET2G__MODIFY(dst, src) \
73344 ~0x00001fc0U) | (((u_int32_t)(src) <<\
73346 #define TXRF5__OFFSET2G__VERIFY(src) \
73347 (!((((u_int32_t)(src)\
73354 #define TXRF5__ENOFFSETCAL2G__READ(src) \
73355 (((u_int32_t)(src)\
73357 #define TXRF5__ENOFFSETCAL2G__WRITE(src) \
73358 (((u_int32_t)(src)\
73360 #define TXRF5__ENOFFSETCAL2G__MODIFY(dst, src) \
73362 ~0x00002000U) | (((u_int32_t)(src) <<\
73364 #define TXRF5__ENOFFSETCAL2G__VERIFY(src) \
73365 (!((((u_int32_t)(src)\
73378 #define TXRF5__REFHI2G__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14)
73379 #define TXRF5__REFHI2G__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U)
73380 #define TXRF5__REFHI2G__MODIFY(dst, src) \
73382 ~0x0001c000U) | (((u_int32_t)(src) <<\
73384 #define TXRF5__REFHI2G__VERIFY(src) \
73385 (!((((u_int32_t)(src)\
73392 #define TXRF5__REFLO2G__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17)
73393 #define TXRF5__REFLO2G__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U)
73394 #define TXRF5__REFLO2G__MODIFY(dst, src) \
73396 ~0x000e0000U) | (((u_int32_t)(src) <<\
73398 #define TXRF5__REFLO2G__VERIFY(src) \
73399 (!((((u_int32_t)(src)\
73406 #define TXRF5__PALCLAMP2G__READ(src) (((u_int32_t)(src) & 0x00300000U) >> 20)
73407 #define TXRF5__PALCLAMP2G__WRITE(src) (((u_int32_t)(src) << 20) & 0x00300000U)
73408 #define TXRF5__PALCLAMP2G__MODIFY(dst, src) \
73410 ~0x00300000U) | (((u_int32_t)(src) <<\
73412 #define TXRF5__PALCLAMP2G__VERIFY(src) \
73413 (!((((u_int32_t)(src)\
73420 #define TXRF5__PK2B2G_QAM__READ(src) (((u_int32_t)(src) & 0x00c00000U) >> 22)
73421 #define TXRF5__PK2B2G_QAM__WRITE(src) (((u_int32_t)(src) << 22) & 0x00c00000U)
73422 #define TXRF5__PK2B2G_QAM__MODIFY(dst, src) \
73424 ~0x00c00000U) | (((u_int32_t)(src) <<\
73426 #define TXRF5__PK2B2G_QAM__VERIFY(src) \
73427 (!((((u_int32_t)(src)\
73434 #define TXRF5__PK2B2G_PSK__READ(src) (((u_int32_t)(src) & 0x03000000U) >> 24)
73435 #define TXRF5__PK2B2G_PSK__WRITE(src) (((u_int32_t)(src) << 24) & 0x03000000U)
73436 #define TXRF5__PK2B2G_PSK__MODIFY(dst, src) \
73438 ~0x03000000U) | (((u_int32_t)(src) <<\
73440 #define TXRF5__PK2B2G_PSK__VERIFY(src) \
73441 (!((((u_int32_t)(src)\
73448 #define TXRF5__PK2B2G_CCK__READ(src) (((u_int32_t)(src) & 0x0c000000U) >> 26)
73449 #define TXRF5__PK2B2G_CCK__WRITE(src) (((u_int32_t)(src) << 26) & 0x0c000000U)
73450 #define TXRF5__PK2B2G_CCK__MODIFY(dst, src) \
73452 ~0x0c000000U) | (((u_int32_t)(src) <<\
73454 #define TXRF5__PK2B2G_CCK__VERIFY(src) \
73455 (!((((u_int32_t)(src)\
73462 #define TXRF5__PK1B2G_QAM__READ(src) (((u_int32_t)(src) & 0x30000000U) >> 28)
73463 #define TXRF5__PK1B2G_QAM__WRITE(src) (((u_int32_t)(src) << 28) & 0x30000000U)
73464 #define TXRF5__PK1B2G_QAM__MODIFY(dst, src) \
73466 ~0x30000000U) | (((u_int32_t)(src) <<\
73468 #define TXRF5__PK1B2G_QAM__VERIFY(src) \
73469 (!((((u_int32_t)(src)\
73476 #define TXRF5__PK1B2G_PSK__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30)
73477 #define TXRF5__PK1B2G_PSK__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U)
73478 #define TXRF5__PK1B2G_PSK__MODIFY(dst, src) \
73480 ~0xc0000000U) | (((u_int32_t)(src) <<\
73482 #define TXRF5__PK1B2G_PSK__VERIFY(src) \
73483 (!((((u_int32_t)(src)\
73503 #define TXRF6__PALCLKGATE2G__READ(src) (u_int32_t)(src) & 0x00000001U
73504 #define TXRF6__PALCLKGATE2G__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
73505 #define TXRF6__PALCLKGATE2G__MODIFY(dst, src) \
73507 ~0x00000001U) | ((u_int32_t)(src) &\
73509 #define TXRF6__PALCLKGATE2G__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
73521 #define TXRF6__PALFLUCTCOUNT2G__READ(src) \
73522 (((u_int32_t)(src)\
73524 #define TXRF6__PALFLUCTCOUNT2G__WRITE(src) \
73525 (((u_int32_t)(src)\
73527 #define TXRF6__PALFLUCTCOUNT2G__MODIFY(dst, src) \
73529 ~0x000001feU) | (((u_int32_t)(src) <<\
73531 #define TXRF6__PALFLUCTCOUNT2G__VERIFY(src) \
73532 (!((((u_int32_t)(src)\
73539 #define TXRF6__PALFLUCTGAIN2G__READ(src) \
73540 (((u_int32_t)(src)\
73542 #define TXRF6__PALFLUCTGAIN2G__WRITE(src) \
73543 (((u_int32_t)(src)\
73545 #define TXRF6__PALFLUCTGAIN2G__MODIFY(dst, src) \
73547 ~0x00000600U) | (((u_int32_t)(src) <<\
73549 #define TXRF6__PALFLUCTGAIN2G__VERIFY(src) \
73550 (!((((u_int32_t)(src)\
73557 #define TXRF6__PALNOFLUCT2G__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
73558 #define TXRF6__PALNOFLUCT2G__WRITE(src) \
73559 (((u_int32_t)(src)\
73561 #define TXRF6__PALNOFLUCT2G__MODIFY(dst, src) \
73563 ~0x00000800U) | (((u_int32_t)(src) <<\
73565 #define TXRF6__PALNOFLUCT2G__VERIFY(src) \
73566 (!((((u_int32_t)(src)\
73579 #define TXRF6__GAINSTEP2G__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12)
73580 #define TXRF6__GAINSTEP2G__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U)
73581 #define TXRF6__GAINSTEP2G__MODIFY(dst, src) \
73583 ~0x00007000U) | (((u_int32_t)(src) <<\
73585 #define TXRF6__GAINSTEP2G__VERIFY(src) \
73586 (!((((u_int32_t)(src)\
73593 #define TXRF6__USE_GAIN_DELTA2G__READ(src) \
73594 (((u_int32_t)(src)\
73596 #define TXRF6__USE_GAIN_DELTA2G__WRITE(src) \
73597 (((u_int32_t)(src)\
73599 #define TXRF6__USE_GAIN_DELTA2G__MODIFY(dst, src) \
73601 ~0x00008000U) | (((u_int32_t)(src) <<\
73603 #define TXRF6__USE_GAIN_DELTA2G__VERIFY(src) \
73604 (!((((u_int32_t)(src)\
73617 #define TXRF6__CAPDIV_I2G__READ(src) (((u_int32_t)(src) & 0x000f0000U) >> 16)
73618 #define TXRF6__CAPDIV_I2G__WRITE(src) (((u_int32_t)(src) << 16) & 0x000f0000U)
73619 #define TXRF6__CAPDIV_I2G__MODIFY(dst, src) \
73621 ~0x000f0000U) | (((u_int32_t)(src) <<\
73623 #define TXRF6__CAPDIV_I2G__VERIFY(src) \
73624 (!((((u_int32_t)(src)\
73631 #define TXRF6__PADRVGN_INDEX_I2G__READ(src) \
73632 (((u_int32_t)(src)\
73634 #define TXRF6__PADRVGN_INDEX_I2G__WRITE(src) \
73635 (((u_int32_t)(src)\
73637 #define TXRF6__PADRVGN_INDEX_I2G__MODIFY(dst, src) \
73639 ~0x00f00000U) | (((u_int32_t)(src) <<\
73641 #define TXRF6__PADRVGN_INDEX_I2G__VERIFY(src) \
73642 (!((((u_int32_t)(src)\
73649 #define TXRF6__VCMONDELAY2G__READ(src) (((u_int32_t)(src) & 0x07000000U) >> 24)
73650 #define TXRF6__VCMONDELAY2G__WRITE(src) \
73651 (((u_int32_t)(src)\
73653 #define TXRF6__VCMONDELAY2G__MODIFY(dst, src) \
73655 ~0x07000000U) | (((u_int32_t)(src) <<\
73657 #define TXRF6__VCMONDELAY2G__VERIFY(src) \
73658 (!((((u_int32_t)(src)\
73665 #define TXRF6__CAPDIV2G__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27)
73666 #define TXRF6__CAPDIV2G__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U)
73667 #define TXRF6__CAPDIV2G__MODIFY(dst, src) \
73669 ~0x78000000U) | (((u_int32_t)(src) <<\
73671 #define TXRF6__CAPDIV2G__VERIFY(src) \
73672 (!((((u_int32_t)(src)\
73679 #define TXRF6__CAPDIV2GOVR__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
73680 #define TXRF6__CAPDIV2GOVR__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U)
73681 #define TXRF6__CAPDIV2GOVR__MODIFY(dst, src) \
73683 ~0x80000000U) | (((u_int32_t)(src) <<\
73685 #define TXRF6__CAPDIV2GOVR__VERIFY(src) \
73686 (!((((u_int32_t)(src)\
73712 #define TXRF7__SPARE7__READ(src) (u_int32_t)(src) & 0x00000003U
73713 #define TXRF7__SPARE7__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
73714 #define TXRF7__SPARE7__MODIFY(dst, src) \
73716 ~0x00000003U) | ((u_int32_t)(src) &\
73718 #define TXRF7__SPARE7__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
73724 #define TXRF7__PADRVGNTAB_4__READ(src) (((u_int32_t)(src) & 0x000000fcU) >> 2)
73725 #define TXRF7__PADRVGNTAB_4__WRITE(src) (((u_int32_t)(src) << 2) & 0x000000fcU)
73726 #define TXRF7__PADRVGNTAB_4__MODIFY(dst, src) \
73728 ~0x000000fcU) | (((u_int32_t)(src) <<\
73730 #define TXRF7__PADRVGNTAB_4__VERIFY(src) \
73731 (!((((u_int32_t)(src)\
73738 #define TXRF7__PADRVGNTAB_3__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8)
73739 #define TXRF7__PADRVGNTAB_3__WRITE(src) (((u_int32_t)(src) << 8) & 0x00003f00U)
73740 #define TXRF7__PADRVGNTAB_3__MODIFY(dst, src) \
73742 ~0x00003f00U) | (((u_int32_t)(src) <<\
73744 #define TXRF7__PADRVGNTAB_3__VERIFY(src) \
73745 (!((((u_int32_t)(src)\
73752 #define TXRF7__PADRVGNTAB_2__READ(src) (((u_int32_t)(src) & 0x000fc000U) >> 14)
73753 #define TXRF7__PADRVGNTAB_2__WRITE(src) \
73754 (((u_int32_t)(src)\
73756 #define TXRF7__PADRVGNTAB_2__MODIFY(dst, src) \
73758 ~0x000fc000U) | (((u_int32_t)(src) <<\
73760 #define TXRF7__PADRVGNTAB_2__VERIFY(src) \
73761 (!((((u_int32_t)(src)\
73768 #define TXRF7__PADRVGNTAB_1__READ(src) (((u_int32_t)(src) & 0x03f00000U) >> 20)
73769 #define TXRF7__PADRVGNTAB_1__WRITE(src) \
73770 (((u_int32_t)(src)\
73772 #define TXRF7__PADRVGNTAB_1__MODIFY(dst, src) \
73774 ~0x03f00000U) | (((u_int32_t)(src) <<\
73776 #define TXRF7__PADRVGNTAB_1__VERIFY(src) \
73777 (!((((u_int32_t)(src)\
73784 #define TXRF7__PADRVGNTAB_0__READ(src) (((u_int32_t)(src) & 0xfc000000U) >> 26)
73785 #define TXRF7__PADRVGNTAB_0__WRITE(src) \
73786 (((u_int32_t)(src)\
73788 #define TXRF7__PADRVGNTAB_0__MODIFY(dst, src) \
73790 ~0xfc000000U) | (((u_int32_t)(src) <<\
73792 #define TXRF7__PADRVGNTAB_0__VERIFY(src) \
73793 (!((((u_int32_t)(src)\
73813 #define TXRF8__SPARE8__READ(src) (u_int32_t)(src) & 0x00000003U
73814 #define TXRF8__SPARE8__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
73815 #define TXRF8__SPARE8__MODIFY(dst, src) \
73817 ~0x00000003U) | ((u_int32_t)(src) &\
73819 #define TXRF8__SPARE8__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
73825 #define TXRF8__PADRVGNTAB_9__READ(src) (((u_int32_t)(src) & 0x000000fcU) >> 2)
73826 #define TXRF8__PADRVGNTAB_9__WRITE(src) (((u_int32_t)(src) << 2) & 0x000000fcU)
73827 #define TXRF8__PADRVGNTAB_9__MODIFY(dst, src) \
73829 ~0x000000fcU) | (((u_int32_t)(src) <<\
73831 #define TXRF8__PADRVGNTAB_9__VERIFY(src) \
73832 (!((((u_int32_t)(src)\
73839 #define TXRF8__PADRVGNTAB_8__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8)
73840 #define TXRF8__PADRVGNTAB_8__WRITE(src) (((u_int32_t)(src) << 8) & 0x00003f00U)
73841 #define TXRF8__PADRVGNTAB_8__MODIFY(dst, src) \
73843 ~0x00003f00U) | (((u_int32_t)(src) <<\
73845 #define TXRF8__PADRVGNTAB_8__VERIFY(src) \
73846 (!((((u_int32_t)(src)\
73853 #define TXRF8__PADRVGNTAB_7__READ(src) (((u_int32_t)(src) & 0x000fc000U) >> 14)
73854 #define TXRF8__PADRVGNTAB_7__WRITE(src) \
73855 (((u_int32_t)(src)\
73857 #define TXRF8__PADRVGNTAB_7__MODIFY(dst, src) \
73859 ~0x000fc000U) | (((u_int32_t)(src) <<\
73861 #define TXRF8__PADRVGNTAB_7__VERIFY(src) \
73862 (!((((u_int32_t)(src)\
73869 #define TXRF8__PADRVGNTAB_6__READ(src) (((u_int32_t)(src) & 0x03f00000U) >> 20)
73870 #define TXRF8__PADRVGNTAB_6__WRITE(src) \
73871 (((u_int32_t)(src)\
73873 #define TXRF8__PADRVGNTAB_6__MODIFY(dst, src) \
73875 ~0x03f00000U) | (((u_int32_t)(src) <<\
73877 #define TXRF8__PADRVGNTAB_6__VERIFY(src) \
73878 (!((((u_int32_t)(src)\
73885 #define TXRF8__PADRVGNTAB_5__READ(src) (((u_int32_t)(src) & 0xfc000000U) >> 26)
73886 #define TXRF8__PADRVGNTAB_5__WRITE(src) \
73887 (((u_int32_t)(src)\
73889 #define TXRF8__PADRVGNTAB_5__MODIFY(dst, src) \
73891 ~0xfc000000U) | (((u_int32_t)(src) <<\
73893 #define TXRF8__PADRVGNTAB_5__VERIFY(src) \
73894 (!((((u_int32_t)(src)\
73914 #define TXRF9__SPARE9__READ(src) (u_int32_t)(src) & 0x00000003U
73915 #define TXRF9__SPARE9__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
73916 #define TXRF9__SPARE9__MODIFY(dst, src) \
73918 ~0x00000003U) | ((u_int32_t)(src) &\
73920 #define TXRF9__SPARE9__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
73926 #define TXRF9__PADRVGNTAB_14__READ(src) (((u_int32_t)(src) & 0x000000fcU) >> 2)
73927 #define TXRF9__PADRVGNTAB_14__WRITE(src) \
73928 (((u_int32_t)(src)\
73930 #define TXRF9__PADRVGNTAB_14__MODIFY(dst, src) \
73932 ~0x000000fcU) | (((u_int32_t)(src) <<\
73934 #define TXRF9__PADRVGNTAB_14__VERIFY(src) \
73935 (!((((u_int32_t)(src)\
73942 #define TXRF9__PADRVGNTAB_13__READ(src) (((u_int32_t)(src) & 0x00003f00U) >> 8)
73943 #define TXRF9__PADRVGNTAB_13__WRITE(src) \
73944 (((u_int32_t)(src)\
73946 #define TXRF9__PADRVGNTAB_13__MODIFY(dst, src) \
73948 ~0x00003f00U) | (((u_int32_t)(src) <<\
73950 #define TXRF9__PADRVGNTAB_13__VERIFY(src) \
73951 (!((((u_int32_t)(src)\
73958 #define TXRF9__PADRVGNTAB_12__READ(src) \
73959 (((u_int32_t)(src)\
73961 #define TXRF9__PADRVGNTAB_12__WRITE(src) \
73962 (((u_int32_t)(src)\
73964 #define TXRF9__PADRVGNTAB_12__MODIFY(dst, src) \
73966 ~0x000fc000U) | (((u_int32_t)(src) <<\
73968 #define TXRF9__PADRVGNTAB_12__VERIFY(src) \
73969 (!((((u_int32_t)(src)\
73976 #define TXRF9__PADRVGNTAB_11__READ(src) \
73977 (((u_int32_t)(src)\
73979 #define TXRF9__PADRVGNTAB_11__WRITE(src) \
73980 (((u_int32_t)(src)\
73982 #define TXRF9__PADRVGNTAB_11__MODIFY(dst, src) \
73984 ~0x03f00000U) | (((u_int32_t)(src) <<\
73986 #define TXRF9__PADRVGNTAB_11__VERIFY(src) \
73987 (!((((u_int32_t)(src)\
73994 #define TXRF9__PADRVGNTAB_10__READ(src) \
73995 (((u_int32_t)(src)\
73997 #define TXRF9__PADRVGNTAB_10__WRITE(src) \
73998 (((u_int32_t)(src)\
74000 #define TXRF9__PADRVGNTAB_10__MODIFY(dst, src) \
74002 ~0xfc000000U) | (((u_int32_t)(src) <<\
74004 #define TXRF9__PADRVGNTAB_10__VERIFY(src) \
74005 (!((((u_int32_t)(src)\
74025 #define TXRF10__SPARE10__READ(src) (u_int32_t)(src) & 0x00000007U
74026 #define TXRF10__SPARE10__WRITE(src) ((u_int32_t)(src) & 0x00000007U)
74027 #define TXRF10__SPARE10__MODIFY(dst, src) \
74029 ~0x00000007U) | ((u_int32_t)(src) &\
74031 #define TXRF10__SPARE10__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U)))
74037 #define TXRF10__PDOUT5G_3CALTX__READ(src) \
74038 (((u_int32_t)(src)\
74040 #define TXRF10__PDOUT5G_3CALTX__WRITE(src) \
74041 (((u_int32_t)(src)\
74043 #define TXRF10__PDOUT5G_3CALTX__MODIFY(dst, src) \
74045 ~0x00000008U) | (((u_int32_t)(src) <<\
74047 #define TXRF10__PDOUT5G_3CALTX__VERIFY(src) \
74048 (!((((u_int32_t)(src)\
74061 #define TXRF10__D3B5GCALTX__READ(src) (((u_int32_t)(src) & 0x00000070U) >> 4)
74062 #define TXRF10__D3B5GCALTX__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000070U)
74063 #define TXRF10__D3B5GCALTX__MODIFY(dst, src) \
74065 ~0x00000070U) | (((u_int32_t)(src) <<\
74067 #define TXRF10__D3B5GCALTX__VERIFY(src) \
74068 (!((((u_int32_t)(src)\
74075 #define TXRF10__D4B5GCALTX__READ(src) (((u_int32_t)(src) & 0x00000380U) >> 7)
74076 #define TXRF10__D4B5GCALTX__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000380U)
74077 #define TXRF10__D4B5GCALTX__MODIFY(dst, src) \
74079 ~0x00000380U) | (((u_int32_t)(src) <<\
74081 #define TXRF10__D4B5GCALTX__VERIFY(src) \
74082 (!((((u_int32_t)(src)\
74089 #define TXRF10__PADRVGN2GCALTX__READ(src) \
74090 (((u_int32_t)(src)\
74092 #define TXRF10__PADRVGN2GCALTX__WRITE(src) \
74093 (((u_int32_t)(src)\
74095 #define TXRF10__PADRVGN2GCALTX__MODIFY(dst, src) \
74097 ~0x0001fc00U) | (((u_int32_t)(src) <<\
74099 #define TXRF10__PADRVGN2GCALTX__VERIFY(src) \
74100 (!((((u_int32_t)(src)\
74107 #define TXRF10__DB2GCALTX__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17)
74108 #define TXRF10__DB2GCALTX__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U)
74109 #define TXRF10__DB2GCALTX__MODIFY(dst, src) \
74111 ~0x000e0000U) | (((u_int32_t)(src) <<\
74113 #define TXRF10__DB2GCALTX__VERIFY(src) \
74114 (!((((u_int32_t)(src)\
74121 #define TXRF10__CALTXSHIFT__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20)
74122 #define TXRF10__CALTXSHIFT__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U)
74123 #define TXRF10__CALTXSHIFT__MODIFY(dst, src) \
74125 ~0x00100000U) | (((u_int32_t)(src) <<\
74127 #define TXRF10__CALTXSHIFT__VERIFY(src) \
74128 (!((((u_int32_t)(src)\
74141 #define TXRF10__CALTXSHIFTOVR__READ(src) \
74142 (((u_int32_t)(src)\
74144 #define TXRF10__CALTXSHIFTOVR__WRITE(src) \
74145 (((u_int32_t)(src)\
74147 #define TXRF10__CALTXSHIFTOVR__MODIFY(dst, src) \
74149 ~0x00200000U) | (((u_int32_t)(src) <<\
74151 #define TXRF10__CALTXSHIFTOVR__VERIFY(src) \
74152 (!((((u_int32_t)(src)\
74165 #define TXRF10__PADRVGN2G_SMOUT__READ(src) \
74166 (((u_int32_t)(src)\
74173 #define TXRF10__PADRVGN_INDEX2G_SMOUT__READ(src) \
74174 (((u_int32_t)(src)\
74194 #define TXRF11__SPARE11__READ(src) (u_int32_t)(src) & 0x00000003U
74195 #define TXRF11__SPARE11__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
74196 #define TXRF11__SPARE11__MODIFY(dst, src) \
74198 ~0x00000003U) | ((u_int32_t)(src) &\
74200 #define TXRF11__SPARE11__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
74206 #define TXRF11__PWD_IR25MIXDIV5G__READ(src) \
74207 (((u_int32_t)(src)\
74209 #define TXRF11__PWD_IR25MIXDIV5G__WRITE(src) \
74210 (((u_int32_t)(src)\
74212 #define TXRF11__PWD_IR25MIXDIV5G__MODIFY(dst, src) \
74214 ~0x0000001cU) | (((u_int32_t)(src) <<\
74216 #define TXRF11__PWD_IR25MIXDIV5G__VERIFY(src) \
74217 (!((((u_int32_t)(src)\
74224 #define TXRF11__PWD_IR25PA2G__READ(src) (((u_int32_t)(src) & 0x000000e0U) >> 5)
74225 #define TXRF11__PWD_IR25PA2G__WRITE(src) \
74226 (((u_int32_t)(src)\
74228 #define TXRF11__PWD_IR25PA2G__MODIFY(dst, src) \
74230 ~0x000000e0U) | (((u_int32_t)(src) <<\
74232 #define TXRF11__PWD_IR25PA2G__VERIFY(src) \
74233 (!((((u_int32_t)(src)\
74240 #define TXRF11__PWD_IR25MIXBIAS2G__READ(src) \
74241 (((u_int32_t)(src)\
74243 #define TXRF11__PWD_IR25MIXBIAS2G__WRITE(src) \
74244 (((u_int32_t)(src)\
74246 #define TXRF11__PWD_IR25MIXBIAS2G__MODIFY(dst, src) \
74248 ~0x00000700U) | (((u_int32_t)(src) <<\
74250 #define TXRF11__PWD_IR25MIXBIAS2G__VERIFY(src) \
74251 (!((((u_int32_t)(src)\
74258 #define TXRF11__PWD_IR25MIXDIV2G__READ(src) \
74259 (((u_int32_t)(src)\
74261 #define TXRF11__PWD_IR25MIXDIV2G__WRITE(src) \
74262 (((u_int32_t)(src)\
74264 #define TXRF11__PWD_IR25MIXDIV2G__MODIFY(dst, src) \
74266 ~0x00003800U) | (((u_int32_t)(src) <<\
74268 #define TXRF11__PWD_IR25MIXDIV2G__VERIFY(src) \
74269 (!((((u_int32_t)(src)\
74276 #define TXRF11__PWD_ICSPARE__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14)
74277 #define TXRF11__PWD_ICSPARE__WRITE(src) \
74278 (((u_int32_t)(src)\
74280 #define TXRF11__PWD_ICSPARE__MODIFY(dst, src) \
74282 ~0x0001c000U) | (((u_int32_t)(src) <<\
74284 #define TXRF11__PWD_ICSPARE__VERIFY(src) \
74285 (!((((u_int32_t)(src)\
74292 #define TXRF11__PWD_IC25TEMPSEN__READ(src) \
74293 (((u_int32_t)(src)\
74295 #define TXRF11__PWD_IC25TEMPSEN__WRITE(src) \
74296 (((u_int32_t)(src)\
74298 #define TXRF11__PWD_IC25TEMPSEN__MODIFY(dst, src) \
74300 ~0x000e0000U) | (((u_int32_t)(src) <<\
74302 #define TXRF11__PWD_IC25TEMPSEN__VERIFY(src) \
74303 (!((((u_int32_t)(src)\
74310 #define TXRF11__PWD_IC25PA5G2__READ(src) \
74311 (((u_int32_t)(src)\
74313 #define TXRF11__PWD_IC25PA5G2__WRITE(src) \
74314 (((u_int32_t)(src)\
74316 #define TXRF11__PWD_IC25PA5G2__MODIFY(dst, src) \
74318 ~0x00700000U) | (((u_int32_t)(src) <<\
74320 #define TXRF11__PWD_IC25PA5G2__VERIFY(src) \
74321 (!((((u_int32_t)(src)\
74328 #define TXRF11__PWD_IC25PA5G1__READ(src) \
74329 (((u_int32_t)(src)\
74331 #define TXRF11__PWD_IC25PA5G1__WRITE(src) \
74332 (((u_int32_t)(src)\
74334 #define TXRF11__PWD_IC25PA5G1__MODIFY(dst, src) \
74336 ~0x03800000U) | (((u_int32_t)(src) <<\
74338 #define TXRF11__PWD_IC25PA5G1__VERIFY(src) \
74339 (!((((u_int32_t)(src)\
74346 #define TXRF11__PWD_IC25MIXBUF5G__READ(src) \
74347 (((u_int32_t)(src)\
74349 #define TXRF11__PWD_IC25MIXBUF5G__WRITE(src) \
74350 (((u_int32_t)(src)\
74352 #define TXRF11__PWD_IC25MIXBUF5G__MODIFY(dst, src) \
74354 ~0x1c000000U) | (((u_int32_t)(src) <<\
74356 #define TXRF11__PWD_IC25MIXBUF5G__VERIFY(src) \
74357 (!((((u_int32_t)(src)\
74364 #define TXRF11__PWD_IC25PA2G__READ(src) \
74365 (((u_int32_t)(src)\
74367 #define TXRF11__PWD_IC25PA2G__WRITE(src) \
74368 (((u_int32_t)(src)\
74370 #define TXRF11__PWD_IC25PA2G__MODIFY(dst, src) \
74372 ~0xe0000000U) | (((u_int32_t)(src) <<\
74374 #define TXRF11__PWD_IC25PA2G__VERIFY(src) \
74375 (!((((u_int32_t)(src)\
74395 #define TXRF12__SPARE12_2__READ(src) (u_int32_t)(src) & 0x000000ffU
74401 #define TXRF12__SPARE12_1__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8)
74402 #define TXRF12__SPARE12_1__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000300U)
74403 #define TXRF12__SPARE12_1__MODIFY(dst, src) \
74405 ~0x00000300U) | (((u_int32_t)(src) <<\
74407 #define TXRF12__SPARE12_1__VERIFY(src) \
74408 (!((((u_int32_t)(src)\
74415 #define TXRF12__ATBSEL5G__READ(src) (((u_int32_t)(src) & 0x00003c00U) >> 10)
74416 #define TXRF12__ATBSEL5G__WRITE(src) (((u_int32_t)(src) << 10) & 0x00003c00U)
74417 #define TXRF12__ATBSEL5G__MODIFY(dst, src) \
74419 ~0x00003c00U) | (((u_int32_t)(src) <<\
74421 #define TXRF12__ATBSEL5G__VERIFY(src) \
74422 (!((((u_int32_t)(src)\
74429 #define TXRF12__ATBSEL2G__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14)
74430 #define TXRF12__ATBSEL2G__WRITE(src) (((u_int32_t)(src) << 14) & 0x0001c000U)
74431 #define TXRF12__ATBSEL2G__MODIFY(dst, src) \
74433 ~0x0001c000U) | (((u_int32_t)(src) <<\
74435 #define TXRF12__ATBSEL2G__VERIFY(src) \
74436 (!((((u_int32_t)(src)\
74443 #define TXRF12__PWD_IRSPARE__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17)
74444 #define TXRF12__PWD_IRSPARE__WRITE(src) \
74445 (((u_int32_t)(src)\
74447 #define TXRF12__PWD_IRSPARE__MODIFY(dst, src) \
74449 ~0x000e0000U) | (((u_int32_t)(src) <<\
74451 #define TXRF12__PWD_IRSPARE__VERIFY(src) \
74452 (!((((u_int32_t)(src)\
74459 #define TXRF12__PWD_IR25TEMPSEN__READ(src) \
74460 (((u_int32_t)(src)\
74462 #define TXRF12__PWD_IR25TEMPSEN__WRITE(src) \
74463 (((u_int32_t)(src)\
74465 #define TXRF12__PWD_IR25TEMPSEN__MODIFY(dst, src) \
74467 ~0x00700000U) | (((u_int32_t)(src) <<\
74469 #define TXRF12__PWD_IR25TEMPSEN__VERIFY(src) \
74470 (!((((u_int32_t)(src)\
74477 #define TXRF12__PWD_IR25PA5G2__READ(src) \
74478 (((u_int32_t)(src)\
74480 #define TXRF12__PWD_IR25PA5G2__WRITE(src) \
74481 (((u_int32_t)(src)\
74483 #define TXRF12__PWD_IR25PA5G2__MODIFY(dst, src) \
74485 ~0x03800000U) | (((u_int32_t)(src) <<\
74487 #define TXRF12__PWD_IR25PA5G2__VERIFY(src) \
74488 (!((((u_int32_t)(src)\
74495 #define TXRF12__PWD_IR25PA5G1__READ(src) \
74496 (((u_int32_t)(src)\
74498 #define TXRF12__PWD_IR25PA5G1__WRITE(src) \
74499 (((u_int32_t)(src)\
74501 #define TXRF12__PWD_IR25PA5G1__MODIFY(dst, src) \
74503 ~0x1c000000U) | (((u_int32_t)(src) <<\
74505 #define TXRF12__PWD_IR25PA5G1__VERIFY(src) \
74506 (!((((u_int32_t)(src)\
74513 #define TXRF12__PWD_IR25MIXBIAS5G__READ(src) \
74514 (((u_int32_t)(src)\
74516 #define TXRF12__PWD_IR25MIXBIAS5G__WRITE(src) \
74517 (((u_int32_t)(src)\
74519 #define TXRF12__PWD_IR25MIXBIAS5G__MODIFY(dst, src) \
74521 ~0xe0000000U) | (((u_int32_t)(src) <<\
74523 #define TXRF12__PWD_IR25MIXBIAS5G__VERIFY(src) \
74524 (!((((u_int32_t)(src)\
74544 #define SYNTH1__SEL_VCMONABUS__READ(src) (u_int32_t)(src) & 0x00000007U
74545 #define SYNTH1__SEL_VCMONABUS__WRITE(src) ((u_int32_t)(src) & 0x00000007U)
74546 #define SYNTH1__SEL_VCMONABUS__MODIFY(dst, src) \
74548 ~0x00000007U) | ((u_int32_t)(src) &\
74550 #define SYNTH1__SEL_VCMONABUS__VERIFY(src) \
74551 (!(((u_int32_t)(src)\
74558 #define SYNTH1__SEL_VCOABUS__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3)
74559 #define SYNTH1__SEL_VCOABUS__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000038U)
74560 #define SYNTH1__SEL_VCOABUS__MODIFY(dst, src) \
74562 ~0x00000038U) | (((u_int32_t)(src) <<\
74564 #define SYNTH1__SEL_VCOABUS__VERIFY(src) \
74565 (!((((u_int32_t)(src)\
74572 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__READ(src) \
74573 (((u_int32_t)(src)\
74575 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__WRITE(src) \
74576 (((u_int32_t)(src)\
74578 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__MODIFY(dst, src) \
74580 ~0x00000040U) | (((u_int32_t)(src) <<\
74582 #define SYNTH1__MONITOR_SYNTHLOCKVCOK__VERIFY(src) \
74583 (!((((u_int32_t)(src)\
74596 #define SYNTH1__MONITOR_VC2LOW__READ(src) \
74597 (((u_int32_t)(src)\
74599 #define SYNTH1__MONITOR_VC2LOW__WRITE(src) \
74600 (((u_int32_t)(src)\
74602 #define SYNTH1__MONITOR_VC2LOW__MODIFY(dst, src) \
74604 ~0x00000080U) | (((u_int32_t)(src) <<\
74606 #define SYNTH1__MONITOR_VC2LOW__VERIFY(src) \
74607 (!((((u_int32_t)(src)\
74620 #define SYNTH1__MONITOR_VC2HIGH__READ(src) \
74621 (((u_int32_t)(src)\
74623 #define SYNTH1__MONITOR_VC2HIGH__WRITE(src) \
74624 (((u_int32_t)(src)\
74626 #define SYNTH1__MONITOR_VC2HIGH__MODIFY(dst, src) \
74628 ~0x00000100U) | (((u_int32_t)(src) <<\
74630 #define SYNTH1__MONITOR_VC2HIGH__VERIFY(src) \
74631 (!((((u_int32_t)(src)\
74644 #define SYNTH1__MONITOR_FB_DIV2__READ(src) \
74645 (((u_int32_t)(src)\
74647 #define SYNTH1__MONITOR_FB_DIV2__WRITE(src) \
74648 (((u_int32_t)(src)\
74650 #define SYNTH1__MONITOR_FB_DIV2__MODIFY(dst, src) \
74652 ~0x00000200U) | (((u_int32_t)(src) <<\
74654 #define SYNTH1__MONITOR_FB_DIV2__VERIFY(src) \
74655 (!((((u_int32_t)(src)\
74668 #define SYNTH1__MONITOR_REF__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
74669 #define SYNTH1__MONITOR_REF__WRITE(src) \
74670 (((u_int32_t)(src)\
74672 #define SYNTH1__MONITOR_REF__MODIFY(dst, src) \
74674 ~0x00000400U) | (((u_int32_t)(src) <<\
74676 #define SYNTH1__MONITOR_REF__VERIFY(src) \
74677 (!((((u_int32_t)(src)\
74690 #define SYNTH1__MONITOR_FB__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
74691 #define SYNTH1__MONITOR_FB__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U)
74692 #define SYNTH1__MONITOR_FB__MODIFY(dst, src) \
74694 ~0x00000800U) | (((u_int32_t)(src) <<\
74696 #define SYNTH1__MONITOR_FB__VERIFY(src) \
74697 (!((((u_int32_t)(src)\
74710 #define SYNTH1__SEVENBITVCOCAP__READ(src) \
74711 (((u_int32_t)(src)\
74713 #define SYNTH1__SEVENBITVCOCAP__WRITE(src) \
74714 (((u_int32_t)(src)\
74716 #define SYNTH1__SEVENBITVCOCAP__MODIFY(dst, src) \
74718 ~0x00001000U) | (((u_int32_t)(src) <<\
74720 #define SYNTH1__SEVENBITVCOCAP__VERIFY(src) \
74721 (!((((u_int32_t)(src)\
74734 #define SYNTH1__PWUP_PD__READ(src) (((u_int32_t)(src) & 0x0000e000U) >> 13)
74735 #define SYNTH1__PWUP_PD__WRITE(src) (((u_int32_t)(src) << 13) & 0x0000e000U)
74736 #define SYNTH1__PWUP_PD__MODIFY(dst, src) \
74738 ~0x0000e000U) | (((u_int32_t)(src) <<\
74740 #define SYNTH1__PWUP_PD__VERIFY(src) \
74741 (!((((u_int32_t)(src)\
74748 #define SYNTH1__PWD_VCOBUF__READ(src) (((u_int32_t)(src) & 0x00010000U) >> 16)
74749 #define SYNTH1__PWD_VCOBUF__WRITE(src) (((u_int32_t)(src) << 16) & 0x00010000U)
74750 #define SYNTH1__PWD_VCOBUF__MODIFY(dst, src) \
74752 ~0x00010000U) | (((u_int32_t)(src) <<\
74754 #define SYNTH1__PWD_VCOBUF__VERIFY(src) \
74755 (!((((u_int32_t)(src)\
74768 #define SYNTH1__VCOBUFGAIN__READ(src) (((u_int32_t)(src) & 0x00060000U) >> 17)
74769 #define SYNTH1__VCOBUFGAIN__WRITE(src) (((u_int32_t)(src) << 17) & 0x00060000U)
74770 #define SYNTH1__VCOBUFGAIN__MODIFY(dst, src) \
74772 ~0x00060000U) | (((u_int32_t)(src) <<\
74774 #define SYNTH1__VCOBUFGAIN__VERIFY(src) \
74775 (!((((u_int32_t)(src)\
74782 #define SYNTH1__VCOREGLEVEL__READ(src) (((u_int32_t)(src) & 0x00180000U) >> 19)
74783 #define SYNTH1__VCOREGLEVEL__WRITE(src) \
74784 (((u_int32_t)(src)\
74786 #define SYNTH1__VCOREGLEVEL__MODIFY(dst, src) \
74788 ~0x00180000U) | (((u_int32_t)(src) <<\
74790 #define SYNTH1__VCOREGLEVEL__VERIFY(src) \
74791 (!((((u_int32_t)(src)\
74798 #define SYNTH1__VCOREGBYPASS__READ(src) \
74799 (((u_int32_t)(src)\
74801 #define SYNTH1__VCOREGBYPASS__WRITE(src) \
74802 (((u_int32_t)(src)\
74804 #define SYNTH1__VCOREGBYPASS__MODIFY(dst, src) \
74806 ~0x00200000U) | (((u_int32_t)(src) <<\
74808 #define SYNTH1__VCOREGBYPASS__VERIFY(src) \
74809 (!((((u_int32_t)(src)\
74822 #define SYNTH1__PWUP_LOREF__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22)
74823 #define SYNTH1__PWUP_LOREF__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U)
74824 #define SYNTH1__PWUP_LOREF__MODIFY(dst, src) \
74826 ~0x00400000U) | (((u_int32_t)(src) <<\
74828 #define SYNTH1__PWUP_LOREF__VERIFY(src) \
74829 (!((((u_int32_t)(src)\
74842 #define SYNTH1__PWD_LOMIX__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23)
74843 #define SYNTH1__PWD_LOMIX__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U)
74844 #define SYNTH1__PWD_LOMIX__MODIFY(dst, src) \
74846 ~0x00800000U) | (((u_int32_t)(src) <<\
74848 #define SYNTH1__PWD_LOMIX__VERIFY(src) \
74849 (!((((u_int32_t)(src)\
74862 #define SYNTH1__PWD_LODIV__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24)
74863 #define SYNTH1__PWD_LODIV__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U)
74864 #define SYNTH1__PWD_LODIV__MODIFY(dst, src) \
74866 ~0x01000000U) | (((u_int32_t)(src) <<\
74868 #define SYNTH1__PWD_LODIV__VERIFY(src) \
74869 (!((((u_int32_t)(src)\
74882 #define SYNTH1__PWD_LOBUF5G__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25)
74883 #define SYNTH1__PWD_LOBUF5G__WRITE(src) \
74884 (((u_int32_t)(src)\
74886 #define SYNTH1__PWD_LOBUF5G__MODIFY(dst, src) \
74888 ~0x02000000U) | (((u_int32_t)(src) <<\
74890 #define SYNTH1__PWD_LOBUF5G__VERIFY(src) \
74891 (!((((u_int32_t)(src)\
74904 #define SYNTH1__PWD_LOBUF2G__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26)
74905 #define SYNTH1__PWD_LOBUF2G__WRITE(src) \
74906 (((u_int32_t)(src)\
74908 #define SYNTH1__PWD_LOBUF2G__MODIFY(dst, src) \
74910 ~0x04000000U) | (((u_int32_t)(src) <<\
74912 #define SYNTH1__PWD_LOBUF2G__VERIFY(src) \
74913 (!((((u_int32_t)(src)\
74926 #define SYNTH1__PWD_PRESC__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
74927 #define SYNTH1__PWD_PRESC__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U)
74928 #define SYNTH1__PWD_PRESC__MODIFY(dst, src) \
74930 ~0x08000000U) | (((u_int32_t)(src) <<\
74932 #define SYNTH1__PWD_PRESC__VERIFY(src) \
74933 (!((((u_int32_t)(src)\
74946 #define SYNTH1__PWD_VCO__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28)
74947 #define SYNTH1__PWD_VCO__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U)
74948 #define SYNTH1__PWD_VCO__MODIFY(dst, src) \
74950 ~0x10000000U) | (((u_int32_t)(src) <<\
74952 #define SYNTH1__PWD_VCO__VERIFY(src) \
74953 (!((((u_int32_t)(src)\
74966 #define SYNTH1__PWD_VCMON__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
74967 #define SYNTH1__PWD_VCMON__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U)
74968 #define SYNTH1__PWD_VCMON__MODIFY(dst, src) \
74970 ~0x20000000U) | (((u_int32_t)(src) <<\
74972 #define SYNTH1__PWD_VCMON__VERIFY(src) \
74973 (!((((u_int32_t)(src)\
74986 #define SYNTH1__PWD_CP__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30)
74987 #define SYNTH1__PWD_CP__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U)
74988 #define SYNTH1__PWD_CP__MODIFY(dst, src) \
74990 ~0x40000000U) | (((u_int32_t)(src) <<\
74992 #define SYNTH1__PWD_CP__VERIFY(src) \
74993 (!((((u_int32_t)(src)\
75006 #define SYNTH1__PWD_BIAS__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
75007 #define SYNTH1__PWD_BIAS__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U)
75008 #define SYNTH1__PWD_BIAS__MODIFY(dst, src) \
75010 ~0x80000000U) | (((u_int32_t)(src) <<\
75012 #define SYNTH1__PWD_BIAS__VERIFY(src) \
75013 (!((((u_int32_t)(src)\
75039 #define SYNTH2__CAPRANGE3__READ(src) (u_int32_t)(src) & 0x0000000fU
75040 #define SYNTH2__CAPRANGE3__WRITE(src) ((u_int32_t)(src) & 0x0000000fU)
75041 #define SYNTH2__CAPRANGE3__MODIFY(dst, src) \
75043 ~0x0000000fU) | ((u_int32_t)(src) &\
75045 #define SYNTH2__CAPRANGE3__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU)))
75051 #define SYNTH2__CAPRANGE2__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4)
75052 #define SYNTH2__CAPRANGE2__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U)
75053 #define SYNTH2__CAPRANGE2__MODIFY(dst, src) \
75055 ~0x000000f0U) | (((u_int32_t)(src) <<\
75057 #define SYNTH2__CAPRANGE2__VERIFY(src) \
75058 (!((((u_int32_t)(src)\
75065 #define SYNTH2__CAPRANGE1__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8)
75066 #define SYNTH2__CAPRANGE1__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U)
75067 #define SYNTH2__CAPRANGE1__MODIFY(dst, src) \
75069 ~0x00000f00U) | (((u_int32_t)(src) <<\
75071 #define SYNTH2__CAPRANGE1__VERIFY(src) \
75072 (!((((u_int32_t)(src)\
75079 #define SYNTH2__LOOPLEAKCUR_INTN__READ(src) \
75080 (((u_int32_t)(src)\
75082 #define SYNTH2__LOOPLEAKCUR_INTN__WRITE(src) \
75083 (((u_int32_t)(src)\
75085 #define SYNTH2__LOOPLEAKCUR_INTN__MODIFY(dst, src) \
75087 ~0x0000f000U) | (((u_int32_t)(src) <<\
75089 #define SYNTH2__LOOPLEAKCUR_INTN__VERIFY(src) \
75090 (!((((u_int32_t)(src)\
75097 #define SYNTH2__CPLOWLK_INTN__READ(src) \
75098 (((u_int32_t)(src)\
75100 #define SYNTH2__CPLOWLK_INTN__WRITE(src) \
75101 (((u_int32_t)(src)\
75103 #define SYNTH2__CPLOWLK_INTN__MODIFY(dst, src) \
75105 ~0x00010000U) | (((u_int32_t)(src) <<\
75107 #define SYNTH2__CPLOWLK_INTN__VERIFY(src) \
75108 (!((((u_int32_t)(src)\
75121 #define SYNTH2__CPSTEERING_EN_INTN__READ(src) \
75122 (((u_int32_t)(src)\
75124 #define SYNTH2__CPSTEERING_EN_INTN__WRITE(src) \
75125 (((u_int32_t)(src)\
75127 #define SYNTH2__CPSTEERING_EN_INTN__MODIFY(dst, src) \
75129 ~0x00020000U) | (((u_int32_t)(src) <<\
75131 #define SYNTH2__CPSTEERING_EN_INTN__VERIFY(src) \
75132 (!((((u_int32_t)(src)\
75145 #define SYNTH2__CPBIAS_INTN__READ(src) (((u_int32_t)(src) & 0x000c0000U) >> 18)
75146 #define SYNTH2__CPBIAS_INTN__WRITE(src) \
75147 (((u_int32_t)(src)\
75149 #define SYNTH2__CPBIAS_INTN__MODIFY(dst, src) \
75151 ~0x000c0000U) | (((u_int32_t)(src) <<\
75153 #define SYNTH2__CPBIAS_INTN__VERIFY(src) \
75154 (!((((u_int32_t)(src)\
75161 #define SYNTH2__VC_LOW_REF__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20)
75162 #define SYNTH2__VC_LOW_REF__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U)
75163 #define SYNTH2__VC_LOW_REF__MODIFY(dst, src) \
75165 ~0x00700000U) | (((u_int32_t)(src) <<\
75167 #define SYNTH2__VC_LOW_REF__VERIFY(src) \
75168 (!((((u_int32_t)(src)\
75175 #define SYNTH2__VC_MID_REF__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23)
75176 #define SYNTH2__VC_MID_REF__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U)
75177 #define SYNTH2__VC_MID_REF__MODIFY(dst, src) \
75179 ~0x03800000U) | (((u_int32_t)(src) <<\
75181 #define SYNTH2__VC_MID_REF__VERIFY(src) \
75182 (!((((u_int32_t)(src)\
75189 #define SYNTH2__VC_HI_REF__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26)
75190 #define SYNTH2__VC_HI_REF__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U)
75191 #define SYNTH2__VC_HI_REF__MODIFY(dst, src) \
75193 ~0x1c000000U) | (((u_int32_t)(src) <<\
75195 #define SYNTH2__VC_HI_REF__VERIFY(src) \
75196 (!((((u_int32_t)(src)\
75203 #define SYNTH2__VC_CAL_REF__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29)
75204 #define SYNTH2__VC_CAL_REF__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U)
75205 #define SYNTH2__VC_CAL_REF__MODIFY(dst, src) \
75207 ~0xe0000000U) | (((u_int32_t)(src) <<\
75209 #define SYNTH2__VC_CAL_REF__VERIFY(src) \
75210 (!((((u_int32_t)(src)\
75230 #define SYNTH3__WAIT_VC_CHECK__READ(src) (u_int32_t)(src) & 0x0000003fU
75231 #define SYNTH3__WAIT_VC_CHECK__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
75232 #define SYNTH3__WAIT_VC_CHECK__MODIFY(dst, src) \
75234 ~0x0000003fU) | ((u_int32_t)(src) &\
75236 #define SYNTH3__WAIT_VC_CHECK__VERIFY(src) \
75237 (!(((u_int32_t)(src)\
75244 #define SYNTH3__WAIT_CAL_LIN__READ(src) (((u_int32_t)(src) & 0x00000fc0U) >> 6)
75245 #define SYNTH3__WAIT_CAL_LIN__WRITE(src) \
75246 (((u_int32_t)(src)\
75248 #define SYNTH3__WAIT_CAL_LIN__MODIFY(dst, src) \
75250 ~0x00000fc0U) | (((u_int32_t)(src) <<\
75252 #define SYNTH3__WAIT_CAL_LIN__VERIFY(src) \
75253 (!((((u_int32_t)(src)\
75260 #define SYNTH3__WAIT_CAL_BIN__READ(src) \
75261 (((u_int32_t)(src)\
75263 #define SYNTH3__WAIT_CAL_BIN__WRITE(src) \
75264 (((u_int32_t)(src)\
75266 #define SYNTH3__WAIT_CAL_BIN__MODIFY(dst, src) \
75268 ~0x0003f000U) | (((u_int32_t)(src) <<\
75270 #define SYNTH3__WAIT_CAL_BIN__VERIFY(src) \
75271 (!((((u_int32_t)(src)\
75278 #define SYNTH3__WAIT_PWRUP__READ(src) (((u_int32_t)(src) & 0x00fc0000U) >> 18)
75279 #define SYNTH3__WAIT_PWRUP__WRITE(src) (((u_int32_t)(src) << 18) & 0x00fc0000U)
75280 #define SYNTH3__WAIT_PWRUP__MODIFY(dst, src) \
75282 ~0x00fc0000U) | (((u_int32_t)(src) <<\
75284 #define SYNTH3__WAIT_PWRUP__VERIFY(src) \
75285 (!((((u_int32_t)(src)\
75292 #define SYNTH3__WAIT_SHORTR_PWRUP__READ(src) \
75293 (((u_int32_t)(src)\
75295 #define SYNTH3__WAIT_SHORTR_PWRUP__WRITE(src) \
75296 (((u_int32_t)(src)\
75298 #define SYNTH3__WAIT_SHORTR_PWRUP__MODIFY(dst, src) \
75300 ~0x3f000000U) | (((u_int32_t)(src) <<\
75302 #define SYNTH3__WAIT_SHORTR_PWRUP__VERIFY(src) \
75303 (!((((u_int32_t)(src)\
75310 #define SYNTH3__SEL_CLK_DIV2__READ(src) \
75311 (((u_int32_t)(src)\
75313 #define SYNTH3__SEL_CLK_DIV2__WRITE(src) \
75314 (((u_int32_t)(src)\
75316 #define SYNTH3__SEL_CLK_DIV2__MODIFY(dst, src) \
75318 ~0x40000000U) | (((u_int32_t)(src) <<\
75320 #define SYNTH3__SEL_CLK_DIV2__VERIFY(src) \
75321 (!((((u_int32_t)(src)\
75334 #define SYNTH3__DIS_CLK_XTAL__READ(src) \
75335 (((u_int32_t)(src)\
75337 #define SYNTH3__DIS_CLK_XTAL__WRITE(src) \
75338 (((u_int32_t)(src)\
75340 #define SYNTH3__DIS_CLK_XTAL__MODIFY(dst, src) \
75342 ~0x80000000U) | (((u_int32_t)(src) <<\
75344 #define SYNTH3__DIS_CLK_XTAL__VERIFY(src) \
75345 (!((((u_int32_t)(src)\
75371 #define SYNTH4__PS_SINGLE_PULSE__READ(src) (u_int32_t)(src) & 0x00000001U
75372 #define SYNTH4__PS_SINGLE_PULSE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
75373 #define SYNTH4__PS_SINGLE_PULSE__MODIFY(dst, src) \
75375 ~0x00000001U) | ((u_int32_t)(src) &\
75377 #define SYNTH4__PS_SINGLE_PULSE__VERIFY(src) \
75378 (!(((u_int32_t)(src)\
75391 #define SYNTH4__LONGSHIFTSEL__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
75392 #define SYNTH4__LONGSHIFTSEL__WRITE(src) \
75393 (((u_int32_t)(src)\
75395 #define SYNTH4__LONGSHIFTSEL__MODIFY(dst, src) \
75397 ~0x00000002U) | (((u_int32_t)(src) <<\
75399 #define SYNTH4__LONGSHIFTSEL__VERIFY(src) \
75400 (!((((u_int32_t)(src)\
75413 #define SYNTH4__LOBUF5GTUNE_OVR__READ(src) \
75414 (((u_int32_t)(src)\
75416 #define SYNTH4__LOBUF5GTUNE_OVR__WRITE(src) \
75417 (((u_int32_t)(src)\
75419 #define SYNTH4__LOBUF5GTUNE_OVR__MODIFY(dst, src) \
75421 ~0x0000000cU) | (((u_int32_t)(src) <<\
75423 #define SYNTH4__LOBUF5GTUNE_OVR__VERIFY(src) \
75424 (!((((u_int32_t)(src)\
75431 #define SYNTH4__FORCE_LOBUF5GTUNE__READ(src) \
75432 (((u_int32_t)(src)\
75434 #define SYNTH4__FORCE_LOBUF5GTUNE__WRITE(src) \
75435 (((u_int32_t)(src)\
75437 #define SYNTH4__FORCE_LOBUF5GTUNE__MODIFY(dst, src) \
75439 ~0x00000010U) | (((u_int32_t)(src) <<\
75441 #define SYNTH4__FORCE_LOBUF5GTUNE__VERIFY(src) \
75442 (!((((u_int32_t)(src)\
75455 #define SYNTH4__PSCOUNT_FBSEL__READ(src) \
75456 (((u_int32_t)(src)\
75458 #define SYNTH4__PSCOUNT_FBSEL__WRITE(src) \
75459 (((u_int32_t)(src)\
75461 #define SYNTH4__PSCOUNT_FBSEL__MODIFY(dst, src) \
75463 ~0x00000020U) | (((u_int32_t)(src) <<\
75465 #define SYNTH4__PSCOUNT_FBSEL__VERIFY(src) \
75466 (!((((u_int32_t)(src)\
75479 #define SYNTH4__SDM_DITHER1__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6)
75480 #define SYNTH4__SDM_DITHER1__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U)
75481 #define SYNTH4__SDM_DITHER1__MODIFY(dst, src) \
75483 ~0x000000c0U) | (((u_int32_t)(src) <<\
75485 #define SYNTH4__SDM_DITHER1__VERIFY(src) \
75486 (!((((u_int32_t)(src)\
75493 #define SYNTH4__SDM_MODE__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8)
75494 #define SYNTH4__SDM_MODE__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U)
75495 #define SYNTH4__SDM_MODE__MODIFY(dst, src) \
75497 ~0x00000100U) | (((u_int32_t)(src) <<\
75499 #define SYNTH4__SDM_MODE__VERIFY(src) \
75500 (!((((u_int32_t)(src)\
75513 #define SYNTH4__SDM_DISABLE__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9)
75514 #define SYNTH4__SDM_DISABLE__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U)
75515 #define SYNTH4__SDM_DISABLE__MODIFY(dst, src) \
75517 ~0x00000200U) | (((u_int32_t)(src) <<\
75519 #define SYNTH4__SDM_DISABLE__VERIFY(src) \
75520 (!((((u_int32_t)(src)\
75533 #define SYNTH4__RESET_PRESC__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
75534 #define SYNTH4__RESET_PRESC__WRITE(src) \
75535 (((u_int32_t)(src)\
75537 #define SYNTH4__RESET_PRESC__MODIFY(dst, src) \
75539 ~0x00000400U) | (((u_int32_t)(src) <<\
75541 #define SYNTH4__RESET_PRESC__VERIFY(src) \
75542 (!((((u_int32_t)(src)\
75555 #define SYNTH4__PRESCSEL__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11)
75556 #define SYNTH4__PRESCSEL__WRITE(src) (((u_int32_t)(src) << 11) & 0x00001800U)
75557 #define SYNTH4__PRESCSEL__MODIFY(dst, src) \
75559 ~0x00001800U) | (((u_int32_t)(src) <<\
75561 #define SYNTH4__PRESCSEL__VERIFY(src) \
75562 (!((((u_int32_t)(src)\
75569 #define SYNTH4__PFD_DISABLE__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13)
75570 #define SYNTH4__PFD_DISABLE__WRITE(src) \
75571 (((u_int32_t)(src)\
75573 #define SYNTH4__PFD_DISABLE__MODIFY(dst, src) \
75575 ~0x00002000U) | (((u_int32_t)(src) <<\
75577 #define SYNTH4__PFD_DISABLE__VERIFY(src) \
75578 (!((((u_int32_t)(src)\
75591 #define SYNTH4__PFDDELAY_FRACN__READ(src) \
75592 (((u_int32_t)(src)\
75594 #define SYNTH4__PFDDELAY_FRACN__WRITE(src) \
75595 (((u_int32_t)(src)\
75597 #define SYNTH4__PFDDELAY_FRACN__MODIFY(dst, src) \
75599 ~0x00004000U) | (((u_int32_t)(src) <<\
75601 #define SYNTH4__PFDDELAY_FRACN__VERIFY(src) \
75602 (!((((u_int32_t)(src)\
75615 #define SYNTH4__FORCE_LO_ON__READ(src) (((u_int32_t)(src) & 0x00008000U) >> 15)
75616 #define SYNTH4__FORCE_LO_ON__WRITE(src) \
75617 (((u_int32_t)(src)\
75619 #define SYNTH4__FORCE_LO_ON__MODIFY(dst, src) \
75621 ~0x00008000U) | (((u_int32_t)(src) <<\
75623 #define SYNTH4__FORCE_LO_ON__VERIFY(src) \
75624 (!((((u_int32_t)(src)\
75637 #define SYNTH4__CLKXTAL_EDGE_SEL__READ(src) \
75638 (((u_int32_t)(src)\
75640 #define SYNTH4__CLKXTAL_EDGE_SEL__WRITE(src) \
75641 (((u_int32_t)(src)\
75643 #define SYNTH4__CLKXTAL_EDGE_SEL__MODIFY(dst, src) \
75645 ~0x00010000U) | (((u_int32_t)(src) <<\
75647 #define SYNTH4__CLKXTAL_EDGE_SEL__VERIFY(src) \
75648 (!((((u_int32_t)(src)\
75661 #define SYNTH4__VCOCAPPULLUP__READ(src) \
75662 (((u_int32_t)(src)\
75664 #define SYNTH4__VCOCAPPULLUP__WRITE(src) \
75665 (((u_int32_t)(src)\
75667 #define SYNTH4__VCOCAPPULLUP__MODIFY(dst, src) \
75669 ~0x00020000U) | (((u_int32_t)(src) <<\
75671 #define SYNTH4__VCOCAPPULLUP__VERIFY(src) \
75672 (!((((u_int32_t)(src)\
75685 #define SYNTH4__VCOCAP_OVR__READ(src) (((u_int32_t)(src) & 0x03fc0000U) >> 18)
75686 #define SYNTH4__VCOCAP_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x03fc0000U)
75687 #define SYNTH4__VCOCAP_OVR__MODIFY(dst, src) \
75689 ~0x03fc0000U) | (((u_int32_t)(src) <<\
75691 #define SYNTH4__VCOCAP_OVR__VERIFY(src) \
75692 (!((((u_int32_t)(src)\
75699 #define SYNTH4__FORCE_VCOCAP__READ(src) \
75700 (((u_int32_t)(src)\
75702 #define SYNTH4__FORCE_VCOCAP__WRITE(src) \
75703 (((u_int32_t)(src)\
75705 #define SYNTH4__FORCE_VCOCAP__MODIFY(dst, src) \
75707 ~0x04000000U) | (((u_int32_t)(src) <<\
75709 #define SYNTH4__FORCE_VCOCAP__VERIFY(src) \
75710 (!((((u_int32_t)(src)\
75723 #define SYNTH4__FORCE_PINVC__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
75724 #define SYNTH4__FORCE_PINVC__WRITE(src) \
75725 (((u_int32_t)(src)\
75727 #define SYNTH4__FORCE_PINVC__MODIFY(dst, src) \
75729 ~0x08000000U) | (((u_int32_t)(src) <<\
75731 #define SYNTH4__FORCE_PINVC__VERIFY(src) \
75732 (!((((u_int32_t)(src)\
75745 #define SYNTH4__SHORTR_UNTIL_LOCKED__READ(src) \
75746 (((u_int32_t)(src)\
75748 #define SYNTH4__SHORTR_UNTIL_LOCKED__WRITE(src) \
75749 (((u_int32_t)(src)\
75751 #define SYNTH4__SHORTR_UNTIL_LOCKED__MODIFY(dst, src) \
75753 ~0x10000000U) | (((u_int32_t)(src) <<\
75755 #define SYNTH4__SHORTR_UNTIL_LOCKED__VERIFY(src) \
75756 (!((((u_int32_t)(src)\
75769 #define SYNTH4__ALWAYS_SHORTR__READ(src) \
75770 (((u_int32_t)(src)\
75772 #define SYNTH4__ALWAYS_SHORTR__WRITE(src) \
75773 (((u_int32_t)(src)\
75775 #define SYNTH4__ALWAYS_SHORTR__MODIFY(dst, src) \
75777 ~0x20000000U) | (((u_int32_t)(src) <<\
75779 #define SYNTH4__ALWAYS_SHORTR__VERIFY(src) \
75780 (!((((u_int32_t)(src)\
75793 #define SYNTH4__DIS_LOSTVC__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30)
75794 #define SYNTH4__DIS_LOSTVC__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U)
75795 #define SYNTH4__DIS_LOSTVC__MODIFY(dst, src) \
75797 ~0x40000000U) | (((u_int32_t)(src) <<\
75799 #define SYNTH4__DIS_LOSTVC__VERIFY(src) \
75800 (!((((u_int32_t)(src)\
75813 #define SYNTH4__DIS_LIN_CAPSEARCH__READ(src) \
75814 (((u_int32_t)(src)\
75816 #define SYNTH4__DIS_LIN_CAPSEARCH__WRITE(src) \
75817 (((u_int32_t)(src)\
75819 #define SYNTH4__DIS_LIN_CAPSEARCH__MODIFY(dst, src) \
75821 ~0x80000000U) | (((u_int32_t)(src) <<\
75823 #define SYNTH4__DIS_LIN_CAPSEARCH__VERIFY(src) \
75824 (!((((u_int32_t)(src)\
75850 #define SYNTH5__VCOBIAS__READ(src) (u_int32_t)(src) & 0x00000003U
75851 #define SYNTH5__VCOBIAS__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
75852 #define SYNTH5__VCOBIAS__MODIFY(dst, src) \
75854 ~0x00000003U) | ((u_int32_t)(src) &\
75856 #define SYNTH5__VCOBIAS__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
75862 #define SYNTH5__PWDB_ICLOBUF5G50__READ(src) \
75863 (((u_int32_t)(src)\
75865 #define SYNTH5__PWDB_ICLOBUF5G50__WRITE(src) \
75866 (((u_int32_t)(src)\
75868 #define SYNTH5__PWDB_ICLOBUF5G50__MODIFY(dst, src) \
75870 ~0x0000001cU) | (((u_int32_t)(src) <<\
75872 #define SYNTH5__PWDB_ICLOBUF5G50__VERIFY(src) \
75873 (!((((u_int32_t)(src)\
75880 #define SYNTH5__PWDB_ICLOBUF2G50__READ(src) \
75881 (((u_int32_t)(src)\
75883 #define SYNTH5__PWDB_ICLOBUF2G50__WRITE(src) \
75884 (((u_int32_t)(src)\
75886 #define SYNTH5__PWDB_ICLOBUF2G50__MODIFY(dst, src) \
75888 ~0x000000e0U) | (((u_int32_t)(src) <<\
75890 #define SYNTH5__PWDB_ICLOBUF2G50__VERIFY(src) \
75891 (!((((u_int32_t)(src)\
75898 #define SYNTH5__PWDB_ICVCO25__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8)
75899 #define SYNTH5__PWDB_ICVCO25__WRITE(src) \
75900 (((u_int32_t)(src)\
75902 #define SYNTH5__PWDB_ICVCO25__MODIFY(dst, src) \
75904 ~0x00000700U) | (((u_int32_t)(src) <<\
75906 #define SYNTH5__PWDB_ICVCO25__VERIFY(src) \
75907 (!((((u_int32_t)(src)\
75914 #define SYNTH5__PWDB_ICVCOREG25__READ(src) \
75915 (((u_int32_t)(src)\
75917 #define SYNTH5__PWDB_ICVCOREG25__WRITE(src) \
75918 (((u_int32_t)(src)\
75920 #define SYNTH5__PWDB_ICVCOREG25__MODIFY(dst, src) \
75922 ~0x00003800U) | (((u_int32_t)(src) <<\
75924 #define SYNTH5__PWDB_ICVCOREG25__VERIFY(src) \
75925 (!((((u_int32_t)(src)\
75932 #define SYNTH5__PWDB_IRVCOREG50__READ(src) \
75933 (((u_int32_t)(src)\
75935 #define SYNTH5__PWDB_IRVCOREG50__WRITE(src) \
75936 (((u_int32_t)(src)\
75938 #define SYNTH5__PWDB_IRVCOREG50__MODIFY(dst, src) \
75940 ~0x00004000U) | (((u_int32_t)(src) <<\
75942 #define SYNTH5__PWDB_IRVCOREG50__VERIFY(src) \
75943 (!((((u_int32_t)(src)\
75956 #define SYNTH5__PWDB_ICLOMIX__READ(src) \
75957 (((u_int32_t)(src)\
75959 #define SYNTH5__PWDB_ICLOMIX__WRITE(src) \
75960 (((u_int32_t)(src)\
75962 #define SYNTH5__PWDB_ICLOMIX__MODIFY(dst, src) \
75964 ~0x00038000U) | (((u_int32_t)(src) <<\
75966 #define SYNTH5__PWDB_ICLOMIX__VERIFY(src) \
75967 (!((((u_int32_t)(src)\
75974 #define SYNTH5__PWDB_ICLODIV50__READ(src) \
75975 (((u_int32_t)(src)\
75977 #define SYNTH5__PWDB_ICLODIV50__WRITE(src) \
75978 (((u_int32_t)(src)\
75980 #define SYNTH5__PWDB_ICLODIV50__MODIFY(dst, src) \
75982 ~0x001c0000U) | (((u_int32_t)(src) <<\
75984 #define SYNTH5__PWDB_ICLODIV50__VERIFY(src) \
75985 (!((((u_int32_t)(src)\
75992 #define SYNTH5__PWDB_ICPRESC50__READ(src) \
75993 (((u_int32_t)(src)\
75995 #define SYNTH5__PWDB_ICPRESC50__WRITE(src) \
75996 (((u_int32_t)(src)\
75998 #define SYNTH5__PWDB_ICPRESC50__MODIFY(dst, src) \
76000 ~0x00e00000U) | (((u_int32_t)(src) <<\
76002 #define SYNTH5__PWDB_ICPRESC50__VERIFY(src) \
76003 (!((((u_int32_t)(src)\
76010 #define SYNTH5__PWDB_IRVCMON25__READ(src) \
76011 (((u_int32_t)(src)\
76013 #define SYNTH5__PWDB_IRVCMON25__WRITE(src) \
76014 (((u_int32_t)(src)\
76016 #define SYNTH5__PWDB_IRVCMON25__MODIFY(dst, src) \
76018 ~0x07000000U) | (((u_int32_t)(src) <<\
76020 #define SYNTH5__PWDB_IRVCMON25__VERIFY(src) \
76021 (!((((u_int32_t)(src)\
76028 #define SYNTH5__PWDB_IRPFDCP__READ(src) \
76029 (((u_int32_t)(src)\
76031 #define SYNTH5__PWDB_IRPFDCP__WRITE(src) \
76032 (((u_int32_t)(src)\
76034 #define SYNTH5__PWDB_IRPFDCP__MODIFY(dst, src) \
76036 ~0x38000000U) | (((u_int32_t)(src) <<\
76038 #define SYNTH5__PWDB_IRPFDCP__VERIFY(src) \
76039 (!((((u_int32_t)(src)\
76046 #define SYNTH5__SDM_DITHER2__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30)
76047 #define SYNTH5__SDM_DITHER2__WRITE(src) \
76048 (((u_int32_t)(src)\
76050 #define SYNTH5__SDM_DITHER2__MODIFY(dst, src) \
76052 ~0xc0000000U) | (((u_int32_t)(src) <<\
76054 #define SYNTH5__SDM_DITHER2__VERIFY(src) \
76055 (!((((u_int32_t)(src)\
76075 #define SYNTH6__LOBUF5GTUNE__READ(src) (u_int32_t)(src) & 0x00000003U
76081 #define SYNTH6__LOOP_IP__READ(src) (((u_int32_t)(src) & 0x000001fcU) >> 2)
76087 #define SYNTH6__VC2LOW__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9)
76099 #define SYNTH6__VC2HIGH__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
76111 #define SYNTH6__RESET_SDM_B__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
76123 #define SYNTH6__RESET_PSCOUNTERS__READ(src) \
76124 (((u_int32_t)(src)\
76137 #define SYNTH6__RESET_PFD__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13)
76149 #define SYNTH6__RESET_RFD__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14)
76161 #define SYNTH6__SHORT_R__READ(src) (((u_int32_t)(src) & 0x00008000U) >> 15)
76173 #define SYNTH6__VCO_CAP_ST__READ(src) (((u_int32_t)(src) & 0x00ff0000U) >> 16)
76179 #define SYNTH6__PIN_VC__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24)
76191 #define SYNTH6__SYNTH_LOCK_VC_OK__READ(src) \
76192 (((u_int32_t)(src)\
76205 #define SYNTH6__CAP_SEARCH__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26)
76217 #define SYNTH6__SYNTH_SM_STATE__READ(src) \
76218 (((u_int32_t)(src)\
76225 #define SYNTH6__SYNTH_ON__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
76249 #define SYNTH7__OVRCHANDECODER__READ(src) (u_int32_t)(src) & 0x00000001U
76250 #define SYNTH7__OVRCHANDECODER__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
76251 #define SYNTH7__OVRCHANDECODER__MODIFY(dst, src) \
76253 ~0x00000001U) | ((u_int32_t)(src) &\
76255 #define SYNTH7__OVRCHANDECODER__VERIFY(src) \
76256 (!(((u_int32_t)(src)\
76269 #define SYNTH7__FORCE_FRACLSB__READ(src) \
76270 (((u_int32_t)(src)\
76272 #define SYNTH7__FORCE_FRACLSB__WRITE(src) \
76273 (((u_int32_t)(src)\
76275 #define SYNTH7__FORCE_FRACLSB__MODIFY(dst, src) \
76277 ~0x00000002U) | (((u_int32_t)(src) <<\
76279 #define SYNTH7__FORCE_FRACLSB__VERIFY(src) \
76280 (!((((u_int32_t)(src)\
76293 #define SYNTH7__CHANFRAC__READ(src) (((u_int32_t)(src) & 0x0007fffcU) >> 2)
76294 #define SYNTH7__CHANFRAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0007fffcU)
76295 #define SYNTH7__CHANFRAC__MODIFY(dst, src) \
76297 ~0x0007fffcU) | (((u_int32_t)(src) <<\
76299 #define SYNTH7__CHANFRAC__VERIFY(src) \
76300 (!((((u_int32_t)(src)\
76307 #define SYNTH7__CHANSEL__READ(src) (((u_int32_t)(src) & 0x0ff80000U) >> 19)
76308 #define SYNTH7__CHANSEL__WRITE(src) (((u_int32_t)(src) << 19) & 0x0ff80000U)
76309 #define SYNTH7__CHANSEL__MODIFY(dst, src) \
76311 ~0x0ff80000U) | (((u_int32_t)(src) <<\
76313 #define SYNTH7__CHANSEL__VERIFY(src) \
76314 (!((((u_int32_t)(src)\
76321 #define SYNTH7__AMODEREFSEL__READ(src) (((u_int32_t)(src) & 0x30000000U) >> 28)
76322 #define SYNTH7__AMODEREFSEL__WRITE(src) \
76323 (((u_int32_t)(src)\
76325 #define SYNTH7__AMODEREFSEL__MODIFY(dst, src) \
76327 ~0x30000000U) | (((u_int32_t)(src) <<\
76329 #define SYNTH7__AMODEREFSEL__VERIFY(src) \
76330 (!((((u_int32_t)(src)\
76337 #define SYNTH7__FRACMODE__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30)
76338 #define SYNTH7__FRACMODE__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U)
76339 #define SYNTH7__FRACMODE__MODIFY(dst, src) \
76341 ~0x40000000U) | (((u_int32_t)(src) <<\
76343 #define SYNTH7__FRACMODE__VERIFY(src) \
76344 (!((((u_int32_t)(src)\
76357 #define SYNTH7__LOADSYNTHCHANNEL__READ(src) \
76358 (((u_int32_t)(src)\
76360 #define SYNTH7__LOADSYNTHCHANNEL__WRITE(src) \
76361 (((u_int32_t)(src)\
76363 #define SYNTH7__LOADSYNTHCHANNEL__MODIFY(dst, src) \
76365 ~0x80000000U) | (((u_int32_t)(src) <<\
76367 #define SYNTH7__LOADSYNTHCHANNEL__VERIFY(src) \
76368 (!((((u_int32_t)(src)\
76394 #define SYNTH8__CPSTEERING_EN_FRACN__READ(src) (u_int32_t)(src) & 0x00000001U
76395 #define SYNTH8__CPSTEERING_EN_FRACN__WRITE(src) \
76396 ((u_int32_t)(src)\
76398 #define SYNTH8__CPSTEERING_EN_FRACN__MODIFY(dst, src) \
76400 ~0x00000001U) | ((u_int32_t)(src) &\
76402 #define SYNTH8__CPSTEERING_EN_FRACN__VERIFY(src) \
76403 (!(((u_int32_t)(src)\
76416 #define SYNTH8__LOOP_ICPB__READ(src) (((u_int32_t)(src) & 0x000000feU) >> 1)
76417 #define SYNTH8__LOOP_ICPB__WRITE(src) (((u_int32_t)(src) << 1) & 0x000000feU)
76418 #define SYNTH8__LOOP_ICPB__MODIFY(dst, src) \
76420 ~0x000000feU) | (((u_int32_t)(src) <<\
76422 #define SYNTH8__LOOP_ICPB__VERIFY(src) \
76423 (!((((u_int32_t)(src)\
76430 #define SYNTH8__LOOP_CSB__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8)
76431 #define SYNTH8__LOOP_CSB__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U)
76432 #define SYNTH8__LOOP_CSB__MODIFY(dst, src) \
76434 ~0x00000f00U) | (((u_int32_t)(src) <<\
76436 #define SYNTH8__LOOP_CSB__VERIFY(src) \
76437 (!((((u_int32_t)(src)\
76444 #define SYNTH8__LOOP_RSB__READ(src) (((u_int32_t)(src) & 0x0001f000U) >> 12)
76445 #define SYNTH8__LOOP_RSB__WRITE(src) (((u_int32_t)(src) << 12) & 0x0001f000U)
76446 #define SYNTH8__LOOP_RSB__MODIFY(dst, src) \
76448 ~0x0001f000U) | (((u_int32_t)(src) <<\
76450 #define SYNTH8__LOOP_RSB__VERIFY(src) \
76451 (!((((u_int32_t)(src)\
76458 #define SYNTH8__LOOP_CPB__READ(src) (((u_int32_t)(src) & 0x003e0000U) >> 17)
76459 #define SYNTH8__LOOP_CPB__WRITE(src) (((u_int32_t)(src) << 17) & 0x003e0000U)
76460 #define SYNTH8__LOOP_CPB__MODIFY(dst, src) \
76462 ~0x003e0000U) | (((u_int32_t)(src) <<\
76464 #define SYNTH8__LOOP_CPB__VERIFY(src) \
76465 (!((((u_int32_t)(src)\
76472 #define SYNTH8__LOOP_3RD_ORDER_RB__READ(src) \
76473 (((u_int32_t)(src)\
76475 #define SYNTH8__LOOP_3RD_ORDER_RB__WRITE(src) \
76476 (((u_int32_t)(src)\
76478 #define SYNTH8__LOOP_3RD_ORDER_RB__MODIFY(dst, src) \
76480 ~0x07c00000U) | (((u_int32_t)(src) <<\
76482 #define SYNTH8__LOOP_3RD_ORDER_RB__VERIFY(src) \
76483 (!((((u_int32_t)(src)\
76490 #define SYNTH8__REFDIVB__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27)
76491 #define SYNTH8__REFDIVB__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U)
76492 #define SYNTH8__REFDIVB__MODIFY(dst, src) \
76494 ~0xf8000000U) | (((u_int32_t)(src) <<\
76496 #define SYNTH8__REFDIVB__VERIFY(src) \
76497 (!((((u_int32_t)(src)\
76517 #define SYNTH9__PFDDELAY_INTN__READ(src) (u_int32_t)(src) & 0x00000001U
76518 #define SYNTH9__PFDDELAY_INTN__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
76519 #define SYNTH9__PFDDELAY_INTN__MODIFY(dst, src) \
76521 ~0x00000001U) | ((u_int32_t)(src) &\
76523 #define SYNTH9__PFDDELAY_INTN__VERIFY(src) \
76524 (!(((u_int32_t)(src)\
76537 #define SYNTH9__SLOPE_ICPA0__READ(src) (((u_int32_t)(src) & 0x0000000eU) >> 1)
76538 #define SYNTH9__SLOPE_ICPA0__WRITE(src) (((u_int32_t)(src) << 1) & 0x0000000eU)
76539 #define SYNTH9__SLOPE_ICPA0__MODIFY(dst, src) \
76541 ~0x0000000eU) | (((u_int32_t)(src) <<\
76543 #define SYNTH9__SLOPE_ICPA0__VERIFY(src) \
76544 (!((((u_int32_t)(src)\
76551 #define SYNTH9__LOOP_ICPA0__READ(src) (((u_int32_t)(src) & 0x000000f0U) >> 4)
76552 #define SYNTH9__LOOP_ICPA0__WRITE(src) (((u_int32_t)(src) << 4) & 0x000000f0U)
76553 #define SYNTH9__LOOP_ICPA0__MODIFY(dst, src) \
76555 ~0x000000f0U) | (((u_int32_t)(src) <<\
76557 #define SYNTH9__LOOP_ICPA0__VERIFY(src) \
76558 (!((((u_int32_t)(src)\
76565 #define SYNTH9__LOOP_CSA0__READ(src) (((u_int32_t)(src) & 0x00000f00U) >> 8)
76566 #define SYNTH9__LOOP_CSA0__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000f00U)
76567 #define SYNTH9__LOOP_CSA0__MODIFY(dst, src) \
76569 ~0x00000f00U) | (((u_int32_t)(src) <<\
76571 #define SYNTH9__LOOP_CSA0__VERIFY(src) \
76572 (!((((u_int32_t)(src)\
76579 #define SYNTH9__LOOP_RSA0__READ(src) (((u_int32_t)(src) & 0x0001f000U) >> 12)
76580 #define SYNTH9__LOOP_RSA0__WRITE(src) (((u_int32_t)(src) << 12) & 0x0001f000U)
76581 #define SYNTH9__LOOP_RSA0__MODIFY(dst, src) \
76583 ~0x0001f000U) | (((u_int32_t)(src) <<\
76585 #define SYNTH9__LOOP_RSA0__VERIFY(src) \
76586 (!((((u_int32_t)(src)\
76593 #define SYNTH9__LOOP_CPA0__READ(src) (((u_int32_t)(src) & 0x003e0000U) >> 17)
76594 #define SYNTH9__LOOP_CPA0__WRITE(src) (((u_int32_t)(src) << 17) & 0x003e0000U)
76595 #define SYNTH9__LOOP_CPA0__MODIFY(dst, src) \
76597 ~0x003e0000U) | (((u_int32_t)(src) <<\
76599 #define SYNTH9__LOOP_CPA0__VERIFY(src) \
76600 (!((((u_int32_t)(src)\
76607 #define SYNTH9__LOOP_3RD_ORDER_RA__READ(src) \
76608 (((u_int32_t)(src)\
76610 #define SYNTH9__LOOP_3RD_ORDER_RA__WRITE(src) \
76611 (((u_int32_t)(src)\
76613 #define SYNTH9__LOOP_3RD_ORDER_RA__MODIFY(dst, src) \
76615 ~0x07c00000U) | (((u_int32_t)(src) <<\
76617 #define SYNTH9__LOOP_3RD_ORDER_RA__VERIFY(src) \
76618 (!((((u_int32_t)(src)\
76625 #define SYNTH9__REFDIVA__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27)
76626 #define SYNTH9__REFDIVA__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U)
76627 #define SYNTH9__REFDIVA__MODIFY(dst, src) \
76629 ~0xf8000000U) | (((u_int32_t)(src) <<\
76631 #define SYNTH9__REFDIVA__VERIFY(src) \
76632 (!((((u_int32_t)(src)\
76652 #define SYNTH10__SPARE10A__READ(src) (u_int32_t)(src) & 0x00000003U
76653 #define SYNTH10__SPARE10A__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
76654 #define SYNTH10__SPARE10A__MODIFY(dst, src) \
76656 ~0x00000003U) | ((u_int32_t)(src) &\
76658 #define SYNTH10__SPARE10A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
76664 #define SYNTH10__PWDB_ICLOBIAS50__READ(src) \
76665 (((u_int32_t)(src)\
76667 #define SYNTH10__PWDB_ICLOBIAS50__WRITE(src) \
76668 (((u_int32_t)(src)\
76670 #define SYNTH10__PWDB_ICLOBIAS50__MODIFY(dst, src) \
76672 ~0x0000001cU) | (((u_int32_t)(src) <<\
76674 #define SYNTH10__PWDB_ICLOBIAS50__VERIFY(src) \
76675 (!((((u_int32_t)(src)\
76682 #define SYNTH10__PWDB_IRSPARE25__READ(src) \
76683 (((u_int32_t)(src)\
76685 #define SYNTH10__PWDB_IRSPARE25__WRITE(src) \
76686 (((u_int32_t)(src)\
76688 #define SYNTH10__PWDB_IRSPARE25__MODIFY(dst, src) \
76690 ~0x000000e0U) | (((u_int32_t)(src) <<\
76692 #define SYNTH10__PWDB_IRSPARE25__VERIFY(src) \
76693 (!((((u_int32_t)(src)\
76700 #define SYNTH10__PWDB_ICSPARE25__READ(src) \
76701 (((u_int32_t)(src)\
76703 #define SYNTH10__PWDB_ICSPARE25__WRITE(src) \
76704 (((u_int32_t)(src)\
76706 #define SYNTH10__PWDB_ICSPARE25__MODIFY(dst, src) \
76708 ~0x00000700U) | (((u_int32_t)(src) <<\
76710 #define SYNTH10__PWDB_ICSPARE25__VERIFY(src) \
76711 (!((((u_int32_t)(src)\
76718 #define SYNTH10__SLOPE_ICPA1__READ(src) \
76719 (((u_int32_t)(src)\
76721 #define SYNTH10__SLOPE_ICPA1__WRITE(src) \
76722 (((u_int32_t)(src)\
76724 #define SYNTH10__SLOPE_ICPA1__MODIFY(dst, src) \
76726 ~0x00003800U) | (((u_int32_t)(src) <<\
76728 #define SYNTH10__SLOPE_ICPA1__VERIFY(src) \
76729 (!((((u_int32_t)(src)\
76736 #define SYNTH10__LOOP_ICPA1__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14)
76737 #define SYNTH10__LOOP_ICPA1__WRITE(src) \
76738 (((u_int32_t)(src)\
76740 #define SYNTH10__LOOP_ICPA1__MODIFY(dst, src) \
76742 ~0x0003c000U) | (((u_int32_t)(src) <<\
76744 #define SYNTH10__LOOP_ICPA1__VERIFY(src) \
76745 (!((((u_int32_t)(src)\
76752 #define SYNTH10__LOOP_CSA1__READ(src) (((u_int32_t)(src) & 0x003c0000U) >> 18)
76753 #define SYNTH10__LOOP_CSA1__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U)
76754 #define SYNTH10__LOOP_CSA1__MODIFY(dst, src) \
76756 ~0x003c0000U) | (((u_int32_t)(src) <<\
76758 #define SYNTH10__LOOP_CSA1__VERIFY(src) \
76759 (!((((u_int32_t)(src)\
76766 #define SYNTH10__LOOP_RSA1__READ(src) (((u_int32_t)(src) & 0x07c00000U) >> 22)
76767 #define SYNTH10__LOOP_RSA1__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U)
76768 #define SYNTH10__LOOP_RSA1__MODIFY(dst, src) \
76770 ~0x07c00000U) | (((u_int32_t)(src) <<\
76772 #define SYNTH10__LOOP_RSA1__VERIFY(src) \
76773 (!((((u_int32_t)(src)\
76780 #define SYNTH10__LOOP_CPA1__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27)
76781 #define SYNTH10__LOOP_CPA1__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U)
76782 #define SYNTH10__LOOP_CPA1__MODIFY(dst, src) \
76784 ~0xf8000000U) | (((u_int32_t)(src) <<\
76786 #define SYNTH10__LOOP_CPA1__VERIFY(src) \
76787 (!((((u_int32_t)(src)\
76807 #define SYNTH11__SPARE11A__READ(src) (u_int32_t)(src) & 0x0000001fU
76808 #define SYNTH11__SPARE11A__WRITE(src) ((u_int32_t)(src) & 0x0000001fU)
76809 #define SYNTH11__SPARE11A__MODIFY(dst, src) \
76811 ~0x0000001fU) | ((u_int32_t)(src) &\
76813 #define SYNTH11__SPARE11A__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))
76819 #define SYNTH11__FORCE_LOBUF5G_ON__READ(src) \
76820 (((u_int32_t)(src)\
76822 #define SYNTH11__FORCE_LOBUF5G_ON__WRITE(src) \
76823 (((u_int32_t)(src)\
76825 #define SYNTH11__FORCE_LOBUF5G_ON__MODIFY(dst, src) \
76827 ~0x00000020U) | (((u_int32_t)(src) <<\
76829 #define SYNTH11__FORCE_LOBUF5G_ON__VERIFY(src) \
76830 (!((((u_int32_t)(src)\
76843 #define SYNTH11__LOREFSEL__READ(src) (((u_int32_t)(src) & 0x000000c0U) >> 6)
76844 #define SYNTH11__LOREFSEL__WRITE(src) (((u_int32_t)(src) << 6) & 0x000000c0U)
76845 #define SYNTH11__LOREFSEL__MODIFY(dst, src) \
76847 ~0x000000c0U) | (((u_int32_t)(src) <<\
76849 #define SYNTH11__LOREFSEL__VERIFY(src) \
76850 (!((((u_int32_t)(src)\
76857 #define SYNTH11__LOBUF2GTUNE__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8)
76858 #define SYNTH11__LOBUF2GTUNE__WRITE(src) \
76859 (((u_int32_t)(src)\
76861 #define SYNTH11__LOBUF2GTUNE__MODIFY(dst, src) \
76863 ~0x00000300U) | (((u_int32_t)(src) <<\
76865 #define SYNTH11__LOBUF2GTUNE__VERIFY(src) \
76866 (!((((u_int32_t)(src)\
76873 #define SYNTH11__CPSTEERING_MODE__READ(src) \
76874 (((u_int32_t)(src)\
76876 #define SYNTH11__CPSTEERING_MODE__WRITE(src) \
76877 (((u_int32_t)(src)\
76879 #define SYNTH11__CPSTEERING_MODE__MODIFY(dst, src) \
76881 ~0x00000400U) | (((u_int32_t)(src) <<\
76883 #define SYNTH11__CPSTEERING_MODE__VERIFY(src) \
76884 (!((((u_int32_t)(src)\
76897 #define SYNTH11__SLOPE_ICPA2__READ(src) \
76898 (((u_int32_t)(src)\
76900 #define SYNTH11__SLOPE_ICPA2__WRITE(src) \
76901 (((u_int32_t)(src)\
76903 #define SYNTH11__SLOPE_ICPA2__MODIFY(dst, src) \
76905 ~0x00003800U) | (((u_int32_t)(src) <<\
76907 #define SYNTH11__SLOPE_ICPA2__VERIFY(src) \
76908 (!((((u_int32_t)(src)\
76915 #define SYNTH11__LOOP_ICPA2__READ(src) (((u_int32_t)(src) & 0x0003c000U) >> 14)
76916 #define SYNTH11__LOOP_ICPA2__WRITE(src) \
76917 (((u_int32_t)(src)\
76919 #define SYNTH11__LOOP_ICPA2__MODIFY(dst, src) \
76921 ~0x0003c000U) | (((u_int32_t)(src) <<\
76923 #define SYNTH11__LOOP_ICPA2__VERIFY(src) \
76924 (!((((u_int32_t)(src)\
76931 #define SYNTH11__LOOP_CSA2__READ(src) (((u_int32_t)(src) & 0x003c0000U) >> 18)
76932 #define SYNTH11__LOOP_CSA2__WRITE(src) (((u_int32_t)(src) << 18) & 0x003c0000U)
76933 #define SYNTH11__LOOP_CSA2__MODIFY(dst, src) \
76935 ~0x003c0000U) | (((u_int32_t)(src) <<\
76937 #define SYNTH11__LOOP_CSA2__VERIFY(src) \
76938 (!((((u_int32_t)(src)\
76945 #define SYNTH11__LOOP_RSA2__READ(src) (((u_int32_t)(src) & 0x07c00000U) >> 22)
76946 #define SYNTH11__LOOP_RSA2__WRITE(src) (((u_int32_t)(src) << 22) & 0x07c00000U)
76947 #define SYNTH11__LOOP_RSA2__MODIFY(dst, src) \
76949 ~0x07c00000U) | (((u_int32_t)(src) <<\
76951 #define SYNTH11__LOOP_RSA2__VERIFY(src) \
76952 (!((((u_int32_t)(src)\
76959 #define SYNTH11__LOOP_CPA2__READ(src) (((u_int32_t)(src) & 0xf8000000U) >> 27)
76960 #define SYNTH11__LOOP_CPA2__WRITE(src) (((u_int32_t)(src) << 27) & 0xf8000000U)
76961 #define SYNTH11__LOOP_CPA2__MODIFY(dst, src) \
76963 ~0xf8000000U) | (((u_int32_t)(src) <<\
76965 #define SYNTH11__LOOP_CPA2__VERIFY(src) \
76966 (!((((u_int32_t)(src)\
76986 #define SYNTH12__SPARE12A__READ(src) (u_int32_t)(src) & 0x000003ffU
76987 #define SYNTH12__SPARE12A__WRITE(src) ((u_int32_t)(src) & 0x000003ffU)
76988 #define SYNTH12__SPARE12A__MODIFY(dst, src) \
76990 ~0x000003ffU) | ((u_int32_t)(src) &\
76992 #define SYNTH12__SPARE12A__VERIFY(src) (!(((u_int32_t)(src) & ~0x000003ffU)))
76998 #define SYNTH12__LOOPLEAKCUR_FRACN__READ(src) \
76999 (((u_int32_t)(src)\
77001 #define SYNTH12__LOOPLEAKCUR_FRACN__WRITE(src) \
77002 (((u_int32_t)(src)\
77004 #define SYNTH12__LOOPLEAKCUR_FRACN__MODIFY(dst, src) \
77006 ~0x00003c00U) | (((u_int32_t)(src) <<\
77008 #define SYNTH12__LOOPLEAKCUR_FRACN__VERIFY(src) \
77009 (!((((u_int32_t)(src)\
77016 #define SYNTH12__CPLOWLK_FRACN__READ(src) \
77017 (((u_int32_t)(src)\
77019 #define SYNTH12__CPLOWLK_FRACN__WRITE(src) \
77020 (((u_int32_t)(src)\
77022 #define SYNTH12__CPLOWLK_FRACN__MODIFY(dst, src) \
77024 ~0x00004000U) | (((u_int32_t)(src) <<\
77026 #define SYNTH12__CPLOWLK_FRACN__VERIFY(src) \
77027 (!((((u_int32_t)(src)\
77040 #define SYNTH12__CPBIAS_FRACN__READ(src) \
77041 (((u_int32_t)(src)\
77043 #define SYNTH12__CPBIAS_FRACN__WRITE(src) \
77044 (((u_int32_t)(src)\
77046 #define SYNTH12__CPBIAS_FRACN__MODIFY(dst, src) \
77048 ~0x00018000U) | (((u_int32_t)(src) <<\
77050 #define SYNTH12__CPBIAS_FRACN__VERIFY(src) \
77051 (!((((u_int32_t)(src)\
77058 #define SYNTH12__SYNTHDIGOUTEN__READ(src) \
77059 (((u_int32_t)(src)\
77061 #define SYNTH12__SYNTHDIGOUTEN__WRITE(src) \
77062 (((u_int32_t)(src)\
77064 #define SYNTH12__SYNTHDIGOUTEN__MODIFY(dst, src) \
77066 ~0x00020000U) | (((u_int32_t)(src) <<\
77068 #define SYNTH12__SYNTHDIGOUTEN__VERIFY(src) \
77069 (!((((u_int32_t)(src)\
77082 #define SYNTH12__STRCONT__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18)
77083 #define SYNTH12__STRCONT__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U)
77084 #define SYNTH12__STRCONT__MODIFY(dst, src) \
77086 ~0x00040000U) | (((u_int32_t)(src) <<\
77088 #define SYNTH12__STRCONT__VERIFY(src) \
77089 (!((((u_int32_t)(src)\
77102 #define SYNTH12__VREFMUL3__READ(src) (((u_int32_t)(src) & 0x00780000U) >> 19)
77103 #define SYNTH12__VREFMUL3__WRITE(src) (((u_int32_t)(src) << 19) & 0x00780000U)
77104 #define SYNTH12__VREFMUL3__MODIFY(dst, src) \
77106 ~0x00780000U) | (((u_int32_t)(src) <<\
77108 #define SYNTH12__VREFMUL3__VERIFY(src) \
77109 (!((((u_int32_t)(src)\
77116 #define SYNTH12__VREFMUL2__READ(src) (((u_int32_t)(src) & 0x07800000U) >> 23)
77117 #define SYNTH12__VREFMUL2__WRITE(src) (((u_int32_t)(src) << 23) & 0x07800000U)
77118 #define SYNTH12__VREFMUL2__MODIFY(dst, src) \
77120 ~0x07800000U) | (((u_int32_t)(src) <<\
77122 #define SYNTH12__VREFMUL2__VERIFY(src) \
77123 (!((((u_int32_t)(src)\
77130 #define SYNTH12__VREFMUL1__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27)
77131 #define SYNTH12__VREFMUL1__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U)
77132 #define SYNTH12__VREFMUL1__MODIFY(dst, src) \
77134 ~0x78000000U) | (((u_int32_t)(src) <<\
77136 #define SYNTH12__VREFMUL1__VERIFY(src) \
77137 (!((((u_int32_t)(src)\
77144 #define SYNTH12__CLK_DOUBLER_EN__READ(src) \
77145 (((u_int32_t)(src)\
77147 #define SYNTH12__CLK_DOUBLER_EN__WRITE(src) \
77148 (((u_int32_t)(src)\
77150 #define SYNTH12__CLK_DOUBLER_EN__MODIFY(dst, src) \
77152 ~0x80000000U) | (((u_int32_t)(src) <<\
77154 #define SYNTH12__CLK_DOUBLER_EN__VERIFY(src) \
77155 (!((((u_int32_t)(src)\
77181 #define SYNTH13__SPARE13A__READ(src) (u_int32_t)(src) & 0x00000001U
77182 #define SYNTH13__SPARE13A__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
77183 #define SYNTH13__SPARE13A__MODIFY(dst, src) \
77185 ~0x00000001U) | ((u_int32_t)(src) &\
77187 #define SYNTH13__SPARE13A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
77199 #define SYNTH13__SLOPE_ICPA_FRACN__READ(src) \
77200 (((u_int32_t)(src)\
77202 #define SYNTH13__SLOPE_ICPA_FRACN__WRITE(src) \
77203 (((u_int32_t)(src)\
77205 #define SYNTH13__SLOPE_ICPA_FRACN__MODIFY(dst, src) \
77207 ~0x0000000eU) | (((u_int32_t)(src) <<\
77209 #define SYNTH13__SLOPE_ICPA_FRACN__VERIFY(src) \
77210 (!((((u_int32_t)(src)\
77217 #define SYNTH13__LOOP_ICPA_FRACN__READ(src) \
77218 (((u_int32_t)(src)\
77220 #define SYNTH13__LOOP_ICPA_FRACN__WRITE(src) \
77221 (((u_int32_t)(src)\
77223 #define SYNTH13__LOOP_ICPA_FRACN__MODIFY(dst, src) \
77225 ~0x000000f0U) | (((u_int32_t)(src) <<\
77227 #define SYNTH13__LOOP_ICPA_FRACN__VERIFY(src) \
77228 (!((((u_int32_t)(src)\
77235 #define SYNTH13__LOOP_CSA_FRACN__READ(src) \
77236 (((u_int32_t)(src)\
77238 #define SYNTH13__LOOP_CSA_FRACN__WRITE(src) \
77239 (((u_int32_t)(src)\
77241 #define SYNTH13__LOOP_CSA_FRACN__MODIFY(dst, src) \
77243 ~0x00000f00U) | (((u_int32_t)(src) <<\
77245 #define SYNTH13__LOOP_CSA_FRACN__VERIFY(src) \
77246 (!((((u_int32_t)(src)\
77253 #define SYNTH13__LOOP_RSA_FRACN__READ(src) \
77254 (((u_int32_t)(src)\
77256 #define SYNTH13__LOOP_RSA_FRACN__WRITE(src) \
77257 (((u_int32_t)(src)\
77259 #define SYNTH13__LOOP_RSA_FRACN__MODIFY(dst, src) \
77261 ~0x0001f000U) | (((u_int32_t)(src) <<\
77263 #define SYNTH13__LOOP_RSA_FRACN__VERIFY(src) \
77264 (!((((u_int32_t)(src)\
77271 #define SYNTH13__LOOP_CPA_FRACN__READ(src) \
77272 (((u_int32_t)(src)\
77274 #define SYNTH13__LOOP_CPA_FRACN__WRITE(src) \
77275 (((u_int32_t)(src)\
77277 #define SYNTH13__LOOP_CPA_FRACN__MODIFY(dst, src) \
77279 ~0x003e0000U) | (((u_int32_t)(src) <<\
77281 #define SYNTH13__LOOP_CPA_FRACN__VERIFY(src) \
77282 (!((((u_int32_t)(src)\
77289 #define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__READ(src) \
77290 (((u_int32_t)(src)\
77292 #define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__WRITE(src) \
77293 (((u_int32_t)(src)\
77295 #define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__MODIFY(dst, src) \
77297 ~0x07c00000U) | (((u_int32_t)(src) <<\
77299 #define SYNTH13__LOOP_3RD_ORDER_RA_FRACN__VERIFY(src) \
77300 (!((((u_int32_t)(src)\
77307 #define SYNTH13__REFDIVA_FRACN__READ(src) \
77308 (((u_int32_t)(src)\
77310 #define SYNTH13__REFDIVA_FRACN__WRITE(src) \
77311 (((u_int32_t)(src)\
77313 #define SYNTH13__REFDIVA_FRACN__MODIFY(dst, src) \
77315 ~0xf8000000U) | (((u_int32_t)(src) <<\
77317 #define SYNTH13__REFDIVA_FRACN__VERIFY(src) \
77318 (!((((u_int32_t)(src)\
77338 #define SYNTH14__SPARE14A__READ(src) (u_int32_t)(src) & 0x00000003U
77339 #define SYNTH14__SPARE14A__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
77340 #define SYNTH14__SPARE14A__MODIFY(dst, src) \
77342 ~0x00000003U) | ((u_int32_t)(src) &\
77344 #define SYNTH14__SPARE14A__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
77350 #define SYNTH14__LOBUF5GTUNE_3__READ(src) \
77351 (((u_int32_t)(src)\
77353 #define SYNTH14__LOBUF5GTUNE_3__WRITE(src) \
77354 (((u_int32_t)(src)\
77356 #define SYNTH14__LOBUF5GTUNE_3__MODIFY(dst, src) \
77358 ~0x0000000cU) | (((u_int32_t)(src) <<\
77360 #define SYNTH14__LOBUF5GTUNE_3__VERIFY(src) \
77361 (!((((u_int32_t)(src)\
77368 #define SYNTH14__LOBUF2GTUNE_3__READ(src) \
77369 (((u_int32_t)(src)\
77371 #define SYNTH14__LOBUF2GTUNE_3__WRITE(src) \
77372 (((u_int32_t)(src)\
77374 #define SYNTH14__LOBUF2GTUNE_3__MODIFY(dst, src) \
77376 ~0x00000030U) | (((u_int32_t)(src) <<\
77378 #define SYNTH14__LOBUF2GTUNE_3__VERIFY(src) \
77379 (!((((u_int32_t)(src)\
77386 #define SYNTH14__LOBUF5GTUNE_2__READ(src) \
77387 (((u_int32_t)(src)\
77389 #define SYNTH14__LOBUF5GTUNE_2__WRITE(src) \
77390 (((u_int32_t)(src)\
77392 #define SYNTH14__LOBUF5GTUNE_2__MODIFY(dst, src) \
77394 ~0x000000c0U) | (((u_int32_t)(src) <<\
77396 #define SYNTH14__LOBUF5GTUNE_2__VERIFY(src) \
77397 (!((((u_int32_t)(src)\
77404 #define SYNTH14__LOBUF2GTUNE_2__READ(src) \
77405 (((u_int32_t)(src)\
77407 #define SYNTH14__LOBUF2GTUNE_2__WRITE(src) \
77408 (((u_int32_t)(src)\
77410 #define SYNTH14__LOBUF2GTUNE_2__MODIFY(dst, src) \
77412 ~0x00000300U) | (((u_int32_t)(src) <<\
77414 #define SYNTH14__LOBUF2GTUNE_2__VERIFY(src) \
77415 (!((((u_int32_t)(src)\
77422 #define SYNTH14__PWD_LOBUF5G_3__READ(src) \
77423 (((u_int32_t)(src)\
77425 #define SYNTH14__PWD_LOBUF5G_3__WRITE(src) \
77426 (((u_int32_t)(src)\
77428 #define SYNTH14__PWD_LOBUF5G_3__MODIFY(dst, src) \
77430 ~0x00000400U) | (((u_int32_t)(src) <<\
77432 #define SYNTH14__PWD_LOBUF5G_3__VERIFY(src) \
77433 (!((((u_int32_t)(src)\
77446 #define SYNTH14__PWD_LOBUF2G_3__READ(src) \
77447 (((u_int32_t)(src)\
77449 #define SYNTH14__PWD_LOBUF2G_3__WRITE(src) \
77450 (((u_int32_t)(src)\
77452 #define SYNTH14__PWD_LOBUF2G_3__MODIFY(dst, src) \
77454 ~0x00000800U) | (((u_int32_t)(src) <<\
77456 #define SYNTH14__PWD_LOBUF2G_3__VERIFY(src) \
77457 (!((((u_int32_t)(src)\
77470 #define SYNTH14__PWD_LOBUF5G_2__READ(src) \
77471 (((u_int32_t)(src)\
77473 #define SYNTH14__PWD_LOBUF5G_2__WRITE(src) \
77474 (((u_int32_t)(src)\
77476 #define SYNTH14__PWD_LOBUF5G_2__MODIFY(dst, src) \
77478 ~0x00001000U) | (((u_int32_t)(src) <<\
77480 #define SYNTH14__PWD_LOBUF5G_2__VERIFY(src) \
77481 (!((((u_int32_t)(src)\
77494 #define SYNTH14__PWD_LOBUF2G_2__READ(src) \
77495 (((u_int32_t)(src)\
77497 #define SYNTH14__PWD_LOBUF2G_2__WRITE(src) \
77498 (((u_int32_t)(src)\
77500 #define SYNTH14__PWD_LOBUF2G_2__MODIFY(dst, src) \
77502 ~0x00002000U) | (((u_int32_t)(src) <<\
77504 #define SYNTH14__PWD_LOBUF2G_2__VERIFY(src) \
77505 (!((((u_int32_t)(src)\
77518 #define SYNTH14__PWUPLO23_PD__READ(src) \
77519 (((u_int32_t)(src)\
77521 #define SYNTH14__PWUPLO23_PD__WRITE(src) \
77522 (((u_int32_t)(src)\
77524 #define SYNTH14__PWUPLO23_PD__MODIFY(dst, src) \
77526 ~0x0001c000U) | (((u_int32_t)(src) <<\
77528 #define SYNTH14__PWUPLO23_PD__VERIFY(src) \
77529 (!((((u_int32_t)(src)\
77536 #define SYNTH14__PWDB_ICLOBUF5G50_3__READ(src) \
77537 (((u_int32_t)(src)\
77539 #define SYNTH14__PWDB_ICLOBUF5G50_3__WRITE(src) \
77540 (((u_int32_t)(src)\
77542 #define SYNTH14__PWDB_ICLOBUF5G50_3__MODIFY(dst, src) \
77544 ~0x000e0000U) | (((u_int32_t)(src) <<\
77546 #define SYNTH14__PWDB_ICLOBUF5G50_3__VERIFY(src) \
77547 (!((((u_int32_t)(src)\
77554 #define SYNTH14__PWDB_ICLOBUF2G50_3__READ(src) \
77555 (((u_int32_t)(src)\
77557 #define SYNTH14__PWDB_ICLOBUF2G50_3__WRITE(src) \
77558 (((u_int32_t)(src)\
77560 #define SYNTH14__PWDB_ICLOBUF2G50_3__MODIFY(dst, src) \
77562 ~0x00700000U) | (((u_int32_t)(src) <<\
77564 #define SYNTH14__PWDB_ICLOBUF2G50_3__VERIFY(src) \
77565 (!((((u_int32_t)(src)\
77572 #define SYNTH14__PWDB_ICLOBUF5G50_2__READ(src) \
77573 (((u_int32_t)(src)\
77575 #define SYNTH14__PWDB_ICLOBUF5G50_2__WRITE(src) \
77576 (((u_int32_t)(src)\
77578 #define SYNTH14__PWDB_ICLOBUF5G50_2__MODIFY(dst, src) \
77580 ~0x03800000U) | (((u_int32_t)(src) <<\
77582 #define SYNTH14__PWDB_ICLOBUF5G50_2__VERIFY(src) \
77583 (!((((u_int32_t)(src)\
77590 #define SYNTH14__PWDB_ICLOBUF2G50_2__READ(src) \
77591 (((u_int32_t)(src)\
77593 #define SYNTH14__PWDB_ICLOBUF2G50_2__WRITE(src) \
77594 (((u_int32_t)(src)\
77596 #define SYNTH14__PWDB_ICLOBUF2G50_2__MODIFY(dst, src) \
77598 ~0x1c000000U) | (((u_int32_t)(src) <<\
77600 #define SYNTH14__PWDB_ICLOBUF2G50_2__VERIFY(src) \
77601 (!((((u_int32_t)(src)\
77608 #define SYNTH14__PWDB_ICLVLSHFT__READ(src) \
77609 (((u_int32_t)(src)\
77611 #define SYNTH14__PWDB_ICLVLSHFT__WRITE(src) \
77612 (((u_int32_t)(src)\
77614 #define SYNTH14__PWDB_ICLVLSHFT__MODIFY(dst, src) \
77616 ~0xe0000000U) | (((u_int32_t)(src) <<\
77618 #define SYNTH14__PWDB_ICLVLSHFT__VERIFY(src) \
77619 (!((((u_int32_t)(src)\
77639 #define BIAS1__SPARE1__READ(src) (u_int32_t)(src) & 0x00000007U
77640 #define BIAS1__SPARE1__WRITE(src) ((u_int32_t)(src) & 0x00000007U)
77641 #define BIAS1__SPARE1__MODIFY(dst, src) \
77643 ~0x00000007U) | ((u_int32_t)(src) &\
77645 #define BIAS1__SPARE1__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U)))
77651 #define BIAS1__PWD_IC100PCIE__READ(src) (((u_int32_t)(src) & 0x00000038U) >> 3)
77652 #define BIAS1__PWD_IC100PCIE__WRITE(src) \
77653 (((u_int32_t)(src)\
77655 #define BIAS1__PWD_IC100PCIE__MODIFY(dst, src) \
77657 ~0x00000038U) | (((u_int32_t)(src) <<\
77659 #define BIAS1__PWD_IC100PCIE__VERIFY(src) \
77660 (!((((u_int32_t)(src)\
77667 #define BIAS1__PWD_IC25V2IQ__READ(src) (((u_int32_t)(src) & 0x000001c0U) >> 6)
77668 #define BIAS1__PWD_IC25V2IQ__WRITE(src) (((u_int32_t)(src) << 6) & 0x000001c0U)
77669 #define BIAS1__PWD_IC25V2IQ__MODIFY(dst, src) \
77671 ~0x000001c0U) | (((u_int32_t)(src) <<\
77673 #define BIAS1__PWD_IC25V2IQ__VERIFY(src) \
77674 (!((((u_int32_t)(src)\
77681 #define BIAS1__PWD_IC25V2II__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9)
77682 #define BIAS1__PWD_IC25V2II__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U)
77683 #define BIAS1__PWD_IC25V2II__MODIFY(dst, src) \
77685 ~0x00000e00U) | (((u_int32_t)(src) <<\
77687 #define BIAS1__PWD_IC25V2II__VERIFY(src) \
77688 (!((((u_int32_t)(src)\
77695 #define BIAS1__PWD_IC25BB__READ(src) (((u_int32_t)(src) & 0x00007000U) >> 12)
77696 #define BIAS1__PWD_IC25BB__WRITE(src) (((u_int32_t)(src) << 12) & 0x00007000U)
77697 #define BIAS1__PWD_IC25BB__MODIFY(dst, src) \
77699 ~0x00007000U) | (((u_int32_t)(src) <<\
77701 #define BIAS1__PWD_IC25BB__VERIFY(src) \
77702 (!((((u_int32_t)(src)\
77709 #define BIAS1__PWD_IC25DAC__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15)
77710 #define BIAS1__PWD_IC25DAC__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U)
77711 #define BIAS1__PWD_IC25DAC__MODIFY(dst, src) \
77713 ~0x00038000U) | (((u_int32_t)(src) <<\
77715 #define BIAS1__PWD_IC25DAC__VERIFY(src) \
77716 (!((((u_int32_t)(src)\
77723 #define BIAS1__PWD_IC25FIR__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18)
77724 #define BIAS1__PWD_IC25FIR__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U)
77725 #define BIAS1__PWD_IC25FIR__MODIFY(dst, src) \
77727 ~0x001c0000U) | (((u_int32_t)(src) <<\
77729 #define BIAS1__PWD_IC25FIR__VERIFY(src) \
77730 (!((((u_int32_t)(src)\
77737 #define BIAS1__PWD_IC25ADC__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21)
77738 #define BIAS1__PWD_IC25ADC__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U)
77739 #define BIAS1__PWD_IC25ADC__MODIFY(dst, src) \
77741 ~0x00e00000U) | (((u_int32_t)(src) <<\
77743 #define BIAS1__PWD_IC25ADC__VERIFY(src) \
77744 (!((((u_int32_t)(src)\
77751 #define BIAS1__BIAS_SEL__READ(src) (((u_int32_t)(src) & 0xff000000U) >> 24)
77752 #define BIAS1__BIAS_SEL__WRITE(src) (((u_int32_t)(src) << 24) & 0xff000000U)
77753 #define BIAS1__BIAS_SEL__MODIFY(dst, src) \
77755 ~0xff000000U) | (((u_int32_t)(src) <<\
77757 #define BIAS1__BIAS_SEL__VERIFY(src) \
77758 (!((((u_int32_t)(src)\
77778 #define BIAS2__SPARE2__READ(src) (u_int32_t)(src) & 0x0000001fU
77779 #define BIAS2__SPARE2__WRITE(src) ((u_int32_t)(src) & 0x0000001fU)
77780 #define BIAS2__SPARE2__MODIFY(dst, src) \
77782 ~0x0000001fU) | ((u_int32_t)(src) &\
77784 #define BIAS2__SPARE2__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000001fU)))
77790 #define BIAS2__PWD_IC25XTALREG__READ(src) \
77791 (((u_int32_t)(src)\
77793 #define BIAS2__PWD_IC25XTALREG__WRITE(src) \
77794 (((u_int32_t)(src)\
77796 #define BIAS2__PWD_IC25XTALREG__MODIFY(dst, src) \
77798 ~0x000000e0U) | (((u_int32_t)(src) <<\
77800 #define BIAS2__PWD_IC25XTALREG__VERIFY(src) \
77801 (!((((u_int32_t)(src)\
77808 #define BIAS2__PWD_IC25XTAL__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8)
77809 #define BIAS2__PWD_IC25XTAL__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U)
77810 #define BIAS2__PWD_IC25XTAL__MODIFY(dst, src) \
77812 ~0x00000700U) | (((u_int32_t)(src) <<\
77814 #define BIAS2__PWD_IC25XTAL__VERIFY(src) \
77815 (!((((u_int32_t)(src)\
77822 #define BIAS2__PWD_IC25TXRF__READ(src) (((u_int32_t)(src) & 0x00003800U) >> 11)
77823 #define BIAS2__PWD_IC25TXRF__WRITE(src) \
77824 (((u_int32_t)(src)\
77826 #define BIAS2__PWD_IC25TXRF__MODIFY(dst, src) \
77828 ~0x00003800U) | (((u_int32_t)(src) <<\
77830 #define BIAS2__PWD_IC25TXRF__VERIFY(src) \
77831 (!((((u_int32_t)(src)\
77838 #define BIAS2__PWD_IC25RXRF__READ(src) (((u_int32_t)(src) & 0x0001c000U) >> 14)
77839 #define BIAS2__PWD_IC25RXRF__WRITE(src) \
77840 (((u_int32_t)(src)\
77842 #define BIAS2__PWD_IC25RXRF__MODIFY(dst, src) \
77844 ~0x0001c000U) | (((u_int32_t)(src) <<\
77846 #define BIAS2__PWD_IC25RXRF__VERIFY(src) \
77847 (!((((u_int32_t)(src)\
77854 #define BIAS2__PWD_IC25SYNTH__READ(src) \
77855 (((u_int32_t)(src)\
77857 #define BIAS2__PWD_IC25SYNTH__WRITE(src) \
77858 (((u_int32_t)(src)\
77860 #define BIAS2__PWD_IC25SYNTH__MODIFY(dst, src) \
77862 ~0x000e0000U) | (((u_int32_t)(src) <<\
77864 #define BIAS2__PWD_IC25SYNTH__VERIFY(src) \
77865 (!((((u_int32_t)(src)\
77872 #define BIAS2__PWD_IC25PLLREG__READ(src) \
77873 (((u_int32_t)(src)\
77875 #define BIAS2__PWD_IC25PLLREG__WRITE(src) \
77876 (((u_int32_t)(src)\
77878 #define BIAS2__PWD_IC25PLLREG__MODIFY(dst, src) \
77880 ~0x00700000U) | (((u_int32_t)(src) <<\
77882 #define BIAS2__PWD_IC25PLLREG__VERIFY(src) \
77883 (!((((u_int32_t)(src)\
77890 #define BIAS2__PWD_IC25PLLCP2__READ(src) \
77891 (((u_int32_t)(src)\
77893 #define BIAS2__PWD_IC25PLLCP2__WRITE(src) \
77894 (((u_int32_t)(src)\
77896 #define BIAS2__PWD_IC25PLLCP2__MODIFY(dst, src) \
77898 ~0x03800000U) | (((u_int32_t)(src) <<\
77900 #define BIAS2__PWD_IC25PLLCP2__VERIFY(src) \
77901 (!((((u_int32_t)(src)\
77908 #define BIAS2__PWD_IC25PLLCP__READ(src) \
77909 (((u_int32_t)(src)\
77911 #define BIAS2__PWD_IC25PLLCP__WRITE(src) \
77912 (((u_int32_t)(src)\
77914 #define BIAS2__PWD_IC25PLLCP__MODIFY(dst, src) \
77916 ~0x1c000000U) | (((u_int32_t)(src) <<\
77918 #define BIAS2__PWD_IC25PLLCP__VERIFY(src) \
77919 (!((((u_int32_t)(src)\
77926 #define BIAS2__PWD_IC25PLLGM__READ(src) \
77927 (((u_int32_t)(src)\
77929 #define BIAS2__PWD_IC25PLLGM__WRITE(src) \
77930 (((u_int32_t)(src)\
77932 #define BIAS2__PWD_IC25PLLGM__MODIFY(dst, src) \
77934 ~0xe0000000U) | (((u_int32_t)(src) <<\
77936 #define BIAS2__PWD_IC25PLLGM__VERIFY(src) \
77937 (!((((u_int32_t)(src)\
77957 #define BIAS3__SPARE3__READ(src) (u_int32_t)(src) & 0x00000003U
77958 #define BIAS3__SPARE3__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
77959 #define BIAS3__SPARE3__MODIFY(dst, src) \
77961 ~0x00000003U) | ((u_int32_t)(src) &\
77963 #define BIAS3__SPARE3__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000003U)))
77969 #define BIAS3__PWD_IR25XTALREG__READ(src) \
77970 (((u_int32_t)(src)\
77972 #define BIAS3__PWD_IR25XTALREG__WRITE(src) \
77973 (((u_int32_t)(src)\
77975 #define BIAS3__PWD_IR25XTALREG__MODIFY(dst, src) \
77977 ~0x0000001cU) | (((u_int32_t)(src) <<\
77979 #define BIAS3__PWD_IR25XTALREG__VERIFY(src) \
77980 (!((((u_int32_t)(src)\
77987 #define BIAS3__PWD_IR25TXRF__READ(src) (((u_int32_t)(src) & 0x000000e0U) >> 5)
77988 #define BIAS3__PWD_IR25TXRF__WRITE(src) (((u_int32_t)(src) << 5) & 0x000000e0U)
77989 #define BIAS3__PWD_IR25TXRF__MODIFY(dst, src) \
77991 ~0x000000e0U) | (((u_int32_t)(src) <<\
77993 #define BIAS3__PWD_IR25TXRF__VERIFY(src) \
77994 (!((((u_int32_t)(src)\
78001 #define BIAS3__PWD_IR25RXRF__READ(src) (((u_int32_t)(src) & 0x00000700U) >> 8)
78002 #define BIAS3__PWD_IR25RXRF__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000700U)
78003 #define BIAS3__PWD_IR25RXRF__MODIFY(dst, src) \
78005 ~0x00000700U) | (((u_int32_t)(src) <<\
78007 #define BIAS3__PWD_IR25RXRF__VERIFY(src) \
78008 (!((((u_int32_t)(src)\
78015 #define BIAS3__PWD_IR25SYNTH__READ(src) \
78016 (((u_int32_t)(src)\
78018 #define BIAS3__PWD_IR25SYNTH__WRITE(src) \
78019 (((u_int32_t)(src)\
78021 #define BIAS3__PWD_IR25SYNTH__MODIFY(dst, src) \
78023 ~0x00003800U) | (((u_int32_t)(src) <<\
78025 #define BIAS3__PWD_IR25SYNTH__VERIFY(src) \
78026 (!((((u_int32_t)(src)\
78033 #define BIAS3__PWD_IR25PLLREG__READ(src) \
78034 (((u_int32_t)(src)\
78036 #define BIAS3__PWD_IR25PLLREG__WRITE(src) \
78037 (((u_int32_t)(src)\
78039 #define BIAS3__PWD_IR25PLLREG__MODIFY(dst, src) \
78041 ~0x0001c000U) | (((u_int32_t)(src) <<\
78043 #define BIAS3__PWD_IR25PLLREG__VERIFY(src) \
78044 (!((((u_int32_t)(src)\
78051 #define BIAS3__PWD_IR25BB__READ(src) (((u_int32_t)(src) & 0x000e0000U) >> 17)
78052 #define BIAS3__PWD_IR25BB__WRITE(src) (((u_int32_t)(src) << 17) & 0x000e0000U)
78053 #define BIAS3__PWD_IR25BB__MODIFY(dst, src) \
78055 ~0x000e0000U) | (((u_int32_t)(src) <<\
78057 #define BIAS3__PWD_IR25BB__VERIFY(src) \
78058 (!((((u_int32_t)(src)\
78065 #define BIAS3__PWD_IR50DAC__READ(src) (((u_int32_t)(src) & 0x00700000U) >> 20)
78066 #define BIAS3__PWD_IR50DAC__WRITE(src) (((u_int32_t)(src) << 20) & 0x00700000U)
78067 #define BIAS3__PWD_IR50DAC__MODIFY(dst, src) \
78069 ~0x00700000U) | (((u_int32_t)(src) <<\
78071 #define BIAS3__PWD_IR50DAC__VERIFY(src) \
78072 (!((((u_int32_t)(src)\
78079 #define BIAS3__PWD_IR25DAC__READ(src) (((u_int32_t)(src) & 0x03800000U) >> 23)
78080 #define BIAS3__PWD_IR25DAC__WRITE(src) (((u_int32_t)(src) << 23) & 0x03800000U)
78081 #define BIAS3__PWD_IR25DAC__MODIFY(dst, src) \
78083 ~0x03800000U) | (((u_int32_t)(src) <<\
78085 #define BIAS3__PWD_IR25DAC__VERIFY(src) \
78086 (!((((u_int32_t)(src)\
78093 #define BIAS3__PWD_IR25FIR__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26)
78094 #define BIAS3__PWD_IR25FIR__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U)
78095 #define BIAS3__PWD_IR25FIR__MODIFY(dst, src) \
78097 ~0x1c000000U) | (((u_int32_t)(src) <<\
78099 #define BIAS3__PWD_IR25FIR__VERIFY(src) \
78100 (!((((u_int32_t)(src)\
78107 #define BIAS3__PWD_IR50ADC__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29)
78108 #define BIAS3__PWD_IR50ADC__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U)
78109 #define BIAS3__PWD_IR50ADC__MODIFY(dst, src) \
78111 ~0xe0000000U) | (((u_int32_t)(src) <<\
78113 #define BIAS3__PWD_IR50ADC__VERIFY(src) \
78114 (!((((u_int32_t)(src)\
78134 #define BIAS4__SPARE4__READ(src) (u_int32_t)(src) & 0x00003fffU
78135 #define BIAS4__SPARE4__WRITE(src) ((u_int32_t)(src) & 0x00003fffU)
78136 #define BIAS4__SPARE4__MODIFY(dst, src) \
78138 ~0x00003fffU) | ((u_int32_t)(src) &\
78140 #define BIAS4__SPARE4__VERIFY(src) (!(((u_int32_t)(src) & ~0x00003fffU)))
78146 #define BIAS4__PWD_IR25XPABIAS__READ(src) \
78147 (((u_int32_t)(src)\
78149 #define BIAS4__PWD_IR25XPABIAS__WRITE(src) \
78150 (((u_int32_t)(src)\
78152 #define BIAS4__PWD_IR25XPABIAS__MODIFY(dst, src) \
78154 ~0x0001c000U) | (((u_int32_t)(src) <<\
78156 #define BIAS4__PWD_IR25XPABIAS__VERIFY(src) \
78157 (!((((u_int32_t)(src)\
78164 #define BIAS4__PWD_IR25THERMADC__READ(src) \
78165 (((u_int32_t)(src)\
78167 #define BIAS4__PWD_IR25THERMADC__WRITE(src) \
78168 (((u_int32_t)(src)\
78170 #define BIAS4__PWD_IR25THERMADC__MODIFY(dst, src) \
78172 ~0x000e0000U) | (((u_int32_t)(src) <<\
78174 #define BIAS4__PWD_IR25THERMADC__VERIFY(src) \
78175 (!((((u_int32_t)(src)\
78182 #define BIAS4__PWD_IR25OTPREG__READ(src) \
78183 (((u_int32_t)(src)\
78185 #define BIAS4__PWD_IR25OTPREG__WRITE(src) \
78186 (((u_int32_t)(src)\
78188 #define BIAS4__PWD_IR25OTPREG__MODIFY(dst, src) \
78190 ~0x00700000U) | (((u_int32_t)(src) <<\
78192 #define BIAS4__PWD_IR25OTPREG__VERIFY(src) \
78193 (!((((u_int32_t)(src)\
78200 #define BIAS4__PWD_IC25XPABIAS__READ(src) \
78201 (((u_int32_t)(src)\
78203 #define BIAS4__PWD_IC25XPABIAS__WRITE(src) \
78204 (((u_int32_t)(src)\
78206 #define BIAS4__PWD_IC25XPABIAS__MODIFY(dst, src) \
78208 ~0x03800000U) | (((u_int32_t)(src) <<\
78210 #define BIAS4__PWD_IC25XPABIAS__VERIFY(src) \
78211 (!((((u_int32_t)(src)\
78218 #define BIAS4__PWD_IC25SPAREB__READ(src) \
78219 (((u_int32_t)(src)\
78221 #define BIAS4__PWD_IC25SPAREB__WRITE(src) \
78222 (((u_int32_t)(src)\
78224 #define BIAS4__PWD_IC25SPAREB__MODIFY(dst, src) \
78226 ~0x1c000000U) | (((u_int32_t)(src) <<\
78228 #define BIAS4__PWD_IC25SPAREB__VERIFY(src) \
78229 (!((((u_int32_t)(src)\
78236 #define BIAS4__PWD_IC25SPAREA__READ(src) \
78237 (((u_int32_t)(src)\
78239 #define BIAS4__PWD_IC25SPAREA__WRITE(src) \
78240 (((u_int32_t)(src)\
78242 #define BIAS4__PWD_IC25SPAREA__MODIFY(dst, src) \
78244 ~0xe0000000U) | (((u_int32_t)(src) <<\
78246 #define BIAS4__PWD_IC25SPAREA__VERIFY(src) \
78247 (!((((u_int32_t)(src)\
78267 #define RXTX1__SCFIR_GAIN__READ(src) (u_int32_t)(src) & 0x00000001U
78268 #define RXTX1__SCFIR_GAIN__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
78269 #define RXTX1__SCFIR_GAIN__MODIFY(dst, src) \
78271 ~0x00000001U) | ((u_int32_t)(src) &\
78273 #define RXTX1__SCFIR_GAIN__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
78285 #define RXTX1__MANRXGAIN__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
78286 #define RXTX1__MANRXGAIN__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
78287 #define RXTX1__MANRXGAIN__MODIFY(dst, src) \
78289 ~0x00000002U) | (((u_int32_t)(src) <<\
78291 #define RXTX1__MANRXGAIN__VERIFY(src) \
78292 (!((((u_int32_t)(src)\
78305 #define RXTX1__AGC_DBDAC__READ(src) (((u_int32_t)(src) & 0x0000003cU) >> 2)
78306 #define RXTX1__AGC_DBDAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0000003cU)
78307 #define RXTX1__AGC_DBDAC__MODIFY(dst, src) \
78309 ~0x0000003cU) | (((u_int32_t)(src) <<\
78311 #define RXTX1__AGC_DBDAC__VERIFY(src) \
78312 (!((((u_int32_t)(src)\
78319 #define RXTX1__OVR_AGC_DBDAC__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6)
78320 #define RXTX1__OVR_AGC_DBDAC__WRITE(src) \
78321 (((u_int32_t)(src)\
78323 #define RXTX1__OVR_AGC_DBDAC__MODIFY(dst, src) \
78325 ~0x00000040U) | (((u_int32_t)(src) <<\
78327 #define RXTX1__OVR_AGC_DBDAC__VERIFY(src) \
78328 (!((((u_int32_t)(src)\
78341 #define RXTX1__ENABLE_PAL__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7)
78342 #define RXTX1__ENABLE_PAL__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U)
78343 #define RXTX1__ENABLE_PAL__MODIFY(dst, src) \
78345 ~0x00000080U) | (((u_int32_t)(src) <<\
78347 #define RXTX1__ENABLE_PAL__VERIFY(src) \
78348 (!((((u_int32_t)(src)\
78361 #define RXTX1__ENABLE_PAL_OVR__READ(src) \
78362 (((u_int32_t)(src)\
78364 #define RXTX1__ENABLE_PAL_OVR__WRITE(src) \
78365 (((u_int32_t)(src)\
78367 #define RXTX1__ENABLE_PAL_OVR__MODIFY(dst, src) \
78369 ~0x00000100U) | (((u_int32_t)(src) <<\
78371 #define RXTX1__ENABLE_PAL_OVR__VERIFY(src) \
78372 (!((((u_int32_t)(src)\
78385 #define RXTX1__TX1DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9)
78386 #define RXTX1__TX1DB_BIQUAD__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000e00U)
78387 #define RXTX1__TX1DB_BIQUAD__MODIFY(dst, src) \
78389 ~0x00000e00U) | (((u_int32_t)(src) <<\
78391 #define RXTX1__TX1DB_BIQUAD__VERIFY(src) \
78392 (!((((u_int32_t)(src)\
78399 #define RXTX1__TX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00003000U) >> 12)
78400 #define RXTX1__TX6DB_BIQUAD__WRITE(src) \
78401 (((u_int32_t)(src)\
78403 #define RXTX1__TX6DB_BIQUAD__MODIFY(dst, src) \
78405 ~0x00003000U) | (((u_int32_t)(src) <<\
78407 #define RXTX1__TX6DB_BIQUAD__VERIFY(src) \
78408 (!((((u_int32_t)(src)\
78415 #define RXTX1__PADRVHALFGN2G__READ(src) \
78416 (((u_int32_t)(src)\
78418 #define RXTX1__PADRVHALFGN2G__WRITE(src) \
78419 (((u_int32_t)(src)\
78421 #define RXTX1__PADRVHALFGN2G__MODIFY(dst, src) \
78423 ~0x00004000U) | (((u_int32_t)(src) <<\
78425 #define RXTX1__PADRVHALFGN2G__VERIFY(src) \
78426 (!((((u_int32_t)(src)\
78439 #define RXTX1__PADRV2GN__READ(src) (((u_int32_t)(src) & 0x00078000U) >> 15)
78440 #define RXTX1__PADRV2GN__WRITE(src) (((u_int32_t)(src) << 15) & 0x00078000U)
78441 #define RXTX1__PADRV2GN__MODIFY(dst, src) \
78443 ~0x00078000U) | (((u_int32_t)(src) <<\
78445 #define RXTX1__PADRV2GN__VERIFY(src) \
78446 (!((((u_int32_t)(src)\
78453 #define RXTX1__PADRV3GN5G__READ(src) (((u_int32_t)(src) & 0x00780000U) >> 19)
78454 #define RXTX1__PADRV3GN5G__WRITE(src) (((u_int32_t)(src) << 19) & 0x00780000U)
78455 #define RXTX1__PADRV3GN5G__MODIFY(dst, src) \
78457 ~0x00780000U) | (((u_int32_t)(src) <<\
78459 #define RXTX1__PADRV3GN5G__VERIFY(src) \
78460 (!((((u_int32_t)(src)\
78467 #define RXTX1__PADRV4GN5G__READ(src) (((u_int32_t)(src) & 0x07800000U) >> 23)
78468 #define RXTX1__PADRV4GN5G__WRITE(src) (((u_int32_t)(src) << 23) & 0x07800000U)
78469 #define RXTX1__PADRV4GN5G__MODIFY(dst, src) \
78471 ~0x07800000U) | (((u_int32_t)(src) <<\
78473 #define RXTX1__PADRV4GN5G__VERIFY(src) \
78474 (!((((u_int32_t)(src)\
78481 #define RXTX1__TXBB_GC__READ(src) (((u_int32_t)(src) & 0x78000000U) >> 27)
78482 #define RXTX1__TXBB_GC__WRITE(src) (((u_int32_t)(src) << 27) & 0x78000000U)
78483 #define RXTX1__TXBB_GC__MODIFY(dst, src) \
78485 ~0x78000000U) | (((u_int32_t)(src) <<\
78487 #define RXTX1__TXBB_GC__VERIFY(src) \
78488 (!((((u_int32_t)(src)\
78495 #define RXTX1__MANTXGAIN__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
78496 #define RXTX1__MANTXGAIN__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U)
78497 #define RXTX1__MANTXGAIN__MODIFY(dst, src) \
78499 ~0x80000000U) | (((u_int32_t)(src) <<\
78501 #define RXTX1__MANTXGAIN__VERIFY(src) \
78502 (!((((u_int32_t)(src)\
78528 #define RXTX2__BMODE__READ(src) (u_int32_t)(src) & 0x00000001U
78529 #define RXTX2__BMODE__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
78530 #define RXTX2__BMODE__MODIFY(dst, src) \
78532 ~0x00000001U) | ((u_int32_t)(src) &\
78534 #define RXTX2__BMODE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
78542 #define RXTX2__BMODE_OVR__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
78543 #define RXTX2__BMODE_OVR__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
78544 #define RXTX2__BMODE_OVR__MODIFY(dst, src) \
78546 ~0x00000002U) | (((u_int32_t)(src) <<\
78548 #define RXTX2__BMODE_OVR__VERIFY(src) \
78549 (!((((u_int32_t)(src)\
78562 #define RXTX2__SYNTHON__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
78563 #define RXTX2__SYNTHON__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
78564 #define RXTX2__SYNTHON__MODIFY(dst, src) \
78566 ~0x00000004U) | (((u_int32_t)(src) <<\
78568 #define RXTX2__SYNTHON__VERIFY(src) \
78569 (!((((u_int32_t)(src)\
78582 #define RXTX2__SYNTHON_OVR__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
78583 #define RXTX2__SYNTHON_OVR__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U)
78584 #define RXTX2__SYNTHON_OVR__MODIFY(dst, src) \
78586 ~0x00000008U) | (((u_int32_t)(src) <<\
78588 #define RXTX2__SYNTHON_OVR__VERIFY(src) \
78589 (!((((u_int32_t)(src)\
78602 #define RXTX2__BW_ST__READ(src) (((u_int32_t)(src) & 0x00000030U) >> 4)
78603 #define RXTX2__BW_ST__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000030U)
78604 #define RXTX2__BW_ST__MODIFY(dst, src) \
78606 ~0x00000030U) | (((u_int32_t)(src) <<\
78608 #define RXTX2__BW_ST__VERIFY(src) (!((((u_int32_t)(src) << 4) & ~0x00000030U)))
78614 #define RXTX2__BW_ST_OVR__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6)
78615 #define RXTX2__BW_ST_OVR__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U)
78616 #define RXTX2__BW_ST_OVR__MODIFY(dst, src) \
78618 ~0x00000040U) | (((u_int32_t)(src) <<\
78620 #define RXTX2__BW_ST_OVR__VERIFY(src) \
78621 (!((((u_int32_t)(src)\
78634 #define RXTX2__TXON_OVR__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7)
78635 #define RXTX2__TXON_OVR__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U)
78636 #define RXTX2__TXON_OVR__MODIFY(dst, src) \
78638 ~0x00000080U) | (((u_int32_t)(src) <<\
78640 #define RXTX2__TXON_OVR__VERIFY(src) \
78641 (!((((u_int32_t)(src)\
78654 #define RXTX2__TXON__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8)
78655 #define RXTX2__TXON__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U)
78656 #define RXTX2__TXON__MODIFY(dst, src) \
78658 ~0x00000100U) | (((u_int32_t)(src) <<\
78660 #define RXTX2__TXON__VERIFY(src) (!((((u_int32_t)(src) << 8) & ~0x00000100U)))
78672 #define RXTX2__PAON__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9)
78673 #define RXTX2__PAON__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U)
78674 #define RXTX2__PAON__MODIFY(dst, src) \
78676 ~0x00000200U) | (((u_int32_t)(src) <<\
78678 #define RXTX2__PAON__VERIFY(src) (!((((u_int32_t)(src) << 9) & ~0x00000200U)))
78690 #define RXTX2__PAON_OVR__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
78691 #define RXTX2__PAON_OVR__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U)
78692 #define RXTX2__PAON_OVR__MODIFY(dst, src) \
78694 ~0x00000400U) | (((u_int32_t)(src) <<\
78696 #define RXTX2__PAON_OVR__VERIFY(src) \
78697 (!((((u_int32_t)(src)\
78710 #define RXTX2__RXON__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
78711 #define RXTX2__RXON__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U)
78712 #define RXTX2__RXON__MODIFY(dst, src) \
78714 ~0x00000800U) | (((u_int32_t)(src) <<\
78716 #define RXTX2__RXON__VERIFY(src) (!((((u_int32_t)(src) << 11) & ~0x00000800U)))
78728 #define RXTX2__RXON_OVR__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12)
78729 #define RXTX2__RXON_OVR__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U)
78730 #define RXTX2__RXON_OVR__MODIFY(dst, src) \
78732 ~0x00001000U) | (((u_int32_t)(src) <<\
78734 #define RXTX2__RXON_OVR__VERIFY(src) \
78735 (!((((u_int32_t)(src)\
78748 #define RXTX2__AGCON__READ(src) (((u_int32_t)(src) & 0x00002000U) >> 13)
78749 #define RXTX2__AGCON__WRITE(src) (((u_int32_t)(src) << 13) & 0x00002000U)
78750 #define RXTX2__AGCON__MODIFY(dst, src) \
78752 ~0x00002000U) | (((u_int32_t)(src) <<\
78754 #define RXTX2__AGCON__VERIFY(src) \
78755 (!((((u_int32_t)(src)\
78768 #define RXTX2__AGCON_OVR__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14)
78769 #define RXTX2__AGCON_OVR__WRITE(src) (((u_int32_t)(src) << 14) & 0x00004000U)
78770 #define RXTX2__AGCON_OVR__MODIFY(dst, src) \
78772 ~0x00004000U) | (((u_int32_t)(src) <<\
78774 #define RXTX2__AGCON_OVR__VERIFY(src) \
78775 (!((((u_int32_t)(src)\
78788 #define RXTX2__TXMOD__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15)
78789 #define RXTX2__TXMOD__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U)
78790 #define RXTX2__TXMOD__MODIFY(dst, src) \
78792 ~0x00038000U) | (((u_int32_t)(src) <<\
78794 #define RXTX2__TXMOD__VERIFY(src) \
78795 (!((((u_int32_t)(src)\
78802 #define RXTX2__TXMOD_OVR__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18)
78803 #define RXTX2__TXMOD_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U)
78804 #define RXTX2__TXMOD_OVR__MODIFY(dst, src) \
78806 ~0x00040000U) | (((u_int32_t)(src) <<\
78808 #define RXTX2__TXMOD_OVR__VERIFY(src) \
78809 (!((((u_int32_t)(src)\
78822 #define RXTX2__RX1DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00380000U) >> 19)
78823 #define RXTX2__RX1DB_BIQUAD__WRITE(src) \
78824 (((u_int32_t)(src)\
78826 #define RXTX2__RX1DB_BIQUAD__MODIFY(dst, src) \
78828 ~0x00380000U) | (((u_int32_t)(src) <<\
78830 #define RXTX2__RX1DB_BIQUAD__VERIFY(src) \
78831 (!((((u_int32_t)(src)\
78838 #define RXTX2__RX6DB_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00c00000U) >> 22)
78839 #define RXTX2__RX6DB_BIQUAD__WRITE(src) \
78840 (((u_int32_t)(src)\
78842 #define RXTX2__RX6DB_BIQUAD__MODIFY(dst, src) \
78844 ~0x00c00000U) | (((u_int32_t)(src) <<\
78846 #define RXTX2__RX6DB_BIQUAD__VERIFY(src) \
78847 (!((((u_int32_t)(src)\
78854 #define RXTX2__MXRGAIN__READ(src) (((u_int32_t)(src) & 0x03000000U) >> 24)
78855 #define RXTX2__MXRGAIN__WRITE(src) (((u_int32_t)(src) << 24) & 0x03000000U)
78856 #define RXTX2__MXRGAIN__MODIFY(dst, src) \
78858 ~0x03000000U) | (((u_int32_t)(src) <<\
78860 #define RXTX2__MXRGAIN__VERIFY(src) \
78861 (!((((u_int32_t)(src)\
78868 #define RXTX2__VGAGAIN__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26)
78869 #define RXTX2__VGAGAIN__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U)
78870 #define RXTX2__VGAGAIN__MODIFY(dst, src) \
78872 ~0x1c000000U) | (((u_int32_t)(src) <<\
78874 #define RXTX2__VGAGAIN__VERIFY(src) \
78875 (!((((u_int32_t)(src)\
78882 #define RXTX2__LNAGAIN__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29)
78883 #define RXTX2__LNAGAIN__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U)
78884 #define RXTX2__LNAGAIN__MODIFY(dst, src) \
78886 ~0xe0000000U) | (((u_int32_t)(src) <<\
78888 #define RXTX2__LNAGAIN__VERIFY(src) \
78889 (!((((u_int32_t)(src)\
78909 #define RXTX3__XLNABIAS_PWD__READ(src) (u_int32_t)(src) & 0x00000001U
78910 #define RXTX3__XLNABIAS_PWD__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
78911 #define RXTX3__XLNABIAS_PWD__MODIFY(dst, src) \
78913 ~0x00000001U) | ((u_int32_t)(src) &\
78915 #define RXTX3__XLNABIAS_PWD__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
78927 #define RXTX3__XLNAON__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
78928 #define RXTX3__XLNAON__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
78929 #define RXTX3__XLNAON__MODIFY(dst, src) \
78931 ~0x00000002U) | (((u_int32_t)(src) <<\
78933 #define RXTX3__XLNAON__VERIFY(src) \
78934 (!((((u_int32_t)(src)\
78947 #define RXTX3__XLNAON_OVR__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
78948 #define RXTX3__XLNAON_OVR__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
78949 #define RXTX3__XLNAON_OVR__MODIFY(dst, src) \
78951 ~0x00000004U) | (((u_int32_t)(src) <<\
78953 #define RXTX3__XLNAON_OVR__VERIFY(src) \
78954 (!((((u_int32_t)(src)\
78967 #define RXTX3__DACFULLSCALE__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
78968 #define RXTX3__DACFULLSCALE__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U)
78969 #define RXTX3__DACFULLSCALE__MODIFY(dst, src) \
78971 ~0x00000008U) | (((u_int32_t)(src) <<\
78973 #define RXTX3__DACFULLSCALE__VERIFY(src) \
78974 (!((((u_int32_t)(src)\
78987 #define RXTX3__DACRSTB__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4)
78988 #define RXTX3__DACRSTB__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U)
78989 #define RXTX3__DACRSTB__MODIFY(dst, src) \
78991 ~0x00000010U) | (((u_int32_t)(src) <<\
78993 #define RXTX3__DACRSTB__VERIFY(src) \
78994 (!((((u_int32_t)(src)\
79007 #define RXTX3__ADDACLOOPBACK__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
79008 #define RXTX3__ADDACLOOPBACK__WRITE(src) \
79009 (((u_int32_t)(src)\
79011 #define RXTX3__ADDACLOOPBACK__MODIFY(dst, src) \
79013 ~0x00000020U) | (((u_int32_t)(src) <<\
79015 #define RXTX3__ADDACLOOPBACK__VERIFY(src) \
79016 (!((((u_int32_t)(src)\
79029 #define RXTX3__ADCSHORT__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6)
79030 #define RXTX3__ADCSHORT__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U)
79031 #define RXTX3__ADCSHORT__MODIFY(dst, src) \
79033 ~0x00000040U) | (((u_int32_t)(src) <<\
79035 #define RXTX3__ADCSHORT__VERIFY(src) \
79036 (!((((u_int32_t)(src)\
79049 #define RXTX3__DACPWD__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7)
79050 #define RXTX3__DACPWD__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U)
79051 #define RXTX3__DACPWD__MODIFY(dst, src) \
79053 ~0x00000080U) | (((u_int32_t)(src) <<\
79055 #define RXTX3__DACPWD__VERIFY(src) \
79056 (!((((u_int32_t)(src)\
79069 #define RXTX3__DACPWD_OVR__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8)
79070 #define RXTX3__DACPWD_OVR__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U)
79071 #define RXTX3__DACPWD_OVR__MODIFY(dst, src) \
79073 ~0x00000100U) | (((u_int32_t)(src) <<\
79075 #define RXTX3__DACPWD_OVR__VERIFY(src) \
79076 (!((((u_int32_t)(src)\
79089 #define RXTX3__ADCPWD__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9)
79090 #define RXTX3__ADCPWD__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U)
79091 #define RXTX3__ADCPWD__MODIFY(dst, src) \
79093 ~0x00000200U) | (((u_int32_t)(src) <<\
79095 #define RXTX3__ADCPWD__VERIFY(src) \
79096 (!((((u_int32_t)(src)\
79109 #define RXTX3__ADCPWD_OVR__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
79110 #define RXTX3__ADCPWD_OVR__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U)
79111 #define RXTX3__ADCPWD_OVR__MODIFY(dst, src) \
79113 ~0x00000400U) | (((u_int32_t)(src) <<\
79115 #define RXTX3__ADCPWD_OVR__VERIFY(src) \
79116 (!((((u_int32_t)(src)\
79129 #define RXTX3__AGC_CALDAC__READ(src) (((u_int32_t)(src) & 0x0001f800U) >> 11)
79130 #define RXTX3__AGC_CALDAC__WRITE(src) (((u_int32_t)(src) << 11) & 0x0001f800U)
79131 #define RXTX3__AGC_CALDAC__MODIFY(dst, src) \
79133 ~0x0001f800U) | (((u_int32_t)(src) <<\
79135 #define RXTX3__AGC_CALDAC__VERIFY(src) \
79136 (!((((u_int32_t)(src)\
79143 #define RXTX3__AGC_CAL__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17)
79144 #define RXTX3__AGC_CAL__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U)
79145 #define RXTX3__AGC_CAL__MODIFY(dst, src) \
79147 ~0x00020000U) | (((u_int32_t)(src) <<\
79149 #define RXTX3__AGC_CAL__VERIFY(src) \
79150 (!((((u_int32_t)(src)\
79163 #define RXTX3__AGC_CAL_OVR__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18)
79164 #define RXTX3__AGC_CAL_OVR__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U)
79165 #define RXTX3__AGC_CAL_OVR__MODIFY(dst, src) \
79167 ~0x00040000U) | (((u_int32_t)(src) <<\
79169 #define RXTX3__AGC_CAL_OVR__VERIFY(src) \
79170 (!((((u_int32_t)(src)\
79183 #define RXTX3__LOFORCEDON__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19)
79184 #define RXTX3__LOFORCEDON__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U)
79185 #define RXTX3__LOFORCEDON__MODIFY(dst, src) \
79187 ~0x00080000U) | (((u_int32_t)(src) <<\
79189 #define RXTX3__LOFORCEDON__VERIFY(src) \
79190 (!((((u_int32_t)(src)\
79203 #define RXTX3__CALRESIDUE__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20)
79204 #define RXTX3__CALRESIDUE__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U)
79205 #define RXTX3__CALRESIDUE__MODIFY(dst, src) \
79207 ~0x00100000U) | (((u_int32_t)(src) <<\
79209 #define RXTX3__CALRESIDUE__VERIFY(src) \
79210 (!((((u_int32_t)(src)\
79223 #define RXTX3__CALRESIDUE_OVR__READ(src) \
79224 (((u_int32_t)(src)\
79226 #define RXTX3__CALRESIDUE_OVR__WRITE(src) \
79227 (((u_int32_t)(src)\
79229 #define RXTX3__CALRESIDUE_OVR__MODIFY(dst, src) \
79231 ~0x00200000U) | (((u_int32_t)(src) <<\
79233 #define RXTX3__CALRESIDUE_OVR__VERIFY(src) \
79234 (!((((u_int32_t)(src)\
79247 #define RXTX3__CALFC__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22)
79248 #define RXTX3__CALFC__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U)
79249 #define RXTX3__CALFC__MODIFY(dst, src) \
79251 ~0x00400000U) | (((u_int32_t)(src) <<\
79253 #define RXTX3__CALFC__VERIFY(src) \
79254 (!((((u_int32_t)(src)\
79267 #define RXTX3__CALFC_OVR__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23)
79268 #define RXTX3__CALFC_OVR__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U)
79269 #define RXTX3__CALFC_OVR__MODIFY(dst, src) \
79271 ~0x00800000U) | (((u_int32_t)(src) <<\
79273 #define RXTX3__CALFC_OVR__VERIFY(src) \
79274 (!((((u_int32_t)(src)\
79287 #define RXTX3__CALTX__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24)
79288 #define RXTX3__CALTX__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U)
79289 #define RXTX3__CALTX__MODIFY(dst, src) \
79291 ~0x01000000U) | (((u_int32_t)(src) <<\
79293 #define RXTX3__CALTX__VERIFY(src) \
79294 (!((((u_int32_t)(src)\
79307 #define RXTX3__CALTX_OVR__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25)
79308 #define RXTX3__CALTX_OVR__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U)
79309 #define RXTX3__CALTX_OVR__MODIFY(dst, src) \
79311 ~0x02000000U) | (((u_int32_t)(src) <<\
79313 #define RXTX3__CALTX_OVR__VERIFY(src) \
79314 (!((((u_int32_t)(src)\
79327 #define RXTX3__CALTXSHIFT__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26)
79328 #define RXTX3__CALTXSHIFT__WRITE(src) (((u_int32_t)(src) << 26) & 0x04000000U)
79329 #define RXTX3__CALTXSHIFT__MODIFY(dst, src) \
79331 ~0x04000000U) | (((u_int32_t)(src) <<\
79333 #define RXTX3__CALTXSHIFT__VERIFY(src) \
79334 (!((((u_int32_t)(src)\
79347 #define RXTX3__CALTXSHIFT_OVR__READ(src) \
79348 (((u_int32_t)(src)\
79350 #define RXTX3__CALTXSHIFT_OVR__WRITE(src) \
79351 (((u_int32_t)(src)\
79353 #define RXTX3__CALTXSHIFT_OVR__MODIFY(dst, src) \
79355 ~0x08000000U) | (((u_int32_t)(src) <<\
79357 #define RXTX3__CALTXSHIFT_OVR__VERIFY(src) \
79358 (!((((u_int32_t)(src)\
79371 #define RXTX3__CALPA__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28)
79372 #define RXTX3__CALPA__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U)
79373 #define RXTX3__CALPA__MODIFY(dst, src) \
79375 ~0x10000000U) | (((u_int32_t)(src) <<\
79377 #define RXTX3__CALPA__VERIFY(src) \
79378 (!((((u_int32_t)(src)\
79391 #define RXTX3__CALPA_OVR__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
79392 #define RXTX3__CALPA_OVR__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U)
79393 #define RXTX3__CALPA_OVR__MODIFY(dst, src) \
79395 ~0x20000000U) | (((u_int32_t)(src) <<\
79397 #define RXTX3__CALPA_OVR__VERIFY(src) \
79398 (!((((u_int32_t)(src)\
79411 #define RXTX3__SPURON__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30)
79412 #define RXTX3__SPURON__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U)
79413 #define RXTX3__SPURON__MODIFY(dst, src) \
79415 ~0x40000000U) | (((u_int32_t)(src) <<\
79417 #define RXTX3__SPURON__VERIFY(src) \
79418 (!((((u_int32_t)(src)\
79431 #define RXTX3__PAL_LOCKEDEN__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
79432 #define RXTX3__PAL_LOCKEDEN__WRITE(src) \
79433 (((u_int32_t)(src)\
79435 #define RXTX3__PAL_LOCKEDEN__MODIFY(dst, src) \
79437 ~0x80000000U) | (((u_int32_t)(src) <<\
79439 #define RXTX3__PAL_LOCKEDEN__VERIFY(src) \
79440 (!((((u_int32_t)(src)\
79466 #define RXTX4__SPARE4__READ(src) (u_int32_t)(src) & 0x007fffffU
79467 #define RXTX4__SPARE4__WRITE(src) ((u_int32_t)(src) & 0x007fffffU)
79468 #define RXTX4__SPARE4__MODIFY(dst, src) \
79470 ~0x007fffffU) | ((u_int32_t)(src) &\
79472 #define RXTX4__SPARE4__VERIFY(src) (!(((u_int32_t)(src) & ~0x007fffffU)))
79478 #define RXTX4__TESTIQ_ON__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23)
79479 #define RXTX4__TESTIQ_ON__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U)
79480 #define RXTX4__TESTIQ_ON__MODIFY(dst, src) \
79482 ~0x00800000U) | (((u_int32_t)(src) <<\
79484 #define RXTX4__TESTIQ_ON__VERIFY(src) \
79485 (!((((u_int32_t)(src)\
79498 #define RXTX4__TESTIQ_BUFEN__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24)
79499 #define RXTX4__TESTIQ_BUFEN__WRITE(src) \
79500 (((u_int32_t)(src)\
79502 #define RXTX4__TESTIQ_BUFEN__MODIFY(dst, src) \
79504 ~0x01000000U) | (((u_int32_t)(src) <<\
79506 #define RXTX4__TESTIQ_BUFEN__VERIFY(src) \
79507 (!((((u_int32_t)(src)\
79520 #define RXTX4__TESTIQ_RSEL__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25)
79521 #define RXTX4__TESTIQ_RSEL__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U)
79522 #define RXTX4__TESTIQ_RSEL__MODIFY(dst, src) \
79524 ~0x02000000U) | (((u_int32_t)(src) <<\
79526 #define RXTX4__TESTIQ_RSEL__VERIFY(src) \
79527 (!((((u_int32_t)(src)\
79540 #define RXTX4__TURBOADC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26)
79541 #define RXTX4__TURBOADC__WRITE(src) (((u_int32_t)(src) << 26) & 0x04000000U)
79542 #define RXTX4__TURBOADC__MODIFY(dst, src) \
79544 ~0x04000000U) | (((u_int32_t)(src) <<\
79546 #define RXTX4__TURBOADC__VERIFY(src) \
79547 (!((((u_int32_t)(src)\
79560 #define RXTX4__TURBOADC_OVR__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
79561 #define RXTX4__TURBOADC_OVR__WRITE(src) \
79562 (((u_int32_t)(src)\
79564 #define RXTX4__TURBOADC_OVR__MODIFY(dst, src) \
79566 ~0x08000000U) | (((u_int32_t)(src) <<\
79568 #define RXTX4__TURBOADC_OVR__VERIFY(src) \
79569 (!((((u_int32_t)(src)\
79582 #define RXTX4__THERMON__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28)
79583 #define RXTX4__THERMON__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U)
79584 #define RXTX4__THERMON__MODIFY(dst, src) \
79586 ~0x10000000U) | (((u_int32_t)(src) <<\
79588 #define RXTX4__THERMON__VERIFY(src) \
79589 (!((((u_int32_t)(src)\
79602 #define RXTX4__THERMON_OVR__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
79603 #define RXTX4__THERMON_OVR__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U)
79604 #define RXTX4__THERMON_OVR__MODIFY(dst, src) \
79606 ~0x20000000U) | (((u_int32_t)(src) <<\
79608 #define RXTX4__THERMON_OVR__VERIFY(src) \
79609 (!((((u_int32_t)(src)\
79622 #define RXTX4__XLNA_STRENGTH__READ(src) \
79623 (((u_int32_t)(src)\
79625 #define RXTX4__XLNA_STRENGTH__WRITE(src) \
79626 (((u_int32_t)(src)\
79628 #define RXTX4__XLNA_STRENGTH__MODIFY(dst, src) \
79630 ~0xc0000000U) | (((u_int32_t)(src) <<\
79632 #define RXTX4__XLNA_STRENGTH__VERIFY(src) \
79633 (!((((u_int32_t)(src)\
79653 #define BB1__I2V_CURR2X__READ(src) (u_int32_t)(src) & 0x00000001U
79654 #define BB1__I2V_CURR2X__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
79655 #define BB1__I2V_CURR2X__MODIFY(dst, src) \
79657 ~0x00000001U) | ((u_int32_t)(src) &\
79659 #define BB1__I2V_CURR2X__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
79671 #define BB1__ENABLE_LOQ__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
79672 #define BB1__ENABLE_LOQ__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
79673 #define BB1__ENABLE_LOQ__MODIFY(dst, src) \
79675 ~0x00000002U) | (((u_int32_t)(src) <<\
79677 #define BB1__ENABLE_LOQ__VERIFY(src) \
79678 (!((((u_int32_t)(src)\
79691 #define BB1__FORCE_LOQ__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
79692 #define BB1__FORCE_LOQ__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
79693 #define BB1__FORCE_LOQ__MODIFY(dst, src) \
79695 ~0x00000004U) | (((u_int32_t)(src) <<\
79697 #define BB1__FORCE_LOQ__VERIFY(src) \
79698 (!((((u_int32_t)(src)\
79711 #define BB1__ENABLE_NOTCH__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
79712 #define BB1__ENABLE_NOTCH__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U)
79713 #define BB1__ENABLE_NOTCH__MODIFY(dst, src) \
79715 ~0x00000008U) | (((u_int32_t)(src) <<\
79717 #define BB1__ENABLE_NOTCH__VERIFY(src) \
79718 (!((((u_int32_t)(src)\
79731 #define BB1__FORCE_NOTCH__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4)
79732 #define BB1__FORCE_NOTCH__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U)
79733 #define BB1__FORCE_NOTCH__MODIFY(dst, src) \
79735 ~0x00000010U) | (((u_int32_t)(src) <<\
79737 #define BB1__FORCE_NOTCH__VERIFY(src) \
79738 (!((((u_int32_t)(src)\
79751 #define BB1__ENABLE_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
79752 #define BB1__ENABLE_BIQUAD__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
79753 #define BB1__ENABLE_BIQUAD__MODIFY(dst, src) \
79755 ~0x00000020U) | (((u_int32_t)(src) <<\
79757 #define BB1__ENABLE_BIQUAD__VERIFY(src) \
79758 (!((((u_int32_t)(src)\
79771 #define BB1__FORCE_BIQUAD__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6)
79772 #define BB1__FORCE_BIQUAD__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U)
79773 #define BB1__FORCE_BIQUAD__MODIFY(dst, src) \
79775 ~0x00000040U) | (((u_int32_t)(src) <<\
79777 #define BB1__FORCE_BIQUAD__VERIFY(src) \
79778 (!((((u_int32_t)(src)\
79791 #define BB1__ENABLE_OSDAC__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7)
79792 #define BB1__ENABLE_OSDAC__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U)
79793 #define BB1__ENABLE_OSDAC__MODIFY(dst, src) \
79795 ~0x00000080U) | (((u_int32_t)(src) <<\
79797 #define BB1__ENABLE_OSDAC__VERIFY(src) \
79798 (!((((u_int32_t)(src)\
79811 #define BB1__FORCE_OSDAC__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8)
79812 #define BB1__FORCE_OSDAC__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U)
79813 #define BB1__FORCE_OSDAC__MODIFY(dst, src) \
79815 ~0x00000100U) | (((u_int32_t)(src) <<\
79817 #define BB1__FORCE_OSDAC__VERIFY(src) \
79818 (!((((u_int32_t)(src)\
79831 #define BB1__ENABLE_V2I__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9)
79832 #define BB1__ENABLE_V2I__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U)
79833 #define BB1__ENABLE_V2I__MODIFY(dst, src) \
79835 ~0x00000200U) | (((u_int32_t)(src) <<\
79837 #define BB1__ENABLE_V2I__VERIFY(src) \
79838 (!((((u_int32_t)(src)\
79851 #define BB1__FORCE_V2I__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
79852 #define BB1__FORCE_V2I__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U)
79853 #define BB1__FORCE_V2I__MODIFY(dst, src) \
79855 ~0x00000400U) | (((u_int32_t)(src) <<\
79857 #define BB1__FORCE_V2I__VERIFY(src) \
79858 (!((((u_int32_t)(src)\
79871 #define BB1__ENABLE_I2V__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
79872 #define BB1__ENABLE_I2V__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U)
79873 #define BB1__ENABLE_I2V__MODIFY(dst, src) \
79875 ~0x00000800U) | (((u_int32_t)(src) <<\
79877 #define BB1__ENABLE_I2V__VERIFY(src) \
79878 (!((((u_int32_t)(src)\
79891 #define BB1__FORCE_I2V__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12)
79892 #define BB1__FORCE_I2V__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U)
79893 #define BB1__FORCE_I2V__MODIFY(dst, src) \
79895 ~0x00001000U) | (((u_int32_t)(src) <<\
79897 #define BB1__FORCE_I2V__VERIFY(src) \
79898 (!((((u_int32_t)(src)\
79911 #define BB1__CMSEL__READ(src) (((u_int32_t)(src) & 0x0000e000U) >> 13)
79912 #define BB1__CMSEL__WRITE(src) (((u_int32_t)(src) << 13) & 0x0000e000U)
79913 #define BB1__CMSEL__MODIFY(dst, src) \
79915 ~0x0000e000U) | (((u_int32_t)(src) <<\
79917 #define BB1__CMSEL__VERIFY(src) (!((((u_int32_t)(src) << 13) & ~0x0000e000U)))
79923 #define BB1__ATBSEL__READ(src) (((u_int32_t)(src) & 0x00030000U) >> 16)
79924 #define BB1__ATBSEL__WRITE(src) (((u_int32_t)(src) << 16) & 0x00030000U)
79925 #define BB1__ATBSEL__MODIFY(dst, src) \
79927 ~0x00030000U) | (((u_int32_t)(src) <<\
79929 #define BB1__ATBSEL__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x00030000U)))
79935 #define BB1__PD_OSDAC_CALTX_CALPA__READ(src) \
79936 (((u_int32_t)(src)\
79938 #define BB1__PD_OSDAC_CALTX_CALPA__WRITE(src) \
79939 (((u_int32_t)(src)\
79941 #define BB1__PD_OSDAC_CALTX_CALPA__MODIFY(dst, src) \
79943 ~0x00040000U) | (((u_int32_t)(src) <<\
79945 #define BB1__PD_OSDAC_CALTX_CALPA__VERIFY(src) \
79946 (!((((u_int32_t)(src)\
79959 #define BB1__OFSTCORRI2VQ__READ(src) (((u_int32_t)(src) & 0x00f80000U) >> 19)
79960 #define BB1__OFSTCORRI2VQ__WRITE(src) (((u_int32_t)(src) << 19) & 0x00f80000U)
79961 #define BB1__OFSTCORRI2VQ__MODIFY(dst, src) \
79963 ~0x00f80000U) | (((u_int32_t)(src) <<\
79965 #define BB1__OFSTCORRI2VQ__VERIFY(src) \
79966 (!((((u_int32_t)(src)\
79973 #define BB1__OFSTCORRI2VI__READ(src) (((u_int32_t)(src) & 0x1f000000U) >> 24)
79974 #define BB1__OFSTCORRI2VI__WRITE(src) (((u_int32_t)(src) << 24) & 0x1f000000U)
79975 #define BB1__OFSTCORRI2VI__MODIFY(dst, src) \
79977 ~0x1f000000U) | (((u_int32_t)(src) <<\
79979 #define BB1__OFSTCORRI2VI__VERIFY(src) \
79980 (!((((u_int32_t)(src)\
79987 #define BB1__LOCALOFFSET__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
79988 #define BB1__LOCALOFFSET__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U)
79989 #define BB1__LOCALOFFSET__MODIFY(dst, src) \
79991 ~0x20000000U) | (((u_int32_t)(src) <<\
79993 #define BB1__LOCALOFFSET__VERIFY(src) \
79994 (!((((u_int32_t)(src)\
80007 #define BB1__RANGE_OSDAC__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30)
80008 #define BB1__RANGE_OSDAC__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U)
80009 #define BB1__RANGE_OSDAC__MODIFY(dst, src) \
80011 ~0xc0000000U) | (((u_int32_t)(src) <<\
80013 #define BB1__RANGE_OSDAC__VERIFY(src) \
80014 (!((((u_int32_t)(src)\
80034 #define BB2__SPARE__READ(src) (u_int32_t)(src) & 0x0000000fU
80035 #define BB2__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000000fU)
80036 #define BB2__SPARE__MODIFY(dst, src) \
80038 ~0x0000000fU) | ((u_int32_t)(src) &\
80040 #define BB2__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000000fU)))
80046 #define BB2__MXR_HIGHGAINMASK__READ(src) \
80047 (((u_int32_t)(src)\
80049 #define BB2__MXR_HIGHGAINMASK__WRITE(src) \
80050 (((u_int32_t)(src)\
80052 #define BB2__MXR_HIGHGAINMASK__MODIFY(dst, src) \
80054 ~0x000000f0U) | (((u_int32_t)(src) <<\
80056 #define BB2__MXR_HIGHGAINMASK__VERIFY(src) \
80057 (!((((u_int32_t)(src)\
80064 #define BB2__SEL_TEST__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8)
80065 #define BB2__SEL_TEST__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000300U)
80066 #define BB2__SEL_TEST__MODIFY(dst, src) \
80068 ~0x00000300U) | (((u_int32_t)(src) <<\
80070 #define BB2__SEL_TEST__VERIFY(src) \
80071 (!((((u_int32_t)(src)\
80078 #define BB2__RCFILTER_CAP__READ(src) (((u_int32_t)(src) & 0x00007c00U) >> 10)
80079 #define BB2__RCFILTER_CAP__WRITE(src) (((u_int32_t)(src) << 10) & 0x00007c00U)
80080 #define BB2__RCFILTER_CAP__MODIFY(dst, src) \
80082 ~0x00007c00U) | (((u_int32_t)(src) <<\
80084 #define BB2__RCFILTER_CAP__VERIFY(src) \
80085 (!((((u_int32_t)(src)\
80092 #define BB2__OVERRIDE_RCFILTER_CAP__READ(src) \
80093 (((u_int32_t)(src)\
80095 #define BB2__OVERRIDE_RCFILTER_CAP__WRITE(src) \
80096 (((u_int32_t)(src)\
80098 #define BB2__OVERRIDE_RCFILTER_CAP__MODIFY(dst, src) \
80100 ~0x00008000U) | (((u_int32_t)(src) <<\
80102 #define BB2__OVERRIDE_RCFILTER_CAP__VERIFY(src) \
80103 (!((((u_int32_t)(src)\
80116 #define BB2__FNOTCH__READ(src) (((u_int32_t)(src) & 0x000f0000U) >> 16)
80117 #define BB2__FNOTCH__WRITE(src) (((u_int32_t)(src) << 16) & 0x000f0000U)
80118 #define BB2__FNOTCH__MODIFY(dst, src) \
80120 ~0x000f0000U) | (((u_int32_t)(src) <<\
80122 #define BB2__FNOTCH__VERIFY(src) (!((((u_int32_t)(src) << 16) & ~0x000f0000U)))
80128 #define BB2__OVERRIDE_FNOTCH__READ(src) \
80129 (((u_int32_t)(src)\
80131 #define BB2__OVERRIDE_FNOTCH__WRITE(src) \
80132 (((u_int32_t)(src)\
80134 #define BB2__OVERRIDE_FNOTCH__MODIFY(dst, src) \
80136 ~0x00100000U) | (((u_int32_t)(src) <<\
80138 #define BB2__OVERRIDE_FNOTCH__VERIFY(src) \
80139 (!((((u_int32_t)(src)\
80152 #define BB2__FILTERFC__READ(src) (((u_int32_t)(src) & 0x03e00000U) >> 21)
80153 #define BB2__FILTERFC__WRITE(src) (((u_int32_t)(src) << 21) & 0x03e00000U)
80154 #define BB2__FILTERFC__MODIFY(dst, src) \
80156 ~0x03e00000U) | (((u_int32_t)(src) <<\
80158 #define BB2__FILTERFC__VERIFY(src) \
80159 (!((((u_int32_t)(src)\
80166 #define BB2__OVERRIDE_FILTERFC__READ(src) \
80167 (((u_int32_t)(src)\
80169 #define BB2__OVERRIDE_FILTERFC__WRITE(src) \
80170 (((u_int32_t)(src)\
80172 #define BB2__OVERRIDE_FILTERFC__MODIFY(dst, src) \
80174 ~0x04000000U) | (((u_int32_t)(src) <<\
80176 #define BB2__OVERRIDE_FILTERFC__VERIFY(src) \
80177 (!((((u_int32_t)(src)\
80190 #define BB2__I2V2RXOUT_EN__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
80191 #define BB2__I2V2RXOUT_EN__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U)
80192 #define BB2__I2V2RXOUT_EN__MODIFY(dst, src) \
80194 ~0x08000000U) | (((u_int32_t)(src) <<\
80196 #define BB2__I2V2RXOUT_EN__VERIFY(src) \
80197 (!((((u_int32_t)(src)\
80210 #define BB2__BQ2RXOUT_EN__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28)
80211 #define BB2__BQ2RXOUT_EN__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U)
80212 #define BB2__BQ2RXOUT_EN__MODIFY(dst, src) \
80214 ~0x10000000U) | (((u_int32_t)(src) <<\
80216 #define BB2__BQ2RXOUT_EN__VERIFY(src) \
80217 (!((((u_int32_t)(src)\
80230 #define BB2__RXIN2I2V_EN__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
80231 #define BB2__RXIN2I2V_EN__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U)
80232 #define BB2__RXIN2I2V_EN__MODIFY(dst, src) \
80234 ~0x20000000U) | (((u_int32_t)(src) <<\
80236 #define BB2__RXIN2I2V_EN__VERIFY(src) \
80237 (!((((u_int32_t)(src)\
80250 #define BB2__RXIN2BQ_EN__READ(src) (((u_int32_t)(src) & 0x40000000U) >> 30)
80251 #define BB2__RXIN2BQ_EN__WRITE(src) (((u_int32_t)(src) << 30) & 0x40000000U)
80252 #define BB2__RXIN2BQ_EN__MODIFY(dst, src) \
80254 ~0x40000000U) | (((u_int32_t)(src) <<\
80256 #define BB2__RXIN2BQ_EN__VERIFY(src) \
80257 (!((((u_int32_t)(src)\
80270 #define BB2__SWITCH_OVERRIDE__READ(src) \
80271 (((u_int32_t)(src)\
80273 #define BB2__SWITCH_OVERRIDE__WRITE(src) \
80274 (((u_int32_t)(src)\
80276 #define BB2__SWITCH_OVERRIDE__MODIFY(dst, src) \
80278 ~0x80000000U) | (((u_int32_t)(src) <<\
80280 #define BB2__SWITCH_OVERRIDE__VERIFY(src) \
80281 (!((((u_int32_t)(src)\
80307 #define BB3__SPARE__READ(src) (u_int32_t)(src) & 0x000000ffU
80308 #define BB3__SPARE__WRITE(src) ((u_int32_t)(src) & 0x000000ffU)
80309 #define BB3__SPARE__MODIFY(dst, src) \
80311 ~0x000000ffU) | ((u_int32_t)(src) &\
80313 #define BB3__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x000000ffU)))
80319 #define BB3__SEL_OFST_READBK__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8)
80320 #define BB3__SEL_OFST_READBK__WRITE(src) \
80321 (((u_int32_t)(src)\
80323 #define BB3__SEL_OFST_READBK__MODIFY(dst, src) \
80325 ~0x00000300U) | (((u_int32_t)(src) <<\
80327 #define BB3__SEL_OFST_READBK__VERIFY(src) \
80328 (!((((u_int32_t)(src)\
80335 #define BB3__OVERRIDE_RXONLY_FILTERFC__READ(src) \
80336 (((u_int32_t)(src)\
80338 #define BB3__OVERRIDE_RXONLY_FILTERFC__WRITE(src) \
80339 (((u_int32_t)(src)\
80341 #define BB3__OVERRIDE_RXONLY_FILTERFC__MODIFY(dst, src) \
80343 ~0x00000400U) | (((u_int32_t)(src) <<\
80345 #define BB3__OVERRIDE_RXONLY_FILTERFC__VERIFY(src) \
80346 (!((((u_int32_t)(src)\
80359 #define BB3__RXONLY_FILTERFC__READ(src) \
80360 (((u_int32_t)(src)\
80362 #define BB3__RXONLY_FILTERFC__WRITE(src) \
80363 (((u_int32_t)(src)\
80365 #define BB3__RXONLY_FILTERFC__MODIFY(dst, src) \
80367 ~0x0000f800U) | (((u_int32_t)(src) <<\
80369 #define BB3__RXONLY_FILTERFC__VERIFY(src) \
80370 (!((((u_int32_t)(src)\
80377 #define BB3__FILTERFC__READ(src) (((u_int32_t)(src) & 0x001f0000U) >> 16)
80383 #define BB3__OFSTCORRI2VQ__READ(src) (((u_int32_t)(src) & 0x03e00000U) >> 21)
80389 #define BB3__OFSTCORRI2VI__READ(src) (((u_int32_t)(src) & 0x7c000000U) >> 26)
80395 #define BB3__EN_TXBBCONSTCUR__READ(src) \
80396 (((u_int32_t)(src)\
80398 #define BB3__EN_TXBBCONSTCUR__WRITE(src) \
80399 (((u_int32_t)(src)\
80401 #define BB3__EN_TXBBCONSTCUR__MODIFY(dst, src) \
80403 ~0x80000000U) | (((u_int32_t)(src) <<\
80405 #define BB3__EN_TXBBCONSTCUR__VERIFY(src) \
80406 (!((((u_int32_t)(src)\
80432 #define PLLCLKMODA__PWD_PLLSDM__READ(src) (u_int32_t)(src) & 0x00000001U
80433 #define PLLCLKMODA__PWD_PLLSDM__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
80434 #define PLLCLKMODA__PWD_PLLSDM__MODIFY(dst, src) \
80436 ~0x00000001U) | ((u_int32_t)(src) &\
80438 #define PLLCLKMODA__PWD_PLLSDM__VERIFY(src) \
80439 (!(((u_int32_t)(src)\
80452 #define PLLCLKMODA__PWDPLL__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
80453 #define PLLCLKMODA__PWDPLL__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
80454 #define PLLCLKMODA__PWDPLL__MODIFY(dst, src) \
80456 ~0x00000002U) | (((u_int32_t)(src) <<\
80458 #define PLLCLKMODA__PWDPLL__VERIFY(src) \
80459 (!((((u_int32_t)(src)\
80472 #define PLLCLKMODA__PLLFRAC__READ(src) (((u_int32_t)(src) & 0x0001fffcU) >> 2)
80473 #define PLLCLKMODA__PLLFRAC__WRITE(src) (((u_int32_t)(src) << 2) & 0x0001fffcU)
80474 #define PLLCLKMODA__PLLFRAC__MODIFY(dst, src) \
80476 ~0x0001fffcU) | (((u_int32_t)(src) <<\
80478 #define PLLCLKMODA__PLLFRAC__VERIFY(src) \
80479 (!((((u_int32_t)(src)\
80486 #define PLLCLKMODA__REFDIV__READ(src) (((u_int32_t)(src) & 0x001e0000U) >> 17)
80487 #define PLLCLKMODA__REFDIV__WRITE(src) (((u_int32_t)(src) << 17) & 0x001e0000U)
80488 #define PLLCLKMODA__REFDIV__MODIFY(dst, src) \
80490 ~0x001e0000U) | (((u_int32_t)(src) <<\
80492 #define PLLCLKMODA__REFDIV__VERIFY(src) \
80493 (!((((u_int32_t)(src)\
80500 #define PLLCLKMODA__DIV__READ(src) (((u_int32_t)(src) & 0x7fe00000U) >> 21)
80501 #define PLLCLKMODA__DIV__WRITE(src) (((u_int32_t)(src) << 21) & 0x7fe00000U)
80502 #define PLLCLKMODA__DIV__MODIFY(dst, src) \
80504 ~0x7fe00000U) | (((u_int32_t)(src) <<\
80506 #define PLLCLKMODA__DIV__VERIFY(src) \
80507 (!((((u_int32_t)(src)\
80514 #define PLLCLKMODA__LOCAL_PLL__READ(src) \
80515 (((u_int32_t)(src)\
80517 #define PLLCLKMODA__LOCAL_PLL__WRITE(src) \
80518 (((u_int32_t)(src)\
80520 #define PLLCLKMODA__LOCAL_PLL__MODIFY(dst, src) \
80522 ~0x80000000U) | (((u_int32_t)(src) <<\
80524 #define PLLCLKMODA__LOCAL_PLL__VERIFY(src) \
80525 (!((((u_int32_t)(src)\
80551 #define PLLCLKMODA2__SPARE__READ(src) (u_int32_t)(src) & 0x00000007U
80552 #define PLLCLKMODA2__SPARE__WRITE(src) ((u_int32_t)(src) & 0x00000007U)
80553 #define PLLCLKMODA2__SPARE__MODIFY(dst, src) \
80555 ~0x00000007U) | ((u_int32_t)(src) &\
80557 #define PLLCLKMODA2__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000007U)))
80563 #define PLLCLKMODA2__GLOBAL_CLK_EN__READ(src) \
80564 (((u_int32_t)(src)\
80566 #define PLLCLKMODA2__GLOBAL_CLK_EN__WRITE(src) \
80567 (((u_int32_t)(src)\
80569 #define PLLCLKMODA2__GLOBAL_CLK_EN__MODIFY(dst, src) \
80571 ~0x00000008U) | (((u_int32_t)(src) <<\
80573 #define PLLCLKMODA2__GLOBAL_CLK_EN__VERIFY(src) \
80574 (!((((u_int32_t)(src)\
80587 #define PLLCLKMODA2__ADC_CLK_SEL__READ(src) \
80588 (((u_int32_t)(src)\
80590 #define PLLCLKMODA2__ADC_CLK_SEL__WRITE(src) \
80591 (((u_int32_t)(src)\
80593 #define PLLCLKMODA2__ADC_CLK_SEL__MODIFY(dst, src) \
80595 ~0x000000f0U) | (((u_int32_t)(src) <<\
80597 #define PLLCLKMODA2__ADC_CLK_SEL__VERIFY(src) \
80598 (!((((u_int32_t)(src)\
80605 #define PLLCLKMODA2__LOCAL_CLKMODA__READ(src) \
80606 (((u_int32_t)(src)\
80608 #define PLLCLKMODA2__LOCAL_CLKMODA__WRITE(src) \
80609 (((u_int32_t)(src)\
80611 #define PLLCLKMODA2__LOCAL_CLKMODA__MODIFY(dst, src) \
80613 ~0x00000100U) | (((u_int32_t)(src) <<\
80615 #define PLLCLKMODA2__LOCAL_CLKMODA__VERIFY(src) \
80616 (!((((u_int32_t)(src)\
80629 #define PLLCLKMODA2__PLLBYPASS__READ(src) \
80630 (((u_int32_t)(src)\
80632 #define PLLCLKMODA2__PLLBYPASS__WRITE(src) \
80633 (((u_int32_t)(src)\
80635 #define PLLCLKMODA2__PLLBYPASS__MODIFY(dst, src) \
80637 ~0x00000200U) | (((u_int32_t)(src) <<\
80639 #define PLLCLKMODA2__PLLBYPASS__VERIFY(src) \
80640 (!((((u_int32_t)(src)\
80653 #define PLLCLKMODA2__LOCAL_PLLBYPASS__READ(src) \
80654 (((u_int32_t)(src)\
80656 #define PLLCLKMODA2__LOCAL_PLLBYPASS__WRITE(src) \
80657 (((u_int32_t)(src)\
80659 #define PLLCLKMODA2__LOCAL_PLLBYPASS__MODIFY(dst, src) \
80661 ~0x00000400U) | (((u_int32_t)(src) <<\
80663 #define PLLCLKMODA2__LOCAL_PLLBYPASS__VERIFY(src) \
80664 (!((((u_int32_t)(src)\
80677 #define PLLCLKMODA2__PLLATB__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11)
80678 #define PLLCLKMODA2__PLLATB__WRITE(src) \
80679 (((u_int32_t)(src)\
80681 #define PLLCLKMODA2__PLLATB__MODIFY(dst, src) \
80683 ~0x00001800U) | (((u_int32_t)(src) <<\
80685 #define PLLCLKMODA2__PLLATB__VERIFY(src) \
80686 (!((((u_int32_t)(src)\
80693 #define PLLCLKMODA2__PLL_SVREG__READ(src) \
80694 (((u_int32_t)(src)\
80696 #define PLLCLKMODA2__PLL_SVREG__WRITE(src) \
80697 (((u_int32_t)(src)\
80699 #define PLLCLKMODA2__PLL_SVREG__MODIFY(dst, src) \
80701 ~0x00002000U) | (((u_int32_t)(src) <<\
80703 #define PLLCLKMODA2__PLL_SVREG__VERIFY(src) \
80704 (!((((u_int32_t)(src)\
80717 #define PLLCLKMODA2__HI_FREQ_EN__READ(src) \
80718 (((u_int32_t)(src)\
80720 #define PLLCLKMODA2__HI_FREQ_EN__WRITE(src) \
80721 (((u_int32_t)(src)\
80723 #define PLLCLKMODA2__HI_FREQ_EN__MODIFY(dst, src) \
80725 ~0x00004000U) | (((u_int32_t)(src) <<\
80727 #define PLLCLKMODA2__HI_FREQ_EN__VERIFY(src) \
80728 (!((((u_int32_t)(src)\
80741 #define PLLCLKMODA2__DAC_CLK_SEL__READ(src) \
80742 (((u_int32_t)(src)\
80744 #define PLLCLKMODA2__DAC_CLK_SEL__WRITE(src) \
80745 (((u_int32_t)(src)\
80747 #define PLLCLKMODA2__DAC_CLK_SEL__MODIFY(dst, src) \
80749 ~0x00038000U) | (((u_int32_t)(src) <<\
80751 #define PLLCLKMODA2__DAC_CLK_SEL__VERIFY(src) \
80752 (!((((u_int32_t)(src)\
80759 #define PLLCLKMODA2__RST_WARM_INT_L__READ(src) \
80760 (((u_int32_t)(src)\
80762 #define PLLCLKMODA2__RST_WARM_INT_L__WRITE(src) \
80763 (((u_int32_t)(src)\
80765 #define PLLCLKMODA2__RST_WARM_INT_L__MODIFY(dst, src) \
80767 ~0x00040000U) | (((u_int32_t)(src) <<\
80769 #define PLLCLKMODA2__RST_WARM_INT_L__VERIFY(src) \
80770 (!((((u_int32_t)(src)\
80783 #define PLLCLKMODA2__PLL_KVCO__READ(src) \
80784 (((u_int32_t)(src)\
80786 #define PLLCLKMODA2__PLL_KVCO__WRITE(src) \
80787 (((u_int32_t)(src)\
80789 #define PLLCLKMODA2__PLL_KVCO__MODIFY(dst, src) \
80791 ~0x00180000U) | (((u_int32_t)(src) <<\
80793 #define PLLCLKMODA2__PLL_KVCO__VERIFY(src) \
80794 (!((((u_int32_t)(src)\
80801 #define PLLCLKMODA2__PLLICP__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21)
80802 #define PLLCLKMODA2__PLLICP__WRITE(src) \
80803 (((u_int32_t)(src)\
80805 #define PLLCLKMODA2__PLLICP__MODIFY(dst, src) \
80807 ~0x00e00000U) | (((u_int32_t)(src) <<\
80809 #define PLLCLKMODA2__PLLICP__VERIFY(src) \
80810 (!((((u_int32_t)(src)\
80817 #define PLLCLKMODA2__PLLFILTER__READ(src) \
80818 (((u_int32_t)(src)\
80820 #define PLLCLKMODA2__PLLFILTER__WRITE(src) \
80821 (((u_int32_t)(src)\
80823 #define PLLCLKMODA2__PLLFILTER__MODIFY(dst, src) \
80825 ~0xff000000U) | (((u_int32_t)(src) <<\
80827 #define PLLCLKMODA2__PLLFILTER__VERIFY(src) \
80828 (!((((u_int32_t)(src)\
80848 #define TOP__SEL_TEMPSENSOR__READ(src) (u_int32_t)(src) & 0x00000001U
80849 #define TOP__SEL_TEMPSENSOR__WRITE(src) ((u_int32_t)(src) & 0x00000001U)
80850 #define TOP__SEL_TEMPSENSOR__MODIFY(dst, src) \
80852 ~0x00000001U) | ((u_int32_t)(src) &\
80854 #define TOP__SEL_TEMPSENSOR__VERIFY(src) (!(((u_int32_t)(src) & ~0x00000001U)))
80866 #define TOP__XPABIAS_BYPASS__READ(src) (((u_int32_t)(src) & 0x00000002U) >> 1)
80867 #define TOP__XPABIAS_BYPASS__WRITE(src) (((u_int32_t)(src) << 1) & 0x00000002U)
80868 #define TOP__XPABIAS_BYPASS__MODIFY(dst, src) \
80870 ~0x00000002U) | (((u_int32_t)(src) <<\
80872 #define TOP__XPABIAS_BYPASS__VERIFY(src) \
80873 (!((((u_int32_t)(src)\
80886 #define TOP__TESTIQ_RSEL__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
80887 #define TOP__TESTIQ_RSEL__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
80888 #define TOP__TESTIQ_RSEL__MODIFY(dst, src) \
80890 ~0x00000004U) | (((u_int32_t)(src) <<\
80892 #define TOP__TESTIQ_RSEL__VERIFY(src) \
80893 (!((((u_int32_t)(src)\
80906 #define TOP__CLK107_EN__READ(src) (((u_int32_t)(src) & 0x00000008U) >> 3)
80907 #define TOP__CLK107_EN__WRITE(src) (((u_int32_t)(src) << 3) & 0x00000008U)
80908 #define TOP__CLK107_EN__MODIFY(dst, src) \
80910 ~0x00000008U) | (((u_int32_t)(src) <<\
80912 #define TOP__CLK107_EN__VERIFY(src) \
80913 (!((((u_int32_t)(src)\
80926 #define TOP__TEST_PAD_EN__READ(src) (((u_int32_t)(src) & 0x00000010U) >> 4)
80927 #define TOP__TEST_PAD_EN__WRITE(src) (((u_int32_t)(src) << 4) & 0x00000010U)
80928 #define TOP__TEST_PAD_EN__MODIFY(dst, src) \
80930 ~0x00000010U) | (((u_int32_t)(src) <<\
80932 #define TOP__TEST_PAD_EN__VERIFY(src) \
80933 (!((((u_int32_t)(src)\
80946 #define TOP__PWDV2I__READ(src) (((u_int32_t)(src) & 0x00000020U) >> 5)
80947 #define TOP__PWDV2I__WRITE(src) (((u_int32_t)(src) << 5) & 0x00000020U)
80948 #define TOP__PWDV2I__MODIFY(dst, src) \
80950 ~0x00000020U) | (((u_int32_t)(src) <<\
80952 #define TOP__PWDV2I__VERIFY(src) (!((((u_int32_t)(src) << 5) & ~0x00000020U)))
80964 #define TOP__PWDBIAS__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6)
80965 #define TOP__PWDBIAS__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U)
80966 #define TOP__PWDBIAS__MODIFY(dst, src) \
80968 ~0x00000040U) | (((u_int32_t)(src) <<\
80970 #define TOP__PWDBIAS__VERIFY(src) (!((((u_int32_t)(src) << 6) & ~0x00000040U)))
80982 #define TOP__PWDBG__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7)
80983 #define TOP__PWDBG__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U)
80984 #define TOP__PWDBG__MODIFY(dst, src) \
80986 ~0x00000080U) | (((u_int32_t)(src) <<\
80988 #define TOP__PWDBG__VERIFY(src) (!((((u_int32_t)(src) << 7) & ~0x00000080U)))
81000 #define TOP__XPABIASLVL__READ(src) (((u_int32_t)(src) & 0x00000300U) >> 8)
81001 #define TOP__XPABIASLVL__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000300U)
81002 #define TOP__XPABIASLVL__MODIFY(dst, src) \
81004 ~0x00000300U) | (((u_int32_t)(src) <<\
81006 #define TOP__XPABIASLVL__VERIFY(src) \
81007 (!((((u_int32_t)(src)\
81014 #define TOP__XPAREGULATOR_EN__READ(src) \
81015 (((u_int32_t)(src)\
81017 #define TOP__XPAREGULATOR_EN__WRITE(src) \
81018 (((u_int32_t)(src)\
81020 #define TOP__XPAREGULATOR_EN__MODIFY(dst, src) \
81022 ~0x00000400U) | (((u_int32_t)(src) <<\
81024 #define TOP__XPAREGULATOR_EN__VERIFY(src) \
81025 (!((((u_int32_t)(src)\
81038 #define TOP__SPARE__READ(src) (((u_int32_t)(src) & 0x00001800U) >> 11)
81039 #define TOP__SPARE__WRITE(src) (((u_int32_t)(src) << 11) & 0x00001800U)
81040 #define TOP__SPARE__MODIFY(dst, src) \
81042 ~0x00001800U) | (((u_int32_t)(src) <<\
81044 #define TOP__SPARE__VERIFY(src) (!((((u_int32_t)(src) << 11) & ~0x00001800U)))
81050 #define TOP__ADC_CLK_SEL_CH1__READ(src) \
81051 (((u_int32_t)(src)\
81053 #define TOP__ADC_CLK_SEL_CH1__WRITE(src) \
81054 (((u_int32_t)(src)\
81056 #define TOP__ADC_CLK_SEL_CH1__MODIFY(dst, src) \
81058 ~0x0001e000U) | (((u_int32_t)(src) <<\
81060 #define TOP__ADC_CLK_SEL_CH1__VERIFY(src) \
81061 (!((((u_int32_t)(src)\
81068 #define TOP__TESTIQ_OFF__READ(src) (((u_int32_t)(src) & 0x00020000U) >> 17)
81069 #define TOP__TESTIQ_OFF__WRITE(src) (((u_int32_t)(src) << 17) & 0x00020000U)
81070 #define TOP__TESTIQ_OFF__MODIFY(dst, src) \
81072 ~0x00020000U) | (((u_int32_t)(src) <<\
81074 #define TOP__TESTIQ_OFF__VERIFY(src) \
81075 (!((((u_int32_t)(src)\
81088 #define TOP__TESTIQ_BUFEN__READ(src) (((u_int32_t)(src) & 0x00040000U) >> 18)
81089 #define TOP__TESTIQ_BUFEN__WRITE(src) (((u_int32_t)(src) << 18) & 0x00040000U)
81090 #define TOP__TESTIQ_BUFEN__MODIFY(dst, src) \
81092 ~0x00040000U) | (((u_int32_t)(src) <<\
81094 #define TOP__TESTIQ_BUFEN__VERIFY(src) \
81095 (!((((u_int32_t)(src)\
81108 #define TOP__PAD2GND__READ(src) (((u_int32_t)(src) & 0x00080000U) >> 19)
81109 #define TOP__PAD2GND__WRITE(src) (((u_int32_t)(src) << 19) & 0x00080000U)
81110 #define TOP__PAD2GND__MODIFY(dst, src) \
81112 ~0x00080000U) | (((u_int32_t)(src) <<\
81114 #define TOP__PAD2GND__VERIFY(src) \
81115 (!((((u_int32_t)(src)\
81128 #define TOP__INTH2PAD__READ(src) (((u_int32_t)(src) & 0x00100000U) >> 20)
81129 #define TOP__INTH2PAD__WRITE(src) (((u_int32_t)(src) << 20) & 0x00100000U)
81130 #define TOP__INTH2PAD__MODIFY(dst, src) \
81132 ~0x00100000U) | (((u_int32_t)(src) <<\
81134 #define TOP__INTH2PAD__VERIFY(src) \
81135 (!((((u_int32_t)(src)\
81148 #define TOP__INTH2GND__READ(src) (((u_int32_t)(src) & 0x00200000U) >> 21)
81149 #define TOP__INTH2GND__WRITE(src) (((u_int32_t)(src) << 21) & 0x00200000U)
81150 #define TOP__INTH2GND__MODIFY(dst, src) \
81152 ~0x00200000U) | (((u_int32_t)(src) <<\
81154 #define TOP__INTH2GND__VERIFY(src) \
81155 (!((((u_int32_t)(src)\
81168 #define TOP__INT2PAD__READ(src) (((u_int32_t)(src) & 0x00400000U) >> 22)
81169 #define TOP__INT2PAD__WRITE(src) (((u_int32_t)(src) << 22) & 0x00400000U)
81170 #define TOP__INT2PAD__MODIFY(dst, src) \
81172 ~0x00400000U) | (((u_int32_t)(src) <<\
81174 #define TOP__INT2PAD__VERIFY(src) \
81175 (!((((u_int32_t)(src)\
81188 #define TOP__INT2GND__READ(src) (((u_int32_t)(src) & 0x00800000U) >> 23)
81189 #define TOP__INT2GND__WRITE(src) (((u_int32_t)(src) << 23) & 0x00800000U)
81190 #define TOP__INT2GND__MODIFY(dst, src) \
81192 ~0x00800000U) | (((u_int32_t)(src) <<\
81194 #define TOP__INT2GND__VERIFY(src) \
81195 (!((((u_int32_t)(src)\
81208 #define TOP__ENBTCLK__READ(src) (((u_int32_t)(src) & 0x01000000U) >> 24)
81209 #define TOP__ENBTCLK__WRITE(src) (((u_int32_t)(src) << 24) & 0x01000000U)
81210 #define TOP__ENBTCLK__MODIFY(dst, src) \
81212 ~0x01000000U) | (((u_int32_t)(src) <<\
81214 #define TOP__ENBTCLK__VERIFY(src) \
81215 (!((((u_int32_t)(src)\
81228 #define TOP__PWDPALCLK__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25)
81229 #define TOP__PWDPALCLK__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U)
81230 #define TOP__PWDPALCLK__MODIFY(dst, src) \
81232 ~0x02000000U) | (((u_int32_t)(src) <<\
81234 #define TOP__PWDPALCLK__VERIFY(src) \
81235 (!((((u_int32_t)(src)\
81248 #define TOP__INV_CLK320_ADC__READ(src) (((u_int32_t)(src) & 0x04000000U) >> 26)
81249 #define TOP__INV_CLK320_ADC__WRITE(src) \
81250 (((u_int32_t)(src)\
81252 #define TOP__INV_CLK320_ADC__MODIFY(dst, src) \
81254 ~0x04000000U) | (((u_int32_t)(src) <<\
81256 #define TOP__INV_CLK320_ADC__VERIFY(src) \
81257 (!((((u_int32_t)(src)\
81270 #define TOP__FLIP_REFCLK40__READ(src) (((u_int32_t)(src) & 0x08000000U) >> 27)
81271 #define TOP__FLIP_REFCLK40__WRITE(src) (((u_int32_t)(src) << 27) & 0x08000000U)
81272 #define TOP__FLIP_REFCLK40__MODIFY(dst, src) \
81274 ~0x08000000U) | (((u_int32_t)(src) <<\
81276 #define TOP__FLIP_REFCLK40__VERIFY(src) \
81277 (!((((u_int32_t)(src)\
81290 #define TOP__FLIP_PLLCLK320__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28)
81291 #define TOP__FLIP_PLLCLK320__WRITE(src) \
81292 (((u_int32_t)(src)\
81294 #define TOP__FLIP_PLLCLK320__MODIFY(dst, src) \
81296 ~0x10000000U) | (((u_int32_t)(src) <<\
81298 #define TOP__FLIP_PLLCLK320__VERIFY(src) \
81299 (!((((u_int32_t)(src)\
81312 #define TOP__FLIP_PLLCLK160__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
81313 #define TOP__FLIP_PLLCLK160__WRITE(src) \
81314 (((u_int32_t)(src)\
81316 #define TOP__FLIP_PLLCLK160__MODIFY(dst, src) \
81318 ~0x20000000U) | (((u_int32_t)(src) <<\
81320 #define TOP__FLIP_PLLCLK160__VERIFY(src) \
81321 (!((((u_int32_t)(src)\
81334 #define TOP__CLK_SEL__READ(src) (((u_int32_t)(src) & 0xc0000000U) >> 30)
81335 #define TOP__CLK_SEL__WRITE(src) (((u_int32_t)(src) << 30) & 0xc0000000U)
81336 #define TOP__CLK_SEL__MODIFY(dst, src) \
81338 ~0xc0000000U) | (((u_int32_t)(src) <<\
81340 #define TOP__CLK_SEL__VERIFY(src) \
81341 (!((((u_int32_t)(src)\
81361 #define TOP2__TESTTXIQ_ENBYPASS_B__READ(src) (u_int32_t)(src) & 0x00000007U
81362 #define TOP2__TESTTXIQ_ENBYPASS_B__WRITE(src) ((u_int32_t)(src) & 0x00000007U)
81363 #define TOP2__TESTTXIQ_ENBYPASS_B__MODIFY(dst, src) \
81365 ~0x00000007U) | ((u_int32_t)(src) &\
81367 #define TOP2__TESTTXIQ_ENBYPASS_B__VERIFY(src) \
81368 (!(((u_int32_t)(src)\
81375 #define TOP2__DAC_CLK_SEL_CH2__READ(src) \
81376 (((u_int32_t)(src)\
81378 #define TOP2__DAC_CLK_SEL_CH2__WRITE(src) \
81379 (((u_int32_t)(src)\
81381 #define TOP2__DAC_CLK_SEL_CH2__MODIFY(dst, src) \
81383 ~0x00000038U) | (((u_int32_t)(src) <<\
81385 #define TOP2__DAC_CLK_SEL_CH2__VERIFY(src) \
81386 (!((((u_int32_t)(src)\
81393 #define TOP2__DAC_CLK_SEL_CH1__READ(src) \
81394 (((u_int32_t)(src)\
81396 #define TOP2__DAC_CLK_SEL_CH1__WRITE(src) \
81397 (((u_int32_t)(src)\
81399 #define TOP2__DAC_CLK_SEL_CH1__MODIFY(dst, src) \
81401 ~0x000001c0U) | (((u_int32_t)(src) <<\
81403 #define TOP2__DAC_CLK_SEL_CH1__VERIFY(src) \
81404 (!((((u_int32_t)(src)\
81411 #define TOP2__TESTTXIQ_RCTRL__READ(src) (((u_int32_t)(src) & 0x00000e00U) >> 9)
81412 #define TOP2__TESTTXIQ_RCTRL__WRITE(src) \
81413 (((u_int32_t)(src)\
81415 #define TOP2__TESTTXIQ_RCTRL__MODIFY(dst, src) \
81417 ~0x00000e00U) | (((u_int32_t)(src) <<\
81419 #define TOP2__TESTTXIQ_RCTRL__VERIFY(src) \
81420 (!((((u_int32_t)(src)\
81427 #define TOP2__TESTTXIQ_ENLOOPBACK__READ(src) \
81428 (((u_int32_t)(src)\
81430 #define TOP2__TESTTXIQ_ENLOOPBACK__WRITE(src) \
81431 (((u_int32_t)(src)\
81433 #define TOP2__TESTTXIQ_ENLOOPBACK__MODIFY(dst, src) \
81435 ~0x00007000U) | (((u_int32_t)(src) <<\
81437 #define TOP2__TESTTXIQ_ENLOOPBACK__VERIFY(src) \
81438 (!((((u_int32_t)(src)\
81445 #define TOP2__TESTTXIQ_PWD__READ(src) (((u_int32_t)(src) & 0x00038000U) >> 15)
81446 #define TOP2__TESTTXIQ_PWD__WRITE(src) (((u_int32_t)(src) << 15) & 0x00038000U)
81447 #define TOP2__TESTTXIQ_PWD__MODIFY(dst, src) \
81449 ~0x00038000U) | (((u_int32_t)(src) <<\
81451 #define TOP2__TESTTXIQ_PWD__VERIFY(src) \
81452 (!((((u_int32_t)(src)\
81459 #define TOP2__DACPWD__READ(src) (((u_int32_t)(src) & 0x001c0000U) >> 18)
81460 #define TOP2__DACPWD__WRITE(src) (((u_int32_t)(src) << 18) & 0x001c0000U)
81461 #define TOP2__DACPWD__MODIFY(dst, src) \
81463 ~0x001c0000U) | (((u_int32_t)(src) <<\
81465 #define TOP2__DACPWD__VERIFY(src) \
81466 (!((((u_int32_t)(src)\
81473 #define TOP2__ADCPWD__READ(src) (((u_int32_t)(src) & 0x00e00000U) >> 21)
81474 #define TOP2__ADCPWD__WRITE(src) (((u_int32_t)(src) << 21) & 0x00e00000U)
81475 #define TOP2__ADCPWD__MODIFY(dst, src) \
81477 ~0x00e00000U) | (((u_int32_t)(src) <<\
81479 #define TOP2__ADCPWD__VERIFY(src) \
81480 (!((((u_int32_t)(src)\
81487 #define TOP2__LOCAL_ADDACPWD__READ(src) \
81488 (((u_int32_t)(src)\
81490 #define TOP2__LOCAL_ADDACPWD__WRITE(src) \
81491 (((u_int32_t)(src)\
81493 #define TOP2__LOCAL_ADDACPWD__MODIFY(dst, src) \
81495 ~0x01000000U) | (((u_int32_t)(src) <<\
81497 #define TOP2__LOCAL_ADDACPWD__VERIFY(src) \
81498 (!((((u_int32_t)(src)\
81511 #define TOP2__LOCAL_XPAON__READ(src) (((u_int32_t)(src) & 0x02000000U) >> 25)
81512 #define TOP2__LOCAL_XPAON__WRITE(src) (((u_int32_t)(src) << 25) & 0x02000000U)
81513 #define TOP2__LOCAL_XPAON__MODIFY(dst, src) \
81515 ~0x02000000U) | (((u_int32_t)(src) <<\
81517 #define TOP2__LOCAL_XPAON__VERIFY(src) \
81518 (!((((u_int32_t)(src)\
81531 #define TOP2__XPA5ON__READ(src) (((u_int32_t)(src) & 0x1c000000U) >> 26)
81532 #define TOP2__XPA5ON__WRITE(src) (((u_int32_t)(src) << 26) & 0x1c000000U)
81533 #define TOP2__XPA5ON__MODIFY(dst, src) \
81535 ~0x1c000000U) | (((u_int32_t)(src) <<\
81537 #define TOP2__XPA5ON__VERIFY(src) \
81538 (!((((u_int32_t)(src)\
81545 #define TOP2__XPA2ON__READ(src) (((u_int32_t)(src) & 0xe0000000U) >> 29)
81546 #define TOP2__XPA2ON__WRITE(src) (((u_int32_t)(src) << 29) & 0xe0000000U)
81547 #define TOP2__XPA2ON__MODIFY(dst, src) \
81549 ~0xe0000000U) | (((u_int32_t)(src) <<\
81551 #define TOP2__XPA2ON__VERIFY(src) \
81552 (!((((u_int32_t)(src)\
81572 #define THERM__XPABIASLVL_MSB__READ(src) (u_int32_t)(src) & 0x00000003U
81573 #define THERM__XPABIASLVL_MSB__WRITE(src) ((u_int32_t)(src) & 0x00000003U)
81574 #define THERM__XPABIASLVL_MSB__MODIFY(dst, src) \
81576 ~0x00000003U) | ((u_int32_t)(src) &\
81578 #define THERM__XPABIASLVL_MSB__VERIFY(src) \
81579 (!(((u_int32_t)(src)\
81586 #define THERM__XPASHORT2GND__READ(src) (((u_int32_t)(src) & 0x00000004U) >> 2)
81587 #define THERM__XPASHORT2GND__WRITE(src) (((u_int32_t)(src) << 2) & 0x00000004U)
81588 #define THERM__XPASHORT2GND__MODIFY(dst, src) \
81590 ~0x00000004U) | (((u_int32_t)(src) <<\
81592 #define THERM__XPASHORT2GND__VERIFY(src) \
81593 (!((((u_int32_t)(src)\
81606 #define THERM__ADC_CLK_SEL_CH2__READ(src) \
81607 (((u_int32_t)(src)\
81609 #define THERM__ADC_CLK_SEL_CH2__WRITE(src) \
81610 (((u_int32_t)(src)\
81612 #define THERM__ADC_CLK_SEL_CH2__MODIFY(dst, src) \
81614 ~0x00000078U) | (((u_int32_t)(src) <<\
81616 #define THERM__ADC_CLK_SEL_CH2__VERIFY(src) \
81617 (!((((u_int32_t)(src)\
81624 #define THERM__SAR_ADC_DONE__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7)
81636 #define THERM__SAR_ADC_OUT__READ(src) (((u_int32_t)(src) & 0x0000ff00U) >> 8)
81642 #define THERM__SAR_DACTEST_CODE__READ(src) \
81643 (((u_int32_t)(src)\
81645 #define THERM__SAR_DACTEST_CODE__WRITE(src) \
81646 (((u_int32_t)(src)\
81648 #define THERM__SAR_DACTEST_CODE__MODIFY(dst, src) \
81650 ~0x00ff0000U) | (((u_int32_t)(src) <<\
81652 #define THERM__SAR_DACTEST_CODE__VERIFY(src) \
81653 (!((((u_int32_t)(src)\
81660 #define THERM__SAR_DACTEST_EN__READ(src) \
81661 (((u_int32_t)(src)\
81663 #define THERM__SAR_DACTEST_EN__WRITE(src) \
81664 (((u_int32_t)(src)\
81666 #define THERM__SAR_DACTEST_EN__MODIFY(dst, src) \
81668 ~0x01000000U) | (((u_int32_t)(src) <<\
81670 #define THERM__SAR_DACTEST_EN__VERIFY(src) \
81671 (!((((u_int32_t)(src)\
81684 #define THERM__SAR_ADCCAL_EN__READ(src) \
81685 (((u_int32_t)(src)\
81687 #define THERM__SAR_ADCCAL_EN__WRITE(src) \
81688 (((u_int32_t)(src)\
81690 #define THERM__SAR_ADCCAL_EN__MODIFY(dst, src) \
81692 ~0x02000000U) | (((u_int32_t)(src) <<\
81694 #define THERM__SAR_ADCCAL_EN__VERIFY(src) \
81695 (!((((u_int32_t)(src)\
81708 #define THERM__THERMSEL__READ(src) (((u_int32_t)(src) & 0x0c000000U) >> 26)
81709 #define THERM__THERMSEL__WRITE(src) (((u_int32_t)(src) << 26) & 0x0c000000U)
81710 #define THERM__THERMSEL__MODIFY(dst, src) \
81712 ~0x0c000000U) | (((u_int32_t)(src) <<\
81714 #define THERM__THERMSEL__VERIFY(src) \
81715 (!((((u_int32_t)(src)\
81722 #define THERM__SAR_SLOW_EN__READ(src) (((u_int32_t)(src) & 0x10000000U) >> 28)
81723 #define THERM__SAR_SLOW_EN__WRITE(src) (((u_int32_t)(src) << 28) & 0x10000000U)
81724 #define THERM__SAR_SLOW_EN__MODIFY(dst, src) \
81726 ~0x10000000U) | (((u_int32_t)(src) <<\
81728 #define THERM__SAR_SLOW_EN__VERIFY(src) \
81729 (!((((u_int32_t)(src)\
81742 #define THERM__THERMSTART__READ(src) (((u_int32_t)(src) & 0x20000000U) >> 29)
81743 #define THERM__THERMSTART__WRITE(src) (((u_int32_t)(src) << 29) & 0x20000000U)
81744 #define THERM__THERMSTART__MODIFY(dst, src) \
81746 ~0x20000000U) | (((u_int32_t)(src) <<\
81748 #define THERM__THERMSTART__VERIFY(src) \
81749 (!((((u_int32_t)(src)\
81762 #define THERM__SAR_AUTOPWD_EN__READ(src) \
81763 (((u_int32_t)(src)\
81765 #define THERM__SAR_AUTOPWD_EN__WRITE(src) \
81766 (((u_int32_t)(src)\
81768 #define THERM__SAR_AUTOPWD_EN__MODIFY(dst, src) \
81770 ~0x40000000U) | (((u_int32_t)(src) <<\
81772 #define THERM__SAR_AUTOPWD_EN__VERIFY(src) \
81773 (!((((u_int32_t)(src)\
81786 #define THERM__LOCAL_THERM__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
81787 #define THERM__LOCAL_THERM__WRITE(src) (((u_int32_t)(src) << 31) & 0x80000000U)
81788 #define THERM__LOCAL_THERM__MODIFY(dst, src) \
81790 ~0x80000000U) | (((u_int32_t)(src) <<\
81792 #define THERM__LOCAL_THERM__VERIFY(src) \
81793 (!((((u_int32_t)(src)\
81819 #define XTAL__SPARE__READ(src) (u_int32_t)(src) & 0x0000003fU
81820 #define XTAL__SPARE__WRITE(src) ((u_int32_t)(src) & 0x0000003fU)
81821 #define XTAL__SPARE__MODIFY(dst, src) \
81823 ~0x0000003fU) | ((u_int32_t)(src) &\
81825 #define XTAL__SPARE__VERIFY(src) (!(((u_int32_t)(src) & ~0x0000003fU)))
81831 #define XTAL__LOCAL_XTAL__READ(src) (((u_int32_t)(src) & 0x00000040U) >> 6)
81832 #define XTAL__LOCAL_XTAL__WRITE(src) (((u_int32_t)(src) << 6) & 0x00000040U)
81833 #define XTAL__LOCAL_XTAL__MODIFY(dst, src) \
81835 ~0x00000040U) | (((u_int32_t)(src) <<\
81837 #define XTAL__LOCAL_XTAL__VERIFY(src) \
81838 (!((((u_int32_t)(src)\
81851 #define XTAL__XTAL_PWDCLKIN__READ(src) (((u_int32_t)(src) & 0x00000080U) >> 7)
81852 #define XTAL__XTAL_PWDCLKIN__WRITE(src) (((u_int32_t)(src) << 7) & 0x00000080U)
81853 #define XTAL__XTAL_PWDCLKIN__MODIFY(dst, src) \
81855 ~0x00000080U) | (((u_int32_t)(src) <<\
81857 #define XTAL__XTAL_PWDCLKIN__VERIFY(src) \
81858 (!((((u_int32_t)(src)\
81871 #define XTAL__XTAL_OSCON__READ(src) (((u_int32_t)(src) & 0x00000100U) >> 8)
81872 #define XTAL__XTAL_OSCON__WRITE(src) (((u_int32_t)(src) << 8) & 0x00000100U)
81873 #define XTAL__XTAL_OSCON__MODIFY(dst, src) \
81875 ~0x00000100U) | (((u_int32_t)(src) <<\
81877 #define XTAL__XTAL_OSCON__VERIFY(src) \
81878 (!((((u_int32_t)(src)\
81891 #define XTAL__XTAL_SELVREG__READ(src) (((u_int32_t)(src) & 0x00000200U) >> 9)
81892 #define XTAL__XTAL_SELVREG__WRITE(src) (((u_int32_t)(src) << 9) & 0x00000200U)
81893 #define XTAL__XTAL_SELVREG__MODIFY(dst, src) \
81895 ~0x00000200U) | (((u_int32_t)(src) <<\
81897 #define XTAL__XTAL_SELVREG__VERIFY(src) \
81898 (!((((u_int32_t)(src)\
81911 #define XTAL__XTAL_LBIAS2X__READ(src) (((u_int32_t)(src) & 0x00000400U) >> 10)
81912 #define XTAL__XTAL_LBIAS2X__WRITE(src) (((u_int32_t)(src) << 10) & 0x00000400U)
81913 #define XTAL__XTAL_LBIAS2X__MODIFY(dst, src) \
81915 ~0x00000400U) | (((u_int32_t)(src) <<\
81917 #define XTAL__XTAL_LBIAS2X__VERIFY(src) \
81918 (!((((u_int32_t)(src)\
81931 #define XTAL__XTAL_BIAS2X__READ(src) (((u_int32_t)(src) & 0x00000800U) >> 11)
81932 #define XTAL__XTAL_BIAS2X__WRITE(src) (((u_int32_t)(src) << 11) & 0x00000800U)
81933 #define XTAL__XTAL_BIAS2X__MODIFY(dst, src) \
81935 ~0x00000800U) | (((u_int32_t)(src) <<\
81937 #define XTAL__XTAL_BIAS2X__VERIFY(src) \
81938 (!((((u_int32_t)(src)\
81951 #define XTAL__XTAL_PWDCLKD__READ(src) (((u_int32_t)(src) & 0x00001000U) >> 12)
81952 #define XTAL__XTAL_PWDCLKD__WRITE(src) (((u_int32_t)(src) << 12) & 0x00001000U)
81953 #define XTAL__XTAL_PWDCLKD__MODIFY(dst, src) \
81955 ~0x00001000U) | (((u_int32_t)(src) <<\
81957 #define XTAL__XTAL_PWDCLKD__VERIFY(src) \
81958 (!((((u_int32_t)(src)\
81971 #define XTAL__XTAL_LOCALBIAS__READ(src) \
81972 (((u_int32_t)(src)\
81974 #define XTAL__XTAL_LOCALBIAS__WRITE(src) \
81975 (((u_int32_t)(src)\
81977 #define XTAL__XTAL_LOCALBIAS__MODIFY(dst, src) \
81979 ~0x00002000U) | (((u_int32_t)(src) <<\
81981 #define XTAL__XTAL_LOCALBIAS__VERIFY(src) \
81982 (!((((u_int32_t)(src)\
81995 #define XTAL__XTAL_SHORTXIN__READ(src) (((u_int32_t)(src) & 0x00004000U) >> 14)
81996 #define XTAL__XTAL_SHORTXIN__WRITE(src) \
81997 (((u_int32_t)(src)\
81999 #define XTAL__XTAL_SHORTXIN__MODIFY(dst, src) \
82001 ~0x00004000U) | (((u_int32_t)(src) <<\
82003 #define XTAL__XTAL_SHORTXIN__VERIFY(src) \
82004 (!((((u_int32_t)(src)\
82017 #define XTAL__XTAL_DRVSTR__READ(src) (((u_int32_t)(src) & 0x00018000U) >> 15)
82018 #define XTAL__XTAL_DRVSTR__WRITE(src) (((u_int32_t)(src) << 15) & 0x00018000U)
82019 #define XTAL__XTAL_DRVSTR__MODIFY(dst, src) \
82021 ~0x00018000U) | (((u_int32_t)(src) <<\
82023 #define XTAL__XTAL_DRVSTR__VERIFY(src) \
82024 (!((((u_int32_t)(src)\
82031 #define XTAL__XTAL_CAPOUTDAC__READ(src) \
82032 (((u_int32_t)(src)\
82034 #define XTAL__XTAL_CAPOUTDAC__WRITE(src) \
82035 (((u_int32_t)(src)\
82037 #define XTAL__XTAL_CAPOUTDAC__MODIFY(dst, src) \
82039 ~0x00fe0000U) | (((u_int32_t)(src) <<\
82041 #define XTAL__XTAL_CAPOUTDAC__VERIFY(src) \
82042 (!((((u_int32_t)(src)\
82049 #define XTAL__XTAL_CAPINDAC__READ(src) (((u_int32_t)(src) & 0x7f000000U) >> 24)
82050 #define XTAL__XTAL_CAPINDAC__WRITE(src) \
82051 (((u_int32_t)(src)\
82053 #define XTAL__XTAL_CAPINDAC__MODIFY(dst, src) \
82055 ~0x7f000000U) | (((u_int32_t)(src) <<\
82057 #define XTAL__XTAL_CAPINDAC__VERIFY(src) \
82058 (!((((u_int32_t)(src)\
82065 #define XTAL__TCXODET__READ(src) (((u_int32_t)(src) & 0x80000000U) >> 31)
82090 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__READ(src) \
82091 (u_int32_t)(src)\
82093 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__WRITE(src) \
82094 ((u_int32_t)(src)\
82096 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__MODIFY(dst, src) \
82098 ~0x00000001U) | ((u_int32_t)(src) &\
82100 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_DC_ENABLE__VERIFY(src) \
82101 (!(((u_int32_t)(src)\
82114 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__READ(src) \
82115 (((u_int32_t)(src)\
82117 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__WRITE(src) \
82118 (((u_int32_t)(src)\
82120 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__MODIFY(dst, src) \
82122 ~0x00000002U) | (((u_int32_t)(src) <<\
82124 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE0_ENABLE__VERIFY(src) \
82125 (!((((u_int32_t)(src)\
82138 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__READ(src) \
82139 (((u_int32_t)(src)\
82141 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__WRITE(src) \
82142 (((u_int32_t)(src)\
82144 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__MODIFY(dst, src) \
82146 ~0x00000004U) | (((u_int32_t)(src) <<\
82148 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_TONE1_ENABLE__VERIFY(src) \
82149 (!((((u_int32_t)(src)\
82162 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__READ(src) \
82163 (((u_int32_t)(src)\
82165 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__WRITE(src) \
82166 (((u_int32_t)(src)\
82168 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__MODIFY(dst, src) \
82170 ~0x00000008U) | (((u_int32_t)(src) <<\
82172 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LFTONE0_ENABLE__VERIFY(src) \
82173 (!((((u_int32_t)(src)\
82186 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__READ(src) \
82187 (((u_int32_t)(src)\
82189 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__WRITE(src) \
82190 (((u_int32_t)(src)\
82192 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__MODIFY(dst, src) \
82194 ~0x00000010U) | (((u_int32_t)(src) <<\
82196 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_I__VERIFY(src) \
82197 (!((((u_int32_t)(src)\
82210 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__READ(src) \
82211 (((u_int32_t)(src)\
82213 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__WRITE(src) \
82214 (((u_int32_t)(src)\
82216 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__MODIFY(dst, src) \
82218 ~0x00000020U) | (((u_int32_t)(src) <<\
82220 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_LINRAMP_ENABLE_Q__VERIFY(src) \
82221 (!((((u_int32_t)(src)\
82234 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__READ(src) \
82235 (((u_int32_t)(src)\
82237 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__WRITE(src) \
82238 (((u_int32_t)(src)\
82240 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__MODIFY(dst, src) \
82242 ~0x00000040U) | (((u_int32_t)(src) <<\
82244 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_I__VERIFY(src) \
82245 (!((((u_int32_t)(src)\
82258 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__READ(src) \
82259 (((u_int32_t)(src)\
82261 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__WRITE(src) \
82262 (((u_int32_t)(src)\
82264 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__MODIFY(dst, src) \
82266 ~0x00000080U) | (((u_int32_t)(src) <<\
82268 #define RBIST_CNTRL_TYPE__ATE_TONEGEN_PRBS_ENABLE_Q__VERIFY(src) \
82269 (!((((u_int32_t)(src)\
82282 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__READ(src) \
82283 (((u_int32_t)(src)\
82285 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__WRITE(src) \
82286 (((u_int32_t)(src)\
82288 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__MODIFY(dst, src) \
82290 ~0x00000100U) | (((u_int32_t)(src) <<\
82292 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_WRITE_TO_CANCEL__VERIFY(src) \
82293 (!((((u_int32_t)(src)\
82306 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__READ(src) \
82307 (((u_int32_t)(src)\
82309 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__WRITE(src) \
82310 (((u_int32_t)(src)\
82312 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__MODIFY(dst, src) \
82314 ~0x00000200U) | (((u_int32_t)(src) <<\
82316 #define RBIST_CNTRL_TYPE__ATE_CMAC_DC_ENABLE__VERIFY(src) \
82317 (!((((u_int32_t)(src)\
82330 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__READ(src) \
82331 (((u_int32_t)(src)\
82333 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__WRITE(src) \
82334 (((u_int32_t)(src)\
82336 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__MODIFY(dst, src) \
82338 ~0x00000400U) | (((u_int32_t)(src) <<\
82340 #define RBIST_CNTRL_TYPE__ATE_CMAC_CORR_ENABLE__VERIFY(src) \
82341 (!((((u_int32_t)(src)\
82354 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__READ(src) \
82355 (((u_int32_t)(src)\
82357 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__WRITE(src) \
82358 (((u_int32_t)(src)\
82360 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__MODIFY(dst, src) \
82362 ~0x00000800U) | (((u_int32_t)(src) <<\
82364 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_ENABLE__VERIFY(src) \
82365 (!((((u_int32_t)(src)\
82378 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__READ(src) \
82379 (((u_int32_t)(src)\
82381 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__WRITE(src) \
82382 (((u_int32_t)(src)\
82384 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__MODIFY(dst, src) \
82386 ~0x00001000U) | (((u_int32_t)(src) <<\
82388 #define RBIST_CNTRL_TYPE__ATE_CMAC_IQ_ENABLE__VERIFY(src) \
82389 (!((((u_int32_t)(src)\
82402 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__READ(src) \
82403 (((u_int32_t)(src)\
82405 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__WRITE(src) \
82406 (((u_int32_t)(src)\
82408 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__MODIFY(dst, src) \
82410 ~0x00002000U) | (((u_int32_t)(src) <<\
82412 #define RBIST_CNTRL_TYPE__ATE_CMAC_I2Q2_ENABLE__VERIFY(src) \
82413 (!((((u_int32_t)(src)\
82426 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__READ(src) \
82427 (((u_int32_t)(src)\
82429 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__WRITE(src) \
82430 (((u_int32_t)(src)\
82432 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__MODIFY(dst, src) \
82434 ~0x00004000U) | (((u_int32_t)(src) <<\
82436 #define RBIST_CNTRL_TYPE__ATE_CMAC_POWER_HPF_ENABLE__VERIFY(src) \
82437 (!((((u_int32_t)(src)\
82450 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__READ(src) \
82451 (((u_int32_t)(src)\
82453 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__WRITE(src) \
82454 (((u_int32_t)(src)\
82456 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__MODIFY(dst, src) \
82458 ~0x00008000U) | (((u_int32_t)(src) <<\
82460 #define RBIST_CNTRL_TYPE__ATE_RXDAC_CALIBRATE__VERIFY(src) \
82461 (!((((u_int32_t)(src)\
82474 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__READ(src) \
82475 (((u_int32_t)(src)\
82477 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__WRITE(src) \
82478 (((u_int32_t)(src)\
82480 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__MODIFY(dst, src) \
82482 ~0x00010000U) | (((u_int32_t)(src) <<\
82484 #define RBIST_CNTRL_TYPE__ATE_RBIST_ENABLE__VERIFY(src) \
82485 (!((((u_int32_t)(src)\
82511 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__READ(src) \
82512 (u_int32_t)(src)\
82514 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__WRITE(src) \
82515 ((u_int32_t)(src)\
82517 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__MODIFY(dst, src) \
82519 ~0x000007ffU) | ((u_int32_t)(src) &\
82521 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_I__VERIFY(src) \
82522 (!(((u_int32_t)(src)\
82529 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__READ(src) \
82530 (((u_int32_t)(src)\
82532 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__WRITE(src) \
82533 (((u_int32_t)(src)\
82535 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__MODIFY(dst, src) \
82537 ~0x07ff0000U) | (((u_int32_t)(src) <<\
82539 #define TX_DC_OFFSET_TYPE__ATE_TONEGEN_DC_Q__VERIFY(src) \
82540 (!((((u_int32_t)(src)\
82560 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__READ(src) \
82561 (u_int32_t)(src)\
82563 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__WRITE(src) \
82564 ((u_int32_t)(src)\
82566 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__MODIFY(dst, src) \
82568 ~0x0000007fU) | ((u_int32_t)(src) &\
82570 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_FREQ__VERIFY(src) \
82571 (!(((u_int32_t)(src)\
82578 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__READ(src) \
82579 (((u_int32_t)(src)\
82581 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__WRITE(src) \
82582 (((u_int32_t)(src)\
82584 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__MODIFY(dst, src) \
82586 ~0x00000f00U) | (((u_int32_t)(src) <<\
82588 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_EXP__VERIFY(src) \
82589 (!((((u_int32_t)(src)\
82596 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__READ(src) \
82597 (((u_int32_t)(src)\
82599 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__WRITE(src) \
82600 (((u_int32_t)(src)\
82602 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__MODIFY(dst, src) \
82604 ~0x00ff0000U) | (((u_int32_t)(src) <<\
82606 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_A_MAN__VERIFY(src) \
82607 (!((((u_int32_t)(src)\
82614 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__READ(src) \
82615 (((u_int32_t)(src)\
82617 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__WRITE(src) \
82618 (((u_int32_t)(src)\
82620 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__MODIFY(dst, src) \
82622 ~0x7f000000U) | (((u_int32_t)(src) <<\
82624 #define TX_TONEGEN_TYPE__ATE_TONEGEN_TONE_TAU_K__VERIFY(src) \
82625 (!((((u_int32_t)(src)\
82651 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__READ(src) \
82652 (u_int32_t)(src)\
82654 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__WRITE(src) \
82655 ((u_int32_t)(src)\
82657 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__MODIFY(dst, src) \
82659 ~0x000007ffU) | ((u_int32_t)(src) &\
82661 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_INIT__VERIFY(src) \
82662 (!(((u_int32_t)(src)\
82669 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__READ(src) \
82670 (((u_int32_t)(src)\
82672 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__WRITE(src) \
82673 (((u_int32_t)(src)\
82675 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__MODIFY(dst, src) \
82677 ~0x003ff000U) | (((u_int32_t)(src) <<\
82679 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_DWELL__VERIFY(src) \
82680 (!((((u_int32_t)(src)\
82687 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__READ(src) \
82688 (((u_int32_t)(src)\
82690 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__WRITE(src) \
82691 (((u_int32_t)(src)\
82693 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__MODIFY(dst, src) \
82695 ~0x3f000000U) | (((u_int32_t)(src) <<\
82697 #define TX_LINEAR_RAMP_TYPE__ATE_TONEGEN_LINRAMP_STEP__VERIFY(src) \
82698 (!((((u_int32_t)(src)\
82721 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__READ(src) \
82722 (u_int32_t)(src)\
82724 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__WRITE(src) \
82725 ((u_int32_t)(src)\
82727 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__MODIFY(dst, src) \
82729 ~0x000003ffU) | ((u_int32_t)(src) &\
82731 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_I__VERIFY(src) \
82732 (!(((u_int32_t)(src)\
82739 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__READ(src) \
82740 (((u_int32_t)(src)\
82742 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__WRITE(src) \
82743 (((u_int32_t)(src)\
82745 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__MODIFY(dst, src) \
82747 ~0x03ff0000U) | (((u_int32_t)(src) <<\
82749 #define TX_PRBS_MAG_TYPE__ATE_TONEGEN_PRBS_MAGNITUDE_Q__VERIFY(src) \
82750 (!((((u_int32_t)(src)\
82770 #define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__READ(src) \
82771 (u_int32_t)(src)\
82773 #define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__WRITE(src) \
82774 ((u_int32_t)(src)\
82776 #define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__MODIFY(dst, src) \
82778 ~0x7fffffffU) | ((u_int32_t)(src) &\
82780 #define TX_PRBS_SEED_TYPE__ATE_TONEGEN_PRBS_SEED__VERIFY(src) \
82781 (!(((u_int32_t)(src)\
82804 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__READ(src) \
82805 (u_int32_t)(src)\
82807 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__WRITE(src) \
82808 ((u_int32_t)(src)\
82810 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__MODIFY(dst, src) \
82812 ~0x000003ffU) | ((u_int32_t)(src) &\
82814 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_I__VERIFY(src) \
82815 (!(((u_int32_t)(src)\
82822 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__READ(src) \
82823 (((u_int32_t)(src)\
82825 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__WRITE(src) \
82826 (((u_int32_t)(src)\
82828 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__MODIFY(dst, src) \
82830 ~0x03ff0000U) | (((u_int32_t)(src) <<\
82832 #define CMAC_DC_CANCEL_TYPE__ATE_CMAC_DC_CANCEL_Q__VERIFY(src) \
82833 (!((((u_int32_t)(src)\
82853 #define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__READ(src) \
82854 (u_int32_t)(src)\
82856 #define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__WRITE(src) \
82857 ((u_int32_t)(src)\
82859 #define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__MODIFY(dst, src) \
82861 ~0x0000000fU) | ((u_int32_t)(src) &\
82863 #define CMAC_DC_OFFSET_TYPE__ATE_CMAC_DC_CYCLES__VERIFY(src) \
82864 (!(((u_int32_t)(src)\
82884 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__READ(src) \
82885 (u_int32_t)(src)\
82887 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__WRITE(src) \
82888 ((u_int32_t)(src)\
82890 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__MODIFY(dst, src) \
82892 ~0x0000001fU) | ((u_int32_t)(src) &\
82894 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_CYCLES__VERIFY(src) \
82895 (!(((u_int32_t)(src)\
82902 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__READ(src) \
82903 (((u_int32_t)(src)\
82905 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__WRITE(src) \
82906 (((u_int32_t)(src)\
82908 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__MODIFY(dst, src) \
82910 ~0x00003f00U) | (((u_int32_t)(src) <<\
82912 #define CMAC_CORR_TYPE__ATE_CMAC_CORR_FREQ__VERIFY(src) \
82913 (!((((u_int32_t)(src)\
82933 #define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__READ(src) \
82934 (u_int32_t)(src)\
82936 #define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__WRITE(src) \
82937 ((u_int32_t)(src)\
82939 #define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__MODIFY(dst, src) \
82941 ~0x0000000fU) | ((u_int32_t)(src) &\
82943 #define CMAC_POWER_TYPE__ATE_CMAC_POWER_CYCLES__VERIFY(src) \
82944 (!(((u_int32_t)(src)\
82964 #define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__READ(src) \
82965 (u_int32_t)(src)\
82967 #define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__WRITE(src) \
82968 ((u_int32_t)(src)\
82970 #define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__MODIFY(dst, src) \
82972 ~0x0000000fU) | ((u_int32_t)(src) &\
82974 #define CMAC_CROSS_CORR_TYPE__ATE_CMAC_IQ_CYCLES__VERIFY(src) \
82975 (!(((u_int32_t)(src)\
82995 #define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__READ(src) \
82996 (u_int32_t)(src)\
82998 #define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__WRITE(src) \
82999 ((u_int32_t)(src)\
83001 #define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__MODIFY(dst, src) \
83003 ~0x0000000fU) | ((u_int32_t)(src) &\
83005 #define CMAC_I2Q2_TYPE__ATE_CMAC_I2Q2_CYCLES__VERIFY(src) \
83006 (!(((u_int32_t)(src)\
83026 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__READ(src) \
83027 (u_int32_t)(src)\
83029 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__WRITE(src) \
83030 ((u_int32_t)(src)\
83032 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__MODIFY(dst, src) \
83034 ~0x0000000fU) | ((u_int32_t)(src) &\
83036 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_CYCLES__VERIFY(src) \
83037 (!(((u_int32_t)(src)\
83044 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__READ(src) \
83045 (((u_int32_t)(src)\
83047 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__WRITE(src) \
83048 (((u_int32_t)(src)\
83050 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__MODIFY(dst, src) \
83052 ~0x000000f0U) | (((u_int32_t)(src) <<\
83054 #define CMAC_POWER_HPF_TYPE__ATE_CMAC_POWER_HPF_WAIT__VERIFY(src) \
83055 (!((((u_int32_t)(src)\
83075 #define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__READ(src) \
83076 (u_int32_t)(src)\
83078 #define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__WRITE(src) \
83079 ((u_int32_t)(src)\
83081 #define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__MODIFY(dst, src) \
83083 ~0x00000003U) | ((u_int32_t)(src) &\
83085 #define RXDAC_SET1_TYPE__ATE_RXDAC_MUX__VERIFY(src) \
83086 (!(((u_int32_t)(src)\
83093 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__READ(src) \
83094 (((u_int32_t)(src)\
83096 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__WRITE(src) \
83097 (((u_int32_t)(src)\
83099 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__MODIFY(dst, src) \
83101 ~0x00000010U) | (((u_int32_t)(src) <<\
83103 #define RXDAC_SET1_TYPE__ATE_RXDAC_HI_GAIN__VERIFY(src) \
83104 (!((((u_int32_t)(src)\
83117 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__READ(src) \
83118 (((u_int32_t)(src)\
83120 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__WRITE(src) \
83121 (((u_int32_t)(src)\
83123 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__MODIFY(dst, src) \
83125 ~0x00003f00U) | (((u_int32_t)(src) <<\
83127 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_WAIT__VERIFY(src) \
83128 (!((((u_int32_t)(src)\
83135 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__READ(src) \
83136 (((u_int32_t)(src)\
83138 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__WRITE(src) \
83139 (((u_int32_t)(src)\
83141 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__MODIFY(dst, src) \
83143 ~0x000f0000U) | (((u_int32_t)(src) <<\
83145 #define RXDAC_SET1_TYPE__ATE_RXDAC_CAL_MEASURE_TIME__VERIFY(src) \
83146 (!((((u_int32_t)(src)\
83166 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__READ(src) \
83167 (u_int32_t)(src)\
83169 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__WRITE(src) \
83170 ((u_int32_t)(src)\
83172 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__MODIFY(dst, src) \
83174 ~0x0000001fU) | ((u_int32_t)(src) &\
83176 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_HI__VERIFY(src) \
83177 (!(((u_int32_t)(src)\
83184 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__READ(src) \
83185 (((u_int32_t)(src)\
83187 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__WRITE(src) \
83188 (((u_int32_t)(src)\
83190 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__MODIFY(dst, src) \
83192 ~0x00001f00U) | (((u_int32_t)(src) <<\
83194 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_HI__VERIFY(src) \
83195 (!((((u_int32_t)(src)\
83202 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__READ(src) \
83203 (((u_int32_t)(src)\
83205 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__WRITE(src) \
83206 (((u_int32_t)(src)\
83208 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__MODIFY(dst, src) \
83210 ~0x001f0000U) | (((u_int32_t)(src) <<\
83212 #define RXDAC_SET2_TYPE__ATE_RXDAC_I_LOW__VERIFY(src) \
83213 (!((((u_int32_t)(src)\
83220 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__READ(src) \
83221 (((u_int32_t)(src)\
83223 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__WRITE(src) \
83224 (((u_int32_t)(src)\
83226 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__MODIFY(dst, src) \
83228 ~0x1f000000U) | (((u_int32_t)(src) <<\
83230 #define RXDAC_SET2_TYPE__ATE_RXDAC_Q_LOW__VERIFY(src) \
83231 (!((((u_int32_t)(src)\
83251 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__READ(src) \
83252 (u_int32_t)(src)\
83254 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__WRITE(src) \
83255 ((u_int32_t)(src)\
83257 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__MODIFY(dst, src) \
83259 ~0x0000001fU) | ((u_int32_t)(src) &\
83261 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_I_STATIC__VERIFY(src) \
83262 (!(((u_int32_t)(src)\
83269 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__READ(src) \
83270 (((u_int32_t)(src)\
83272 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__WRITE(src) \
83273 (((u_int32_t)(src)\
83275 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__MODIFY(dst, src) \
83277 ~0x00001f00U) | (((u_int32_t)(src) <<\
83279 #define RXDAC_LONG_SHIFT_TYPE__ATE_RXDAC_Q_STATIC__VERIFY(src) \
83280 (!((((u_int32_t)(src)\
83300 #define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__READ(src) \
83301 (u_int32_t)(src)\
83303 #define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__WRITE(src) \
83304 ((u_int32_t)(src)\
83306 #define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__MODIFY(dst, src) \
83308 ~0xffffffffU) | ((u_int32_t)(src) &\
83310 #define CMAC_RESULTS_TYPE__ATE_CMAC_RESULTS__VERIFY(src) \
83311 (!(((u_int32_t)(src)\