ath_hal/ar9300/ar9300_xmit_ds.c

19 #include "ah.h"
34 ar9300_tx_req_intr_desc(struct ath_hal *ah, void *ds)
36     HALDEBUG(ah, HAL_DEBUG_INTERRUPT,
59     struct ath_hal *ah,
74     desclen = (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) ? 0x18 : 0x17;
136 ar9300_set_desc_link(struct ath_hal *ah, void *ds, u_int32_t link)
151 ar9300_get_desc_link_ptr(struct ath_hal *ah, void *ds, u_int32_t **link)
159 ar9300_clear_tx_desc_status(struct ath_hal *ah, void *ds)
170 ar9300_clear_dest_mask(struct ath_hal *ah, void *ds)
202 ar9300_get_tx_rate_code(struct ath_hal *ah, void *ds, struct ath_tx_status *ts)
221     ar9300_set_selfgenrate_limit(ah, ts->ts_rate);
228 ar9300_get_raw_tx_desc(struct ath_hal *ah, u_int32_t *txstatus)
230     struct ath_hal_9300 *ahp = AH9300(ah);
242 ar9300_proc_tx_desc(struct ath_hal *ah, void *txstatus)
244     struct ath_hal_9300 *ahp = AH9300(ah);
260     ath_hal_printf(ah,
262     ath_hal_printf(ah,
314         ar9300_update_tx_trig_level(ah, AH_TRUE);
327         ar9300_update_tx_trig_level(ah, AH_TRUE);
331         ar9300_update_tx_trig_level(ah, AH_TRUE);
371 ar9300_calc_tx_airtime(struct ath_hal *ah, void *ds, struct ath_tx_status *ts,
438 ar9300__cont_tx_mode(struct ath_hal *ah, void *ds, int mode)
455             HALDEBUG(ah, HAL_DEBUG_TXDESC, "s0(%x) s1(%x)\n",
458         HALDEBUG(ah, HAL_DEBUG_TXDESC, "txe(%x) txd(%x)\n",
459                                    OS_REG_READ(ah, AR_Q_TXE),
460                                    OS_REG_READ(ah, AR_Q_TXD)
463             val = OS_REG_READ(ah, AR_QTXDP(i));
464             val2 = OS_REG_READ(ah, AR_QSTS(i)) & AR_Q_STS_PEND_FR_CNT;
465             HALDEBUG(ah, HAL_DEBUG_TXDESC, "[%d] %x %d\n", i, val, val2);
470         OS_REG_WRITE(ah, AR_Q_TXE, 1 << qnum);
482         OS_REG_WRITE(ah, AR_PHY_TEST,
483             (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) );
485         OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000);
486         OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe);
487         OS_REG_WRITE(ah, AR_DIAG_SW,
488             (OS_REG_READ(ah, AR_DIAG_SW) |
492         OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);     /* set receive disable */
498                 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
499                 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
500                 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 100);
501                 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 100);
502                 OS_REG_WRITE(ah, AR_TIME_OUT, 2);
503                 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 100);
506             OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
508             OS_REG_WRITE(ah, AR_D_FPCTL, 0x10 | qnum);
510             OS_REG_WRITE(ah, AR_TXCFG, txcfg);
512             OS_REG_WRITE(ah, AR_QMISC(qnum),        /* set QCU modes */
526                 OS_REG_WRITE(ah, AR_Q_TXD, 1 << i);
529             OS_REG_WRITE(ah, AR_Q_TXD, qbits);
532             OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
533             OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
535             OS_REG_WRITE(ah, AR_DMISC(qnum),
547                 OS_REG_WRITE(ah, AR_DQCUMASK(i), 0);
552         OS_REG_WRITE(ah, AR_PHY_TEST,
553             (OS_REG_READ(ah, AR_PHY_TEST) & ~PHY_AGC_CLR));
554         OS_REG_WRITE(ah, AR_DIAG_SW,
555             (OS_REG_READ(ah, AR_DIAG_SW) &
563 ar9300_set_paprd_tx_desc(struct ath_hal *ah, void *ds, int chain_num)
570 ar9300_is_tx_done(struct ath_hal *ah)
572     struct ath_hal_9300 *ahp = AH9300(ah);
585     struct ath_hal *ah,
595     struct ath_hal_9300 *ahp = AH9300(ah);
637 void ar9300_set_rx_chainmask(struct ath_hal *ah, int rxchainmask)
639     OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rxchainmask);
642 void ar9300_update_loc_ctl_reg(struct ath_hal *ah, int pos_bit)
645     reg_val = OS_REG_READ(ah, AR_LOC_CTL_REG);
649             OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val | AR_LOC_CTL_REG_FS));
650             OS_REG_WRITE(ah, AR_LOC_TIMER_REG, 0);
654         OS_REG_WRITE(ah, AR_LOC_CTL_REG, (reg_val & ~AR_LOC_CTL_REG_FS));
693     struct ath_hal *ah,
704     struct ath_hal_private *ap = AH_PRIVATE(ah);
731     mode = ath_hal_get_curmode(ah, ap->ah_curchan);
734     if (ah->ah_config.ath_hal_desc_tpc) {
740             txpower = ar9300_get_rate_txpower(ah, mode, series[0].RateIndex,
743             txpower = AH9300(ah)->paprd_training_power;
779     if (ah->ah_config.ath_hal_desc_tpc) {
786                 ah, mode, series[1].RateIndex, series[1].ChSel, tx_mode);
788             txpower = AH9300(ah)->paprd_training_power;
798                 ah, mode, series[2].RateIndex, series[2].ChSel, tx_mode);
800             txpower = AH9300(ah)->paprd_training_power;
809                 ah, mode, series[3].RateIndex, series[3].ChSel, tx_mode);
811             txpower = AH9300(ah)->paprd_training_power;
846 ar9300_set_11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
861 ar9300_set_11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
880 ar9300_set_11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
890 ar9300_clr_11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
898 ar9300_set_11n_burst_duration(struct ath_hal *ah, struct ath_desc *ds,
908 ar9300_set_11n_rifs_burst_middle(struct ath_hal *ah, void *ds)
916 ar9300_set_11n_rifs_burst_last(struct ath_hal *ah, void *ds)
924 ar9300_clr_11n_rifs_burst(struct ath_hal *ah, void *ds)
932 ar9300_set_11n_aggr_rifs_burst(struct ath_hal *ah, void *ds)
941 ar9300_set_11n_virtual_more_frag(struct ath_hal *ah, struct ath_desc *ds,
954 ar9300_get_desc_info(struct ath_hal *ah, HAL_DESC_INFO *desc_info)
956     desc_info->txctl_numwords = TXCTL_NUMWORDS(ah);
957     desc_info->txctl_offset = TXCTL_OFFSET(ah);
958     desc_info->txstatus_numwords = TXSTATUS_NUMWORDS(ah);
959     desc_info->txstatus_offset = TXSTATUS_OFFSET(ah);
961     desc_info->rxctl_numwords = RXCTL_NUMWORDS(ah);
962     desc_info->rxctl_offset = RXCTL_OFFSET(ah);
963     desc_info->rxstatus_numwords = RXSTATUS_NUMWORDS(ah);
964     desc_info->rxstatus_offset = RXSTATUS_OFFSET(ah);