Lines Matching refs:ah
21 #include "ah.h"
44 extern HAL_BOOL ar9300_reset_tx_queue(struct ath_hal *ah, u_int q);
45 extern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q);
59 static HAL_BOOL ar9300_tx_iq_cal_hw_run(struct ath_hal *ah);
60 static void ar9300_tx_iq_cal_post_proc(struct ath_hal *ah,HAL_CHANNEL_INTERNAL *ichan,
62 static void ar9300_tx_iq_cal_outlier_detection(struct ath_hal *ah,HAL_CHANNEL_INTERNAL *ichan,
65 static void ar9300_tx_iq_cal_apply(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan);
69 static inline void ar9300_prog_ini(struct ath_hal *ah, struct ar9300_ini_array *ini_arr, int column);
70 static inline void ar9300_set_rf_mode(struct ath_hal *ah, struct ieee80211_channel *chan);
71 static inline HAL_BOOL ar9300_init_cal(struct ath_hal *ah, struct ieee80211_channel *chan, HAL_BOOL skip_if_none, HAL_BOOL apply_last_corr);
72 static inline void ar9300_init_user_settings(struct ath_hal *ah);
94 ar9300_attach_hw_platform(struct ath_hal *ah)
96 struct ath_hal_9300 *ahp = AH9300(ah);
108 ar9300_set_ifs_timing(struct ath_hal *ah, struct ieee80211_channel *chan)
112 regval = OS_REG_READ(ah, AR_USEC);
115 slot = ar9300_mac_to_clks(ah, AR_SLOT_HALF);
116 eifs = ar9300_mac_to_clks(ah, AR_EIFS_HALF);
117 if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { /* fast clock */
127 slot = ar9300_mac_to_clks(ah, AR_SLOT_QUARTER);
128 eifs = ar9300_mac_to_clks(ah, AR_EIFS_QUARTER);
129 if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { /* fast clock */
140 OS_REG_WRITE(ah, AR_USEC, (usec | regval | tx_lat | rx_lat));
141 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
142 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
151 ar9300_init_mfp(struct ath_hal * ah)
155 ath_hal_getcapability(ah, HAL_CAP_MFP, 0, &mfpcap);
159 HALDEBUG(ah, HAL_DEBUG_RESET, "%s forced to use QOSDATA\n", __func__);
166 HALDEBUG(ah, HAL_DEBUG_RESET, "%s using HW crypto\n", __func__);
167 OS_REG_RMW_FIELD(ah,
169 OS_REG_RMW(ah,
177 if (ath_hal_get_mfp_qos(ah)) {
182 OS_REG_RMW_FIELD(ah,
186 HALDEBUG(ah, HAL_DEBUG_RESET, "%s using passthru\n", __func__);
187 OS_REG_RMW(ah,
195 ar9300_get_channel_centers(struct ath_hal *ah, const struct ieee80211_channel *chan,
199 struct ath_hal_9300 *ahp = AH9300(ah);
200 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
255 ar9300_upload_noise_floor(struct ath_hal *ah, int is_2g,
289 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
291 } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah) || AR_SREV_HONEYBEE(ah)) {
305 nf = (OS_REG_READ(ah, regs[i]) & masks[chan]) >> shifts[chan];
322 int16_t ar9300_get_min_cca_pwr(struct ath_hal *ah)
325 // struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
328 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0) {
329 nf = MS(OS_REG_READ(ah, AR_PHY_CCA_0), AR9280_PHY_MINCCA_PWR);
335 nf = AH9300(ah)->nfp->nominal + AH9300(ah)->nf_cw_int_delta +
346 void ar9300_chain_noise_floor(struct ath_hal *ah, int16_t *nf_buf,
349 struct ath_hal_9300 *ahp = AH9300(ah);
353 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
373 if ((!is_scan) && chan == AH_PRIVATE(ah)->ah_curchan) {
374 h = &AH_PRIVATE(ah)->nf_cal_hist;
409 int16_t ar9300_get_nf_from_reg(struct ath_hal *ah, struct ieee80211_channel *chan, int wait_time)
415 ichan = ath_hal_checkchannel(ah, chan);
423 if (!ath_hal_waitfor(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF, 0, wait_time)) {
424 ath_hal_printf(ah, "%s: NF cal is not complete in %dus", __func__, wait_time);
428 ar9300_upload_noise_floor(ah, is_2g, nfarray);
438 ar9300_get_nf_hist_mid(struct ath_hal *ah, HAL_NFCAL_HIST_FULL *h, int reading,
448 HALDEBUG(ah, HAL_DEBUG_NFCAL,
465 static int16_t ar9300_limit_nf_range(struct ath_hal *ah, int16_t nf)
467 if (nf < AH9300(ah)->nfp->min) {
468 return AH9300(ah)->nfp->nominal;
469 } else if (nf > AH9300(ah)->nfp->max) {
470 return AH9300(ah)->nfp->max;
477 ar9300_reset_nf_hist_buff(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
480 HAL_NFCAL_HIST_FULL *home = &AH_PRIVATE(ah)->nf_cal_hist;
512 nf = ar9300_limit_nf_range(ah, h->nf_cal_buffer[0][i]);
516 AH_PRIVATE(ah)->nf_cal_hist.base.priv_nf[i] = nf;
525 ar9300_update_nf_hist_buff(struct ath_hal *ah, HAL_NFCAL_HIST_FULL *h,
531 nf_no_lim_chain0 = ar9300_get_nf_hist_mid(ah, h, 0, hist_len);
533 HALDEBUG(ah, HAL_DEBUG_NFCAL, "%s[%d] BEFORE\n", __func__, __LINE__);
536 HALDEBUG(ah, HAL_DEBUG_NFCAL,
544 ah, ar9300_get_nf_hist_mid(ah, h, i, hist_len));
546 HALDEBUG(ah, HAL_DEBUG_NFCAL, "%s[%d] AFTER\n", __func__, __LINE__);
549 HALDEBUG(ah, HAL_DEBUG_NFCAL,
564 get_noise_floor_thresh(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *chan,
567 struct ath_hal_9300 *ahp = AH9300(ah);
585 HALDEBUG(ah, HAL_DEBUG_CHANNEL, "%s: invalid channel flags 0x%x\n",
598 ar9300_store_new_nf(struct ath_hal *ah, struct ieee80211_channel *chan,
601 // struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
607 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
608 struct ath_hal_9300 *ahp = AH9300(ah);
610 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
648 tsf32 = ar9300_get_tsf32(ah);
649 nf_cal_dur_tsf = tsf32 - AH9300(ah)->nf_tsf32;
657 AH9300(ah)->nf_tsf32 = tsf32;
659 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
666 HALDEBUG(ah, HAL_DEBUG_NFCAL,
669 ar9300_upload_noise_floor(ah, is_2g, nfarray);
687 h = &AH_PRIVATE(ah)->nf_cal_hist;
696 nf_no_lim = ar9300_update_nf_hist_buff(ah, h, nfarray, nf_hist_len);
713 HALDEBUG(ah, HAL_DEBUG_NFCAL,
723 ar9300_get_delta_slope_values(struct ath_hal *ah, u_int32_t coef_scaled,
759 ar9300_set_delta_slope(struct ath_hal *ah, struct ieee80211_channel *chan)
781 ar9300_get_channel_centers(ah, chan, ¢ers);
784 ar9300_get_delta_slope_values(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);
786 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
787 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
795 ar9300_get_delta_slope_values(ah, coef_scaled, &ds_coef_man, &ds_coef_exp);
798 OS_REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, AR_PHY_SGI_DSC_MAN, ds_coef_man);
799 OS_REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA, AR_PHY_SGI_DSC_EXP, ds_coef_exp);
808 ar9300_check_chan(struct ath_hal *ah, const struct ieee80211_channel *chan)
816 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
830 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
838 return (ath_hal_checkchannel(ah, chan));
843 ar9300_set_11n_regs(struct ath_hal *ah, struct ieee80211_channel *chan,
847 // struct ath_hal_9300 *ahp = AH9300(ah);
852 OS_REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO;
875 phymode |= OS_REG_READ(ah, AR_PHY_GEN_CTRL);
880 OS_REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
884 u_int32_t modeselect = OS_REG_READ(ah, AR_PHY_MODE);
891 OS_REG_WRITE(ah, AR_PHY_MODE, modeselect);
893 ar9300_set_ifs_timing(ah, chan);
895 ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 0x3);
899 ar9300_set_11n_mac2040(ah, macmode);
903 OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
906 OS_REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
913 ar9300_spur_mitigate_mrc_cck(struct ath_hal *ah, struct ieee80211_channel *chan)
924 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
930 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) ||
931 AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
932 spur_fbin_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 1);
938 if (OS_REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH)
949 } else if(AR_SREV_JUPITER(ah)) {
962 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) ||
963 AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
966 } else if(AR_SREV_JUPITER(ah)) {
982 /*OS_REG_WRITE_field(ah, BB_agc_control.ycok_max, 0x7);*/
983 OS_REG_RMW_FIELD(ah,
985 /*OS_REG_WRITE_field(ah, BB_cck_spur_mit.spur_rssi_thr, 0x7f);*/
986 OS_REG_RMW_FIELD(ah,
988 /*OS_REG_WRITE(ah, BB_cck_spur_mit.spur_filter_type, 0x2);*/
989 OS_REG_RMW_FIELD(ah,
991 /*OS_REG_WRITE(ah, BB_cck_spur_mit.use_cck_spur_mit, 0x1);*/
992 OS_REG_RMW_FIELD(ah,
994 /*OS_REG_WRITE(ah, BB_cck_spur_mit.cck_spur_freq, cck_spur_freq);*/
995 OS_REG_RMW_FIELD(ah,
1002 /*OS_REG_WRITE(ah, BB_agc_control.ycok_max, 0x5);*/
1003 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
1004 /*OS_REG_WRITE(ah, BB_cck_spur_mit.use_cck_spur_mit, 0x0);*/
1005 OS_REG_RMW_FIELD(ah,
1007 /*OS_REG_WRITE(ah, BB_cck_spur_mit.cck_spur_freq, 0x0);*/
1008 OS_REG_RMW_FIELD(ah,
1014 ar9300_spur_mitigate_ofdm(struct ath_hal *ah, struct ieee80211_channel *chan)
1027 ahp = AH9300(ah);
1028 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
1031 spur_chans_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 0);
1034 spur_chans_ptr = ar9300_eeprom_get_spur_chans_ptr(ah, 1);
1040 if (OS_REG_READ_FIELD(ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH)
1053 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
1054 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
1055 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING11, AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
1056 OS_REG_RMW_FIELD(ah,
1058 OS_REG_RMW_FIELD(ah,
1060 OS_REG_RMW_FIELD(ah,
1062 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
1063 OS_REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
1064 OS_REG_RMW_FIELD(ah,
1066 OS_REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
1067 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
1068 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
1069 OS_REG_RMW_FIELD(ah,
1071 OS_REG_RMW_FIELD(ah,
1073 OS_REG_RMW_FIELD(ah,
1075 OS_REG_RMW_FIELD(ah,
1077 OS_REG_RMW_FIELD(ah,
1079 OS_REG_RMW_FIELD(ah,
1081 OS_REG_RMW_FIELD(ah, AR_PHY_SPUR_REG, AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
1096 ah, AR_PHY_GEN_CTRL, AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
1104 if (OS_REG_READ_FIELD(ah,
1129 OS_REG_RMW_FIELD(ah,
1131 OS_REG_RMW_FIELD(ah,
1133 OS_REG_RMW_FIELD(ah,
1136 OS_REG_RMW_FIELD(ah,
1139 OS_REG_RMW_FIELD(ah,
1141 OS_REG_RMW_FIELD(ah,
1144 OS_REG_RMW_FIELD(ah,
1146 OS_REG_RMW_FIELD(ah,
1148 OS_REG_RMW_FIELD(ah,
1157 if (!AR_SREV_WASP(ah) && (OS_REG_READ_FIELD(ah, AR_PHY_MODE,
1159 OS_REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
1170 OS_REG_RMW_FIELD(ah,
1172 OS_REG_RMW_FIELD(ah,
1174 OS_REG_RMW_FIELD(ah,
1176 OS_REG_RMW_FIELD(ah,
1179 OS_REG_RMW_FIELD(ah,
1182 OS_REG_RMW_FIELD(ah,
1185 OS_REG_RMW_FIELD(ah,
1188 OS_REG_RMW_FIELD(ah,
1191 OS_REG_RMW_FIELD(ah,
1193 OS_REG_RMW_FIELD(ah,
1197 OS_REG_READ(ah, AR_PHY_TIMING4));
1199 OS_REG_READ(ah, AR_PHY_TIMING11));
1201 OS_REG_READ(ah, AR_PHY_SFCORR_EXT));
1203 OS_REG_READ(ah, AR_PHY_SPUR_REG));
1205 OS_REG_READ(ah, AR_PHY_PILOT_SPUR_MASK));
1207 OS_REG_READ(ah, AR_PHY_CHAN_SPUR_MASK));
1209 OS_REG_READ(ah, AR_PHY_SPUR_MASK_A));
1223 ar9300_spur_mitigate(struct ath_hal *ah, struct ieee80211_channel *chan)
1225 ar9300_spur_mitigate_ofdm(ah, chan);
1226 ar9300_spur_mitigate_mrc_cck(ah, chan);
1234 ar9300_channel_change(struct ath_hal *ah, struct ieee80211_channel *chan,
1239 struct ath_hal_9300 *ahp = AH9300(ah);
1243 if (ar9300_num_tx_pending(ah, qnum)) {
1244 HALDEBUG(ah, HAL_DEBUG_QUEUE,
1255 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1256 if (!ath_hal_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1259 HALDEBUG(ah, HAL_DEBUG_PHYIO,
1266 ar9300_set_11n_regs(ah, chan, macmode);
1271 if (!ahp->ah_rf_hal.set_channel(ah, chan)) {
1272 HALDEBUG(ah, HAL_DEBUG_CHANNEL, "%s: failed to set channel\n", __func__);
1279 ar9300_init_user_settings(ah);
1289 ah, &ahp->ah_eeprom, chan, ath_hal_getctl(ah, chan),
1290 ath_hal_getantennaallowed(ah, chan),
1291 ath_hal_get_twice_max_regpower(AH_PRIVATE(ah), ichan, chan),
1292 AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit)) != HAL_OK)
1294 HALDEBUG(ah, HAL_DEBUG_EEPROM,
1302 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1308 ar9300_set_delta_slope(ah, chan);
1311 OS_REG_WRITE(ah, AR_PHY_TIMING3, 0x9c0a9f6b);
1312 OS_REG_WRITE(ah, AR_PHY_SGI_DELTA, 0x00046384);
1315 ar9300_spur_mitigate(ah, chan);
1322 synth_delay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1339 ar9300_set_operating_mode(struct ath_hal *ah, int opmode)
1343 val = OS_REG_READ(ah, AR_STA_ID1);
1347 OS_REG_WRITE(ah, AR_STA_ID1,
1349 OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1352 OS_REG_WRITE(ah, AR_STA_ID1,
1354 OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1358 OS_REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1365 ar9300_init_pll(struct ath_hal *ah, struct ieee80211_channel *chan)
1368 u_int8_t clk_25mhz = AH9300(ah)->clk_25mhz;
1372 ichan = ath_hal_checkchannel(ah, chan);
1374 if (AR_SREV_HORNET(ah)) {
1394 OS_REG_WRITE(ah, AR_HORNET_CH0_DDR_DPLL2, 0x18e82f01);
1397 OS_REG_RMW_FIELD(ah, AR_HORNET_CH0_DDR_DPLL3,
1400 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
1404 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0xe04a3d);
1407 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2,
1409 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2,
1413 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL3,
1422 OS_REG_WRITE(ah, AR_HORNET_CH0_DDR_DPLL2, 0x19e82f01);
1425 OS_REG_RMW_FIELD(ah, AR_HORNET_CH0_DDR_DPLL3,
1428 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
1432 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL2, 0x886666);
1435 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2,
1437 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2,
1441 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL3,
1444 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
1446 } else if (AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
1447 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2, AR_PHY_BB_DPLL2_PLL_PWD, 0x1);
1450 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2,
1452 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2,
1455 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL1,
1457 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL1,
1459 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL1,
1462 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2,
1464 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2,
1466 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2,
1470 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL3,
1473 OS_REG_RMW_FIELD(ah, AR_PHY_BB_DPLL2,
1477 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
1479 } else if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
1495 if (AR_SREV_HONEYBEE(ah)) {
1510 if (AR_SREV_WASP(ah)) {
1525 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c); /* Bypass mode */
1528 regdata = OS_REG_READ(ah, AR_PHY_PLL_MODE);
1529 if (AR_SREV_HONEYBEE(ah)) {
1534 OS_REG_WRITE(ah, AR_PHY_PLL_MODE, regdata); /* PWD_PLL set to 1 */
1538 OS_REG_WRITE(ah, AR_PHY_PLL_CONTROL,
1541 OS_REG_WRITE(ah, AR_PHY_PLL_CONTROL,
1545 regdata = OS_REG_READ(ah, AR_PHY_PLL_MODE);
1550 if (AR_SREV_WASP(ah)) {
1553 } else if (AR_SREV_HONEYBEE(ah)) {
1565 OS_REG_WRITE(ah, AR_PHY_PLL_MODE, regdata);
1566 regdata = OS_REG_READ(ah, AR_PHY_PLL_MODE);
1567 if (AR_SREV_HONEYBEE(ah)) {
1572 OS_REG_WRITE(ah, AR_PHY_PLL_MODE, regdata); /* PWD_PLL set to 0 */
1574 if (AR_SREV_WASP(ah)) {
1576 regdata = OS_REG_READ(ah, AR_PHY_PLL_BB_DPLL3);
1578 OS_REG_WRITE(ah, AR_PHY_PLL_BB_DPLL3, regdata);
1582 regdata = OS_REG_READ(ah, AR_PHY_PLL_BB_DPLL3);
1584 OS_REG_WRITE(ah, AR_PHY_PLL_BB_DPLL3, regdata);
1588 regdata = OS_REG_READ(ah, AR_PHY_PLL_BB_DPLL4);
1592 regdata = OS_REG_READ(ah, AR_PHY_PLL_BB_DPLL3);
1594 OS_REG_WRITE(ah, AR_PHY_PLL_BB_DPLL3, regdata);
1597 regdata = (OS_REG_READ(ah, AR_PHY_PLL_BB_DPLL3) & 0x007FFFF8) >> 3;
1604 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x142c);
1622 if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
1629 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1637 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK,
1641 if (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
1643 OS_REG_WRITE(ah,
1645 OS_REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
1646 OS_REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
1648 OS_REG_WRITE(ah,
1650 OS_REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
1651 OS_REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
1658 ar9300_set_reset(struct ath_hal *ah, int type)
1662 struct ath_hal_9300 *ahp = AH9300(ah);
1670 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), AH9300(ah)->ah_wa_reg_val);
1672 OS_REG_WRITE(ah,
1677 tmp_reg = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE));
1678 if (AR_SREV_WASP(ah)) {
1680 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE), 0);
1681 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF);
1685 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE), 0);
1686 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_HOSTIF);
1690 /*OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), AR_RC_AHB);*/
1704 if (AR_SREV_HORNET(ah) &&
1706 ah, AH_PRIVATE(ah)->ah_caps.halTotalQueues - 1) != 0 ||
1715 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Hornet SoC reset WMAC.\n", __func__);
1736 OS_REG_WRITE(ah, AR_RTC_RESET, 1);
1746 if (AR_SREV_SCORPION(ah)) {
1779 OS_REG_WRITE(ah,MAC_DMA_CFG_OFFSET, (OS_REG_READ(ah,MAC_DMA_CFG_OFFSET) & ~MAC_DMA_CFG_HALT_REQ_MASK) |
1787 while (!MAC_DMA_CFG_HALT_ACK_GET(OS_REG_READ(ah, MAC_DMA_CFG_OFFSET) ))
1791 ath_hal_printf(ah, "Halt ACK timeout\n");
1797 data = DDR_REG_READ(ah,DDR_CTL_CONFIG_OFFSET);
1798 HALDEBUG(ah, HAL_DEBUG_RESET, "check DDR Activity - HIGH\n");
1803 HALDEBUG(ah, HAL_DEBUG_RESET, "DDR Activity - HIGH\n");
1806 data = DDR_REG_READ(ah,DDR_CTL_CONFIG_OFFSET);
1808 ath_hal_printf(ah, "DDR Activity timeout\n");
1821 OS_REG_WRITE(ah, AR_RTC_RESET, 0);
1823 OS_REG_WRITE(ah, AR_RTC_RESET, 1);
1825 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Scorpion SoC RTC reset done.\n", __func__);
1835 OS_REG_WRITE(ah, AR_RTC_RC, rst_flags);
1842 OS_REG_WRITE(ah, AR_RTC_RC, 0);
1843 if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1844 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1846 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1847 "%s: AR_RTC_RC = 0x%x\n", __func__, OS_REG_READ(ah, AR_RTC_RC));
1852 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_RC), 0);
1854 ar9300_attach_hw_platform(ah);
1861 ar9300_set_reset_power_on(struct ath_hal *ah)
1864 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), AH9300(ah)->ah_wa_reg_val);
1866 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1872 OS_REG_WRITE(ah, AR_RTC_RESET, 0);
1874 OS_REG_WRITE(ah, AR_RTC_RESET, 1);
1879 if (!ath_hal_wait(ah,
1883 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1892 ar9300_read_revisions(ah);
1898 return ar9300_set_reset(ah, HAL_RESET_WARM);
1905 ar9300_set_reset_reg(struct ath_hal *ah, u_int32_t type)
1912 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), AH9300(ah)->ah_wa_reg_val);
1914 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1919 ret = ar9300_set_reset_power_on(ah);
1923 ret = ar9300_set_reset(ah, type);
1930 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
1931 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1945 ar9300_phy_disable(struct ath_hal *ah)
1947 if (!ar9300_set_reset_reg(ah, HAL_RESET_WARM)) {
1956 if (AR_SREV_WASP(ah)) {
1957 if (IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan))) {
1964 else if (AR_SREV_SCORPION(ah)) {
1965 if (IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan))) {
1974 else if (AR_SREV_HONEYBEE(ah)) {
1981 if ( AR_SREV_OSPREY(ah) ) {
1982 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1), 0x0, 0x1f);
1986 ar9300_init_pll(ah, AH_NULL);
1995 ar9300_disable(struct ath_hal *ah)
1997 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
2000 if (!ar9300_set_reset_reg(ah, HAL_RESET_COLD)) {
2004 ar9300_init_pll(ah, AH_NULL);
2015 ar9300_set_rf_mode(struct ath_hal *ah, struct ieee80211_channel *chan)
2022 switch (AH9300(ah)->ah_hwp) {
2032 if ( IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
2035 OS_REG_WRITE(ah, AR_PHY_MODE, rf_mode);
2042 ar9300_chip_reset(struct ath_hal *ah, struct ieee80211_channel *chan)
2044 struct ath_hal_9300 *ahp = AH9300(ah);
2047 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0);
2057 (ah->ah_config.ah_force_full_reset == 1) ||
2058 OS_REG_READ(ah, AR_Q_TXE) ||
2059 (OS_REG_READ(ah, AR_CR) & AR_CR_RXE)) {
2063 if (!ar9300_set_reset_reg(ah, type)) {
2068 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
2074 if (AR_SREV_HORNET(ah)) {
2075 ar9300_internal_regulator_apply(ah);
2078 ar9300_init_pll(ah, chan);
2086 ar9300_set_rf_mode(ah, chan);
2095 ar9300_setup_calibration(struct ath_hal *ah, HAL_CAL_LIST *curr_cal)
2101 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING4,
2104 OS_REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
2106 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2110 OS_REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
2114 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) ||
2115 AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
2116 OS_REG_RMW_FIELD(ah,
2118 OS_REG_RMW_FIELD(ah,
2120 } else if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
2121 OS_REG_RMW_FIELD(ah,
2123 OS_REG_RMW_FIELD(ah,
2126 OS_REG_RMW_FIELD(ah,
2128 OS_REG_RMW_FIELD(ah,
2132 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2136 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
2145 ar9300_reset_calibration(struct ath_hal *ah, HAL_CAL_LIST *curr_cal)
2147 struct ath_hal_9300 *ahp = AH9300(ah);
2151 ar9300_setup_calibration(ah, curr_cal);
2172 ar9300_get_rx_chain_mask(struct ath_hal *ah)
2174 u_int32_t ret_val = OS_REG_READ(ah, AR_PHY_RX_CHAINMASK);
2186 ar9300_get_nf_hist_base(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *chan,
2206 h_base = &AH_PRIVATE(ah)->nf_cal_hist.base;
2213 ar9300_load_nf(struct ath_hal *ah, int16_t nf[])
2232 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
2234 } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah) || AR_SREV_HONEYBEE(ah)) {
2246 val = OS_REG_READ(ah, ar9300_cca_regs[i]);
2249 OS_REG_WRITE(ah, ar9300_cca_regs[i], val);
2253 HALDEBUG(ah, HAL_DEBUG_NFCAL, "%s: load %d %d %d %d %d %d\n",
2262 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
2263 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2264 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2272 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0){
2292 __func__, OS_REG_READ(ah, AR_PHY_AGC_CONTROL));
2303 val = OS_REG_READ(ah, ar9300_cca_regs[i]);
2306 OS_REG_WRITE(ah, ar9300_cca_regs[i], val);
2318 ar9300_per_calibration(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan,
2321 struct ath_hal_9300 *ahp = AH9300(ah);
2329 if (!(OS_REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
2340 curr_cal->cal_data->cal_collect(ah, num_chains);
2348 curr_cal->cal_data->cal_post_proc(ah, num_chains);
2358 ar9300_setup_calibration(ah, curr_cal);
2363 ar9300_reset_calibration(ah, curr_cal);
2368 ar9300_start_nf_cal(struct ath_hal *ah)
2370 struct ath_hal_9300 *ahp = AH9300(ah);
2371 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_ENABLE_NF);
2372 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
2373 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
2374 AH9300(ah)->nf_tsf32 = ar9300_get_tsf32(ah);
2393 ar9300_calibration(struct ath_hal *ah, struct ieee80211_channel *chan, u_int8_t rxchainmask,
2397 struct ath_hal_9300 *ahp = AH9300(ah);
2399 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2408 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
2414 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2416 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s: Chain 0 Rx IQ Cal Correction 0x%08x\n",
2417 __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
2418 if (!AR_SREV_HORNET(ah) && !AR_SREV_POSEIDON(ah) && !AR_SREV_APHRODITE(ah)) {
2419 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2421 __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B1));
2422 if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah) && !AR_SREV_HONEYBEE(ah)) {
2423 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2425 __func__, OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B2));
2429 OS_MARK(ah, AH_MARK_PERCAL, chan->ic_freq);
2443 ar9300_per_calibration(ah, ichan, rxchainmask, curr_cal, is_cal_done);
2450 ar9300_reset_calibration(ah, curr_cal);
2462 nf_done = ar9300_store_new_nf(ah, chan, is_scan);
2475 ar9300_get_nf_hist_base(ah, ichan, is_scan, nf_buf);
2476 ar9300_load_nf(ah, nf_buf);
2479 ar9300_start_nf_cal(ah);
2489 ar9300_iq_cal_collect(struct ath_hal *ah, u_int8_t num_chains)
2491 struct ath_hal_9300 *ahp = AH9300(ah);
2498 ahp->ah_total_power_meas_i[i] = OS_REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
2499 ahp->ah_total_power_meas_q[i] = OS_REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
2501 (int32_t) OS_REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
2502 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2522 ar9300_iq_calibration(struct ath_hal *ah, u_int8_t num_chains)
2524 struct ath_hal_9300 *ahp = AH9300(ah);
2536 ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan);
2543 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2545 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2557 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2559 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2561 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2572 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2574 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2599 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2601 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2603 offset_array[i], OS_REG_READ(ah, offset_array[i]));
2605 OS_REG_RMW_FIELD(ah, offset_array[i],
2607 OS_REG_RMW_FIELD(ah, offset_array[i],
2612 ahp->ah_rx_cal_corr[i] = OS_REG_READ(ah, offset_array[i]) & 0x7fff;
2623 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2627 OS_REG_READ(ah, offset_array[i]));
2628 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2632 OS_REG_READ(ah, offset_array[i]));
2633 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2638 OS_REG_SET_BIT(ah,
2640 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2645 OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
2654 ar9300_rx_iq_cal_restore(struct ath_hal *ah)
2656 struct ath_hal_9300 *ahp = AH9300(ah);
2675 OS_REG_RMW_FIELD(ah, offset_array[i],
2677 OS_REG_RMW_FIELD(ah, offset_array[i],
2685 OS_REG_SET_BIT(ah,
2688 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2694 OS_REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
2704 ar9300_set_tx_power_limit(struct ath_hal *ah, u_int32_t limit,
2707 struct ath_hal_9300 *ahp = AH9300(ah);
2708 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2710 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2722 if (ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, chan,
2723 ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan),
2737 ar9300_get_rfgain(struct ath_hal *ah)
2745 ar9300_init_chain_masks(struct ath_hal *ah, int rx_chainmask, int tx_chainmask)
2747 if (AH9300(ah)->green_ap_ps_on) {
2751 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
2753 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2754 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2765 if (AH_PRIVATE(ah)->ah_caps.halApmEnable && (tx_chainmask == 0x7)) {
2766 OS_REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
2769 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
2773 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN);
2781 ar9300_override_ini(struct ath_hal *ah, struct ieee80211_channel *chan)
2784 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2791 OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
2799 val = OS_REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
2800 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2,
2810 OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_MISSING_TX_INTR_FIX_ENABLE);
2814 ar9300_hwgreentx_set_pal_spare(ah, 1);
2818 ar9300_prog_ini(struct ath_hal *ah, struct ar9300_ini_array *ini_arr,
2847 OS_REG_WRITE(ah, reg, val);
2854 ar9300_process_ini(struct ath_hal *ah, struct ieee80211_channel *chan,
2858 struct ath_hal_9300 *ahp = AH9300(ah);
2862 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
2872 if (AR_SREV_SCORPION(ah)){
2887 if (AR_SREV_SCORPION(ah)){
2903 if (AR_SREV_SCORPION(ah)){
2905 }else if (AR_SREV_HONEYBEE(ah)){
2914 if (AR_SREV_SCORPION(ah)){
2916 }else if (AR_SREV_HONEYBEE(ah)){
2937 if (AR_SREV_SCORPION(ah)){
2948 if (AR_SREV_SCORPION(ah)){
2964 if (AR_SREV_SCORPION(ah)){
2966 } else if (AR_SREV_HONEYBEE(ah)){
2971 if (AR_SREV_SCORPION(ah)){
2973 } else if (AR_SREV_HONEYBEE(ah)){
2984 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007);
2987 HALDEBUG(ah, HAL_DEBUG_RESET,
2989 "Skipping OS-REG-WRITE(ah, AR-PHY(0), 0x00000007)\n");
2990 HALDEBUG(ah, HAL_DEBUG_RESET,
2999 ar9300_prog_ini(ah, &ahp->ah_ini_soc[i], modes_index);
3000 ar9300_prog_ini(ah, &ahp->ah_ini_mac[i], modes_index);
3001 ar9300_prog_ini(ah, &ahp->ah_ini_bb[i], modes_index);
3002 ar9300_prog_ini(ah, &ahp->ah_ini_radio[i], modes_index);
3003 if ((i == ATH_INI_POST) && (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah))) {
3004 ar9300_prog_ini(ah, &ahp->ah_ini_radio_post_sys2ant, modes_index);
3009 if (!(AR_SREV_SOC(ah))) {
3011 //ath_hal_printf(ah, "%s[%d] ==== before reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
3012 OS_REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
3014 //ath_hal_printf(ah, "%s[%d] ==== after reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
3016 OS_REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
3018 OS_REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
3022 //ath_hal_printf(ah, "%s[%d] ==== before reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
3023 OS_REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); /* clr synthon */
3024 OS_REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); /* clr synthon */
3025 OS_REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK); /* clr synthon */
3026 //ath_hal_printf(ah, "%s[%d] ==== after reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
3030 //ath_hal_printf(ah, "%s[%d] ==== before reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
3031 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); /* set synthon */
3032 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); /* set synthon */
3033 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2, AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1); /* set synthon */
3034 //ath_hal_printf(ah, "%s[%d] ==== after reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
3038 //ath_hal_printf(ah, "%s[%d] ==== before reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_SYNTH12, OS_REG_READ(ah, AR_PHY_65NM_CH0_SYNTH12));
3039 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12, AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
3040 //OS_REG_CLR_BIT(ah, AR_PHY_65NM_CH0_SYNTH12, 1<< 16); /* clr charge pump */
3041 //ath_hal_printf(ah, "%s[%d] ==== After reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_SYNTH12, OS_REG_READ(ah, AR_PHY_65NM_CH0_SYNTH12));
3043 OS_REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
3045 OS_REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
3047 OS_REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
3049 //ath_hal_printf(ah, "%s[%d] ==== after reg[0x%08x] = 0x%08x\n", __func__, __LINE__, AR_PHY_65NM_CH0_RXTX2, OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2));
3054 HALDEBUG(ah, HAL_DEBUG_RESET, "ar9300_process_ini: Rx Gain programming\n");
3056 if (AR_SREV_JUPITER_20_OR_LATER(ah)) {
3060 if (ar9300_rx_gain_index_get(ah) == 2) {
3069 if ((ar9300_rx_gain_index_get(ah) == 2) ||
3070 (ar9300_rx_gain_index_get(ah) == 3)) {
3076 if (AR_SREV_SCORPION(ah)) {
3079 HALDEBUG(ah, HAL_DEBUG_RESET, "ar9300_process_ini: Rx Gain table bounds programming\n");
3082 if (AR_SREV_WASP(ah) && ar9300_rx_gain_index_get(ah) == 2) {
3105 if (AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
3111 HALDEBUG(ah, HAL_DEBUG_RESET, "ar9300_process_ini: Tx Gain programming\n");
3115 if (IS_5GHZ_FAST_CLOCK_EN(ah, chan)) {
3116 HALDEBUG(ah, HAL_DEBUG_RESET,
3121 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah)) {
3122 HALDEBUG(ah, HAL_DEBUG_RESET,
3123 "%s: use xtal ini for AH9300(ah)->clk_25mhz: %d\n",
3124 __func__, AH9300(ah)->clk_25mhz);
3129 if (AR_SREV_WASP(ah) && (AH9300(ah)->clk_25mhz == 0)) {
3130 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Apply 40MHz ini settings\n", __func__);
3137 ar9300_prog_ini(ah, &ahp->ah_ini_japan2484, 1);
3142 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
3143 ar9300_prog_ini(ah, &ahp->ah_ini_BTCOEX_MAX_TXPWR, 1);
3148 ar9300_override_ini(ah, chan);
3151 ar9300_set_11n_regs(ah, chan, macmode);
3159 ar9300_init_chain_masks(ah, ahp->ah_rx_chainmask, ahp->ah_tx_chainmask);
3168 status = ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, chan,
3169 ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan),
3173 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT,
3187 ar9300_is_cal_supp(struct ath_hal *ah, const struct ieee80211_channel *chan,
3190 struct ath_hal_9300 *ahp = AH9300(ah);
3215 ar9285_pa_cal(struct ath_hal *ah)
3226 if (AR_SREV_KITE_11(ah)) {
3227 OS_REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14) );
3229 an_top2_reg_val = OS_REG_READ(ah, AR9285_AN_TOP2);
3232 reg_val = OS_REG_READ(ah, AR9285_AN_RXTXBB1);
3234 OS_REG_WRITE(ah, AR9285_AN_RXTXBB1, reg_val);
3237 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G7);
3239 OS_REG_WRITE(ah, AR9285_AN_RF2G7, reg_val);
3242 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G1);
3244 OS_REG_WRITE(ah, AR9285_AN_RF2G1, reg_val);
3247 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G2);
3249 OS_REG_WRITE(ah, AR9285_AN_RF2G2, reg_val);
3252 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G1);
3254 OS_REG_WRITE(ah, AR9285_AN_RF2G1, reg_val);
3257 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3);
3264 OS_REG_WRITE(ah, AR9285_AN_RF2G3, reg_val);
3266 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3);
3273 phy_tst_dac_reg_val = OS_REG_READ(ah, AR_PHY_TSTDAC_CONST);
3274 OS_REG_WRITE(ah, AR_PHY_TSTDAC_CONST, ((0x7ff << 11) | 0x7ff));
3275 reg_val = OS_REG_READ(ah, AR_PHY_TSTDAC_CONST);
3280 phy_test2_reg_val = OS_REG_READ(ah, AR_PHY_TEST2);
3281 OS_REG_WRITE(ah, AR_PHY_TEST2, ((0x1 << 7) | (0x1 << 1)));
3282 reg_val = OS_REG_READ(ah, AR_PHY_TEST2);
3287 phy_adc_ctl_reg_val = OS_REG_READ(ah, AR_PHY_ADC_CTL);
3288 OS_REG_WRITE(ah, AR_PHY_ADC_CTL, 0x80008000);
3289 reg_val = OS_REG_READ(ah, AR_PHY_ADC_CTL);
3291 OS_REG_WRITE(ah, AR9285_AN_TOP2, (0x1 << 27) | (0x1 << 17) | (0x1 << 16) |
3298 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G6);
3300 OS_REG_WRITE(ah, AR9285_AN_RF2G6, reg_val);
3301 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3);
3303 OS_REG_WRITE(ah, AR9285_AN_RF2G3, reg_val);
3308 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G6);
3311 OS_REG_WRITE(ah, AR9285_AN_RF2G6, reg_val);
3312 lo_gn = (OS_REG_READ(ah, AR9285_AN_RF2G9)) & 0x1;
3316 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G6);
3319 OS_REG_WRITE(ah, AR9285_AN_RF2G6, reg_val);
3322 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3);
3325 OS_REG_WRITE(ah, AR9285_AN_RF2G3, reg_val);
3327 lo_gn = OS_REG_READ(ah, AR9285_AN_RF2G9) & 0x1;
3330 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3);
3333 OS_REG_WRITE(ah, AR9285_AN_RF2G3, reg_val);
3336 reg_val = OS_REG_READ(ah, AR9285_AN_RXTXBB1);
3338 OS_REG_WRITE(ah, AR9285_AN_RXTXBB1, reg_val);
3341 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G1);
3343 OS_REG_WRITE(ah, AR9285_AN_RF2G1, reg_val);
3346 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G2);
3348 OS_REG_WRITE(ah, AR9285_AN_RF2G2, reg_val);
3351 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G1);
3353 OS_REG_WRITE(ah, AR9285_AN_RF2G1, reg_val);
3356 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3);
3362 OS_REG_WRITE(ah, AR9285_AN_RF2G3, reg_val);
3363 reg_val = OS_REG_READ(ah, AR9285_AN_RF2G3);
3367 OS_REG_WRITE(ah, AR_PHY_TSTDAC_CONST, phy_tst_dac_reg_val);
3368 OS_REG_WRITE(ah, AR_PHY_TEST2, phy_test2_reg_val);
3369 OS_REG_WRITE(ah, AR_PHY_ADC_CTL, phy_adc_ctl_reg_val);
3370 OS_REG_WRITE(ah, AR9285_AN_TOP2, an_top2_reg_val);
3374 if (AR_SREV_KITE_11(ah)) {
3375 OS_REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
3384 ar9300_run_init_cals(struct ath_hal *ah, int init_cal_count)
3386 struct ath_hal_9300 *ahp = AH9300(ah);
3402 ar9300_reset_calibration(ah, curr_cal);
3405 ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL, 0))
3407 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3417 ah, &ichan, ahp->ah_rx_chainmask, curr_cal, &is_cal_done);
3419 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3435 ar9300_tx_carrier_leak_war(struct ath_hal *ah)
3452 OS_REG_RMW_FIELD(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_MAP_HW_GEN, 0);
3455 tx_gain_table_max = OS_REG_READ_FIELD(ah,
3459 tx_gain = OS_REG_READ(ah, AR_PHY_TXGAIN_TAB(1) + i * 4);
3504 OS_REG_WRITE(ah, AR_PHY_CL_MAP_0_B0, reg_bb_cl_map_0_b0);
3505 OS_REG_WRITE(ah, AR_PHY_CL_MAP_1_B0, reg_bb_cl_map_1_b0);
3506 OS_REG_WRITE(ah, AR_PHY_CL_MAP_2_B0, reg_bb_cl_map_2_b0);
3507 OS_REG_WRITE(ah, AR_PHY_CL_MAP_3_B0, reg_bb_cl_map_3_b0);
3508 if (AR_SREV_WASP(ah)) {
3509 OS_REG_WRITE(ah, AR_PHY_CL_MAP_0_B1, reg_bb_cl_map_0_b0);
3510 OS_REG_WRITE(ah, AR_PHY_CL_MAP_1_B1, reg_bb_cl_map_1_b0);
3511 OS_REG_WRITE(ah, AR_PHY_CL_MAP_2_B1, reg_bb_cl_map_2_b0);
3512 OS_REG_WRITE(ah, AR_PHY_CL_MAP_3_B1, reg_bb_cl_map_3_b0);
3519 ar9300_invalidate_saved_cals(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
3522 if (AH_PRIVATE(ah)->ah_config.ath_hal_cal_reuse &
3532 ar9300_restore_rtt_cals(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
3543 ar9300_init_cal_internal(struct ath_hal *ah, struct ieee80211_channel *chan,
3547 struct ath_hal_9300 *ahp = AH9300(ah);
3555 HAL_BOOL cal_reuse_enable = AH_PRIVATE(ah)->ah_config.ath_hal_cal_reuse &
3567 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah)) {
3571 } else if (AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah) || AR_SREV_HONEYBEE(ah)) {
3589 ar9300_init_chain_masks(ah, ahp->ah_rx_cal_chainmask, ahp->ah_tx_cal_chainmask);
3597 OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
3601 OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
3612 OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1(ah),
3629 OS_REG_WRITE(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah),
3630 OS_REG_READ(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah)) |
3633 OS_REG_WRITE(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah),
3634 OS_REG_READ(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah)) &
3638 if (OS_REG_READ_FIELD(ah,
3639 AR_PHY_TX_IQCAL_CONTROL_0(ah),
3642 OS_REG_CLR_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah),
3667 if (AH_PRIVATE(ah)->ah_caps.halMciSupport &&
3671 !(ah->ah_config.ath_hal_mci_config &
3677 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send WLAN_CAL_REQ 0x%X\n",
3681 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, AH_TRUE, AH_FALSE);
3684 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
3686 if (ar9300_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_GRANT, 0, 50000))
3688 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
3693 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
3702 txiqcal_success_flag = ar9300_tx_iq_cal_hw_run(ah);
3703 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
3705 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
3708 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah)) {
3709 ar9300_tx_carrier_leak_war(ah);
3719 if(!AR_SREV_SCORPION(ah)) {
3721 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
3722 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
3725 cal_done = ath_hal_wait(ah,
3728 HALDEBUG(ah, HAL_DEBUG_FCS_RTT,
3740 ar9300_tx_iq_cal_post_proc(ah,ichan, 1, 1,is_cal_reusable, AH_FALSE);
3744 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
3745 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
3746 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
3748 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3754 ar9300_tx_iq_cal_post_proc(ah, ichan, 0, 0, is_cal_reusable, AH_TRUE);
3758 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
3759 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL);
3762 if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL,
3764 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3774 ar9300_tx_iq_cal_post_proc(ah, ichan, iqcal_idx+1, MAXIQCAL, is_cal_reusable, AH_FALSE);
3781 if (AH_PRIVATE(ah)->ah_caps.halMciSupport &&
3785 !(ah->ah_config.ath_hal_mci_config &
3790 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send WLAN_CAL_DONE 0x%X\n",
3794 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, AH_TRUE, AH_FALSE);
3799 if (!cal_done && !AR_SREV_SCORPION(ah) )
3801 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3809 if(IS_CHAN_2GHZ(chan) && AR_SREV_SCORPION(ah))
3810 OS_REG_WRITE(ah, AR_PHY_TIMING5, OS_REG_READ(ah,AR_PHY_TIMING5) & ~AR_PHY_TIMING5_CYCPWR_THR1_ENABLE);
3815 if (AR_SREV_KITE(ah) && AR_SREV_KITE_11_OR_LATER(ah)) {
3816 ar9285_pa_cal(ah);
3822 ar9300_tx_iq_cal_apply(ah, ichan);
3823 HALDEBUG(ah, HAL_DEBUG_FCS_RTT,
3831 clc_success = (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) &
3843 OS_REG_WRITE(ah, cl_tab_reg, ichan->tx_clcal[ch_idx][j]);
3847 HALDEBUG(ah, HAL_DEBUG_FCS_RTT,
3858 ichan->tx_clcal[ch_idx][j] = OS_REG_READ(ah, cl_tab_reg);
3863 HALDEBUG(ah, HAL_DEBUG_FCS_RTT,
3870 ar9300_init_chain_masks(ah, ahp->ah_rx_chainmask, ahp->ah_tx_chainmask);
3879 OS_REG_WRITE(ah, AR_PHY_AGC_CONTROL,
3880 OS_REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_NF);
3892 if (AH_TRUE == ar9300_is_cal_supp(ah, chan, ADC_DC_INIT_CAL)) {
3901 if (ar9300_run_init_cals(ah, 0) == AH_FALSE) {
3910 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3916 if (AH_TRUE == ar9300_is_cal_supp(ah, chan, IQ_MISMATCH_CAL)) {
3919 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3922 if (AH_TRUE == ar9300_is_cal_supp(ah, chan, TEMP_COMP_CAL)) {
3925 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3934 ar9300_reset_calibration(ah, ahp->ah_cal_list_curr);
3944 ar9300_init_cal(struct ath_hal *ah, struct ieee80211_channel *chan, HAL_BOOL skip_if_none, HAL_BOOL apply_last_iqcorr)
3946 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
3952 return ar9300_init_cal_internal(ah, chan, ichan, enable_rtt, do_rtt_cal, skip_if_none, apply_last_iqcorr);
3960 ar9300_reset_cal_valid(struct ath_hal *ah, const struct ieee80211_channel *chan,
3963 struct ath_hal_9300 *ahp = AH9300(ah);
3964 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
3973 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3988 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
3995 if (ar9300_is_cal_supp(ah, chan, curr_cal->cal_data->cal_type) == AH_FALSE) {
3999 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
4011 ar9300_set_dma(struct ath_hal *ah)
4014 struct ath_hal_9300 *ahp = AH9300(ah);
4015 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
4022 regval = OS_REG_READ(ah, AR_AHB_MODE);
4023 OS_REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
4029 regval = OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
4030 OS_REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
4038 OS_REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, AH_PRIVATE(ah)->ah_tx_trig_level);
4045 OS_REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, 0x3f);
4050 regval = OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
4051 OS_REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
4056 OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
4063 if (AR_SREV_WASP(ah) &&
4064 (AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_12)) {
4068 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, 0x500);
4070 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE);
4078 if (AH_PRIVATE(ah)->ah_opmode == HAL_M_HOSTAP) {
4079 OS_REG_WRITE(ah, AR_HP_Q_CONTROL,
4089 ar9300_reset_tx_status_ring(ah);
4096 OS_REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
4097 OS_REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
4103 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size);
4108 ar9300_init_bb(struct ath_hal *ah, struct ieee80211_channel *chan)
4117 synth_delay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
4125 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
4138 ar9300_init_interrupt_masks(struct ath_hal *ah, HAL_OPMODE opmode)
4140 struct ath_hal_9300 *ahp = AH9300(ah);
4175 OS_REG_WRITE(ah, AR_IMR, ahp->ah_mask_reg);
4176 OS_REG_WRITE(ah, AR_IMR_S2, OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
4177 ahp->ah_mask2Reg = OS_REG_READ(ah, AR_IMR_S2);
4179 if (ah->ah_config.ath_hal_enable_msi) {
4181 ahp->ah_msi_reg = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_MSI));
4183 if (AR_SREV_POSEIDON(ah)) {
4189 OS_REG_WRITE(ah, AR_INTCFG, msi_cfg);
4196 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE), 0xFFFFFFFF);
4199 if (AR_SREV_POSEIDON(ah)) {
4202 else if (AR_SREV_WASP(ah)) {
4205 OS_REG_WRITE(ah,
4206 AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE), sync_en_def);
4209 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK), 0);
4211 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_ENABLE), 0);
4212 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_ASYNC_MASK), 0);
4213 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_ENABLE), 0);
4214 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_PRIO_SYNC_MASK), 0);
4218 ar9300_init_qos(struct ath_hal *ah)
4220 OS_REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); /* XXX magic */
4221 OS_REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); /* XXX magic */
4224 OS_REG_WRITE(ah, AR_QOS_NO_ACK,
4232 OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
4233 OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
4234 OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
4235 OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
4236 OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
4240 ar9300_init_user_settings(struct ath_hal *ah)
4242 struct ath_hal_9300 *ahp = AH9300(ah);
4245 HALDEBUG(ah, HAL_DEBUG_RESET,
4248 OS_REG_WRITE(ah,
4249 AR_PCU_MISC, OS_REG_READ(ah, AR_PCU_MISC) | ahp->ah_misc_mode);
4252 OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM);
4255 ar9300_set_slot_time(ah, ahp->ah_slot_time);
4258 ar9300_set_ack_timeout(ah, ahp->ah_ack_timeout);
4260 if (AH_PRIVATE(ah)->ah_diagreg != 0) {
4261 OS_REG_SET_BIT(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
4264 ar9300_set_hw_beacon_rssi_threshold(ah, ahp->ah_beacon_rssi_threshold);
4268 ar9300_cac_tx_quiet(ah, 1);
4274 ar9300_get_spur_info(struct ath_hal * ah, int *enable, int len, u_int16_t *freq)
4276 // struct ath_hal_private *ap = AH_PRIVATE(ah);
4283 *enable = ah->ah_config.ath_hal_spur_mode;
4285 if (AH9300(ah)->ath_hal_spur_chans[i][0] != AR_NO_SPUR) {
4286 freq[j++] = AH9300(ah)->ath_hal_spur_chans[i][0];
4287 HALDEBUG(ah, HAL_DEBUG_ANI,
4288 "1. get spur %d\n", AH9300(ah)->ath_hal_spur_chans[i][0]);
4290 if (AH9300(ah)->ath_hal_spur_chans[i][1] != AR_NO_SPUR) {
4291 freq[j++] = AH9300(ah)->ath_hal_spur_chans[i][1];
4292 HALDEBUG(ah, HAL_DEBUG_ANI,
4293 "2. get spur %d\n", AH9300(ah)->ath_hal_spur_chans[i][1]);
4307 ar9300_set_spur_info(struct ath_hal * ah, int enable, int len, u_int16_t *freq)
4309 struct ath_hal_private *ap = AH_PRIVATE(ah);
4316 AH9300(ah)->ath_hal_spur_chans[i][0] = AR_NO_SPUR;
4317 AH9300(ah)->ath_hal_spur_chans[i][1] = AR_NO_SPUR;
4325 AH9300(ah)->ath_hal_spur_chans[j++][1] = freq[i];
4326 HALDEBUG(ah, HAL_DEBUG_ANI, "1 set spur %d\n", freq[i]);
4333 AH9300(ah)->ath_hal_spur_chans[k++][0] = freq[i];
4334 HALDEBUG(ah, HAL_DEBUG_ANI, "2 set spur %d\n", freq[i]);
4357 First_NFCal(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan,
4372 chan->ic_freq == AH_PRIVATE(ah)->ah_curchan->ic_freq)
4374 nfh = &AH_PRIVATE(ah)->nf_cal_hist;
4379 ar9300_start_nf_cal(ah);
4381 if ((OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) == 0){
4388 ar9300_upload_noise_floor(ah, is_2g, nfarray);
4401 nfh = &AH_PRIVATE(ah)->nf_cal_hist;
4409 nfh->base.priv_nf[i] = ar9300_limit_nf_range(ah,
4410 ar9300_get_nf_hist_mid(ah, nfh, i, nf_hist_len));
4414 //ar9300StoreNewNf(ah, ichan, is_scan);
4430 AH_PRIVATE(ah)->nf_cal_hist.nf_cal_buffer[0][i];
4433 if (AR_SREV_AR9580(ah)) {
4438 AH_PRIVATE(ah)->nf_cal_hist.nf_cal_buffer[0][i];
4445 AH_PRIVATE(ah)->nf_cal_hist.nf_cal_buffer[0][i];
4454 ar9300_reset_nf_hist_buff(ah, ichan);
4455 ar9300_get_nf_hist_base(ah, ichan, is_scan, nf_buf);
4456 ar9300_load_nf(ah, nf_buf);
4476 ar9300_reset(struct ath_hal *ah, HAL_OPMODE opmode, struct ieee80211_channel *chan,
4483 struct ath_hal_9300 *ahp = AH9300(ah);
4484 struct ath_hal_private *ap = AH_PRIVATE(ah);
4499 u_int8_t clk_25mhz = AH9300(ah)->clk_25mhz;
4504 if (OS_REG_READ(ah, AR_IER) == AR_IER_ENABLE) {
4506 "interrupt enabled %08x **\n", ar9300_get_interrupts(ah));
4515 if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable)) {
4516 AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_NONE;
4520 if (AH_PRIVATE(ah)->ah_caps.halMciSupport &&
4521 (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)))
4523 ar9300_mci_2g5g_changed(ah, IEEE80211_IS_CHAN_2GHZ(chan));
4539 OS_MARK(ah, AH_MARK_RESET, b_channel_change);
4544 ichan = ar9300_check_chan(ah, chan);
4546 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
4557 if (ar9300_get_power_mode(ah) != HAL_PM_FULL_SLEEP) {
4559 stopped = ar9300_set_rx_abort(ah, AH_TRUE); /* abort and disable PCU */
4560 ar9300_set_rx_filter(ah, 0);
4561 stopped &= ar9300_stop_dma_receive(ah, 0); /* stop and disable RX DMA */
4567 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
4572 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
4577 if ((AH_PRIVATE(ah)->ah_caps.halMciSupport) &&
4582 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
4590 ar9300_mci_disable_interrupt(ah);
4592 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
4595 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, AH_TRUE, AH_FALSE);
4598 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
4600 if (ar9300_mci_wait_for_gpm(ah, MCI_GPM_BT_CAL_DONE, 0, 25000)) {
4601 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
4605 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
4611 ar9300_mci_enable_interrupt(ah);
4618 if (!ar9300_set_power_mode(ah, HAL_PM_AWAKE, AH_TRUE)) {
4626 if (ah->ah_config.ath_hal_intr_mitigation_rx != 0) {
4654 ar9300_store_new_nf(ah, curchan, !is_scan);
4656 ar9300_store_new_nf(ah, curchan, is_scan);
4665 AH9300(ah)->nfp = IS_CHAN_2GHZ(ichan) ? &ahp->nf_2GHz : &ahp->nf_5GHz;
4675 if (AR_SREV_SCORPION(ah) && curchan && (chan->channel == curchan->channel) &&
4701 ar9300_reset_nf_hist_buff(ah, ichan);
4712 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
4722 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
4730 ath_hal_survey_clear(ah);
4750 (AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
4751 ((chan->channel != AH_PRIVATE(ah)->ah_curchan->channel) &&
4753 ((CHANNEL_ALL|CHANNEL_HALF|CHANNEL_QUARTER) & AH_PRIVATE(ah)->ah_curchan->channel_flags))))
4755 if (ar9300_channel_change(ah, chan, ichan, macmode)) {
4758 AH_PRIVATE(ah)->ah_curchan->ah_channel_time = 0;
4759 AH_PRIVATE(ah)->ah_curchan->ah_tsf_last = ar9300_get_tsf64(ah);
4765 ar9300_get_nf_hist_base(ah,
4766 AH_PRIVATE(ah)->ah_curchan, is_scan, nf_buf);
4767 ar9300_load_nf(ah, nf_buf);
4770 ar9300_start_nf_cal(ah);
4776 if (AH9300(ah)->ah_dma_stuck != AH_TRUE) {
4777 WAR_USB_DISABLE_PLL_LOCK_DETECT(ah);
4779 if (AH_PRIVATE(ah)->ah_caps.halMciSupport && ahp->ah_mci_ready)
4781 ar9300_mci_2g5g_switch(ah, AH_TRUE);
4791 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
4792 ar9300_mci_disable_interrupt(ah);
4794 ar9300_mci_mute_bt(ah);
4796 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, 0);
4804 AH9300(ah)->ah_dma_stuck = AH_FALSE;
4808 OS_REG_READ(ah, AR_PHY_TIMING2) &
4814 save_def_antenna = OS_REG_READ(ah, AR_DEF_ANTENNA);
4823 mac_sta_id1 = OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
4826 save_led_state = OS_REG_READ(ah, AR_CFG_LED) &
4831 ar9300_mark_phy_inactive(ah);
4833 if (!ar9300_chip_reset(ah, chan)) {
4834 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: chip reset failed\n", __func__);
4838 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
4842 OS_REG_SET_BIT(ah,
4843 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE);
4850 ecode = ar9300_process_ini(ah, chan, ichan, macmode);
4858 if(AR_SREV_WASP(ah) || AR_SREV_HONEYBEE(ah) || AR_SREV_SCORPION(ah) ) {
4860 OS_REG_WRITE(ah, AR_RTC_DERIVED_RTC_CLK, (0x17c << 1)); // 32KHz sleep clk
4862 OS_REG_WRITE(ah, AR_RTC_DERIVED_RTC_CLK, (0x261 << 1)); // 32KHz sleep clk
4869 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
4870 ahp->tx_iq_cal_enable = OS_REG_READ_FIELD(ah,
4871 AR_PHY_TX_IQCAL_CONTROL_0(ah),
4875 ahp->tx_cl_cal_enable = (OS_REG_READ(ah, AR_PHY_CL_CAL_CTL) &
4881 if ((AH_PRIVATE(ah)->ah_curchan != AH_NULL) &&
4882 (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK))
4885 ar9300_set_rifs_delay(ah, ahp->ah_rifs_enabled);
4889 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
4890 ar9300_mci_reset(ah, AH_FALSE, IS_CHAN_2GHZ(ichan), save_full_sleep);
4895 ar9300_init_mfp(ah);
4897 ahp->ah_immunity_vals[0] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR_LOW,
4899 ahp->ah_immunity_vals[1] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR_LOW,
4901 ahp->ah_immunity_vals[2] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR,
4903 ahp->ah_immunity_vals[3] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR,
4905 ahp->ah_immunity_vals[4] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR,
4907 ahp->ah_immunity_vals[5] = OS_REG_READ_FIELD(ah, AR_PHY_SFCORR_LOW,
4912 ar9300_set_delta_slope(ah, chan);
4915 ar9300_spur_mitigate(ah, chan);
4916 if (!ar9300_eeprom_set_board_values(ah, chan)) {
4917 HALDEBUG(ah, HAL_DEBUG_EEPROM,
4924 if (AR_SREV_WASP(ah)) {
4925 OS_REG_WRITE(ah, 0x16284, 0x1553e000);
4929 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
4931 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
4932 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
4935 | (ah->ah_config.ath_hal_6mb_ack ? AR_STA_ID1_ACKCTS_6MB : 0)
4938 ar9300_set_operating_mode(ah, opmode);
4941 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask));
4942 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4));
4945 OS_REG_WRITE(ah, AR_DEF_ANTENNA, save_def_antenna);
4948 tmp_reg = OS_REG_READ(ah, AR_PHY_TIMING2) &
4950 OS_REG_WRITE(ah, AR_PHY_TIMING2, tmp_reg | save_force_val);
4954 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
4955 OS_REG_WRITE(ah, AR_BSS_ID1,
4959 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */
4961 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR, INIT_RSSI_THR);
4968 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_BCN_WEIGHT,
4970 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE |
4972 if (ah->ah_config.ath_hal_beacon_filter_interval) {
4973 OS_REG_RMW_FIELD(ah, AR_HWBCNPROC2, AR_HWBCNPROC2_FILTER_INTERVAL,
4974 ah->ah_config.ath_hal_beacon_filter_interval);
4975 OS_REG_SET_BIT(ah, AR_HWBCNPROC2,
4986 if (!ahp->ah_rf_hal.set_channel(ah, chan)) {
4991 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__);
4995 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
4999 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) {
5000 ar9300_reset_tx_queue(ah, i);
5003 ar9300_init_interrupt_masks(ah, opmode);
5007 if (ath_hal_isrfkillenabled(ah)) {
5008 ar9300_enable_rf_kill(ah);
5012 ar9300_ani_init_defaults(ah, macmode);
5014 ar9300_init_qos(ah);
5016 ar9300_init_user_settings(ah);
5019 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
5021 OS_MARK(ah, AH_MARK_RESET_DONE, 0);
5026 OS_REG_WRITE(ah, AR_STA_ID1,
5027 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
5029 ar9300_set_dma(ah);
5035 if (!AH_PRIVATE(ah)->ah_caps.halMciSupport) {
5036 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 8);
5039 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 8);
5046 OS_REG_WRITE(ah, AR_GTTM, AR_GTTM_IGNORE_IDLE);
5052 OS_REG_WRITE(ah, 0x64, 0x00320000);
5053 OS_REG_WRITE(ah, 0x68, 7);
5054 OS_REG_WRITE(ah, 0x4080, 0xC);
5060 OS_REG_WRITE(ah, AR_MIRT, 0);
5074 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC);
5075 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC);
5078 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST,
5080 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST,
5098 OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, AH_TIMT_LAST_MICROSEC);
5099 OS_REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, AH_TIMT_FIRST_MICROSEC);
5104 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5105 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5107 ar9300_init_bb(ah, chan);
5127 ar9300_invalidate_saved_cals(ah, ichan);
5128 cal_ret = ar9300_init_cal(ah, chan, AH_FALSE, apply_last_iqcorr);
5131 if (AH_PRIVATE(ah)->ah_caps.halMciSupport && ahp->ah_mci_ready) {
5135 if (ar9300_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REMOTE_RESET) ||
5136 ar9300_mci_check_int(ah, AR_MCI_INTERRUPT_RX_MSG_REQ_WAKE))
5143 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
5146 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
5149 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) send REMOTE_RESET\n");
5150 ar9300_mci_remote_reset(ah, AH_TRUE);
5151 ar9300_mci_send_sys_waking(ah, AH_TRUE);
5154 ar9300_mci_send_lna_transfer(ah, AH_TRUE);
5159 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Re-calibrate.\n",
5161 ar9300_invalidate_saved_cals(ah, ichan);
5162 cal_ret = ar9300_init_cal(ah, chan, AH_FALSE, apply_last_iqcorr);
5165 ar9300_mci_enable_interrupt(ah);
5170 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: Init Cal Failed\n", __func__);
5174 ar9300_init_txbf(ah);
5181 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5182 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5187 OS_REG_WRITE(ah, AR_CFG_LED, save_led_state | AR_CFG_SCLK_32KHZ);
5191 ar9300_init_bt_coex(ah);
5194 if (AH_PRIVATE(ah)->ah_caps.halMciSupport && ahp->ah_mci_ready) {
5196 ar9300_mci_sync_bt_state(ah);
5197 ar9300_mci_2g5g_switch(ah, AH_TRUE);
5210 ar9300_start_tsf2(ah);
5213 if (ar9300_get_capability(ah, HAL_CAP_DYNAMIC_SMPS, 0, AH_NULL) == HAL_OK) {
5214 ar9300_set_sm_power_mode(ah, ahp->ah_sm_power_mode);
5221 if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
5222 OS_REG_RMW(ah, AR_CFG, AR_CFG_SWTB | AR_CFG_SWRB, 0);
5224 ar9300_init_cfg_reg(ah);
5228 if ( AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah) ) {
5229 OS_REG_RMW(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, AR_CFG_LED_ASSOC_CTL);
5237 if ( AR_SREV_WASP(ah)) {
5238 if (IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan))) {
5254 else if (AR_SREV_SCORPION(ah)) {
5255 if (IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan))) {
5258 } else if (IS_CHAN_5GHZ((AH_PRIVATE(ah)->ah_curchan))) {
5263 else if (AR_SREV_HONEYBEE(ah)) {
5279 ar9300_get_nf_hist_base(ah, ichan, is_scan, nf_buf);
5280 ar9300_load_nf(ah, nf_buf);
5285 if (First_NFCal(ah, ichan, is_scan, chan)){
5288 ar9300_rx_iq_cal_restore(ah);
5295 ar9300_start_nf_cal(ah);
5301 if (ar9300_get_capability(ah, HAL_CAP_BB_PANIC_WATCHDOG, 0, AH_NULL) ==
5304 ar9300_config_bb_panic_watchdog(ah);
5318 if ((ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL)
5319 == HAL_OK) && (((MS((AH9300(ah)->ah_bb_panic_last_status),
5321 AH9300(ah)->ah_phyrestart_disabled) )
5323 ar9300_disable_phy_restart(ah, 1);
5328 ahp->ah_radar1 = MS(OS_REG_READ(ah, AR_PHY_RADAR_1),
5330 ahp->ah_dc_offset = MS(OS_REG_READ(ah, AR_PHY_TIMING2),
5332 ahp->ah_disable_cck = MS(OS_REG_READ(ah, AR_PHY_MODE),
5335 if (AH9300(ah)->ah_enable_keysearch_always) {
5336 ar9300_enable_keysearch_always(ah, 1);
5342 if (AR_SREV_OSPREY(ah)) {
5344 OS_REG_WRITE(ah, AR_RTC_RESET, 1);
5345 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL),
5347 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_SPARE), 0xffffffff);
5353 WAR_USB_DISABLE_PLL_LOCK_DETECT(ah);
5356 ar9300_control_signals_for_green_tx_mode(ah);
5358 if (IEEE80211_IS_CHAN_2GHZ((AH_PRIVATE(ah)->ah_curchan)) && AR_SREV_SCORPION(ah)) {
5362 ar9300_set_smart_antenna(ah, ahp->ah_smartantenna_enable);
5364 if (AR_SREV_APHRODITE(ah) && ahp->ah_lna_div_use_bt_ant_enable)
5365 OS_REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
5369 ar9300_rx_iq_cal_restore(ah);
5376 OS_MARK(ah, AH_MARK_RESET_DONE, ecode);
5381 ar9300_rx_iq_cal_restore(ah);
5390 ar9300_green_ap_ps_on_off( struct ath_hal *ah, u_int16_t on_off)
5393 AH9300(ah)->green_ap_ps_on = !!on_off;
5401 ar9300_is_single_ant_power_save_possible(struct ath_hal *ah)
5411 ar9300_find_mag_approx(struct ath_hal *ah, int32_t in_re, int32_t in_im)
5434 struct ath_hal *ah,
5454 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s: Divide by 0(%d).\n",
5486 ar9300_calc_iq_corr(struct ath_hal *ah, int32_t chain_idx,
5551 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5594 mag1 = ar9300_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
5595 mag2 = ar9300_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
5598 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5611 if (AH_FALSE == ar9300_solve_iq_cal(ah,
5615 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5625 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5630 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5643 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5662 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s: tx chain %d: iq corr coeff=%x\n",
5666 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5679 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5698 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s: rx chain %d: iq corr coeff=%x\n",
5736 ar9300_tx_iq_cal_outlier_detection(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan, u_int32_t num_chains,
5752 if (AR_SREV_POSEIDON(ah)) {
5766 nmeasurement = OS_REG_READ_FIELD(ah,
5767 AR_PHY_TX_IQCAL_STATUS_B0(ah), AR_PHY_CALIBRATED_GAINS_0);
5772 if (!AR_SREV_SCORPION(ah)) {
5848 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5864 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
5885 OS_REG_RMW_FIELD(ah,
5890 OS_REG_RMW_FIELD(ah,
5904 OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
5906 OS_REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
5912 HALDEBUG(ah, HAL_DEBUG_FCS_RTT,
5920 ar9300_tx_iq_cal_apply(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
5922 struct ath_hal_9300 *ahp = AH9300(ah);
5952 if (AR_SREV_POSEIDON(ah)) {
5973 OS_REG_RMW_FIELD(ah,
5978 OS_REG_RMW_FIELD(ah,
5986 OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
5988 OS_REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
5998 ar9300_tx_iq_cal_hw_run(struct ath_hal *ah)
6002 is_tx_gain_forced = OS_REG_READ_FIELD(ah,
6006 OS_REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN, AR_PHY_TXGAIN_FORCE, 0);
6010 OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START(ah),
6013 if (!ath_hal_wait(ah,
6014 AR_PHY_TX_IQCAL_START(ah), AR_PHY_TX_IQCAL_START_DO_CAL, 0))
6016 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
6024 ar9300_tx_iq_cal_post_proc(struct ath_hal *ah,HAL_CHANNEL_INTERNAL *ichan,
6028 struct ath_hal_9300 *ahp = AH9300(ah);
6030 AR_PHY_TX_IQCAL_STATUS_B0(ah),
6043 txiqcal_status[0] = AR_PHY_TX_IQCAL_STATUS_B0(ah);
6093 OS_REG_RMW_FIELD(ah,
6098 OS_REG_RMW_FIELD(ah,
6105 OS_REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
6113 nmeasurement = OS_REG_READ_FIELD(ah,
6114 AR_PHY_TX_IQCAL_STATUS_B0(ah), AR_PHY_CALIBRATED_GAINS_0);
6120 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
6122 if (OS_REG_READ(ah, txiqcal_status[ch_idx]) &
6125 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
6135 OS_REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
6138 iq_res[idx] = OS_REG_READ(ah, chan_info_tab[ch_idx] + offset);
6139 OS_REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY,
6143 OS_REG_READ(ah, chan_info_tab[ch_idx] + offset);
6145 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
6151 ah, ch_idx, iq_res, coeff.iqc_coeff))
6153 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
6168 ath_hal_printf(ah, "IQCAL::[ch%d][gain%d]:: mag = %d phase = %d \n",
6203 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
6210 ar9300_tx_iq_cal_outlier_detection(ah,ichan, num_chains, &coeff,is_cal_reusable);
6221 /*ath_hal_printf(ah, "Tx IQ Cal failed(%d)\n", line);*/
6235 void ar9300_disable_phy_restart(struct ath_hal *ah, int disable_phy_restart)
6239 val = OS_REG_READ(ah, AR_PHY_RESTART);
6242 AH9300(ah)->ah_phyrestart_disabled = 1;
6245 AH9300(ah)->ah_phyrestart_disabled = 0;
6247 OS_REG_WRITE(ah, AR_PHY_RESTART, val);
6249 val = OS_REG_READ(ah, AR_PHY_RESTART);
6253 ar9300_interference_is_present(struct ath_hal *ah)
6256 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
6258 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
6261 ath_hal_printf(ah, "%s: called with ichan=NULL\n", __func__);
6272 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan);
6275 AH9300(ah)->nfp->nominal + AH9300(ah)->nf_cw_int_delta)
6286 ar9300_crdc_rx_notify(struct ath_hal *ah, struct ath_rx_status *rxs)
6288 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
6291 if ((!AR_SREV_WASP(ah)) ||
6305 rssi_index = ah->ah_crdc_rssi_ptr % HAL_MAX_CRDC_RSSI_SAMPLE;
6307 ah->ah_crdc_rssi_sample[0][rssi_index] = rxs->rs_rssi_ctl0;
6308 ah->ah_crdc_rssi_sample[1][rssi_index] = rxs->rs_rssi_ctl1;
6310 ah->ah_crdc_rssi_ptr++;
6314 ar9300_crdc_avg_rssi(struct ath_hal *ah, int chain)
6317 int crdc_rssi_ptr = ah->ah_crdc_rssi_ptr, i;
6318 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
6327 ah->ah_crdc_rssi_sample[chain]
6335 ar9300_crdc_activate(struct ath_hal *ah, int rssi_diff, int enable)
6338 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
6343 val = orig_val = OS_REG_READ(ah, AR_PHY_MULTICHAIN_CTRL);
6349 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_CTRL, val);
6350 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "diff: %02d comp: %02d reg: %08x %08x\n",
6355 void ar9300_chain_rssi_diff_compensation(struct ath_hal *ah)
6357 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
6359 int crdc_rssi_ptr = ah->ah_crdc_rssi_ptr;
6364 if ((!AR_SREV_WASP(ah)) ||
6366 if (ah->ah_crdc_rssi_ptr) {
6367 ar9300_crdc_activate(ah, 0, 0);
6368 ah->ah_crdc_rssi_ptr = 0;
6381 avg_rssi[0] = ar9300_crdc_avg_rssi(ah, 0);
6382 avg_rssi[1] = ar9300_crdc_avg_rssi(ah, 1);
6385 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "crdc: avg: %02d %02d ",
6390 ar9300_crdc_activate(ah, 0, 0);
6393 ar9300_crdc_activate(ah, avg_rssi_diff, 1);
6395 ar9300_crdc_activate(ah, 0, 1);
6403 ar9300_ant_ctrl_set_lna_div_use_bt_ant(struct ath_hal *ah, HAL_BOOL enable, const struct ieee80211_channel *chan)
6407 struct ath_hal_9300 *ahp = AH9300(ah);
6409 struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
6412 HALDEBUG(ah, HAL_DEBUG_RESET | HAL_DEBUG_BT_COEX,
6415 if (AR_SREV_POSEIDON(ah)) {
6419 ichan = ar9300_check_chan(ah, chan);
6421 HALDEBUG(ah, HAL_DEBUG_CHANNEL, "%s: invalid channel %u/0x%x; no mapping\n",
6434 value = ar9300_ant_ctrl_common2_get(ah, IS_CHAN_2GHZ(ichan));
6437 value |= ah->ah_config.ath_hal_ant_ctrl_comm2g_switch_enable;
6439 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: com2=0x%08x\n", __func__, value);
6440 OS_REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
6444 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
6454 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
6457 regval = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
6464 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
6466 if ( AR_SREV_POSEIDON_11_OR_LATER(ah) ) {
6469 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
6479 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
6484 } else if (AR_SREV_APHRODITE(ah)) {
6487 OS_REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, ANT_DIV_ENABLE);
6488 OS_REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, (1 << MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SHIFT));
6489 OS_REG_SET_BIT(ah, AR_PHY_CCK_DETECT, AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
6490 OS_REG_SET_BIT(ah, AR_PHY_RESTART, RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MASK);
6491 OS_REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
6493 OS_REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, ANT_DIV_ENABLE);
6494 OS_REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, (1 << MULTICHAIN_GAIN_CTRL__ENABLE_ANT_SW_RX_PROT__SHIFT));
6495 OS_REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
6496 OS_REG_CLR_BIT(ah, AR_PHY_RESTART, RESTART__ENABLE_ANT_FAST_DIV_M2FLAG__MASK);
6497 OS_REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
6499 regval = OS_REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
6509 OS_REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);