ath_hal/ar9300/ar9300_recv.c

19 #include "ah.h"
44 ar9300_set_rx_dp(struct ath_hal *ah, u_int32_t rxdp, HAL_RX_QUEUE qtype)
49         OS_REG_WRITE(ah, AR_HP_RXDP, rxdp);
51         OS_REG_WRITE(ah, AR_LP_RXDP, rxdp);
59 ar9300_enable_receive(struct ath_hal *ah)
61     OS_REG_WRITE(ah, AR_CR, 0);
68 ar9300_set_rx_abort(struct ath_hal *ah, HAL_BOOL set)
72         OS_REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
74         if ( AH9300(ah)->ah_reset_reason == HAL_RESET_BBPANIC ){
77             OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
82                 ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0);
86                 OS_REG_CLR_BIT(ah, AR_DIAG_SW,
89                 HALDEBUG(ah, HAL_DEBUG_RX,
91                     __func__, OS_REG_READ(ah, AR_OBS_BUS_1));
97         OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
107 ar9300_stop_dma_receive(struct ath_hal *ah, u_int timeout)
116     OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);
122     org_value = OS_REG_READ(ah, AR_MACMISC);
124     OS_REG_WRITE(ah, AR_MACMISC,
129             ah, AR_DMADBG_7, AR_DMADBG_RX_STATE, 0);
132             HALDEBUG(ah, HAL_DEBUG_RX,
134                 OS_REG_READ(ah, AR_DMADBG_7));
138     OS_REG_WRITE(ah, AR_CR, AR_CR_RXD);
142         if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) {
149         HALDEBUG(ah, HAL_DEBUG_RX, "%s: dma failed to stop in %d ms\n"
153                 OS_REG_READ(ah, AR_CR),
154                 OS_REG_READ(ah, AR_DIAG_SW));
160     OS_REG_WRITE(ah, AR_MACMISC, org_value);
162     OS_MARK(ah, AH_MARK_RX_CTL,
174 ar9300_start_pcu_receive(struct ath_hal *ah, HAL_BOOL is_scanning)
176     ar9300_enable_mib_counters(ah);
177     ar9300_ani_reset(ah, is_scanning);
179     OS_REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
186 ar9300_stop_pcu_receive(struct ath_hal *ah)
188     OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
189     ar9300_disable_mib_counters(ah);
198     struct ath_hal *ah,
202     OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
203     OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
210 ar9300_get_rx_filter(struct ath_hal *ah)
212     u_int32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
213     u_int32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
227 ar9300_set_rx_filter(struct ath_hal *ah, u_int32_t bits)
231     if (AR_SREV_SCORPION(ah) || AR_SREV_HONEYBEE(ah)) {
235     if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
239     OS_REG_WRITE(ah, AR_RX_FILTER,
248     OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
250         OS_REG_WRITE(ah, AR_RXCFG,
251             OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
253         OS_REG_WRITE(ah, AR_RXCFG,
254             OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
262 ar9300_set_rx_sel_evm(struct ath_hal *ah, HAL_BOOL sel_evm, HAL_BOOL just_query)
264     struct ath_hal_9300 *ahp = AH9300(ah);
271         OS_REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM);
273         OS_REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_SEL_EVM);
281 void ar9300_promisc_mode(struct ath_hal *ah, HAL_BOOL enable)
284     reg_val =  OS_REG_READ(ah, AR_RX_FILTER);
290     OS_REG_WRITE(ah, AR_RX_FILTER, reg_val);
295     struct ath_hal *ah,
301     *rxfilter_val = OS_REG_READ(ah, AR_RX_FILTER);
302     *rxcfg_val    = OS_REG_READ(ah, AR_RXCFG);
303     *phy_err_mask_val = OS_REG_READ(ah, AR_PHY_ERR);
304     *mac_pcu_phy_err_regval = OS_REG_READ(ah, 0x8338);
305     HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
314     struct ath_hal *ah,
321     if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
326         OS_REG_WRITE(ah, AR_RX_FILTER, 0xffff | AR_RX_COMPR_BAR | rxfilter_val);
327         OS_REG_WRITE(ah, AR_PHY_ERR, 0xFFFFFFFF);
328         OS_REG_WRITE(ah, AR_RXCFG, rxcfg_val | AR_RXCFG_ZLFDMA);
329         OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, mac_pcu_phy_err_reg_val | 0xFF);
331         OS_REG_WRITE(ah, AR_RX_FILTER, rxfilter_val);
332         OS_REG_WRITE(ah, AR_PHY_ERR, phy_err_mask_val);
333         OS_REG_WRITE(ah, AR_RXCFG, rxcfg_val);
334         OS_REG_WRITE(ah, AR_PHY_ERR_MASK_REG, mac_pcu_phy_err_reg_val);
336     HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,