ath_hal/ar9300/ar9300_radar.c

20 #include "ah.h"
135 getchannel(struct ath_hal *ah, const struct ieee80211_channel *c)
145     cc = AH_PRIVATE(ah)->ah_curchan;
152     base = AH_TABLES(ah)->ah_channels;
153     n = AH_PRIVATE(ah)->ah_nchan;
165         HALDEBUG(ah, HAL_DEBUG_DFS, "%s: channel %u/0x%x d %d\n", __func__,
172     HALDEBUG(ah, HAL_DEBUG_DFS, "%s: no match for %u/0x%x\n",
184 ar9300_check_dfs(struct ath_hal *ah, struct ieee80211_channel *chan)
188     ichan = getchannel(ah, chan);
207 ar9300_dfs_found(struct ath_hal *ah, struct ieee80211_channel *chan, u_int64_t nol_time)
211     ichan = getchannel(ah, chan);
216         ichan->dfs_tsf = ar9300_get_tsf64(ah);
229 ar9300_enable_dfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
232     struct ath_hal_private  *ahp = AH_PRIVATE(ah);
234     struct ath_hal_9300 *ah9300 = AH9300(ah);
237     val = OS_REG_READ(ah, AR_PHY_RADAR_0);
253         if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
255             if (ah->ah_use_cac_prssi) {
269     OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
271     val = OS_REG_READ(ah, AR_PHY_RADAR_1);
285     OS_REG_WRITE(ah, AR_PHY_RADAR_1, val);
287     if (ath_hal_getcapability(ah, HAL_CAP_EXT_CHAN_DFS, 0, 0) == HAL_OK) {
288         val = OS_REG_READ(ah, AR_PHY_RADAR_EXT);
291             OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val | AR_PHY_RADAR_EXT_ENA);
294             OS_REG_WRITE(ah, AR_PHY_RADAR_EXT, val & ~AR_PHY_RADAR_EXT_ENA);
302     if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_OSPREY_22(ah) || AR_SREV_SCORPION(ah)) {
306     ath_hal_printf(ah, "DFS change the timing value\n");
307     if (AR_SREV_AR9580(ah) && IEEE80211_IS_CHAN_HT40(chan)) {
308         OS_REG_WRITE(ah, AR_PHY_TIMING6, 0x3140c00a);
319 ar9300_get_dfs_thresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
323     val = OS_REG_READ(ah, AR_PHY_RADAR_0);
332     val = OS_REG_READ(ah, AR_PHY_RADAR_1);
345 ar9300_radar_wait(struct ath_hal *ah, struct ieee80211_channel *chan)
347     struct ath_hal_private *ahp = AH_PRIVATE(ah);
370     struct ath_hal *ah,
385         HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_FCC_DOMAIN_9300\n", __func__);
392         HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_ETSI_DOMAIN_9300\n", __func__);
399         HALDEBUG(ah, HAL_DEBUG_DFS, "%s: DFS_MKK4_DOMAIN_9300\n", __func__);
402         HALDEBUG(ah, HAL_DEBUG_DFS, "%s: no domain\n", __func__);
419 //    ah->ah_use_cac_prssi = 0;
428 void ar9300_adjust_difs(struct ath_hal *ah, u_int32_t val)
437         struct ath_hal_9300 *ahp = AH9300(ah);
441         AH9300(ah)->ah_fccaifs = 0;
442         HALDEBUG(ah, HAL_DEBUG_DFS, "%s: restore DIFS \n", __func__);
445             OS_REG_WRITE(ah, AR_DLCL_IFS(q),
456         AH9300(ah)->ah_fccaifs = 1;
457         HALDEBUG(ah, HAL_DEBUG_DFS, "%s: set DIFS to default\n", __func__);
460         OS_REG_WRITE(ah, AR_DLCL_IFS(0), 0x05fffc0f);
461         OS_REG_WRITE(ah, AR_DLCL_IFS(1), 0x05f0fc0f);
462         OS_REG_WRITE(ah, AR_DLCL_IFS(2), 0x05f03c07);
463         OS_REG_WRITE(ah, AR_DLCL_IFS(3), 0x05f01c03);
467 u_int32_t ar9300_dfs_config_fft(struct ath_hal *ah, HAL_BOOL is_enable)
471     val = OS_REG_READ(ah, AR_PHY_RADAR_0);
479     OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
480     val = OS_REG_READ(ah, AR_PHY_RADAR_0);
488 ar9300_dfs_cac_war(struct ath_hal *ah, u_int32_t start)
492     if (AR_SREV_AR9580(ah) || AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)) {
493         val = OS_REG_READ(ah, AR_PHY_RADAR_0);
501         OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
502 //        ah->ah_use_cac_prssi = start;
508 ar9300_get_extension_channel(struct ath_hal *ah)
510     struct ath_hal_private  *ahp = AH_PRIVATE(ah);
511     struct ath_hal_private_tables  *aht = AH_TABLES(ah);
518     ar9300_get_channel_centers(ah, ichan, &centers);
533 ar9300_is_fast_clock_enabled(struct ath_hal *ah)
535     struct ath_hal_private *ahp = AH_PRIVATE(ah);
537     if (IS_5GHZ_FAST_CLOCK_EN(ah, ahp->ah_curchan)) {
549 ar9300_handle_radar_bb_panic(struct ath_hal *ah)
554     struct ath_hal_9300 *ahp = AH9300(ah);
557     status = AH_PRIVATE(ah)->ah_bb_panic_last_status;
562         val = OS_REG_READ(ah, AR_PHY_RADAR_0);
565         OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
568         val = OS_REG_READ(ah, AR_PHY_RADAR_0);
571         OS_REG_WRITE(ah, AR_PHY_RADAR_0, val);
575         HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x0400000a\n", __func__);
579         HALDEBUG(ah, HAL_DEBUG_DFS, "%s: BB Panic -- 0x1300000a\n", __func__);
581     } else if ((AR_SREV_WASP(ah) || AR_SREV_HONEYBEE(ah)) && (status == 0x04000409)) {
584         if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK &&
593             HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: BB status=0x%08x rifs=%d - disable\n",
595             ar9300_set_rifs_delay(ah, AH_FALSE);