Lines Matching refs:ah
19 #include "ah.h"
26 void ar9300_wowoffload_prep(struct ath_hal *ah)
28 struct ath_hal_9300 *ahp = AH9300(ah);
34 void ar9300_wowoffload_post(struct ath_hal *ah)
36 struct ath_hal_9300 *ahp = AH9300(ah);
40 val = OS_REG_READ(ah, AR_MCAST_FIL0);
42 OS_REG_WRITE(ah, AR_MCAST_FIL0, val);
45 val = OS_REG_READ(ah, AR_MCAST_FIL1);
47 OS_REG_WRITE(ah, AR_MCAST_FIL1, val);
54 static void ar9300_wowoffload_add_mcast_filter(struct ath_hal *ah, u_int8_t *mc_addr)
56 struct ath_hal_9300 *ahp = AH9300(ah);
68 val = OS_REG_READ(ah, reg);
76 OS_REG_WRITE(ah, reg, val);
89 void ar9300_wowoffload_download_devid_swar(struct ath_hal *ah)
93 OS_REG_WRITE(ah, addr, 8);
95 OS_REG_WRITE(ah, addr, 0x5000);
97 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) pcie_000 = %08x\n",
98 AH_PRIVATE(ah)->ah_config.ath_hal_pcie_000);
99 OS_REG_WRITE(ah, addr, AH_PRIVATE(ah)->ah_config.ath_hal_pcie_000);
101 OS_REG_WRITE(ah, addr, 0x5008);
103 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) pcie_008 = %08x\n",
104 AH_PRIVATE(ah)->ah_config.ath_hal_pcie_008);
105 OS_REG_WRITE(ah, addr, AH_PRIVATE(ah)->ah_config.ath_hal_pcie_008);
107 OS_REG_WRITE(ah, addr, 0x502c);
109 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) pcie_02c = %08x\n",
110 AH_PRIVATE(ah)->ah_config.ath_hal_pcie_02c);
111 OS_REG_WRITE(ah, addr, AH_PRIVATE(ah)->ah_config.ath_hal_pcie_02c);
113 OS_REG_WRITE(ah, addr, 0x18c00);
115 OS_REG_WRITE(ah, addr, 0x18212ede);
117 OS_REG_WRITE(ah, addr, 0x18c04);
119 OS_REG_WRITE(ah, addr, 0x008001d8);
121 OS_REG_WRITE(ah, addr, 0x18c08);
123 OS_REG_WRITE(ah, addr, 0x0003580c);
125 OS_REG_WRITE(ah, addr, 0x570c);
127 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) pcie_70c = %08x\n",
128 AH_PRIVATE(ah)->ah_config.ath_hal_pcie_70c);
129 OS_REG_WRITE(ah, addr, AH_PRIVATE(ah)->ah_config.ath_hal_pcie_70c);
131 OS_REG_WRITE(ah, addr, 0x5040);
133 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) pcie_040 = %08x\n",
134 AH_PRIVATE(ah)->ah_config.ath_hal_pcie_040);
135 OS_REG_WRITE(ah, addr, AH_PRIVATE(ah)->ah_config.ath_hal_pcie_040);
152 void ar9300_wowoffload_retrieve_data(struct ath_hal *ah, void *buf, u_int32_t param)
157 rc_lower = OS_REG_READ(ah, AR_WOW_TXBUF(0));
158 rc_upper = OS_REG_READ(ah, AR_WOW_TXBUF(1));
162 rc_lower = OS_REG_READ(ah, AR_WOW_TXBUF(2));
163 rc_upper = OS_REG_READ(ah, AR_WOW_TXBUF(3));
167 *(u_int32_t *)buf = OS_REG_READ(ah, AR_WOW_TXBUF(4));
173 u_int32_t ar9300_wowoffload_download_rekey_data(struct ath_hal *ah, u_int32_t *data, u_int32_t bytes)
176 int mbox_status = OS_REG_READ(ah, AR_MBOX_CTRL_STATUS);
179 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) %s, bytes=%d\n", __func__, bytes);
180 if (AR_SREV_JUPITER(ah) &&
184 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) bytes truncated to %d\n", bytes);
188 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: Mailbox register busy! Reg = 0x%x", __func__, mbox_status);
193 OS_REG_WRITE(ah, AR_EMB_CPU_WOW_STATUS, 0x0);
194 OS_REG_WRITE(ah, AR_WLAN_WOW_ENABLE, 0);
195 OS_REG_WRITE(ah, AR_WLAN_WOW_STATUS, 0xFFFFFFFF);
197 if (AR_SREV_JUPITER(ah)) {
203 OS_REG_WRITE(ah, gtk_data_start + i * 4, data[i]);
209 void ar9300_wowoffload_download_acer_magic( struct ath_hal *ah,
223 OS_REG_WRITE(ah, AR_WOW_OFFLOAD_ACER_MAGIC_START, l);
224 OS_REG_WRITE(ah, AR_WOW_OFFLOAD_ACER_MAGIC_START + 4, u);
226 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
231 void ar9300_wowoffload_download_acer_swka( struct ath_hal *ah,
258 OS_REG_WRITE(ah, ka_period[id], period);
259 OS_REG_WRITE(ah, ka_size[id], size);
261 OS_REG_WRITE(ah, ka_period[id], 0);
262 OS_REG_WRITE(ah, ka_size[id], 0);
264 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: id=%d, period=%d ms, size=%d bytes\n",
271 OS_REG_WRITE(ah, ka_data[id] + i, *datap);
272 /*HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) %08x\n", *datap);*/
277 void ar9300_wowoffload_download_arp_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data)
291 OS_REG_WRITE(ah, addr, 0x1);
293 OS_REG_WRITE(ah, addr, p_info->RemoteIPv4Address.u32);
295 OS_REG_WRITE(ah, addr, p_info->HostIPv4Address.u32);
297 OS_REG_WRITE(ah, addr, p_info->MacAddress.u32[0]);
299 OS_REG_WRITE(ah, addr, p_info->MacAddress.u32[1]);
301 OS_REG_WRITE(ah, addr, 0x0);
317 void ar9300_wowoffload_download_ns_info(struct ath_hal *ah, u_int32_t id, u_int32_t *data)
332 OS_REG_WRITE(ah, addr, 0x1);
334 WOW_WRITE_NS_IPV6_ADDRESS(ah, addr, &p_info->RemoteIPv6Address.u32[0]);
336 WOW_WRITE_NS_IPV6_ADDRESS(ah, addr, &p_info->SolicitedNodeIPv6Address.u32[0]);
338 OS_REG_WRITE(ah, addr, p_info->MacAddress.u32[0]);
340 OS_REG_WRITE(ah, addr, p_info->MacAddress.u32[1]);
342 WOW_WRITE_NS_IPV6_ADDRESS(ah, addr, &p_info->TargetIPv6Addresses[0].u32[0]);
344 WOW_WRITE_NS_IPV6_ADDRESS(ah, addr, &p_info->TargetIPv6Addresses[1].u32[0]);
352 ar9300_wowoffload_add_mcast_filter(ah, mc_addr);
354 OS_REG_WRITE(ah, addr, 0x0);
360 u_int32_t ar9300_wow_offload_download_hal_params(struct ath_hal *ah)
367 if (AH_PRIVATE(ah)->ah_curchan->channel_flags & CHANNEL_CCK) {
377 if (AR_SREV_JUPITER(ah)) {
386 OS_REG_WRITE(ah, AR_WOW_OFFLOAD_GTK_TXDESC_PARAM(0), tx_rate_series);
387 OS_REG_WRITE(ah, AR_WOW_OFFLOAD_GTK_TXDESC_PARAM(1), tx_tries_series);
388 OS_REG_WRITE(ah, AR_WOW_OFFLOAD_GTK_TXDESC_PARAM(2), AH9300(ah)->ah_tx_chainmask);
389 OS_REG_WRITE(ah, AR_WOW_OFFLOAD_GTK_TXDESC_PARAM(3), tpc);
397 u_int32_t ar9300_wow_offload_handshake(struct ath_hal *ah, u_int32_t pattern_enable)
400 int mbox_status = OS_REG_READ(ah, AR_MBOX_CTRL_STATUS);
402 u_int32_t bt_handshake_timeout_us = HAL_WOW_CTRL_WAIT_BT_TO(ah) * 100000;
408 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) TIMEOUT: %d us\n", bt_handshake_timeout_us);
418 OS_REG_WRITE(ah, AR_MBOX_CTRL_STATUS, 0);
419 OS_REG_WRITE(ah, AR_EMB_CPU_WOW_STATUS, 0x0);
420 OS_REG_WRITE(ah, AR_WLAN_WOW_ENABLE, 0);
421 OS_REG_WRITE(ah, AR_WLAN_WOW_STATUS, 0xFFFFFFFF);
423 OS_REG_WRITE(ah, AR_RIMT, 0);
424 OS_REG_WRITE(ah, AR_TIMT, 0);
428 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - User pattern\n");
432 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - User pattern\n");
441 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Magic pattern\n");
444 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Magic pattern\n");
448 || HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_KAFAIL_ENABLE)
453 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Kepp alive fail\n");
456 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Kepp alive fail\n");
460 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Becon Miss\n");
463 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Becon Miss\n");
466 OS_REG_WRITE(ah, AR_EMB_CPU_WOW_ENABLE, val);
468 OS_REG_CLR_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF);
469 OS_REG_SET_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_REQ);
470 OS_REG_SET_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_INT_EMB_CPU);
472 if (!ath_hal_waitfor(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF, AR_MBOX_WOW_CONF, bt_handshake_timeout_us)) {
473 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: WoW offload handshake failed", __func__);
477 OS_REG_CLR_BIT(ah, AR_MBOX_CTRL_STATUS, AR_MBOX_WOW_CONF);
478 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: WoW offload handshake successful",__func__);
494 ar9300_set_power_mode_awake(struct ath_hal *ah, int set_chip)
496 struct ath_hal_9300 *ahp = AH9300(ah);
502 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), ahp->ah_wa_reg_val);
507 if ((OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_SHUTDOWN)) {
508 if (ar9300_set_reset_reg(ah, HAL_RESET_POWER_ON) != AH_TRUE) {
514 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
519 val = OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
524 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
527 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s: Failed to wakeup in %uus\n",
534 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
544 ar9300_set_power_mode_sleep(struct ath_hal *ah, int set_chip)
546 struct ath_hal_9300 *ahp = AH9300(ah);
548 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
550 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
551 OS_REG_WRITE(ah, AR_TIMER_MODE,
552 OS_REG_READ(ah, AR_TIMER_MODE) & 0xFFFFFF00);
553 OS_REG_WRITE(ah, AR_GEN_TIMERS2_MODE,
554 OS_REG_READ(ah, AR_GEN_TIMERS2_MODE) & 0xFFFFFF00);
555 OS_REG_WRITE(ah, AR_SLP32_INC,
556 OS_REG_READ(ah, AR_SLP32_INC) & 0xFFF00000);
557 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
561 OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
563 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
572 if (!AR_SREV_JUPITER_10(ah)) {
574 OS_REG_CLR_BIT(ah, AR_RTC_RESET, AR_RTC_RESET_EN);
581 if (!AR_SREV_JUPITER(ah) || !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14))
585 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA),
596 ar9300_set_power_mode_network_sleep(struct ath_hal *ah, int set_chip)
598 struct ath_hal_9300 *ahp = AH9300(ah);
600 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
602 HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
606 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
618 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
619 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
620 OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_EN) &
625 OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
627 if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
639 if (!AR_SREV_JUPITER(ah) || !HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SET_4004_BIT14))
643 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA),
653 ar9300_set_power_mode(struct ath_hal *ah, HAL_POWER_MODE mode, int set_chip)
655 struct ath_hal_9300 *ahp = AH9300(ah);
666 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
667 modes[ar9300_get_power_mode(ah)], modes[mode],
669 OS_MARK(ah, AH_MARK_CHIP_POWER, mode);
674 ah->ah_powerMode = mode;
675 status = ar9300_set_power_mode_awake(ah, set_chip);
677 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
678 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
685 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
686 if (ar9300_get_power_mode(ah) == HAL_PM_AWAKE) {
687 if ((ar9300_mci_state(ah, HAL_MCI_STATE_ENABLE, NULL) != 0) &&
691 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
693 ar9300_mci_send_coex_halt_bt_gpm(ah, AH_TRUE, AH_TRUE);
700 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
701 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
704 ar9300_set_power_mode_sleep(ah, set_chip);
707 ah->ah_powerMode = mode;
712 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
713 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
716 ar9300_set_power_mode_network_sleep(ah, set_chip);
718 ah->ah_powerMode = mode;
722 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT,
724 OS_MARK(ah, AH_MARK_CHIP_POWER_DONE, -1);
727 OS_MARK(ah, AH_MARK_CHIP_POWER_DONE, status);
735 ar9300_get_power_mode(struct ath_hal *ah)
737 int mode = OS_REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
751 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT,
761 ar9300_set_sm_power_mode(struct ath_hal *ah, HAL_SMPS_MODE mode)
764 struct ath_hal_9300 *ahp = AH9300(ah);
766 if (ar9300_get_capability(ah, HAL_CAP_DYNAMIC_SMPS, 0, AH_NULL) != HAL_OK) {
778 OS_REG_WRITE(ah, AR_PCU_SMPS, regval);
781 OS_REG_WRITE(ah, AR_PCU_SMPS, regval | AR_PCU_SMPS_SW_CTRL_HPWR);
784 OS_REG_WRITE(ah, AR_PCU_SMPS, regval | AR_PCU_SMPS_HW_CTRL_EN);
787 OS_REG_WRITE(ah, AR_PCU_SMPS, 0);
802 ar9280_config_ser_des__wow_sleep(struct ath_hal *ah)
805 struct ath_hal_9300 *ahp = AH9300(ah);
813 OS_REG_WRITE(ah,
821 ar9300_wow_create_keep_alive_pattern(struct ath_hal *ah)
823 struct ath_hal_9300 *ahp = AH9300(ah);
844 if (AH_PRIVATE(ah)->ah_curchan->channel_flags & CHANNEL_CCK) {
859 OS_REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]);
877 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
880 OS_REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + 12 * 4), 0);
888 OS_REG_WRITE(ah, (wow_ka_dataword0 + i * 4), data_word[i]);
901 struct ath_hal *ah,
939 pattern = (u_int8_t)OS_REG_READ(ah, AR_WOW_PATTERN_REG);
941 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, pattern);
949 OS_REG_WRITE(ah, (reg_pat[pattern_count] + i), pattern_val);
958 OS_REG_WRITE(ah, (reg_mask[pattern_count] + i), mask_val);
965 val = OS_REG_READ(ah, AR_WOW_LENGTH1_REG);
969 OS_REG_WRITE(ah, AR_WOW_LENGTH1_REG, val);
972 val = OS_REG_READ(ah, AR_WOW_LENGTH2_REG);
976 OS_REG_WRITE(ah, AR_WOW_LENGTH2_REG, val);
979 AH_PRIVATE(ah)->ah_wow_event_mask |=
986 ar9300_set_power_mode_wow_sleep(struct ath_hal *ah)
988 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
990 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
991 if (!ath_hal_waitfor(ah, AR_CR, AR_CR_RXE, 0, AH_WAIT_TIMEOUT)) {
992 HALDEBUG(ah, HAL_DEBUG_POWER_MGMT, "%s: dma failed to stop in 10ms\n"
994 OS_REG_READ(ah, AR_CR), OS_REG_READ(ah, AR_DIAG_SW));
998 OS_REG_WRITE(ah, AR_RXDP, 0x0);
1005 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
1006 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1009 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT);
1018 struct ath_hal *ah,
1046 wow_event_mask = AH_PRIVATE(ah)->ah_wow_event_mask;
1056 if (AH_PRIVATE(ah)->ah_is_pci_express == AH_TRUE) {
1066 wa_reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_WA));
1088 if (AR_SREV_JUPITER(ah)) {
1093 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), wa_reg_val);
1099 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL));
1110 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val);
1112 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val);
1125 init_val = OS_REG_READ(ah, AR_WOW_PATTERN_REG);
1127 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, val);
1128 rval = OS_REG_READ(ah, AR_WOW_PATTERN_REG);
1134 OS_REG_WRITE(ah, AR_WOW_COUNT_REG, val);
1135 rval = OS_REG_READ(ah, AR_WOW_COUNT_REG);
1143 OS_REG_WRITE(ah, AR_WOW_BCN_TIMO_REG, val);
1144 rval = OS_REG_READ(ah, AR_WOW_BCN_TIMO_REG);
1152 val = AH_PRIVATE(ah)->ah_config.ath_hal_keep_alive_timeout * 32;
1154 OS_REG_WRITE(ah, AR_WOW_KEEP_ALIVE_TIMO_REG, val);
1155 rval = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_TIMO_REG);
1161 OS_REG_WRITE(ah, AR_WOW_KEEP_ALIVE_DELAY_REG, val);
1162 rval = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_DELAY_REG);
1167 ar9300_wow_create_keep_alive_pattern(ah);
1173 val = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_REG);
1194 OS_REG_WRITE(ah, AR_WOW_KEEP_ALIVE_REG, val);
1195 val = OS_REG_READ(ah, AR_WOW_KEEP_ALIVE_REG);
1203 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR,
1206 val = OS_REG_READ(ah, AR_WOW_BCN_EN_REG);
1213 OS_REG_WRITE(ah, AR_WOW_BCN_EN_REG, val);
1214 val = OS_REG_READ(ah, AR_WOW_BCN_EN_REG);
1219 val = OS_REG_READ(ah, AR_WOW_PATTERN_REG);
1232 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG, val);
1233 val = OS_REG_READ(ah, AR_WOW_PATTERN_REG);
1236 if (HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_FORCE_BT_SLEEP)) {
1238 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - BT SLEEP\n");
1241 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - BT SLEEP\n");
1244 if (HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_SW_NULL_DISABLE)) {
1245 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - SW NULL\n");
1248 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - SW NULL\n");
1252 if (HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_DEVID_SWAR_DISABLE)) {
1253 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - DevID SWAR\n");
1256 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - DevID SWAR\n");
1261 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Acer SWKA\n");
1264 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Acer SWKA\n");
1269 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Standard Magic\n");
1271 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Acer Magic\n");
1274 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - Standard Magic\n");
1276 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - Acer Magic\n");
1281 HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_FORCE_4WAY_HS_WAKE)) {
1282 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - 4Way Handshake\n");
1285 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - 4Way Handshake\n");
1290 HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_FORCE_AP_LOSS_WAKE))
1292 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - AP loss wake\n");
1295 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - AP loss wake\n");
1300 HAL_WOW_CTRL(ah, HAL_WOW_OFFLOAD_FORCE_GTK_ERR_WAKE))
1302 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - GTK error wake\n");
1305 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - GTK error wake\n");
1310 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - GTK offload\n");
1313 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - GTK offload\n");
1318 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - ARP offload\n");
1321 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - ARP offload\n");
1326 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) ENA - NS offload\n");
1329 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) DIS - NS offload\n");
1341 ah, AR_WOW_PATTERN_MATCH_LT_256B_REG, AR_WOW_PATTERN_SUPPORTED);
1346 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL));
1352 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val);
1357 OS_REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1358 OS_REG_READ(ah, AR_TSF_L32) + timeout_in_seconds * 1000000 );
1360 OS_REG_WRITE(ah, AR_NDP_PERIOD, 30 * 1000000);
1361 OS_REG_WRITE(ah, AR_TIMER_MODE, OS_REG_READ(ah, AR_TIMER_MODE) | 0x80);
1362 OS_REG_WRITE(ah, AR_IMR_S5, OS_REG_READ(ah, AR_IMR_S5) | 0x80);
1363 OS_REG_WRITE(ah, AR_IMR, OS_REG_READ(ah, AR_IMR) | AR_IMR_GENTMR);
1365 OS_REG_WRITE(ah, AR_BSS_ID0, 0);
1366 OS_REG_WRITE(ah, AR_BSS_ID1, 0);
1371 OS_REG_WRITE(ah, AR_STA_ID1,
1372 OS_REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_PRESERVE_SEQNUM);
1374 AH_PRIVATE(ah)->ah_wow_event_mask = wow_event_mask;
1379 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN);
1381 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
1382 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1386 OS_REG_WRITE(ah, AR_WOW_OFFLOAD_COMMAND_JUPITER, wow_feature_enable);
1387 OS_REG_WRITE(ah, AR_WOW_OFFLOAD_STATUS_JUPITER, 0x0);
1389 OS_REG_WRITE(ah, AR_WOW_SW_NULL_PARAMETER,
1395 ar9300_wowoffload_download_devid_swar(ah);
1398 ar9300_wow_offload_download_hal_params(ah);
1399 ar9300_wow_offload_handshake(ah, pattern_enable);
1400 AH9300(ah)->ah_chip_full_sleep = AH_FALSE;
1402 //OS_REG_SET_BIT(ah, AR_SW_WOW_CONTROL, AR_HW_WOW_DISABLE);
1408 if (AH_PRIVATE(ah)->ah_caps.halMciSupport) {
1409 OS_REG_WRITE(ah, AR_RTC_KEEP_AWAKE, 0x2);
1412 ar9300_set_power_mode_wow_sleep(ah);
1413 AH9300(ah)->ah_chip_full_sleep = AH_TRUE;
1420 //ar9300_wow_wake_up(struct ath_hal *ah, u_int8_t *chipPatternBytes)
1421 ar9300_wow_wake_up(struct ath_hal *ah, HAL_BOOL offloadEnabled)
1426 OS_REG_CLR_BIT(ah, AR_SW_WOW_CONTROL, AR_HW_WOW_DISABLE);
1427 OS_REG_CLR_BIT(ah, AR_SW_WOW_CONTROL, AR_SW_WOW_ENABLE);
1433 val = OS_REG_READ(ah, AR_EMB_CPU_WOW_STATUS);
1436 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) SW MAGIC_PATTERN\n");
1440 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) SW USER_PATTERN\n");
1444 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) SW KEEP_ALIVE_FAIL\n");
1448 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) SW BEACON_FAIL\n");
1454 OS_REG_WRITE(ah, AR_EMB_CPU_WOW_STATUS, 0x0);
1455 OS_REG_WRITE(ah, AR_EMB_CPU_WOW_ENABLE, 0);
1456 OS_REG_WRITE(ah, AR_MBOX_CTRL_STATUS, 0);
1465 rval = OS_REG_READ(ah, AR_WOW_PATTERN_REG);
1473 val &= AH_PRIVATE(ah)->ah_wow_event_mask;
1477 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) HW MAGIC_PATTERN\n");
1482 //offset = OS_REG_READ(ah, AR_WOW_RXBUF_START_ADDR);
1488 // *(u_int32_t*)(chipPatternBytes + i) = OS_REG_READ( ah,offset );
1492 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) HW USER_PATTERN\n");
1495 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) HW KEEP_ALIVE_FAIL\n");
1499 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "(WOW) HW BEACON_FAIL\n");
1510 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL));
1514 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_PCIE_PM_CTRL), val);
1519 OS_REG_WRITE(ah, AR_WOW_PATTERN_REG,
1520 AR_WOW_CLEAR_EVENTS(OS_REG_READ(ah, AR_WOW_PATTERN_REG)));
1530 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_WA), OS_REG_READ(ah, AR_WA) |
1535 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_BM_THR, INIT_RSSI_THR);
1544 if (AH_PRIVATE(ah)->ah_is_pci_express == AH_TRUE) {
1545 ar9300_config_pci_power_save(ah, 0, 0);
1548 AH_PRIVATE(ah)->ah_wow_event_mask = 0;
1556 ar9300_wow_set_gpio_reset_low(struct ath_hal *ah)
1560 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT));
1562 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT), val);
1563 val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT));
1564 /* val = OS_REG_READ(ah,AR_GPIO_IN_OUT ); */