Lines Matching defs:ah
18 #include "ah.h"
51 ar9300_paprd_setup_single_table(struct ath_hal *ah, struct ieee80211_channel * chan)
54 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
55 struct ath_hal_9300 *ahp = AH9300(ah);
58 u_int32_t val = OS_REG_READ(ah, AR_2040_MODE);
74 ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom;
78 ar9300_set_target_power_from_eeprom(ah, ichan->channel, target_power_val_t2);
105 if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
113 } else if (AR_SREV_POSEIDON(ah)) {
117 OS_REG_READ_FIELD_ALT(ah, AR_PHY_POWERTX_RATE5,
122 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
143 OS_REG_READ_FIELD_ALT(ah, AR_PHY_POWERTX_RATE8,
164 OS_REG_READ_FIELD_ALT(ah, AR_PHY_POWERTX_RATE6,
187 ath_hal_printf(ah, "%s[%d] paprd_scale_factor %d power_delta %d\n",
193 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
202 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s 2G %d HT40 %d am_mask 0x%08x\n",
204 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK,
206 if (AR_SREV_HORNET(ah)) {
207 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK,
211 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_AM2PM, AR_PHY_PAPRD_AM2PM_MASK,
215 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK,
218 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN0_MASK) {
219 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0,
221 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
223 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
225 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
227 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
229 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
231 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
233 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0,
238 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN1_MASK) {
239 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1,
241 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
243 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
245 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
247 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
249 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
251 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
253 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1,
258 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK) {
259 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2,
261 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
263 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
265 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
267 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
269 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
271 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
273 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2,
277 ar9300_enable_paprd(ah, AH_FALSE, chan);
278 if (AR_SREV_POSEIDON(ah)) {
279 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
281 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
283 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
285 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
287 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
289 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
291 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
293 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2_POSEIDON,
295 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
297 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
299 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
301 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
303 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
305 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
307 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
309 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON,
311 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON,
313 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON,
316 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
318 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
320 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
322 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
324 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
326 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
328 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
331 if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){
332 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2,
335 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2,
339 else if (AR_SREV_WASP(ah) && !is_2g) {
340 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2,
343 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2,
346 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
348 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
350 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
352 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
354 if (AR_SREV_HORNET(ah) || AR_SREV_WASP(ah) || AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) {
355 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
358 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
362 if(AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)){
363 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
366 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
371 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
374 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
376 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4,
378 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4,
380 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4,
384 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_0_B0,
386 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_1_B0,
388 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_2_B0,
390 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_3_B0,
392 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_4_B0,
394 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_5_B0,
396 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_6_B0,
398 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_PRE_POST_SCALE_7_B0,
412 ar9300_check_chan(struct ath_hal *ah, HAL_CHANNEL *chan)
417 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
429 HALDEBUG(ah, HAL_DEBUG_CHANNEL,
436 return (ath_hal_checkchannel(ah, chan));
440 void ar9300_enable_paprd(struct ath_hal *ah, HAL_BOOL enable_flag,
445 u_int32_t val = OS_REG_READ(ah, AR_2040_MODE);
447 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
449 struct ath_hal_9300 *ahp = AH9300(ah);
455 ar9300_eeprom_t *eep = &AH9300(ah)->ah_eeprom;
489 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
515 ichan = ar9300_check_chan(ah, chan);
519 ath_hal_printf(ah, "%s[%d] eeprom_set_transmit_power PAPRD\n",
522 if (ar9300_eeprom_set_transmit_power(ah, &ahp->ah_eeprom, chan,
523 ath_hal_getctl(ah, chan), ath_hal_getantennaallowed(ah, chan),
524 ath_hal_get_twice_max_regpower(AH_PRIVATE(ah), ichan, chan),
525 AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit)) != HAL_OK) {
529 ath_hal_printf(ah,
533 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0,
535 if (!AR_SREV_POSEIDON(ah) && !AR_SREV_HORNET(ah)) {
536 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1,
538 if (!AR_SREV_JUPITER(ah) || (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK)) {
539 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2,
547 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s 2G %d HT40 %d am_mask 0x%08x\n",
549 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_AM2AM, AR_PHY_PAPRD_AM2AM_MASK,
551 if (AR_SREV_HORNET(ah)) {
552 OS_REG_RMW_FIELD_ALT(ah,
555 OS_REG_RMW_FIELD_ALT(ah,
559 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_HT40, AR_PHY_PAPRD_HT40_MASK,
562 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN0_MASK) {
563 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0,
565 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
567 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
569 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
571 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
573 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
575 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
577 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0,
581 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN1_MASK) {
582 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1,
584 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
586 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
588 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
590 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
592 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
594 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
596 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1,
600 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK) {
601 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2,
603 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
605 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
607 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
609 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
611 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
613 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
615 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2,
619 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN0_MASK) {
620 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0,
624 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN1_MASK) {
625 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1,
629 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK) {
630 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2,
635 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN0_MASK) {
636 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0,
640 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN1_MASK) {
641 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1,
645 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK) {
646 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2,
652 static void ar9300_gain_table_entries(struct ath_hal *ah)
656 u_int32_t *gain_table_entries = AH9300(ah)->paprd_gain_table_entries;
657 u_int32_t *gain_vs_table_index = AH9300(ah)->paprd_gain_table_index;
662 gain_table_entries[i] = OS_REG_READ(ah, reg);
666 * ah, "+++reg 0x%08x gain_table_entries[%d] = 0x%08x \n",
674 static unsigned int ar9300_get_desired_gain_for_chain(struct ath_hal *ah,
686 if (AR_SREV_POSEIDON(ah)) {
687 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON,
690 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
695 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_12,
699 OS_REG_READ_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM);
702 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALT_ALPHA_VOLT);
706 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_18,
710 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_18,
715 OS_REG_READ_FIELD_ALT(ah, AR_PHY_THERM_ADC_4,
719 OS_REG_READ_FIELD_ALT(ah, AR_PHY_THERM_ADC_4,
732 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_11_B0,
734 cl_gain_mod = OS_REG_READ_FIELD_ALT(ah, AR_PHY_CL_TAB_0,
737 if (!AR_SREV_POSEIDON(ah)) {
739 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_11_B1,
741 cl_gain_mod = OS_REG_READ_FIELD_ALT(ah, AR_PHY_CL_TAB_1,
745 if (!AR_SREV_POSEIDON(ah)) {
747 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_11_B2,
749 cl_gain_mod = OS_REG_READ_FIELD_ALT(ah, AR_PHY_CL_TAB_2,
776 ath_hal_printf(ah,
787 static void ar9300_tx_force_gain(struct ath_hal *ah, unsigned int gain_index)
791 u_int32_t *gain_table_entries = AH9300(ah)->paprd_gain_table_entries;
793 /*u_int32_t *gain_vs_table_index = ah->paprd_gain_table_index;*/
803 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
805 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
807 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
809 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
811 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
813 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
815 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
817 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
819 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
822 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCED_DAC_GAIN, 0);
823 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCE_DAC_GAIN, 0);
829 static void ar9300_paprd_debug_print(struct ath_hal *ah)
835 if (AR_SREV_POSEIDON(ah)) {
838 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
840 HALDEBUG(ah, HAL_DEBUG_PAPRD,
844 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
846 HALDEBUG(ah, HAL_DEBUG_PAPRD,
850 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
852 HALDEBUG(ah, HAL_DEBUG_PAPRD,
859 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
861 HALDEBUG(ah, HAL_DEBUG_PAPRD,
865 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
867 HALDEBUG(ah, HAL_DEBUG_PAPRD,
871 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
873 HALDEBUG(ah, HAL_DEBUG_PAPRD,
877 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1_POSEIDON,
879 HALDEBUG(ah, HAL_DEBUG_PAPRD,
885 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2_POSEIDON,
887 HALDEBUG(ah, HAL_DEBUG_PAPRD,
891 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
893 HALDEBUG(ah, HAL_DEBUG_PAPRD,
899 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
901 HALDEBUG(ah, HAL_DEBUG_PAPRD,
907 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
909 HALDEBUG(ah, HAL_DEBUG_PAPRD,
916 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
918 HALDEBUG(ah, HAL_DEBUG_PAPRD,
922 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
924 HALDEBUG(ah, HAL_DEBUG_PAPRD,
931 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
933 HALDEBUG(ah, HAL_DEBUG_PAPRD,
939 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
941 HALDEBUG(ah, HAL_DEBUG_PAPRD,
945 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON,
947 HALDEBUG(ah, HAL_DEBUG_PAPRD,
951 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4_POSEIDON,
953 HALDEBUG(ah, HAL_DEBUG_PAPRD,
957 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON,
959 HALDEBUG(ah, HAL_DEBUG_PAPRD,
963 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON,
965 HALDEBUG(ah, HAL_DEBUG_PAPRD,
969 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON,
971 HALDEBUG(ah, HAL_DEBUG_PAPRD,
975 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON,
977 HALDEBUG(ah, HAL_DEBUG_PAPRD,
981 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON,
983 HALDEBUG(ah, HAL_DEBUG_PAPRD,
987 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON,
989 HALDEBUG(ah, HAL_DEBUG_PAPRD,
993 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2_POSEIDON,
995 HALDEBUG(ah, HAL_DEBUG_PAPRD,
999 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2_POSEIDON,
1001 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1005 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2_POSEIDON,
1007 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1011 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT3_POSEIDON,
1013 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1018 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
1020 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1024 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
1026 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1030 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
1032 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1039 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
1041 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1045 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
1047 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1051 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
1053 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1057 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL1,
1059 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1065 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL2,
1067 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1071 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
1073 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1079 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
1081 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1087 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
1089 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1096 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
1098 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1102 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
1104 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1111 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
1113 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1120 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
1122 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1126 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4,
1128 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1132 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL4,
1134 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1138 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
1140 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1144 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
1146 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1150 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
1152 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1156 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
1158 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1162 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
1164 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1168 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
1170 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1174 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2,
1176 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1180 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2,
1182 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1186 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT2,
1188 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1192 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT3,
1194 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1200 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCE_DAC_GAIN);
1201 HALDEBUG(ah, HAL_DEBUG_PAPRD, " dac_gain_forced = 0x%08x\n",
1205 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TPC_1, AR_PHY_TPC_1_FORCED_DAC_GAIN);
1206 HALDEBUG(ah, HAL_DEBUG_PAPRD, " forced_dac_gain = 0x%08x\n",
1211 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B0,
1213 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1215 if (!AR_SREV_POSEIDON(ah)) {
1218 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B1,
1220 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1222 if (AH9300(ah)->ah_tx_chainmask & AR9300_CHAIN2_MASK) {
1225 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL0_B2,
1227 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1234 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
1238 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
1242 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
1246 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
1250 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
1254 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
1258 OS_REG_READ_FIELD_ALT(ah, AR_PHY_TX_FORCED_GAIN,
1261 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1264 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1266 HALDEBUG(ah, HAL_DEBUG_PAPRD,
1270 #define ar9300_paprd_debug_print(ah) /* dummy macro */
1273 static int ar9300_create_pa_curve(struct ath_hal *ah, u_int32_t * pa_table,
1282 ar9300_paprd_debug_print(ah);
1283 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_CHAN_INFO_MEMORY,
1294 paprd_train_data_l[i] = OS_REG_READ(ah, reg);
1298 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_CHAN_INFO_MEMORY,
1309 paprd_train_data_u[i] = OS_REG_READ(ah, reg);
1316 * ah, "%08x%08x\n", paprd_train_data_u[i], paprd_train_data_l[i]);
1327 if (AR_SREV_POSEIDON(ah)) {
1328 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON,
1331 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
1810 void ar9300_swizzle_paprd_entries(struct ath_hal *ah, unsigned int txchain)
1822 paprd_table_val = &AH9300(ah)->pa_table[0][0];
1823 small_signal_gain = AH9300(ah)->small_signal_gain[0];
1826 paprd_table_val = &AH9300(ah)->pa_table[1][0];
1827 small_signal_gain = AH9300(ah)->small_signal_gain[1];
1830 paprd_table_val = &AH9300(ah)->pa_table[2][0];
1831 small_signal_gain = AH9300(ah)->small_signal_gain[2];
1835 ath_hal_printf(ah, "YAK! Bad chain mask %x\n", txchain);
1839 OS_REG_WRITE(ah, reg, paprd_table_val[i]);
1840 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", __func__,
1845 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PA_GAIN123_B0,AR_PHY_PA_GAIN123_B0_PA_GAIN1_0, small_signal_gain);
1846 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x small_signal_gain 0x%08x\n", __func__, __LINE__,
1847 (unsigned) AR_PHY_PA_GAIN123_B0, OS_REG_READ(ah, AR_PHY_PA_GAIN123_B0));
1849 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0, AR_PHY_PAPRD_CTRL1_B0_PAPRD_POWER_AT_AM2AM_CAL_0,
1850 AH9300(ah)->paprd_training_power);
1851 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", __func__, __LINE__,
1852 (unsigned) AR_PHY_PAPRD_CTRL1_B0, OS_REG_READ(ah, AR_PHY_PAPRD_CTRL1_B0));
1856 void ar9300_populate_paprd_single_table(struct ath_hal *ah,
1861 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
1863 u_int32_t *paprd_table_val = &AH9300(ah)->pa_table[chain_num][0];
1864 u_int32_t small_signal_gain = AH9300(ah)->small_signal_gain[chain_num];
1867 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
1880 if (AR_SREV_POSEIDON(ah)) {
1892 OS_REG_WRITE(ah, reg, paprd_table_val[i]);
1893 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", __func__,
1900 if (OS_REG_READ(ah, reg) == 0xdeadbeef) {
1901 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1906 if (OS_REG_READ(ah, j) == 0xdeadbeef) {
1907 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1914 if (OS_REG_READ(ah, j) == 0xdeadbeef) {
1915 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1926 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE,
1929 AH9300(ah)->ah_paprd_broken = AH_TRUE;
1933 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PA_GAIN123_B0,
1935 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
1938 OS_REG_READ(ah, AR_PHY_PA_GAIN123_B0));
1940 if (!AR_SREV_POSEIDON(ah) && !AR_SREV_HORNET(ah) && !AR_SREV_APHRODITE(ah)) {
1941 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PA_GAIN123_B1,
1943 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
1947 OS_REG_READ(ah, AR_PHY_PA_GAIN123_B1));
1950 if (!AR_SREV_POSEIDON(ah) && !AR_SREV_HORNET(ah) && !AR_SREV_APHRODITE(ah)) {
1951 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PA_GAIN123_B2,
1953 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
1957 OS_REG_READ(ah, AR_PHY_PA_GAIN123_B2));
1963 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B0,
1965 AH9300(ah)->paprd_training_power);
1966 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", __func__,
1968 OS_REG_READ(ah, AR_PHY_PAPRD_CTRL1_B0));
1969 if (!AR_SREV_POSEIDON(ah) && !AR_SREV_HORNET(ah) && !AR_SREV_APHRODITE(ah)) {
1970 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B1,
1972 AH9300(ah)->paprd_training_power);
1973 HALDEBUG(ah, HAL_DEBUG_CALIBRATE, "%s[%d] reg %08x = 0x%08x\n", __func__,
1975 OS_REG_READ(ah, AR_PHY_PAPRD_CTRL1_B1));
1976 if (!AR_SREV_WASP(ah) && !AR_SREV_JUPITER(ah)) {
1977 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_CTRL1_B2,
1979 AH9300(ah)->paprd_training_power);
1980 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
1983 OS_REG_READ(ah, AR_PHY_PAPRD_CTRL1_B2));
1986 /*ar9300_enable_paprd(ah, AH_TRUE);*/
1989 HAL_STATUS ar9300_paprd_setup_gain_table(struct ath_hal *ah, int chain_num)
1992 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
1994 AH9300(ah)->paprd_training_power / 2);
1996 if (AH9300(ah)->ah_tx_chainmask & (1 << chain_num)) {
1999 ah, chain_num, AH9300(ah)->paprd_training_power);
2004 if (AH9300(ah)->paprd_gain_table_index[i] < desired_gain) {
2012 /*ath_hal_printf(ah, "++++ gain_index = %d\n", gain_index);*/
2013 ar9300_tx_force_gain(ah, gain_index);
2014 if (AR_SREV_POSEIDON(ah)) {
2015 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON,
2018 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
2026 static HAL_BOOL ar9300_paprd_retrain_pain(struct ath_hal * ah, int * pa_in)
2032 capdiv2g = (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) >> 1) & 0xF;
2033 if (!AR_SREV_POSEIDON(ah)) {
2035 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
2039 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3_POSEIDON,
2052 if (AR_SREV_POSEIDON(ah)) {
2067 OS_REG_RMW_FIELD(ah,
2072 OS_REG_RMW_FIELD_ALT(ah,
2096 OS_REG_RMW_FIELD(ah,
2101 OS_REG_RMW_FIELD_ALT(ah,
2110 }else if (AR_SREV_HORNET(ah)) {
2125 OS_REG_RMW_FIELD(ah,
2129 OS_REG_RMW_FIELD_ALT(ah,
2142 OS_REG_RMW_FIELD(ah,
2146 OS_REG_RMW_FIELD_ALT(ah,
2164 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3,
2167 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
2176 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3,
2179 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_CNTL3,
2191 HAL_STATUS ar9300_paprd_create_curve(struct ath_hal * ah,
2198 if (AH9300(ah)->ah_tx_chainmask & (1 << chain_num)) {
2199 pa_table = &AH9300(ah)->pa_table[chain_num][0];
2201 status = ar9300_create_pa_curve(ah, &pa_table[0], &small_signal_gain,
2204 if (AR_SREV_WASP(ah)) {
2209 ath_hal_printf(ah, "ERROR:: paprd failed with error code = %d\n",
2213 AH9300(ah)->small_signal_gain[chain_num] = small_signal_gain;
2215 if (AR_SREV_POSEIDON(ah) || AR_SREV_HORNET(ah)) {
2216 if (ar9300_paprd_retrain_pain(ah, pa_in)) {
2225 int ar9300_paprd_init_table(struct ath_hal *ah, struct ieee80211_channel * chan)
2227 HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan);
2229 if ((AR_SREV_WASP(ah) && IS_CHAN_5GHZ(ichan)) ||
2230 ar9300_paprd_setup_single_table(ah, chan)) {
2233 OS_MEMZERO(AH9300(ah)->paprd_gain_table_entries,
2234 sizeof(AH9300(ah)->paprd_gain_table_entries));
2235 OS_MEMZERO(AH9300(ah)->paprd_gain_table_index,
2236 sizeof(AH9300(ah)->paprd_gain_table_index));
2238 ar9300_gain_table_entries(ah);
2244 int ar9300_paprd_is_done(struct ath_hal *ah)
2249 if (!AR_SREV_POSEIDON(ah)) {
2251 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
2256 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1,
2259 HALDEBUG(ah, HAL_DEBUG_CALIBRATE,
2270 OS_REG_READ_FIELD_ALT(ah, AR_PHY_PAPRD_TRAINER_STAT1_POSEIDON,
2274 /*ath_hal_printf(ah, "%s[%d] PAPRD TEMp Error\n", __func__, __LINE__);*/
2286 ar9300_paprd_dec_tx_pwr(struct ath_hal *ah)
2291 struct ath_hal_9300 *ahp = AH9300(ah);
2293 if (AR_SREV_POSEIDON(ah)) {
2300 pwr_reg = OS_REG_READ(ah, p_item->reg_addr);
2308 OS_REG_WRITE(ah, p_item->reg_addr, pwr_temp);
2315 int ar9300_paprd_thermal_send(struct ath_hal *ah)
2317 if (AR_SREV_HORNET(ah)) {
2318 return OS_REG_READ(ah, AR_TFCNT);
2325 void ar9300_paprd_test_prints(struct ath_hal *ah)
2332 OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B0));
2336 * OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B0));
2338 if (!AR_SREV_POSEIDON(ah) && !AR_SREV_HORNET(ah)) {
2340 OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B1));
2344 * OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B1));
2347 OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B2));
2351 * OS_REG_READ(ah, AR_PHY_PAPRD_CTRL0_B2));
2358 AR_PHY_PA_GAIN123_B0, OS_REG_READ(ah, AR_PHY_PA_GAIN123_B0));
2363 * OS_REG_READ(ah, AR_PHY_PA_GAIN123_B0));
2368 __func__, __LINE__, reg, OS_REG_READ(ah, reg));
2372 * reg, OS_REG_READ(ah, reg));
2377 ar9300_paprd_debug_print(ah);
2382 if (!AR_SREV_POSEIDON(ah)) {
2386 AR_PHY_PA_GAIN123_B1, OS_REG_READ(ah, AR_PHY_PA_GAIN123_B1));
2388 OS_REG_WRITE(ah, reg, paprd_table_val[i]);
2390 __func__, __LINE__, reg, OS_REG_READ(ah, reg));
2392 OS_REG_READ(ah, reg));
2399 AR_PHY_PA_GAIN123_B2, OS_REG_READ(ah, AR_PHY_PA_GAIN123_B2));
2406 ar9300_paprd_init_table(struct ath_hal *ah, HAL_CHANNEL * chan)
2412 ar9300_paprd_setup_gain_table(struct ath_hal * ah, int chain_num)
2418 ar9300_paprd_create_curve(struct ath_hal * ah, HAL_CHANNEL * chan,
2425 ar9300_paprd_is_done(struct ath_hal *ah)
2431 ar9300_enable_paprd(struct ath_hal *ah, HAL_BOOL enable_flag, HAL_CHANNEL * chan)
2437 ar9300_populate_paprd_single_table(struct ath_hal *ah, HAL_CHANNEL * chan,
2444 ar9300_paprd_dec_tx_pwr(struct ath_hal *ah)
2449 int ar9300_paprd_thermal_send(struct ath_hal *ah)