Lines Matching defs:p_cap
685 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
714 return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK;
768 return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
804 *result = p_cap->halNumAntCfg2Ghz;
807 *result = p_cap->halNumAntCfg5Ghz;
810 *result = p_cap->hal_rx_stbc_support;
813 *result = p_cap->hal_tx_stbc_support;
817 *result = p_cap->halLDPCSupport;
823 (p_cap->halTxChainMask & 0x3) != 0x3 ||
824 (p_cap->halRxChainMask & 0x3) != 0x3) ?
828 (p_cap->halTxChainMask & 0x7) != 0x7 ||
829 (p_cap->halRxChainMask & 0x7) != 0x7) ?
882 *result = p_cap->halApmEnable;
885 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP;
887 *result = p_cap->hal_pcie_lcr_offset;
960 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
965 if (! p_cap->halTkipMicTxRxKeySupport)
1016 if (p_cap->halTsfAddSupport) {
2318 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
2323 p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz;
3197 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
3206 for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) {