Lines Matching defs:ah
20 #include "ah.h"
32 static void ar9300_mci_print_msg(struct ath_hal *ah, HAL_BOOL send,u_int8_t hdr,
53 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s\n", s);
57 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) 0x%08x\n", *(pl + i));
64 void ar9300_mci_osla_setup(struct ath_hal *ah, HAL_BOOL enable)
66 // struct ath_hal_9300 *ahp = AH9300(ah);
70 OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_HW_BASED, 1);
71 OS_REG_RMW_FIELD(ah, AR_MCI_SCHD_TABLE_2, AR_MCI_SCHD_TABLE_2_MEM_BASED, 1);
73 if (!(ah->ah_config.ath_hal_mci_config &
77 if (AR_SREV_APHRODITE(ah))
78 OS_REG_RMW_FIELD(ah, AR_MCI_MISC, AR_MCI_MISC_HW_FIX_EN, 1);
80 thresh = MS(ah->ah_config.ath_hal_mci_config,
82 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
84 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
86 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
92 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
94 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) SCHED aggr thresh: off\n");
96 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
98 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) SCHED one step look ahead: on\n");
101 OS_REG_CLR_BIT(ah, AR_BTCOEX_CTRL,
103 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) SCHED one step look ahead: off\n");
107 static void ar9300_mci_reset_req_wakeup(struct ath_hal *ah)
110 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
111 OS_REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
114 OS_REG_RMW_FIELD(ah, AR_MCI_COMMAND2,
119 static int32_t ar9300_mci_wait_for_interrupt(struct ath_hal *ah,
127 data = OS_REG_READ(ah, address);
130 OS_REG_WRITE(ah, address, bit_position);
133 ar9300_mci_reset_req_wakeup(ah);
138 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
141 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG);
154 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
157 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
159 OS_REG_READ(ah, AR_MCI_INTERRUPT_RAW),
160 OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
166 void ar9300_mci_remote_reset(struct ath_hal *ah, HAL_BOOL wait_done)
170 ar9300_mci_send_message(ah, MCI_REMOTE_RESET, 0, payload, 16,
176 void ar9300_mci_send_lna_transfer(struct ath_hal *ah, HAL_BOOL wait_done)
180 ar9300_mci_send_message(ah, MCI_LNA_TRANS, 0, &payload, 1,
184 static void ar9300_mci_send_req_wake(struct ath_hal *ah, HAL_BOOL wait_done)
186 ar9300_mci_send_message(ah, MCI_REQ_WAKE,
192 void ar9300_mci_send_sys_waking(struct ath_hal *ah, HAL_BOOL wait_done)
194 ar9300_mci_send_message(ah, MCI_SYS_WAKING,
198 static void ar9300_mci_send_lna_take(struct ath_hal *ah, HAL_BOOL wait_done)
203 ar9300_mci_send_message(ah, MCI_LNA_TAKE,
207 static void ar9300_mci_send_sys_sleeping(struct ath_hal *ah, HAL_BOOL wait_done)
209 ar9300_mci_send_message(ah, MCI_SYS_SLEEPING,
214 ar9300_mci_send_coex_version_query(struct ath_hal *ah, HAL_BOOL wait_done)
216 struct ath_hal_9300 *ahp = AH9300(ah);
221 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send Coex version query.\n");
224 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE);
229 ar9300_mci_send_coex_version_response(struct ath_hal *ah, HAL_BOOL wait_done)
231 struct ath_hal_9300 *ahp = AH9300(ah);
234 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send Coex version response.\n");
241 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE);
245 ar9300_mci_send_coex_wlan_channels(struct ath_hal *ah, HAL_BOOL wait_done)
247 struct ath_hal_9300 *ahp = AH9300(ah);
255 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE);
260 static void ar9300_mci_send_coex_bt_status_query(struct ath_hal *ah,
263 struct ath_hal_9300 *ahp = AH9300(ah);
269 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
278 if (!ar9300_mci_send_message(ah, MCI_GPM, 0, pld, 16, wait_done, AH_TRUE))
282 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
292 void ar9300_mci_send_coex_halt_bt_gpm(struct ath_hal *ah,
295 struct ath_hal_9300 *ahp = AH9300(ah);
298 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
315 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16, wait_done, AH_TRUE);
318 static HAL_BOOL ar9300_mci_send_coex_bt_flags(struct ath_hal *ah, HAL_BOOL wait_done,
321 // struct ath_hal_9300 *ahp = AH9300(ah);
336 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
342 return ar9300_mci_send_message(ah, MCI_GPM, 0, pld, 16, wait_done, AH_TRUE);
345 void ar9300_mci_2g5g_changed(struct ath_hal *ah, HAL_BOOL is_2g)
347 struct ath_hal_9300 *ahp = AH9300(ah);
351 //HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) BT_MCI_FLAGS: not changed\n");
354 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) BT_MCI_FLAGS: changed\n");
357 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) BT_MCI_FLAGS: force send\n");
362 static void ar9300_mci_send_2g5g_status(struct ath_hal *ah, HAL_BOOL wait_done)
364 struct ath_hal_9300 *ahp = AH9300(ah);
367 if ((AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) &&
380 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
384 ar9300_mci_send_coex_bt_flags(ah, wait_done,
388 ar9300_mci_send_coex_bt_flags(ah, wait_done,
392 if (AR_SREV_JUPITER_10(ah) && (ahp->ah_mci_bt_state != MCI_BT_SLEEP)) {
397 void ar9300_mci_2g5g_switch(struct ath_hal *ah, HAL_BOOL wait_done)
399 struct ath_hal_9300 *ahp = AH9300(ah);
404 ar9300_mci_send_2g5g_status(ah, AH_TRUE);
406 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send LNA trans\n");
407 ar9300_mci_send_lna_transfer(ah, AH_TRUE);
410 OS_REG_CLR_BIT(ah, AR_MCI_TX_CTRL,
412 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
413 OS_REG_CLR_BIT(ah, AR_GLB_CONTROL,
415 if (!(ah->ah_config.ath_hal_mci_config &
418 ar9300_mci_osla_setup(ah, AH_TRUE);
422 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send LNA take\n");
423 ar9300_mci_send_lna_take(ah, AH_TRUE);
426 OS_REG_SET_BIT(ah, AR_MCI_TX_CTRL,
428 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
429 OS_REG_SET_BIT(ah, AR_GLB_CONTROL,
431 ar9300_mci_osla_setup(ah, AH_FALSE);
434 ar9300_mci_send_2g5g_status(ah, AH_TRUE);
442 if (AR_SREV_JUPITER(ah)) {
445 OS_REG_WRITE(ah, AR_SELFGEN_MASK, 0x02);
446 ar9300_txbf_set_basic_set(ah);
450 ar9300_txbf_set_basic_set(ah);
455 void ar9300_mci_mute_bt(struct ath_hal *ah)
458 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called\n", __func__);
461 OS_REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE, 0xFFFF0000);
462 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, 0xFFFFFFFF);
463 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, 0xFFFFFFFF);
464 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, 0xFFFFFFFF);
465 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, 0xFFFFFFFF);
466 OS_REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
475 if (MCI_ANT_ARCH_PA_LNA_SHARED(ah->ah_config.ath_hal_mci_config)) {
476 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send LNA take\n");
477 ar9300_mci_send_lna_take(ah, AH_TRUE);
480 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Send sys sleeping\n");
481 ar9300_mci_send_sys_sleeping(ah, AH_TRUE);
484 static void ar9300_mci_observation_set_up(struct ath_hal *ah)
491 OS_REG_WRITE(ah, AR_GPIO_INTR_POL, 0x00420000);
492 OS_REG_WRITE(ah, AR_GPIO_OE_OUT, 0x000000ff); // 4050
493 OS_REG_WRITE(ah, AR_GPIO_OUTPUT_MUX1, 0x000bdab4); // 4068
494 OS_REG_WRITE(ah, AR_OBS, 0x0000004b); // 4088
495 OS_REG_WRITE(ah, AR_DIAG_SW, 0x080c0000);
496 OS_REG_WRITE(ah, AR_MACMISC, 0x0001a000);
497 OS_REG_WRITE(ah, AR_PHY_TEST, 0x00080000); // a360
498 OS_REG_WRITE(ah, AR_PHY_TEST_CTL_STATUS, 0xe0000000); // a364
500 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called; config=0x%08x\n",
501 __func__, ah->ah_config.ath_hal_mci_config);
503 if (ah->ah_config.ath_hal_mci_config &
506 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: CONFIG_MCI_OBS_MCI\n", __func__);
507 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA);
508 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK);
509 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
510 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
512 else if (ah->ah_config.ath_hal_mci_config &
515 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: CONFIG_MCI_OBS_TXRX\n", __func__);
516 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_TX);
517 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_WL_IN_RX);
518 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
519 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
520 ar9300_gpio_cfg_output(ah, 5, HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
522 else if (ah->ah_config.ath_hal_mci_config &
525 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: CONFIG_MCI_OBS_BT\n", __func__);
526 ar9300_gpio_cfg_output(ah, 3, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_TX);
527 ar9300_gpio_cfg_output(ah, 2, HAL_GPIO_OUTPUT_MUX_AS_BT_IN_RX);
528 ar9300_gpio_cfg_output(ah, 1, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA);
529 ar9300_gpio_cfg_output(ah, 0, HAL_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK);
535 OS_REG_SET_BIT(ah,
536 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE);
538 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
539 OS_REG_RMW_FIELD(ah, AR_GLB_CONTROL, AR_GLB_DS_JTAG_DISABLE, 1);
540 OS_REG_RMW_FIELD(ah, AR_GLB_CONTROL, AR_GLB_WLAN_UART_INTF_EN, 0);
541 OS_REG_WRITE(ah, AR_GLB_GPIO_CONTROL,
542 (OS_REG_READ(ah, AR_GLB_GPIO_CONTROL) |
546 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_GPIO_OBS_SEL, 0);
547 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_MAC_BB_OBS_SEL, 1);
548 OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_OBS), 0x4b);
549 OS_REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL1, 0x03);
550 OS_REG_RMW_FIELD(ah, AR_DIAG_SW, AR_DIAG_OBS_PT_SEL2, 0x01);
551 OS_REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_LSB, 0x02);
552 OS_REG_RMW_FIELD(ah, AR_MACMISC, AR_MACMISC_MISC_OBS_BUS_MSB, 0x03);
553 //OS_REG_RMW_FIELD(ah, AR_PHY_TEST, AR_PHY_TEST_BBB_OBS_SEL, 0x01);
554 OS_REG_RMW_FIELD(ah, AR_PHY_TEST_CTL_STATUS,
558 static void ar9300_mci_process_gpm_extra(struct ath_hal *ah,
561 struct ath_hal_9300 *ahp = AH9300(ah);
570 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
572 ar9300_mci_send_coex_version_response(ah, AH_TRUE);
576 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
583 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
590 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
597 ar9300_mci_send_coex_wlan_channels(ah, AH_TRUE);
603 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
609 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
623 u_int32_t ar9300_mci_wait_for_gpm(struct ath_hal *ah, u_int8_t gpm_type,
627 struct ath_hal_9300 *ahp = AH9300(ah);
644 time_out = ar9300_mci_wait_for_interrupt(ah,
651 offset = ar9300_mci_state(ah,
658 ar9300_mci_print_msg(ah, AH_FALSE, MCI_GPM, 16, p_gpm);
668 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
673 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
706 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
710 ar9300_mci_send_message(ah, MCI_GPM, 0, payload, 16,
713 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
718 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
721 ar9300_mci_process_gpm_extra(ah, recv_type, recv_opcode, p_gpm);
732 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
735 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
740 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) discard remaining GPM\n");
741 offset = ar9300_mci_state(ah,
748 ar9300_mci_print_msg(ah, AH_FALSE, MCI_GPM, 16, p_gpm);
752 ar9300_mci_process_gpm_extra(ah, recv_type, recv_opcode, p_gpm);
760 static void ar9300_mci_prep_interface(struct ath_hal *ah)
762 struct ath_hal_9300 *ahp = AH9300(ah);
768 saved_mci_int_en = OS_REG_READ(ah, AR_MCI_INTERRUPT_EN);
769 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
771 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
772 OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW));
773 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
774 OS_REG_READ(ah, AR_MCI_INTERRUPT_RAW));
777 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Reset sequence start\n", __func__);
778 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) send REMOTE_RESET\n");
779 ar9300_mci_remote_reset(ah, AH_TRUE);
785 if (AR_SREV_JUPITER_10(ah)) {
790 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send REQ_WAKE to remote(BT)\n",
793 ar9300_mci_send_req_wake(ah, AH_TRUE);
795 if (ar9300_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
798 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
802 if (AR_SREV_JUPITER_10(ah)) {
825 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
827 ar9300_mci_send_sys_waking(ah, AH_TRUE);
836 OS_REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF);
837 OS_REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF);
838 OS_REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF);
839 OS_REG_WRITE(ah, AR_MCI_BT_PRI3, 0xFFFFFFFF);
840 OS_REG_WRITE(ah, AR_MCI_BT_PRI, 0X000000FF);
847 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
849 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_BT_PRI);
851 if (AR_SREV_JUPITER_10(ah) ||
853 MCI_ANT_ARCH_PA_LNA_SHARED(ah->ah_config.ath_hal_mci_config))) {
855 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: Send LNA_TRANS to BT\n",
857 ar9300_mci_send_lna_transfer(ah, AH_TRUE);
862 if (AR_SREV_JUPITER_10(ah) ||
864 MCI_ANT_ARCH_PA_LNA_SHARED(ah->ah_config.ath_hal_mci_config))) {
865 if (ar9300_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
867 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
871 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
877 if (AR_SREV_JUPITER_10(ah)) {
879 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
882 ar9300_mci_remote_reset(ah, AH_TRUE);
889 (OS_REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
891 (OS_REG_READ_FIELD(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
894 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
896 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
900 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
903 void ar9300_mci_setup(struct ath_hal *ah, u_int32_t gpm_addr,
907 struct ath_hal_9300 *ahp = AH9300(ah);
916 ar9300_mci_reset(ah, AH_TRUE, AH_TRUE, AH_TRUE);
919 void ar9300_mci_disable_interrupt(struct ath_hal *ah)
921 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
922 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
925 void ar9300_mci_enable_interrupt(struct ath_hal *ah)
927 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, AR_MCI_INTERRUPT_DEFAULT);
928 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
932 static void ar9300_mci_set_btcoex_ctrl_9565_1ANT(struct ath_hal *ah)
936 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called\n", __func__);
947 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
949 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
952 static void ar9300_mci_set_btcoex_ctrl_9565_2ANT(struct ath_hal *ah)
956 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called\n", __func__);
967 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
969 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
972 static void ar9300_mci_set_btcoex_ctrl_9462(struct ath_hal *ah)
976 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: called\n", __func__);
987 if (AR_SREV_JUPITER_10(ah)) {
991 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, regval);
994 void ar9300_mci_reset(struct ath_hal *ah, HAL_BOOL en_int, HAL_BOOL is_2g,
997 struct ath_hal_9300 *ahp = AH9300(ah);
998 // struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
1001 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: full_sleep = %d, is_2g = %d\n",
1006 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1011 if (OS_REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) {
1012 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1018 OS_REG_WRITE(ah, AR_MCI_GPM_0, ahp->ah_mci_gpm_addr);
1019 OS_REG_WRITE(ah, AR_MCI_GPM_1, ahp->ah_mci_gpm_len);
1020 OS_REG_WRITE(ah, AR_MCI_SCHD_TABLE_0, ahp->ah_mci_sched_addr);
1026 if (AR_SREV_APHRODITE(ah)) {
1027 uint8_t ant = MS(ah->ah_config.ath_hal_mci_config,
1030 ar9300_mci_set_btcoex_ctrl_9565_1ANT(ah);
1032 ar9300_mci_set_btcoex_ctrl_9565_2ANT(ah);
1034 ar9300_mci_set_btcoex_ctrl_9462(ah);
1038 if (is_2g && (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) &&
1039 !(ah->ah_config.ath_hal_mci_config &
1042 ar9300_mci_osla_setup(ah, AH_TRUE);
1045 ar9300_mci_osla_setup(ah, AH_FALSE);
1048 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
1049 OS_REG_SET_BIT(ah, AR_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
1051 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL3,
1055 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2, AR_BTCOEX_CTRL2_RX_DEWEIGHT, 0);
1057 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0);
1060 OS_REG_RMW_FIELD(ah, AR_BTCOEX_WL_LNA, AR_BTCOEX_WL_LNA_TIMEOUT, 0x3D090);
1062 if (ah->ah_config.ath_hal_mci_config & ATH_MCI_CONFIG_CONCUR_TX) {
1066 if ((ah->ah_config.ath_hal_mci_config &
1072 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n",
1079 if (AH_PRIVATE(ah)->ah_curchan) {
1080 chan_flags = AH_PRIVATE(ah)->ah_curchan->channel_flags;
1098 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1108 else if ((ah->ah_config.ath_hal_mci_config &
1120 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
1122 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL2,
1124 OS_REG_RMW_FIELD(ah, AR_BTCOEX_CTRL,
1127 OS_REG_WRITE(ah, AR_BTCOEX_MAX_TXPWR(i), pmax_tx_pwr[i]);
1131 regval = MS(ah->ah_config.ath_hal_mci_config,
1133 OS_REG_RMW_FIELD(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_CLK_DIV, regval);
1135 OS_REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN);
1138 regval = OS_REG_READ(ah, AR_MCI_COMMAND2);
1140 OS_REG_WRITE(ah, AR_MCI_COMMAND2, regval);
1143 OS_REG_WRITE(ah, AR_MCI_COMMAND2, regval);
1146 ar9300_mci_mute_bt(ah);
1151 OS_REG_WRITE(ah, AR_MCI_COMMAND2, regval);
1154 OS_REG_WRITE(ah, AR_MCI_COMMAND2, regval);
1156 ar9300_mci_state(ah, HAL_MCI_STATE_INIT_GPM_OFFSET, NULL);
1157 OS_REG_WRITE(ah, AR_MCI_MSG_ATTRIBUTES_TABLE,
1160 if (MCI_ANT_ARCH_PA_LNA_SHARED(ah->ah_config.ath_hal_mci_config)) {
1161 OS_REG_CLR_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
1163 OS_REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE);
1166 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
1167 ar9300_mci_observation_set_up(ah);
1171 ar9300_mci_prep_interface(ah);
1174 ar9300_mci_enable_interrupt(ah);
1179 ar9300_aic_start_normal(ah);
1184 static void ar9300_mci_queue_unsent_gpm(struct ath_hal *ah, u_int8_t header,
1187 struct ath_hal_9300 *ahp = AH9300(ah);
1192 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1199 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1212 if (AR_SREV_JUPITER_10(ah)) {
1222 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1227 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1236 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1240 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1251 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1256 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1265 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1269 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1282 HAL_BOOL ar9300_mci_send_message(struct ath_hal *ah, u_int8_t header,
1287 struct ath_hal_9300 *ahp = AH9300(ah);
1290 u_int32_t saved_mci_int_en = OS_REG_READ(ah, AR_MCI_INTERRUPT_EN);
1292 regval = OS_REG_READ(ah, AR_BTCOEX_CTRL);
1294 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1297 ar9300_mci_queue_unsent_gpm(ah, header, payload, AH_TRUE);
1301 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1304 ar9300_mci_queue_unsent_gpm(ah, header, payload, AH_TRUE);
1309 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0);
1313 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RAW,
1318 OS_REG_WRITE(ah, (AR_MCI_TX_PAYLOAD0 + i*4), *(payload + i));
1321 ar9300_mci_print_msg(ah, AH_TRUE, header, len, payload);
1323 OS_REG_WRITE(ah, AR_MCI_COMMAND0,
1330 ar9300_mci_wait_for_interrupt(ah, AR_MCI_INTERRUPT_RAW,
1333 ar9300_mci_queue_unsent_gpm(ah, header, payload, AH_TRUE);
1336 ar9300_mci_queue_unsent_gpm(ah, header, payload, AH_FALSE);
1341 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_EN, saved_mci_int_en);
1347 u_int32_t ar9300_mci_get_interrupt(struct ath_hal *ah, u_int32_t *mci_int,
1350 struct ath_hal_9300 *ahp = AH9300(ah);
1362 u_int32_t ar9300_mci_check_int(struct ath_hal *ah, u_int32_t ints)
1366 reg = OS_REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW);
1370 void ar9300_mci_sync_bt_state(struct ath_hal *ah)
1372 struct ath_hal_9300 *ahp = AH9300(ah);
1375 cur_bt_state = ar9300_mci_state(ah, HAL_MCI_STATE_REMOTE_SLEEP, NULL);
1377 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1384 ar9300_mci_send_coex_version_query(ah, AH_TRUE);
1386 ar9300_mci_send_coex_wlan_channels(ah, AH_TRUE);
1388 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: UNHALT BT GPM\n", __func__);
1389 ar9300_mci_send_coex_halt_bt_gpm(ah, AH_FALSE, AH_TRUE);
1394 static HAL_BOOL ar9300_mci_is_gpm_valid(struct ath_hal *ah, u_int32_t msg_index)
1396 struct ath_hal_9300 *ahp = AH9300(ah);
1408 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) Skip RSVD GPM\n");
1416 ar9300_mci_state(struct ath_hal *ah, u_int32_t state_type, u_int32_t *p_data)
1419 struct ath_hal_9300 *ahp = AH9300(ah);
1423 if (AH_PRIVATE(ah)->ah_caps.halMciSupport && ahp->ah_mci_ready) {
1424 value = OS_REG_READ(ah, AR_BTCOEX_CTRL);
1426 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1435 value = MS(OS_REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1436 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1452 OS_REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW,
1455 gpm_ptr = MS(OS_REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR);
1464 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1475 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1484 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1505 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1510 if (ar9300_mci_is_gpm_valid(ah, temp_index)) {
1530 value = MS(OS_REG_READ(ah, AR_MCI_RX_STATUS),
1539 u_int32_t wbtimer = OS_REG_READ(ah, AR_BTCOEX_WBTIMER);
1540 u_int32_t schd_ctl = OS_REG_READ(ah, AR_MCI_HW_SCHD_TBL_CTL);
1548 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) SCHED\n");
1549 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1556 ar9300_mci_print_msg(ah, AH_FALSE, MCI_SCHD_INFO, 16, pld);
1557 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1561 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1578 value = MS(OS_REG_READ(ah, AR_MCI_RX_STATUS),
1607 ar9300_mci_send_coex_version_query(ah, AH_TRUE);
1608 ar9300_mci_send_coex_wlan_channels(ah, AH_TRUE);
1610 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1612 ar9300_mci_send_coex_halt_bt_gpm(ah, AH_FALSE, AH_TRUE);
1614 ar9300_mci_2g5g_switch(ah, AH_TRUE);
1626 ar9300_mci_reset_req_wakeup(ah);
1629 if ((AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) &&
1630 (ah->ah_config.ath_hal_mci_config &
1634 if ((OS_REG_READ(ah, AR_GLB_GPIO_CONTROL) &
1638 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1640 ar9300_mci_observation_set_up(ah);
1647 ar9300_mci_send_coex_version_response(ah, AH_TRUE);
1652 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1659 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) BT version set: %d.%d\n",
1681 ar9300_mci_send_coex_wlan_channels(ah, AH_TRUE);
1685 ar9300_mci_send_coex_version_query(ah, AH_TRUE);
1689 if (AR_SREV_JUPITER_10(ah)) {
1690 ar9300_mci_send_coex_bt_status_query(ah, AH_TRUE,
1693 ar9300_mci_send_coex_bt_status_query(ah, AH_TRUE,
1731 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) hal RECOVER_RX\n");
1732 ar9300_mci_prep_interface(ah);
1735 ar9300_mci_send_coex_wlan_channels(ah, AH_TRUE);
1736 ar9300_mci_2g5g_switch(ah, AH_TRUE);
1742 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) QUERY_BT_DEBUG\n");
1743 ar9300_mci_send_coex_bt_status_query(ah, AH_TRUE,
1746 if (AR_SREV_JUPITER_20_OR_LATER(ah) || AR_SREV_APHRODITE(ah)) {
1747 ar9300_mci_send_coex_bt_flags(ah, AH_TRUE,
1755 value = (ah->ah_config.ath_hal_mci_config &
1760 value = (ah->ah_config.ath_hal_mci_config &
1765 value = ((ah->ah_config.ath_hal_mci_config &
1776 void ar9300_mci_detach(struct ath_hal *ah)
1779 OS_REG_WRITE(ah, AR_BTCOEX_CTRL, 0x00);
1780 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) ar9300_mci_detach\n");
1781 ar9300_mci_disable_interrupt(ah);
1823 void ar9300_mci_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type)
1825 struct ath_hal_9300 *ahp = AH9300(ah);
1826 // struct ath_hal_private *ahpriv = AH_PRIVATE(ah);
1829 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "%s: stomp_type=%d\n", __func__, stomp_type);
1857 if (ah->ah_config.ath_hal_mci_config &
1860 ar9300_gpio_set(ah, 5, 1);
1887 if (ah->ah_config.ath_hal_mci_config &
1890 ar9300_gpio_set(ah, 5, 0);
1920 // if (ah->ah_config.ath_hal_mci_config &
1923 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1932 void ar9300_mci_bt_coex_disable(struct ath_hal *ah)
1934 struct ath_hal_9300 *ahp = AH9300(ah);
1936 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1939 ar9300_mci_bt_coex_set_weights(ah, HAL_BT_COEX_STOMP_NONE);
1945 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]);
1946 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]);
1947 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, ahp->ah_bt_coex_wlan_weight[2]);
1948 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, ahp->ah_bt_coex_wlan_weight[3]);
1953 int ar9300_mci_bt_coex_enable(struct ath_hal *ah)
1955 struct ath_hal_9300 *ahp = AH9300(ah);
1957 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) %s: called\n", __func__);
1959 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
1968 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]);
1969 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]);
1970 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS2, ahp->ah_bt_coex_wlan_weight[2]);
1971 OS_REG_WRITE(ah, AR_BTCOEX_WL_WEIGHTS3, ahp->ah_bt_coex_wlan_weight[3]);
1974 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1);
1977 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER);
1980 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER);