ath_hal/ar9300/ar9300_gpio.c

19 #include "ah.h"
37     struct ath_hal *ah,
82 ar9300_gpio_cfg_output_mux(struct ath_hal *ah, u_int32_t gpio, u_int32_t type)
89         addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3);
91         addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2);
93         addr = AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1);
103     OS_REG_RMW(ah, addr, (type << gpio_shift), (0x1f << gpio_shift));
111     struct ath_hal *ah,
163     HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
179         OS_REG_SET_BIT(ah,
180             AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE);
214     if (smart_ant && (AR_SREV_WASP(ah) || AR_SREV_SCORPION(ah)))
217         ar9340_soc_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
223         ar9300_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
229     OS_REG_RMW(ah,
230                AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT),
241     struct ath_hal *ah,
287     HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.hal_num_gpio_pins);
320     if (smart_ant && AR_SREV_WASP(ah))
326     ar9300_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
331     OS_REG_RMW(ah,
332                AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT),
344 ar9300_gpio_cfg_input(struct ath_hal *ah, u_int32_t gpio)
348     HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
356         OS_REG_SET_BIT(ah,
357             AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), AR_GPIO_JTAG_DISABLE);
363     OS_REG_RMW(ah,
364                AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT),
375 ar9300_gpio_set(struct ath_hal *ah, u_int32_t gpio, u_int32_t val)
377     HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
383     OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT),
393 ar9300_gpio_get(struct ath_hal *ah, u_int32_t gpio)
396     HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
402     gpio_in = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN));
403     OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN),
409 ar9300_gpio_get_intr(struct ath_hal *ah)
412     struct ath_hal_9300 *ahp = AH9300(ah);
424 ar9300_gpio_set_intr(struct ath_hal *ah, u_int gpio, u_int32_t ilevel)
438     regs[0] = AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE);
439     regs[1] = AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK);
443     regs[0] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE);
444     regs[1] = AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK);
449     HALASSERT(gpio < AH_PRIVATE(ah)->ah_caps.halNumGpioPins);
458     gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.halNumGpioPins) - 1;
463             reg_val = OS_REG_READ(ah, regs[i]);
466             OS_REG_WRITE(ah, regs[i], reg_val);
477         reg_val = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL));
486         OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), reg_val);
490             reg_val = OS_REG_READ(ah, regs[i]);
493             OS_REG_WRITE(ah, regs[i], reg_val);
506 ar9300_gpio_get_polarity(struct ath_hal *ah)
508     return OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL));
513 ar9300_gpio_set_polarity(struct ath_hal *ah, u_int32_t pol_map,
518     gpio_mask = (1 << AH_PRIVATE(ah)->ah_caps.halNumGpioPins) - 1;
519     OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), gpio_mask & pol_map);
528     OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR),
530     OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE_CLR));
541 ar9300_gpio_get_mask(struct ath_hal *ah)
545     if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) {
553 ar9300_gpio_set_mask(struct ath_hal *ah, u_int32_t mask, u_int32_t pol_map)
557     if (AH_PRIVATE(ah)->ah_devid == AR9300_DEVID_AR9380_PCIE) {
562         ath_hal_printf(ah, "%s: invalid GPIO mask 0x%x\n", __func__, mask);
565     AH9300(ah)->ah_gpio_mask = mask;
566     OS_REG_WRITE(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL), mask & pol_map);
572 void ar9300_gpio_show(struct ath_hal *ah);
573 void ar9300_gpio_show(struct ath_hal *ah)
575     ath_hal_printf(ah, "--- 9382 GPIOs ---(ah=%p)\n", ah );
576     ath_hal_printf(ah,
577         "AH9300(_ah)->ah_hostifregs:%p\r\n", &(AH9300(ah)->ah_hostifregs));
578     ath_hal_printf(ah,
580         OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUT)));
581     ath_hal_printf(ah,
583          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_IN)));
584     ath_hal_printf(ah,
586          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE_OUT)));
587     ath_hal_printf(ah,
589          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OE1_OUT)));
590     ath_hal_printf(ah,
592          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INTR_POL)));
593     ath_hal_printf(ah,
595          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL)));
596     ath_hal_printf(ah,
598          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1)));
599     ath_hal_printf(ah,
601          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2)));
602     ath_hal_printf(ah,
604          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX1)));
605     ath_hal_printf(ah,
607          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX2)));
608     ath_hal_printf(ah,
610          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_OUTPUT_MUX3)));
611     ath_hal_printf(ah,
613          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INPUT_STATE)));
614     ath_hal_printf(ah,
616          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU)));
617     ath_hal_printf(ah,
619          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_GPIO_DS)));
620     ath_hal_printf(ah,
622          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_ENABLE)));
623     ath_hal_printf(ah,
625          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_MASK)));
626     ath_hal_printf(ah,
628          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_ENABLE)));
629     ath_hal_printf(ah,
631          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_MASK)));
632     ath_hal_printf(ah,
634          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_ASYNC_CAUSE)));
635     ath_hal_printf(ah,
637          OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)));