ath_hal/ar9300/ar9300_beacon.c

19 #include "ah.h"
28 extern u_int32_t ar9300_num_tx_pending(struct ath_hal *ah, u_int q);
36 ar9300_beacon_init(struct ath_hal *ah,
44         OS_REG_SET_BIT(ah, AR_TXCFG, AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
46     OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, ONE_EIGHTH_TU_TO_USEC(next_beacon));
47     OS_REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
49         ah->ah_config.ah_dma_beacon_response_time));
50     OS_REG_WRITE(ah, AR_NEXT_SWBA,
52         ah->ah_config.ah_sw_beacon_response_time));
60     HALDEBUG(ah, HAL_DEBUG_BEACON,
64     OS_REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period_usec);
65     OS_REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period_usec);
66     OS_REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period_usec);
70         ar9300_reset_tsf(ah);
74     OS_REG_SET_BIT(ah, AR_TIMER_MODE,
83 ar9300_set_sta_beacon_timers(struct ath_hal *ah, const HAL_BEACON_STATE *bs)
86     HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps;
91     OS_REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
98     OS_REG_WRITE(ah, AR_BEACON_PERIOD,
100     OS_REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
109     OS_REG_RMW_FIELD(ah, AR_RSSI_THR,
156     HALDEBUG(ah, HAL_DEBUG_BEACON,
158     HALDEBUG(ah, HAL_DEBUG_BEACON,
160     HALDEBUG(ah, HAL_DEBUG_BEACON,
162     HALDEBUG(ah, HAL_DEBUG_BEACON,
165     OS_REG_WRITE(ah, AR_NEXT_DTIM, TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
166     OS_REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(next_tbtt - SLEEP_SLOP));
169     OS_REG_WRITE(ah, AR_SLEEP1,
186     OS_REG_WRITE(ah, AR_SLEEP2,
189     OS_REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
190     OS_REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
193     OS_REG_CLR_BIT(ah, AR_TIMER_MODE, (AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN));
195     OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN
199     OS_REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);