ath_hal/ar9300/ar9300_aic.c

22 #include "ah.h"
162 ar9300_aic_gain_table(struct ath_hal *ah)
207     OS_REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
212         OS_REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000),
282 ar9300_aic_cal_post_process (struct ath_hal *ah)
284     struct ath_hal_9300 *ahp = AH9300(ah);
294     HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) CAL_SRAM:\n");
297         OS_REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1,
302         value = OS_REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1);
312         HALDEBUG(ah, HAL_DEBUG_BT_COEX,
353                 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
378                 HALDEBUG(ah, HAL_DEBUG_BT_COEX,
416         HALDEBUG(ah, HAL_DEBUG_BT_COEX,
450     HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Post processing results:\n");
467         HALDEBUG(ah, HAL_DEBUG_BT_COEX,
485 ar9300_aic_calibration(struct ath_hal *ah)
491     struct ath_hal_9300 *ahp = AH9300(ah);
493     if (AR_SREV_JUPITER_10(ah)) {
521     OS_REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x22180600);
522     OS_REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x52443a2e);
524     OS_REG_WRITE(ah, aic_ctrl_b0[0],
534     OS_REG_WRITE(ah, aic_ctrl_b1[0],
541     OS_REG_WRITE(ah, aic_ctrl_b0[1],
552     OS_REG_WRITE(ah, aic_ctrl_b1[1],
558     OS_REG_WRITE(ah, aic_ctrl_b0[2],
568     OS_REG_WRITE(ah, aic_ctrl_b0[3],
579     ar9300_aic_gain_table(ah);
582     OS_REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
583                 (OS_REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) |
589         OS_REG_CLR_BIT(ah, aic_ctrl_b1[0], AR_PHY_AIC_CAL_ENABLE);
590         OS_REG_SET_BIT(ah, aic_ctrl_b1[0], AR_PHY_AIC_CAL_CH_VALID_RESET);
591         OS_REG_SET_BIT(ah, aic_ctrl_b1[0], AR_PHY_AIC_CAL_ENABLE);
593         HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Start calibration #%d\n",
602             if ((OS_REG_READ(ah, aic_ctrl_b1[0]) & AR_PHY_AIC_CAL_ENABLE) == 0)
604                 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Cal is done at #%d\n", i);
611         aic_stat = OS_REG_READ(ah, aic_stat_b1[0]);
612         HALDEBUG(ah, HAL_DEBUG_BT_COEX,
617         HALDEBUG(ah, HAL_DEBUG_BT_COEX,
622         HALDEBUG(ah, HAL_DEBUG_BT_COEX,
627         aic_stat = OS_REG_READ(ah, aic_stat_b1[1]);
628         HALDEBUG(ah, HAL_DEBUG_BT_COEX,
635             HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Calibration failed.\n");
642                 OS_REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1,
644                 value = OS_REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1);
646                     HALDEBUG(ah, HAL_DEBUG_BT_COEX,
656         HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Calibration failed2.\n");
660     OS_REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
661                 (OS_REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) &
664     ahp->ah_aic_enabled = ar9300_aic_cal_post_process(ah) ? AH_TRUE : AH_FALSE;
666     HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) ah_aic_enable = %d\n",
673 ar9300_aic_start_normal (struct ath_hal *ah)
675     struct ath_hal_9300 *ahp = AH9300(ah);
680     OS_REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x22180600);
681     OS_REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x52443a2e);
683     ar9300_aic_gain_table(ah);
685     OS_REG_WRITE(ah, AR_PHY_AIC_SRAM_ADDR_B1, ATH_AIC_SRAM_AUTO_INCREMENT);
688         OS_REG_WRITE(ah, AR_PHY_AIC_SRAM_DATA_B1, ahp->ah_aic_sram[i]);
691     if (AR_SREV_JUPITER_10(ah)) {
702     OS_REG_WRITE(ah, aic_ctrl1_b0,
710     OS_REG_WRITE(ah, aic_ctrl1_b1,
714     OS_REG_WRITE(ah, aic_ctrl0_b1,
720     HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(AIC) Start normal operation mode.\n");