Lines Matching refs:reg
53 uint32_t reg;
57 reg = al_reg_read32(&axi_regs->cfg_2);
58 reg &= ~UDMA_GEN_AXI_CFG_2_ARB_PROMOTION_MASK;
59 reg |= axi->arb_promotion;
60 al_reg_write32(&axi_regs->cfg_2, reg);
62 reg = al_reg_read32(&axi_regs->endian_cfg);
64 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN;
66 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_64B_EN;
69 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA;
71 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DATA;
74 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC;
76 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_S2M_DESC;
79 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA;
81 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DATA;
84 reg |= UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC;
86 reg &= ~UDMA_GEN_AXI_ENDIAN_CFG_SWAP_M2S_DESC;
88 al_reg_write32(&axi_regs->endian_cfg, reg);
98 uint32_t reg;
99 reg = al_reg_read32(cfg_1);
100 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK;
101 reg |= m2s_sm->id & UDMA_AXI_M2S_COMP_WR_CFG_1_AWID_MASK;
102 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWCACHE_MASK;
103 reg |= (m2s_sm->cache_type <<
106 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_MASK;
107 reg |= (m2s_sm->burst << UDMA_AXI_M2S_COMP_WR_CFG_1_AWBURST_SHIFT) &
109 al_reg_write32(cfg_1, reg);
111 reg = al_reg_read32(cfg_2);
112 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK;
113 reg |= m2s_sm->used_ext & UDMA_AXI_M2S_COMP_WR_CFG_2_AWUSER_MASK;
114 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWSIZE_MASK;
115 reg |= (m2s_sm->bus_size <<
118 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_MASK;
119 reg |= (m2s_sm->qos << UDMA_AXI_M2S_COMP_WR_CFG_2_AWQOS_SHIFT) &
121 reg &= ~UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_MASK;
122 reg |= (m2s_sm->prot << UDMA_AXI_M2S_COMP_WR_CFG_2_AWPROT_SHIFT) &
124 al_reg_write32(cfg_2, reg);
126 reg = al_reg_read32(cfg_max_beats);
127 reg &= ~UDMA_AXI_M2S_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
128 reg |= m2s_sm->max_beats &
130 al_reg_write32(cfg_max_beats, reg);
139 uint32_t reg;
156 reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.data_rd_cfg);
158 reg |= UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY;
160 reg &= ~UDMA_AXI_M2S_DATA_RD_CFG_ALWAYS_BREAK_ON_MAX_BOUDRY;
161 al_reg_write32(&udma->udma_regs->m2s.axi_m2s.data_rd_cfg, reg);
163 reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1);
164 reg &= ~UDMA_AXI_M2S_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK;
165 reg |= (axi_m2s->min_axi_beats <<
168 al_reg_write32(&udma->udma_regs->m2s.axi_m2s.desc_wr_cfg_1, reg);
170 reg = al_reg_read32(&udma->udma_regs->m2s.axi_m2s.ostand_cfg);
171 reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_DATA_RD_MASK;
172 reg |= axi_m2s->ostand_max_data_read &
174 reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_DESC_RD_MASK;
175 reg |= (axi_m2s->ostand_max_desc_read <<
178 reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_REQ_MASK;
179 reg |= (axi_m2s->ostand_max_comp_req <<
182 reg &= ~UDMA_AXI_M2S_OSTAND_CFG_MAX_COMP_DATA_WR_MASK;
183 reg |= (axi_m2s->ostand_max_comp_write <<
186 al_reg_write32(&udma->udma_regs->m2s.axi_m2s.ostand_cfg, reg);
195 uint32_t reg;
196 reg = al_reg_read32(cfg_1);
197 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK;
198 reg |= s2m_sm->id & UDMA_AXI_S2M_COMP_WR_CFG_1_AWID_MASK;
199 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWCACHE_MASK;
200 reg |= (s2m_sm->cache_type <<
203 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_MASK;
204 reg |= (s2m_sm->burst << UDMA_AXI_S2M_COMP_WR_CFG_1_AWBURST_SHIFT) &
206 al_reg_write32(cfg_1, reg);
208 reg = al_reg_read32(cfg_2);
209 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK;
210 reg |= s2m_sm->used_ext & UDMA_AXI_S2M_COMP_WR_CFG_2_AWUSER_MASK;
211 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_MASK;
212 reg |= (s2m_sm->bus_size << UDMA_AXI_S2M_COMP_WR_CFG_2_AWSIZE_SHIFT) &
214 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_MASK;
215 reg |= (s2m_sm->qos << UDMA_AXI_S2M_COMP_WR_CFG_2_AWQOS_SHIFT) &
217 reg &= ~UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_MASK;
218 reg |= (s2m_sm->prot << UDMA_AXI_S2M_COMP_WR_CFG_2_AWPROT_SHIFT) &
220 al_reg_write32(cfg_2, reg);
222 reg = al_reg_read32(cfg_max_beats);
223 reg &= ~UDMA_AXI_S2M_DESC_WR_CFG_1_MAX_AXI_BEATS_MASK;
224 reg |= s2m_sm->max_beats &
226 al_reg_write32(cfg_max_beats, reg);
236 uint32_t reg;
253 reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_3);
255 reg |= UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY;
257 reg &= ~UDMA_AXI_S2M_DESC_RD_CFG_3_ALWAYS_BREAK_ON_MAX_BOUDRY;
258 al_reg_write32(&udma->udma_regs->s2m.axi_s2m.desc_rd_cfg_3, reg);
260 reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1);
261 reg &= ~UDMA_AXI_S2M_DESC_WR_CFG_1_MIN_AXI_BEATS_MASK;
262 reg |= (axi_s2m->min_axi_beats <<
265 al_reg_write32(&udma->udma_regs->s2m.axi_s2m.desc_wr_cfg_1, reg);
267 reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_rd);
268 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_DESC_RD_OSTAND_MASK;
269 reg |= axi_s2m->ostand_max_desc_read &
272 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_RD_MAX_STREAM_ACK_MASK;
273 reg |= (axi_s2m->ack_fifo_depth <<
277 al_reg_write32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_rd, reg);
279 reg = al_reg_read32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_wr);
280 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_WR_OSTAND_MASK;
281 reg |= axi_s2m->ostand_max_data_req &
283 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_DATA_BEATS_WR_OSTAND_MASK;
284 reg |= (axi_s2m->ostand_max_data_write <<
287 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_REQ_MASK;
288 reg |= (axi_s2m->ostand_max_comp_req <<
291 reg &= ~UDMA_AXI_S2M_OSTAND_CFG_WR_MAX_COMP_DATA_WR_OSTAND_MASK;
292 reg |= (axi_s2m->ostand_max_comp_write <<
295 al_reg_write32(&udma->udma_regs->s2m.axi_s2m.ostand_cfg_wr, reg);
303 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s.cfg_len);
318 reg &= ~UDMA_M2S_CFG_LEN_ENCODE_64K;
320 reg |= UDMA_M2S_CFG_LEN_ENCODE_64K;
322 reg &= ~UDMA_M2S_CFG_LEN_ENCODE_64K;
324 reg &= ~UDMA_M2S_CFG_LEN_MAX_PKT_SIZE_MASK;
325 reg |= conf->max_pkt_size;
327 al_reg_write32(&udma->udma_regs->m2s.m2s.cfg_len, reg);
347 uint32_t reg;
349 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1);
350 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK;
351 reg |= conf->desc_fifo_depth;
352 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1, reg);
354 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2);
357 reg |= UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
359 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
365 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK;
366 reg |= conf->max_desc_per_packet &
368 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2, reg);
370 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3);
371 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
372 reg |= conf->min_burst_below_thr &
375 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK;
376 reg |=(conf->min_burst_above_thr <<
380 reg &= ~UDMA_M2S_RD_DESC_PREF_CFG_3_PREF_THR_MASK;
381 reg |= (conf->pref_thr <<
385 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3, reg);
387 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.data_cfg);
388 reg &= ~UDMA_M2S_RD_DATA_CFG_DATA_FIFO_DEPTH_MASK;
389 reg |= conf->data_fifo_depth &
392 reg &= ~UDMA_M2S_RD_DATA_CFG_MAX_PKT_LIMIT_MASK;
393 reg |= (conf->max_pkt_limit
396 al_reg_write32(&udma->udma_regs->m2s.m2s_rd.data_cfg, reg);
405 uint32_t reg;
407 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_1);
409 AL_REG_FIELD_GET(reg, UDMA_M2S_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK,
412 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_2);
413 if (reg & UDMA_M2S_RD_DESC_PREF_CFG_2_MAX_DESC_PER_PKT_MASK)
418 AL_REG_FIELD_GET(reg,
422 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rd.desc_pref_cfg_3);
425 AL_REG_FIELD_GET(reg,
430 AL_REG_FIELD_GET(reg,
434 conf->pref_thr = AL_REG_FIELD_GET(reg,
516 uint32_t reg;
518 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_1);
519 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_1_FIFO_DEPTH_MASK;
520 reg |= conf->desc_fifo_depth;
521 al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_1, reg);
523 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_2);
526 reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
528 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_PREF_FORCE_RR;
535 reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION;
537 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_Q_PROMOTION;
540 reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION;
542 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_FORCE_PROMOTION;
545 reg |= UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION;
547 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_EN_PREF_PREDICTION;
549 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_2_PROMOTION_TH_MASK;
550 reg |= (conf->promotion_th
554 al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_2, reg);
556 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_3);
557 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_MASK;
558 reg |= (conf->pref_thr << UDMA_S2M_RD_DESC_PREF_CFG_3_PREF_THR_SHIFT) &
561 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_BELOW_THR_MASK;
562 reg |= conf->min_burst_below_thr &
565 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_3_MIN_BURST_ABOVE_THR_MASK;
566 reg |=(conf->min_burst_above_thr <<
570 al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_3, reg);
572 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_4);
573 reg &= ~UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK;
574 reg |= conf->a_full_thr & UDMA_S2M_RD_DESC_PREF_CFG_4_A_FULL_THR_MASK;
575 al_reg_write32(&udma->udma_regs->s2m.s2m_rd.desc_pref_cfg_4, reg);
585 uint32_t reg;
587 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_1);
588 reg &= ~UDMA_S2M_WR_DATA_CFG_1_DATA_FIFO_DEPTH_MASK;
589 reg |= conf->data_fifo_depth &
591 reg &= ~UDMA_S2M_WR_DATA_CFG_1_MAX_PKT_LIMIT_MASK;
592 reg |= (conf->max_pkt_limit <<
595 reg &= ~UDMA_S2M_WR_DATA_CFG_1_FIFO_MARGIN_MASK;
596 reg |= (conf->fifo_margin <<
599 al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_1, reg);
601 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2);
602 reg &= ~UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK;
603 reg |= conf->desc_wait_timer &
605 reg &= ~(UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC |
610 reg |= conf->flags &
616 al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2, reg);
625 uint32_t reg = al_reg_read32(&udma->udma_regs->s2m.s2m_comp.cfg_1c);
626 reg &= ~UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK;
627 reg |= conf->desc_size & UDMA_S2M_COMP_CFG_1C_DESC_SIZE_MASK;
629 reg |= UDMA_S2M_COMP_CFG_1C_CNT_WORDS;
631 reg &= ~UDMA_S2M_COMP_CFG_1C_CNT_WORDS;
633 reg |= UDMA_S2M_COMP_CFG_1C_Q_PROMOTION;
635 reg &= ~UDMA_S2M_COMP_CFG_1C_Q_PROMOTION;
637 reg |= UDMA_S2M_COMP_CFG_1C_FORCE_RR;
639 reg &= ~UDMA_S2M_COMP_CFG_1C_FORCE_RR;
640 reg &= ~UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_MASK;
641 reg |= (conf->q_free_min << UDMA_S2M_COMP_CFG_1C_Q_FREE_MIN_SHIFT) &
643 al_reg_write32(&udma->udma_regs->s2m.s2m_comp.cfg_1c, reg);
645 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_comp.cfg_2c);
646 reg &= ~UDMA_S2M_COMP_CFG_2C_COMP_FIFO_DEPTH_MASK;
647 reg |= conf->comp_fifo_depth
649 reg &= ~UDMA_S2M_COMP_CFG_2C_UNACK_FIFO_DEPTH_MASK;
650 reg |= (conf->unack_fifo_depth
653 al_reg_write32(&udma->udma_regs->s2m.s2m_comp.cfg_2c, reg);
664 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_dwrr.cfg_sched);
667 reg |= UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR;
669 reg &= ~UDMA_M2S_DWRR_CFG_SCHED_EN_DWRR;
672 reg |= UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN;
674 reg &= ~UDMA_M2S_DWRR_CFG_SCHED_PKT_MODE_EN;
676 reg &= ~UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_MASK;
677 reg |= sched->weight << UDMA_M2S_DWRR_CFG_SCHED_WEIGHT_INC_SHIFT;
678 reg &= ~UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_MASK;
679 reg |= sched->inc_factor << UDMA_M2S_DWRR_CFG_SCHED_INC_FACTOR_SHIFT;
680 al_reg_write32(&udma->udma_regs->m2s.m2s_dwrr.cfg_sched, reg);
682 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_dwrr.ctrl_deficit_cnt);
683 reg &= ~UDMA_M2S_DWRR_CTRL_DEFICIT_CNT_INIT_MASK;
684 reg |= sched->deficit_init_val;
685 al_reg_write32(&udma->udma_regs->m2s.m2s_dwrr.ctrl_deficit_cnt, reg);
694 uint32_t reg = al_reg_read32(
698 reg |= UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN;
700 reg &= ~UDMA_M2S_RATE_LIMITER_GEN_CFG_PKT_MODE_EN;
701 reg &= ~UDMA_M2S_RATE_LIMITER_GEN_CFG_SHORT_CYCLE_SIZE_MASK;
702 reg |= mode->short_cycle_sz &
704 al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.gen_cfg, reg);
706 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_token);
707 reg &= ~UDMA_M2S_RATE_LIMITER_CTRL_TOKEN_RST_MASK;
708 reg |= mode->token_init_val &
710 al_reg_write32(&udma->udma_regs->m2s.m2s_rate_limiter.ctrl_token, reg);
717 uint32_t reg = al_reg_read32(
719 reg |= UDMA_M2S_RATE_LIMITER_CTRL_CYCLE_CNT_RST;
721 reg);
729 uint32_t reg = al_reg_read32(®s->cfg_1s);
731 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_MAX_BURST_SIZE_MASK;
732 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN;
733 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE;
734 reg |= conf->max_burst_sz &
736 al_reg_write32(®s->cfg_1s, reg);
738 reg = al_reg_read32(®s->cfg_cycle);
739 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_CYCLE_LONG_CYCLE_SIZE_MASK;
740 reg |= conf->long_cycle_sz &
742 al_reg_write32(®s->cfg_cycle, reg);
744 reg = al_reg_read32(®s->cfg_token_size_1);
745 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_1_LONG_CYCLE_MASK;
746 reg |= conf->long_cycle &
748 al_reg_write32(®s->cfg_token_size_1, reg);
750 reg = al_reg_read32(®s->cfg_token_size_2);
751 reg &= ~UDMA_M2S_STREAM_RATE_LIMITER_CFG_TOKEN_SIZE_2_SHORT_CYCLE_MASK;
752 reg |= conf->short_cycle &
754 al_reg_write32(®s->cfg_token_size_2, reg);
756 reg = al_reg_read32(®s->mask);
757 reg &= ~0xf; /* only bits 0-3 defined */
758 reg |= conf->mask & 0xf;
759 al_reg_write32(®s->mask, reg);
767 uint32_t reg;
771 reg = al_reg_read32(®s->cfg_1s);
772 reg |= UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_EN;
773 al_reg_write32(®s->cfg_1s, reg);
776 reg = al_reg_read32(®s->cfg_1s);
777 reg |= UDMA_M2S_STREAM_RATE_LIMITER_CFG_1S_PAUSE;
778 al_reg_write32(®s->cfg_1s, reg);
781 reg = al_reg_read32(®s->sw_ctrl);
782 reg |= UDMA_M2S_STREAM_RATE_LIMITER_SW_CTRL_RST_TOKEN_CNT;
783 al_reg_write32(®s->sw_ctrl, reg);
842 uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_1);
844 reg &= ~UDMA_M2S_Q_DWRR_CFG_1_MAX_DEFICIT_CNT_SIZE_MASK;
845 reg |= conf->max_deficit_cnt_sz &
848 reg |= UDMA_M2S_Q_DWRR_CFG_1_STRICT;
850 reg &= ~UDMA_M2S_Q_DWRR_CFG_1_STRICT;
851 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_1, reg);
853 reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_2);
854 reg &= ~UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
855 reg |= (conf->axi_qos << UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_SHIFT) &
857 reg &= ~UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
858 reg |= conf->q_qos & UDMA_M2S_Q_DWRR_CFG_2_Q_QOS_MASK;
859 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_2, reg);
861 reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_3);
862 reg &= ~UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK;
863 reg |= conf->weight & UDMA_M2S_Q_DWRR_CFG_3_WEIGHT_MASK;
864 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_3, reg);
871 uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_cfg_1);
874 reg |= UDMA_M2S_Q_DWRR_CFG_1_PAUSE;
876 reg &= ~UDMA_M2S_Q_DWRR_CFG_1_PAUSE;
877 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_cfg_1, reg);
884 uint32_t reg = al_reg_read32(&udma_q->q_regs->m2s_q.dwrr_sw_ctrl);
886 reg |= UDMA_M2S_Q_DWRR_SW_CTRL_RST_CNT;
887 al_reg_write32(&udma_q->q_regs->m2s_q.dwrr_sw_ctrl, reg);
896 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_1c);
899 reg |= UDMA_M2S_COMP_CFG_1C_FORCE_RR;
901 reg &= ~UDMA_M2S_COMP_CFG_1C_FORCE_RR;
909 reg |= UDMA_M2S_COMP_CFG_1C_Q_PROMOTION;
911 reg &= ~UDMA_M2S_COMP_CFG_1C_Q_PROMOTION;
912 reg &= ~UDMA_M2S_COMP_CFG_1C_COMP_FIFO_DEPTH_MASK;
913 reg |=
916 reg &= ~UDMA_M2S_COMP_CFG_1C_UNACK_FIFO_DEPTH_MASK;
917 reg |= conf->unack_fifo_depth
919 al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_1c, reg);
924 reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_application_ack);
925 reg &= ~UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_MASK;
926 reg |= conf->app_timeout << UDMA_M2S_COMP_CFG_APPLICATION_ACK_TOUT_SHIFT;
927 al_reg_write32(&udma->udma_regs->m2s.m2s_comp.cfg_application_ack, reg);
934 uint32_t reg = al_reg_read32(&udma->udma_regs->m2s.m2s_comp.cfg_1c);
936 if (reg & UDMA_M2S_COMP_CFG_1C_FORCE_RR)
941 if (reg & UDMA_M2S_COMP_CFG_1C_Q_PROMOTION)
947 AL_REG_FIELD_GET(reg,
951 AL_REG_FIELD_GET(reg,
958 reg = al_reg_read32(
962 AL_REG_FIELD_GET(reg,
974 uint32_t reg;
976 reg = al_reg_read32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2);
984 reg |= UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC;
986 reg &= ~UDMA_S2M_WR_DATA_CFG_2_DROP_IF_NO_DESC;
989 reg |= UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC;
991 reg &= ~UDMA_S2M_WR_DATA_CFG_2_HINT_IF_NO_DESC;
993 AL_REG_FIELD_SET(reg, UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_MASK, UDMA_S2M_WR_DATA_CFG_2_DESC_WAIT_TIMER_SHIFT, wait_for_desc_timeout);
995 al_reg_write32(&udma->udma_regs->s2m.s2m_wr.data_cfg_2, reg);
1003 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
1006 reg |= UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
1008 reg &= ~UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
1010 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
1019 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
1022 reg &= ~UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
1024 reg |= UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
1026 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
1056 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.pkt_cfg);
1058 reg &= ~UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
1059 reg &= ~UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
1060 reg &= ~UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
1063 reg |= hdr_len & UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
1064 reg |= UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
1067 reg |= UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
1070 al_reg_write32(&udma_q->q_regs->s2m_q.pkt_cfg, reg);
1079 uint32_t reg = al_reg_read32(&udma_q->q_regs->s2m_q.comp_cfg);
1081 reg |= UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
1083 reg &= ~UDMA_S2M_Q_COMP_CFG_EN_COMP_RING_UPDATE;
1086 reg |= UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
1088 reg &= ~UDMA_S2M_Q_COMP_CFG_DIS_COMP_COAL;
1090 al_reg_write32(&udma_q->q_regs->s2m_q.comp_cfg, reg);
1094 reg = al_reg_read32(&udma_q->q_regs->s2m_q.pkt_cfg);
1096 reg &= ~UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
1097 reg |= conf->hdr_split_size & UDMA_S2M_Q_PKT_CFG_HDR_SPLIT_SIZE_MASK;
1099 reg |= UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
1101 reg &= ~UDMA_S2M_Q_PKT_CFG_FORCE_HDR_SPLIT;
1103 reg |= UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
1105 reg &= ~UDMA_S2M_Q_PKT_CFG_EN_HDR_SPLIT;
1107 al_reg_write32(&udma_q->q_regs->s2m_q.pkt_cfg, reg);
1109 reg = al_reg_read32(&udma_q->q_regs->s2m_q.qos_cfg);
1110 reg &= ~UDMA_S2M_QOS_CFG_Q_QOS_MASK;
1111 reg |= conf->q_qos & UDMA_S2M_QOS_CFG_Q_QOS_MASK;
1112 al_reg_write32(&udma_q->q_regs->s2m_q.qos_cfg, reg);