Lines Matching refs:app
239 al_reg_write32(®s->app.parity->en_core,
242 al_reg_write32_masked(®s->app.int_grp_b->mask,
478 uint32_t port_init = al_reg_read32(regs->app.global_ctrl.port_init);
496 info_0 = al_reg_read32(®s->app.debug->info_0);
831 al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_0, (1 << 21));
834 al_reg_write32(regs->app.soc_int[pf_num].mask_inta_leg_3, (1 << 18));
850 * Backup the value of the app.int_grp_a.mask_a register, because
851 * app.int_grp_a.mask_clear_a gets overwritten during the write to
852 * app.soc.mask_msi_leg_0 register.
853 * Restore the original value after the write to app.soc.mask_msi_leg_0
859 backup = al_reg_read32(®s->app.int_grp_a->mask);
860 al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22));
861 al_reg_write32(®s->app.int_grp_a->mask, backup);
863 al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_0, (1 << 22));
866 al_reg_write32(regs->app.soc_int[pf_num].mask_msi_leg_3, (1 << 19));
891 ®s->app.ctrl_gen->features,
920 al_reg_write32_masked(regs->app.global_ctrl.sris_kp_counter,
1058 pcie_port->regs->app.global_ctrl.port_init = ®s->app.global_ctrl.port_init;
1059 pcie_port->regs->app.global_ctrl.pm_control = ®s->app.global_ctrl.pm_control;
1060 pcie_port->regs->app.global_ctrl.events_gen[0] = ®s->app.global_ctrl.events_gen;
1061 pcie_port->regs->app.debug = ®s->app.debug;
1062 pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = ®s->app.soc_int.mask_inta_leg_0;
1063 pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = ®s->app.soc_int.mask_msi_leg_0;
1064 pcie_port->regs->app.ctrl_gen = ®s->app.ctrl_gen;
1065 pcie_port->regs->app.parity = ®s->app.parity;
1066 pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
1067 pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
1070 pcie_port->regs->app.int_grp_a = ®s->app.int_grp_a_m0;
1071 pcie_port->regs->app.int_grp_b = ®s->app.int_grp_b_m0;
1073 pcie_port->regs->app.int_grp_a = ®s->app.int_grp_a;
1074 pcie_port->regs->app.int_grp_b = ®s->app.int_grp_b;
1118 pcie_port->regs->app.global_ctrl.port_init = ®s->app.global_ctrl.port_init;
1119 pcie_port->regs->app.global_ctrl.pm_control = ®s->app.global_ctrl.pm_control;
1120 pcie_port->regs->app.global_ctrl.events_gen[0] = ®s->app.global_ctrl.events_gen;
1121 pcie_port->regs->app.global_ctrl.corr_err_sts_int = ®s->app.global_ctrl.pended_corr_err_sts_int;
1122 pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = ®s->app.global_ctrl.pended_uncorr_err_sts_int;
1123 pcie_port->regs->app.debug = ®s->app.debug;
1124 pcie_port->regs->app.ap_user_send_msg = ®s->app.ap_user_send_msg;
1125 pcie_port->regs->app.soc_int[0].mask_inta_leg_0 = ®s->app.soc_int.mask_inta_leg_0;
1126 pcie_port->regs->app.soc_int[0].mask_inta_leg_3 = ®s->app.soc_int.mask_inta_leg_3;
1127 pcie_port->regs->app.soc_int[0].mask_msi_leg_0 = ®s->app.soc_int.mask_msi_leg_0;
1128 pcie_port->regs->app.soc_int[0].mask_msi_leg_3 = ®s->app.soc_int.mask_msi_leg_3;
1129 pcie_port->regs->app.ctrl_gen = ®s->app.ctrl_gen;
1130 pcie_port->regs->app.parity = ®s->app.parity;
1131 pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
1132 pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
1133 pcie_port->regs->app.status_per_func[0] = ®s->app.status_per_func;
1134 pcie_port->regs->app.int_grp_a = ®s->app.int_grp_a;
1135 pcie_port->regs->app.int_grp_b = ®s->app.int_grp_b;
1203 pcie_port->regs->app.global_ctrl.port_init = ®s->app.global_ctrl.port_init;
1204 pcie_port->regs->app.global_ctrl.pm_control = ®s->app.global_ctrl.pm_control;
1205 pcie_port->regs->app.global_ctrl.corr_err_sts_int = ®s->app.global_ctrl.pended_corr_err_sts_int;
1206 pcie_port->regs->app.global_ctrl.uncorr_err_sts_int = ®s->app.global_ctrl.pended_uncorr_err_sts_int;
1209 pcie_port->regs->app.global_ctrl.events_gen[i] = ®s->app.events_gen_per_func[i].events_gen;
1212 pcie_port->regs->app.global_ctrl.sris_kp_counter = ®s->app.global_ctrl.sris_kp_counter_value;
1213 pcie_port->regs->app.debug = ®s->app.debug;
1216 pcie_port->regs->app.soc_int[i].mask_inta_leg_0 = ®s->app.soc_int_per_func[i].mask_inta_leg_0;
1217 pcie_port->regs->app.soc_int[i].mask_inta_leg_3 = ®s->app.soc_int_per_func[i].mask_inta_leg_3;
1218 pcie_port->regs->app.soc_int[i].mask_msi_leg_0 = ®s->app.soc_int_per_func[i].mask_msi_leg_0;
1219 pcie_port->regs->app.soc_int[i].mask_msi_leg_3 = ®s->app.soc_int_per_func[i].mask_msi_leg_3;
1222 pcie_port->regs->app.ap_user_send_msg = ®s->app.ap_user_send_msg;
1223 pcie_port->regs->app.ctrl_gen = ®s->app.ctrl_gen;
1224 pcie_port->regs->app.parity = ®s->app.parity;
1225 pcie_port->regs->app.atu.in_mask_pair = regs->app.atu.in_mask_pair;
1226 pcie_port->regs->app.atu.out_mask_pair = regs->app.atu.out_mask_pair;
1229 pcie_port->regs->app.status_per_func[i] = ®s->app.status_per_func[i];
1231 pcie_port->regs->app.int_grp_a = ®s->app.int_grp_a;
1232 pcie_port->regs->app.int_grp_b = ®s->app.int_grp_b;
1233 pcie_port->regs->app.int_grp_c = ®s->app.int_grp_c;
1234 pcie_port->regs->app.int_grp_d = ®s->app.int_grp_d;
1879 regs->app.global_ctrl.port_init,
1900 regs->app.global_ctrl.port_init,
2020 events_gen = al_reg_read32(regs->app.global_ctrl.events_gen[0]);
2033 al_reg_write32_masked(regs->app.global_ctrl.events_gen[0],
2310 al_reg_write32_masked(regs->app.global_ctrl.pm_control,
2375 ®s->app.atu.out_mask_pair[atu_region->index / 2] :
2376 ®s->app.atu.in_mask_pair[atu_region->index / 2];
2522 reg = al_reg_read32(regs->app.global_ctrl.events_gen[pf_num]);
2524 al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);
2538 reg = al_reg_read32(regs->app.global_ctrl.events_gen[pf_num]);
2544 al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);
2547 al_reg_write32(regs->app.global_ctrl.events_gen[pf_num], reg);