Lines Matching refs:__iomem
159 (uint32_t __iomem *)(regs->core_space[0].pcie_link_cap_base),
162 (uint32_t __iomem *)(regs->core_space[0].pcie_cap_base
353 void __iomem *pbs_reg_base,
354 void __iomem *pcie_reg_base)
373 struct al_pcie_revx_regs __iomem *regs =
374 (struct al_pcie_revx_regs __iomem *)pcie_reg_base;
569 uint16_t __iomem *lanes_eq_base = (uint16_t __iomem *)(regs->core_space[0].pcie_sec_ext_cap_base + (0xC >> 2));
710 uint32_t __iomem *bar_addr = ®s->core_space[pf_num].config_header[(AL_PCI_BASE_ADDRESS_0 >> 2) + bar_idx];
815 uint32_t __iomem *exp_rom_bar_addr =
823 uint32_t __iomem *exp_rom_bar_addr =
1006 void __iomem *pcie_reg_base,
1007 void __iomem *pbs_reg_base,
1030 struct al_pcie_rev1_regs __iomem *regs =
1031 (struct al_pcie_rev1_regs __iomem *)pcie_reg_base;
1090 struct al_pcie_rev2_regs __iomem *regs =
1091 (struct al_pcie_rev2_regs __iomem *)pcie_reg_base;
1150 struct al_pcie_rev3_regs __iomem *regs =
1151 (struct al_pcie_rev3_regs __iomem *)pcie_reg_base;
1695 al_reg_write32_masked((uint32_t __iomem *)
1793 (uint16_t __iomem *)(®s->core_space[0].config_header[0] + (0x4 >> 2)),
1801 (uint32_t __iomem *)(®s->core_space[0].config_header[0]
1947 pcie_lnksta = al_reg_read16((uint16_t __iomem *)regs->core_space[0].pcie_cap_base + (AL_PCI_EXP_LNKSTA >> 1));
2174 uint8_t __iomem **addr)
2178 *addr = (uint8_t __iomem *)®s->core_space[pcie_pf->pf_num].config_header[0];