Lines Matching defs:isrc

274 		struct intr_irqsrc *isrc;
280 isrc = &sc->gic_irqs[irq].gi_isrc;
282 err = intr_isrc_register(isrc, sc->dev,
285 err = intr_isrc_register(isrc, sc->dev,
288 err = intr_isrc_register(isrc, sc->dev, 0,
576 gic_v3_setup_intr(device_t dev, struct intr_irqsrc *isrc,
580 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
599 if (isrc->isrc_handlers != 0) {
616 if (isrc->isrc_flags & INTR_ISRCF_PPI)
617 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
644 gic_v3_bind_intr(dev, isrc);
651 gic_v3_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
654 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
656 if (isrc->isrc_handlers == 0) {
665 gic_v3_disable_intr(device_t dev, struct intr_irqsrc *isrc)
672 gi = (struct gic_v3_irqsrc *)isrc;
689 gic_v3_enable_intr(device_t dev, struct intr_irqsrc *isrc)
696 gi = (struct gic_v3_irqsrc *)isrc;
713 gic_v3_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
715 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
717 gic_v3_disable_intr(dev, isrc);
722 gic_v3_post_ithread(device_t dev, struct intr_irqsrc *isrc)
725 gic_v3_enable_intr(dev, isrc);
729 gic_v3_post_filter(device_t dev, struct intr_irqsrc *isrc)
731 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
740 gic_v3_bind_intr(device_t dev, struct intr_irqsrc *isrc)
746 gi = (struct gic_v3_irqsrc *)isrc;
755 if (CPU_EMPTY(&isrc->isrc_cpu)) {
757 CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
765 cpu = CPU_FFS(&isrc->isrc_cpu) - 1;
779 struct intr_irqsrc *isrc;
799 isrc = GIC_INTR_ISRC(sc, irq);
800 if (intr_isrc_init_on_cpu(isrc, cpu))
801 gic_v3_enable_intr(dev, isrc);
806 isrc = GIC_INTR_ISRC(sc, irq);
807 if (intr_isrc_init_on_cpu(isrc, cpu))
808 gic_v3_enable_intr(dev, isrc);
818 gic_v3_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
821 struct gic_v3_irqsrc *gi = (struct gic_v3_irqsrc *)isrc;
868 struct intr_irqsrc *isrc;
874 isrc = GIC_INTR_ISRC(sc, sgi_first_unused);
877 CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
879 *isrcp = isrc;