xscale/ixp425/ixp425_qmgr.c

253 	    struct qmgrInfo *qi = &sc->qinfo[i];
255 	    qi->cb = dummyCallback;
256 	    qi->priority = IX_QMGR_Q_PRIORITY_0;	/* default priority */
263 	    qi->intRegCheckMask = (1<<(i%(IX_QMGR_MIN_QUEUPP_QID)));
272 	    qi->qAccRegAddr = IX_QMGR_Q_ACCESS_ADDR_GET(i);
273 	    qi->qAccRegAddr = IX_QMGR_Q_ACCESS_ADDR_GET(i);
274 	    qi->qConfigRegAddr = IX_QMGR_Q_CONFIG_ADDR_GET(i);
279 		qi->qUOStatRegAddr = IX_QMGR_QUEUOSTAT0_OFFSET +
284 		qi->qUflowStatBitMask =
290 		qi->qOflowStatBitMask =
296 		qi->qStatRegAddr = IX_QMGR_QUELOWSTAT0_OFFSET +
301 		qi->qStatBitsOffset =
305 		qi->qUOStatRegAddr = 0;		/* XXX */
308 		qi->qStat0BitMask = (1 << (i - IX_QMGR_MIN_QUEUPP_QID));
311 		qi->qStat1BitMask = (1 << (i - IX_QMGR_MIN_QUEUPP_QID));
341 	struct qmgrInfo *qi = &sc->qinfo[qId];
347 	qi->qSizeInWords = qEntries;
349 	qi->qReadCount = 0;
350 	qi->qWriteCount = 0;
351 	qi->qSizeInEntries = qEntries;	/* XXX kept for code clarity */
355 	    qi->cb = dummyCallback;
356 	    qi->cbarg = NULL;
358 	    qi->cb = cb;
359 	    qi->cbarg = cbarg;
367 	sc->aqmFreeSramAddress += (qi->qSizeInWords * sizeof(uint32_t));
385 	struct qmgrInfo *qi = &sc->qinfo[qId];
388 	    __func__, qId, entry, qi->qWriteCount, qi->qSizeInEntries);
391 	aqm_reg_write(sc, qi->qAccRegAddr, entry);
395 	    int qSize = qi->qSizeInEntries;
400 	    if (qi->qWriteCount++ == qSize) {	/* check for overflow */
401 		uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
408 		if ((status & qi->qOflowStatBitMask) ||
409 		    ((status = aqm_reg_read(sc, qi->qUOStatRegAddr)) & qi->qOflowStatBitMask)) {
413 		    aqm_reg_write(sc, qi->qUOStatRegAddr,
414 			status & ~qi->qOflowStatBitMask);
415 		    qi->qWriteCount = qSize;
428 		qPtrs = aqm_reg_read(sc, qi->qConfigRegAddr);
440 		    qi->qWriteCount = qSize;
443 		    qi->qWriteCount = qPtrs & (qSize - 1);
454 	struct qmgrInfo *qi = &sc->qinfo[qId];
455 	bus_size_t off = qi->qAccRegAddr;
463 	qi->qReadCount = 0;
468 	    uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
470 	    if (status & qi->qUflowStatBitMask) { /* clear underflow status */
471 		aqm_reg_write(sc, qi->qUOStatRegAddr,
472 		    status &~ qi->qUflowStatBitMask);
483 	struct qmgrInfo *qi = &sc->qinfo[qId];
485 	bus_size_t off = qi->qAccRegAddr;
502 	qi->qReadCount = 0;
507 	    uint32_t status = aqm_reg_read(sc, qi->qUOStatRegAddr);
509 	    if (status & qi->qUflowStatBitMask) { /* clear underflow status */
510 		aqm_reg_write(sc, qi->qUOStatRegAddr,
511 		    status &~ qi->qUflowStatBitMask);
524 	const struct qmgrInfo *qi = &sc->qinfo[qId];
529 	    status = aqm_reg_read(sc, qi->qStatRegAddr);
532 	    status = (status >> qi->qStatBitsOffset) & QLOWSTATMASK;
535 	    if (aqm_reg_read(sc, IX_QMGR_QUEUPPSTAT0_OFFSET)&qi->qStat0BitMask)
537 	    if (aqm_reg_read(sc, IX_QMGR_QUEUPPSTAT1_OFFSET)&qi->qStat1BitMask)
656 	struct qmgrInfo *qi;
666 		qi = &sc->qinfo[q];
667 		if (qi->priority == pri) {
674 			    qi->intRegCheckMask;
681 		qi = &sc->qinfo[q];
682 		if (qi->priority == pri) {
689 			    qi->intRegCheckMask;
737 	struct qmgrInfo *qi;
760 		 qi = &sc->qinfo[qIndex];
761 		 if (intRegVal == qi->intRegCheckMask) {
766 		    qi->cb(qIndex, qi->cbarg);
788 			 qi = &sc->qinfo[qIndex];
791 			 if (intRegVal & qi->intRegCheckMask) {
793 			     qi->cb(qIndex, qi->cbarg);
795 			     intRegVal &= ~qi->intRegCheckMask;
817 	struct qmgrInfo *qi = &qinfo[qId];
823 		qi->statusCheckValue = IX_QMGR_Q_STATUS_E_BIT_MASK;
824 		qi->statusMask = IX_QMGR_Q_STATUS_E_BIT_MASK;
827 		qi->statusCheckValue = IX_QMGR_Q_STATUS_NE_BIT_MASK;
828 		qi->statusMask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
831 		qi->statusCheckValue = IX_QMGR_Q_STATUS_NF_BIT_MASK;
832 		qi->statusMask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
835 		qi->statusCheckValue = IX_QMGR_Q_STATUS_F_BIT_MASK;
836 		qi->statusMask = IX_QMGR_Q_STATUS_F_BIT_MASK;
839 		qi->statusCheckValue = 0;
840 		qi->statusMask = IX_QMGR_Q_STATUS_E_BIT_MASK;
843 		qi->statusCheckValue = 0;
844 		qi->statusMask = IX_QMGR_Q_STATUS_NE_BIT_MASK;
847 		qi->statusCheckValue = 0;
848 		qi->statusMask = IX_QMGR_Q_STATUS_NF_BIT_MASK;
851 		qi->statusCheckValue = 0;
852 		qi->statusMask = IX_QMGR_Q_STATUS_F_BIT_MASK;
869 	    qi->statusWordOffset = qId / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD;
871 	    qi->statusCheckValue <<= shiftVal;
872 	    qi->statusMask <<= shiftVal;
875 	    qi->statusWordOffset = 0;
879 	    qi->statusMask = 1 << (qId - IX_QMGR_MIN_QUEUPP_QID);
880 	    qi->statusCheckValue = qi->statusMask;
958 	const struct qmgrInfo *qi = &sc->qinfo[qId];
965 	     | ((toAqmBufferSize(qi->qSizeInWords) & IX_QMGR_SIZE_MASK) <<