Lines Matching refs:sc
234 npe_reg_read(struct ixpnpe_softc *sc, bus_size_t off)
236 uint32_t v = bus_space_read_4(sc->sc_iot, sc->sc_ioh, off);
237 DPRINTFn(9, sc->sc_dev, "%s(0x%lx) => 0x%x\n", __func__, off, v);
242 npe_reg_write(struct ixpnpe_softc *sc, bus_size_t off, uint32_t val)
244 DPRINTFn(9, sc->sc_dev, "%s(0x%lx, 0x%x)\n", __func__, off, val);
245 bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, val);
282 struct ixpnpe_softc *sc;
290 sc = npes[npeid];
291 if (sc != NULL) {
292 sc->sc_nrefs++;
293 return sc;
298 sc = malloc(sizeof(struct ixpnpe_softc), M_TEMP, M_WAITOK | M_ZERO);
299 sc->sc_dev = dev;
300 sc->sc_iot = sa->sc_iot;
301 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "npe driver", MTX_DEF);
302 sc->sc_npeid = npeid;
303 sc->sc_nrefs = 1;
305 sc->sc_size = config->size;
308 sc->insMemSize = config->ins_memsize;
309 sc->dataMemSize = config->data_memsize;
311 sc->insMemSize = IXP46X_NPEDL_INS_MEMSIZE_WORDS;
312 sc->dataMemSize = IXP46X_NPEDL_DATA_MEMSIZE_WORDS;
315 if (bus_space_map(sc->sc_iot, config->base, sc->sc_size, 0, &sc->sc_ioh))
322 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
324 if (sc->sc_irq == NULL)
328 bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE,
329 NULL, ixpnpe_intr, sc, &sc->sc_ih);
333 npe_reg_write(sc, IX_NPECTL,
334 npe_reg_read(sc, IX_NPECTL) | (IX_NPECTL_OFE | IX_NPECTL_OFWE));
336 npes[npeid] = sc;
338 return sc;
342 ixpnpe_detach(struct ixpnpe_softc *sc)
344 if (--sc->sc_nrefs == 0) {
345 npes[sc->sc_npeid] = NULL;
348 npe_reg_write(sc, IX_NPECTL,
349 npe_reg_read(sc, IX_NPECTL) &~ (IX_NPECTL_OFE | IX_NPECTL_OFWE));
351 bus_teardown_intr(sc->sc_dev, sc->sc_irq, sc->sc_ih);
352 bus_space_unmap(sc->sc_iot, sc->sc_ioh, sc->sc_size);
353 mtx_destroy(&sc->sc_mtx);
354 free(sc, M_TEMP);
359 ixpnpe_stopandreset(struct ixpnpe_softc *sc)
363 mtx_lock(&sc->sc_mtx);
364 error = npe_cpu_stop(sc); /* stop NPE */
366 error = npe_cpu_reset(sc); /* reset it */
368 sc->started = 0; /* mark stopped */
369 mtx_unlock(&sc->sc_mtx);
371 DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
376 ixpnpe_start_locked(struct ixpnpe_softc *sc)
380 if (!sc->started) {
381 error = npe_cpu_start(sc);
383 sc->started = 1;
387 DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
392 ixpnpe_start(struct ixpnpe_softc *sc)
396 mtx_lock(&sc->sc_mtx);
397 ret = ixpnpe_start_locked(sc);
398 mtx_unlock(&sc->sc_mtx);
403 ixpnpe_stop(struct ixpnpe_softc *sc)
407 mtx_lock(&sc->sc_mtx);
408 error = npe_cpu_stop(sc);
410 sc->started = 0;
411 mtx_unlock(&sc->sc_mtx);
413 DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
433 npe_findimage(struct ixpnpe_softc *sc,
445 DPRINTF(sc->sc_dev, "%s: off %u mark 0x%x id 0x%x size %u\n",
454 DPRINTF(sc->sc_dev, "imageId 0x%08x not found in "
465 ixpnpe_load_firmware(struct ixpnpe_softc *sc, const char *imageName,
475 DPRINTF(sc->sc_dev, "load %s, imageId 0x%08x\n", imageName, imageId);
487 error = ixpnpe_stopandreset(sc); /* stop and reset the NPE */
496 error = npe_findimage(sc, fw->data, imageId, &imageCodePtr, &imageSize);
500 device_printf(sc->sc_dev,
511 mtx_lock(&sc->sc_mtx);
512 error = npe_load_image(sc, imageCodePtr, 1 /*VERIFY*/);
514 sc->validImage = 1;
515 error = ixpnpe_start_locked(sc);
517 sc->validImage = 0;
519 sc->functionalityId = IX_NPEDL_FUNCTIONID_FROM_IMAGEID_GET(imageId);
520 mtx_unlock(&sc->sc_mtx);
523 DPRINTF(sc->sc_dev, "%s: error %d\n", __func__, error);
544 ixpnpe_init(struct ixpnpe_softc *sc)
554 if (sc->started)
562 if (!override_imageid(sc->sc_dev, "imageid", &imageid))
563 imageid = npeconfig[sc->sc_npeid];
565 error = ixpnpe_load_firmware(sc, "npe_fw", imageid);
573 device_printf(sc->sc_dev,
579 device_printf(sc->sc_dev, "cannot locate firmware "
586 if (ixpnpe_recvmsg_sync(sc, msg) != 0) {
587 device_printf(sc->sc_dev,
595 ixpnpe_getfunctionality(struct ixpnpe_softc *sc)
597 return (sc->validImage ? sc->functionalityId : 0);
601 npe_checkbits(struct ixpnpe_softc *sc, uint32_t reg, uint32_t expectedBitsSet)
605 val = npe_reg_read(sc, reg);
606 DPRINTFn(5, sc->sc_dev, "%s(0x%x, 0x%x) => 0x%x (%u)\n",
613 npe_isstopped(struct ixpnpe_softc *sc)
615 return npe_checkbits(sc,
620 npe_load_ins(struct ixpnpe_softc *sc,
628 if (npeMemAddress + blockSize > sc->insMemSize) {
629 device_printf(sc->sc_dev,
634 if (npe_ins_write(sc, npeMemAddress, bp->data[i], verify) != 0) {
635 device_printf(sc->sc_dev,
644 npe_load_data(struct ixpnpe_softc *sc,
652 if (npeMemAddress + blockSize > sc->dataMemSize) {
653 device_printf(sc->sc_dev,
658 if (npe_data_write(sc, npeMemAddress, bp->data[i], verify) != 0) {
659 device_printf(sc->sc_dev, "NPE data write failed\n");
667 npe_load_stateinfo(struct ixpnpe_softc *sc,
672 npe_cpu_step_save(sc);
688 device_printf(sc->sc_dev,
694 device_printf(sc->sc_dev,
701 device_printf(sc->sc_dev,
707 if (npe_ctx_reg_write(sc, cNum, reg, regVal, verify) != 0) {
708 device_printf(sc->sc_dev,
715 npe_cpu_step_restore(sc);
720 npe_load_image(struct ixpnpe_softc *sc,
727 if (!npe_isstopped(sc)) { /* verify NPE is stopped */
728 device_printf(sc->sc_dev,
745 error = npe_load_ins(sc,
747 DPRINTF(sc->sc_dev, "%s: inst, error %d\n",
751 error = npe_load_data(sc,
753 DPRINTF(sc->sc_dev, "%s: data, error %d\n",
757 error = npe_load_stateinfo(sc,
759 DPRINTF(sc->sc_dev, "%s: state, error %d\n",
763 device_printf(sc->sc_dev,
826 npe_cpu_reset(struct ixpnpe_softc *sc)
836 ixNpeConfigCtrlRegVal = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_CTL);
840 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_CTL,
842 DPRINTFn(2, sc->sc_dev, "%s: dis parity int, CTL => 0x%x\n",
845 npe_cpu_step_save(sc);
850 while (npe_checkbits(sc,
853 (void) npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WFIFO);
856 while (npe_checkbits(sc,
859 (void) npe_reg_read(sc, IX_NPEDL_REG_OFFSET_FIFO);
862 while (npe_checkbits(sc,
868 error = npe_cpu_step(sc, IX_NPEDL_INSTR_RD_FIFO, 0, 0);
870 DPRINTF(sc->sc_dev, "%s: cannot step (1), error %u\n",
872 npe_cpu_step_restore(sc);
881 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_MBST, IX_NPEDL_REG_RESET_MBST);
883 error = npe_cpu_step(sc, IX_NPEDL_INSTR_RESET_MBOX, 0, 0);
885 DPRINTF(sc->sc_dev, "%s: cannot step (2), error %u\n",
887 npe_cpu_step_restore(sc);
900 error = npe_physical_reg_write(sc, regAddr, 0, TRUE);
902 DPRINTF(sc->sc_dev, "%s: cannot write phy reg,"
904 npe_cpu_step_restore(sc);
919 error = npe_ctx_reg_write(sc, i, ctxtReg,
922 DPRINTF(sc->sc_dev, "%s: cannot write ctx reg,"
924 npe_cpu_step_restore(sc);
930 npe_cpu_step_restore(sc);
934 npe_ecs_reg_write(sc,
939 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT);
945 npe_reg_write(sc, regAddr, 0);
948 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_WC, 0);
956 npe_reset(sc->sc_npeid);
962 error = npe_cpu_stop(sc);
965 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_CTL,
967 DPRINTFn(2, sc->sc_dev, "%s: restore CTL => 0x%x\n",
968 __func__, npe_reg_read(sc, IX_NPEDL_REG_OFFSET_CTL));
975 npe_cpu_start(struct ixpnpe_softc *sc)
983 ecsRegVal = npe_ecs_reg_read(sc, IX_NPEDL_ECS_PRI_1_CTXT_REG_0);
985 npe_ecs_reg_write(sc, IX_NPEDL_ECS_PRI_1_CTXT_REG_0, ecsRegVal);
987 ecsRegVal = npe_ecs_reg_read(sc, IX_NPEDL_ECS_PRI_2_CTXT_REG_0);
989 npe_ecs_reg_write(sc, IX_NPEDL_ECS_PRI_2_CTXT_REG_0, ecsRegVal);
991 ecsRegVal = npe_ecs_reg_read(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0);
993 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0, ecsRegVal);
996 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
999 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_START);
1004 return npe_checkbits(sc,
1009 npe_cpu_stop(struct ixpnpe_softc *sc)
1012 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_STOP);
1015 return npe_checkbits(sc,
1035 npe_cmd_issue_write(struct ixpnpe_softc *sc,
1038 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXDATA, data);
1039 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXAD, addr);
1040 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
1044 npe_cmd_issue_read(struct ixpnpe_softc *sc, uint32_t cmd, uint32_t addr)
1049 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXAD, addr);
1050 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCTL, cmd);
1052 data = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_EXDATA);
1057 npe_ins_write(struct ixpnpe_softc *sc, uint32_t addr, uint32_t data, int verify)
1059 DPRINTFn(4, sc->sc_dev, "%s(0x%x, 0x%x)\n", __func__, addr, data);
1060 npe_cmd_issue_write(sc, IX_NPEDL_EXCTL_CMD_WR_INS_MEM, addr, data);
1068 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXDATA, ~data);
1076 rdata = npe_cmd_issue_read(sc, IX_NPEDL_EXCTL_CMD_RD_INS_MEM,
1087 npe_data_write(struct ixpnpe_softc *sc, uint32_t addr, uint32_t data, int verify)
1089 DPRINTFn(4, sc->sc_dev, "%s(0x%x, 0x%x)\n", __func__, addr, data);
1090 npe_cmd_issue_write(sc, IX_NPEDL_EXCTL_CMD_WR_DATA_MEM, addr, data);
1096 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXDATA, ~data);
1097 if (data != npe_cmd_issue_read(sc, IX_NPEDL_EXCTL_CMD_RD_DATA_MEM, addr))
1104 npe_ecs_reg_write(struct ixpnpe_softc *sc, uint32_t reg, uint32_t data)
1106 npe_cmd_issue_write(sc, IX_NPEDL_EXCTL_CMD_WR_ECS_REG, reg, data);
1110 npe_ecs_reg_read(struct ixpnpe_softc *sc, uint32_t reg)
1112 return npe_cmd_issue_read(sc, IX_NPEDL_EXCTL_CMD_RD_ECS_REG, reg);
1116 npe_issue_cmd(struct ixpnpe_softc *sc, uint32_t command)
1118 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCTL, command);
1122 npe_cpu_step_save(struct ixpnpe_softc *sc)
1126 sc->savedExecCount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_EXCT);
1127 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCT, 0);
1131 sc->savedEcsDbgCtxtReg2 = npe_ecs_reg_read(sc,
1134 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_2,
1135 (sc->savedEcsDbgCtxtReg2 | IX_NPEDL_MASK_ECS_DBG_REG_2_IF |
1140 npe_cpu_step(struct ixpnpe_softc *sc, uint32_t npeInstruction,
1152 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0, ecsDbgRegVal);
1163 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_1, ecsDbgRegVal);
1166 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
1169 npe_ecs_reg_write(sc, IX_NPEDL_ECS_INSTRUCT_REG, npeInstruction);
1172 oldWatchcount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WC);
1175 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_STEP);
1184 newWatchcount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WC);
1188 newWatchcount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WC);
1195 npe_cpu_step_restore(struct ixpnpe_softc *sc)
1198 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_0, 0);
1201 npe_issue_cmd(sc, IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE);
1204 npe_reg_write(sc, IX_NPEDL_REG_OFFSET_EXCT, sc->savedExecCount);
1207 npe_ecs_reg_write(sc, IX_NPEDL_ECS_DBG_CTXT_REG_2, sc->savedEcsDbgCtxtReg2);
1211 npe_logical_reg_read(struct ixpnpe_softc *sc,
1240 error = npe_cpu_step(sc, npeInstruction, ctxtNum,
1243 DPRINTF(sc->sc_dev, "%s(0x%x, %u, %u), cannot step, error %d\n",
1248 *regVal = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_EXDATA);
1257 npe_logical_reg_write(struct ixpnpe_softc *sc, uint32_t regAddr, uint32_t regVal,
1262 DPRINTFn(4, sc->sc_dev, "%s(0x%x, 0x%x, %u, %u)\n",
1269 error = npe_logical_reg_write(sc, regAddr,
1276 error = npe_logical_reg_write(sc,
1309 error = npe_cpu_step(sc, npeInstruction,
1313 DPRINTF(sc->sc_dev, "%s(0x%x, 0x%x, %u, %u), error %u "
1321 error = npe_logical_reg_read(sc, regAddr, regSize, ctxtNum,
1337 npe_physical_reg_write(struct ixpnpe_softc *sc,
1346 error = npe_logical_reg_write(sc, IX_NPEDL_CTXT_REG_ADDR_REGMAP,
1353 error = npe_logical_reg_write(sc, regAddr, regValue,
1360 npe_ctx_reg_write(struct ixpnpe_softc *sc, uint32_t ctxtNum,
1363 DPRINTFn(4, sc->sc_dev, "%s(%u, %u, %u)\n",
1371 uint32_t v = npe_ecs_reg_read(sc, IX_NPEDL_ECS_BG_CTXT_REG_0);
1376 npe_ecs_reg_write(sc, IX_NPEDL_ECS_BG_CTXT_REG_0, v);
1392 return npe_logical_reg_write(sc, regAccInfo[ctxtReg].regAddress,
1403 ofifo_wait(struct ixpnpe_softc *sc)
1408 if (npe_reg_read(sc, IX_NPESTAT) & IX_NPESTAT_OFNE)
1412 device_printf(sc->sc_dev, "%s: timeout, last status 0x%x\n",
1413 __func__, npe_reg_read(sc, IX_NPESTAT));
1418 getmsg(struct ixpnpe_softc *sc, uint32_t msg[2])
1420 mtx_assert(&sc->sc_mtx, MA_OWNED);
1422 if (!ofifo_wait(sc))
1424 msg[0] = npe_reg_read(sc, IX_NPEFIFO);
1425 DPRINTF(sc->sc_dev, "%s: msg0 0x%x\n", __func__, msg[0]);
1426 if (!ofifo_wait(sc))
1428 msg[1] = npe_reg_read(sc, IX_NPEFIFO);
1429 DPRINTF(sc->sc_dev, "%s: msg1 0x%x\n", __func__, msg[1]);
1436 struct ixpnpe_softc *sc = arg;
1439 mtx_lock(&sc->sc_mtx);
1440 status = npe_reg_read(sc, IX_NPESTAT);
1441 DPRINTF(sc->sc_dev, "%s: status 0x%x\n", __func__, status);
1444 device_printf(sc->sc_dev, "%s: status 0x%x\n",
1447 mtx_unlock(&sc->sc_mtx);
1454 if (getmsg(sc, sc->sc_msg) == 0)
1455 sc->sc_msgwaiting = 1;
1456 mtx_unlock(&sc->sc_mtx);
1460 ififo_wait(struct ixpnpe_softc *sc)
1465 if (npe_reg_read(sc, IX_NPESTAT) & IX_NPESTAT_IFNF)
1469 device_printf(sc->sc_dev, "%s: timeout, last status 0x%x\n",
1470 __func__, npe_reg_read(sc, IX_NPESTAT));
1475 putmsg(struct ixpnpe_softc *sc, const uint32_t msg[2])
1477 mtx_assert(&sc->sc_mtx, MA_OWNED);
1479 DPRINTF(sc->sc_dev, "%s: msg 0x%x:0x%x\n", __func__, msg[0], msg[1]);
1480 if (!ififo_wait(sc))
1482 npe_reg_write(sc, IX_NPEFIFO, msg[0]);
1483 if (!ififo_wait(sc))
1485 npe_reg_write(sc, IX_NPEFIFO, msg[1]);
1495 ixpnpe_sendandrecvmsg_sync(struct ixpnpe_softc *sc,
1500 mtx_lock(&sc->sc_mtx);
1501 error = putmsg(sc, send);
1503 error = getmsg(sc, recv);
1504 mtx_unlock(&sc->sc_mtx);
1513 ixpnpe_sendmsg_async(struct ixpnpe_softc *sc, const uint32_t msg[2])
1517 mtx_lock(&sc->sc_mtx);
1518 error = putmsg(sc, msg);
1519 mtx_unlock(&sc->sc_mtx);
1525 recvmsg_locked(struct ixpnpe_softc *sc, uint32_t msg[2])
1527 mtx_assert(&sc->sc_mtx, MA_OWNED);
1529 DPRINTF(sc->sc_dev, "%s: msgwaiting %d\n", __func__, sc->sc_msgwaiting);
1530 if (sc->sc_msgwaiting) {
1531 msg[0] = sc->sc_msg[0];
1532 msg[1] = sc->sc_msg[1];
1533 sc->sc_msgwaiting = 0;
1545 ixpnpe_recvmsg_async(struct ixpnpe_softc *sc, uint32_t msg[2])
1549 mtx_lock(&sc->sc_mtx);
1550 error = recvmsg_locked(sc, msg);
1551 mtx_unlock(&sc->sc_mtx);
1561 ixpnpe_recvmsg_sync(struct ixpnpe_softc *sc, uint32_t msg[2])
1565 mtx_lock(&sc->sc_mtx);
1566 error = recvmsg_locked(sc, msg);
1568 error = getmsg(sc, msg);
1569 mtx_unlock(&sc->sc_mtx);