xscale/i8134x/i81342_pci.c

60 	struct i81342_pci_softc *sc;
62 	sc = device_get_softc(dev);
65 		sc->sc_is_atux = 1;
68 		sc->sc_is_atux = 0;
80 	struct i81342_pci_softc *sc;
86 	sc = device_get_softc(dev);
88 	sc->sc_atu_sh = sc->sc_is_atux ? parent_sc->sc_atux_sh :
90 	sc->sc_st = parent_sc->sc_st;
91 	if (bus_space_read_4(sc->sc_st, parent_sc->sc_sh, IOP34X_ESSTSR0)
93 		if (sc->sc_is_atux)
98 		if (sc->sc_is_atux)
103 	i81342_io_bs_init(&sc->sc_pciio, sc);
104 	i81342_mem_bs_init(&sc->sc_pcimem, sc);
105 	i81342_sdram_bounds(sc->sc_st, IOP34X_VADDR, &memstart, &memsize);
106 	if (sc->sc_is_atux) {
107 		reg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR);
109 			bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR,
115 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR0, 0);
116 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR0, 0);
117 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0, 0);
120 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR1,
123 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR1, 0);
124 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1,
126 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR1, memstart);
127 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUTVR1, 0);
129 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR2, 0);
130 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR2, 0);
131 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2, 0);
134 	if (sc->sc_is_atux)
135 		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OIOBAR,
138 		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OIOBAR,
142 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR0, 0);
143 	if (sc->sc_is_atux)
144 		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR1,
148 		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR1,
151 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMWTVR1, 0);
152 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR2, 0);
153 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR3, 0);
156 	reg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_CR);
157 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_CR,
160 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR,
161 	    bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR) & ATUX_ISR_ERRMSK);
166 	if (sc->sc_is_atux) {
167 		busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
170 		busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR);
173 	reg = bus_space_read_2(sc->sc_st, sc->sc_atu_sh, ATU_CMD);
176 	bus_space_write_2(sc->sc_st, sc->sc_atu_sh, ATU_CMD, reg);
177 	sc->sc_busno = busno;
179 	sc->sc_io_rman.rm_type = RMAN_ARRAY;
180 	sc->sc_io_rman.rm_descr = "I81342 PCI I/O Ports";
181 	if (rman_init(&sc->sc_io_rman) != 0 ||
182 		rman_manage_region(&sc->sc_io_rman,
183 		sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
185 		(sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
189 	sc->sc_mem_rman.rm_type = RMAN_ARRAY;
190 	sc->sc_mem_rman.rm_descr = "I81342 PCI Memory";
191 	if (rman_init(&sc->sc_mem_rman) != 0 ||
192 	    rman_manage_region(&sc->sc_mem_rman,
196 	sc->sc_irq_rman.rm_type = RMAN_ARRAY;
197 	sc->sc_irq_rman.rm_descr = "i81342 PCI IRQs";
198 	if (sc->sc_is_atux) {
199 		if (rman_init(&sc->sc_irq_rman) != 0 ||
200 		    rman_manage_region(&sc->sc_irq_rman, ICU_INT_XINT0,
204 		if (rman_init(&sc->sc_irq_rman) != 0 ||
205 		    rman_manage_region(&sc->sc_irq_rman, ICU_INT_ATUE_MA,
210 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR,
211 	    bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR) & ATUX_ISR_ERRMSK);
224 i81342_pci_conf_setup(struct i81342_pci_softc *sc, int bus, int slot, int func,
229 	if (sc->sc_is_atux) {
230 		busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR);
233 		busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR);
239 	if (sc->sc_is_atux) {
257 	struct i81342_pci_softc *sc = device_get_softc(dev);
264 	i81342_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr);
265 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, sc->sc_is_atux ?
267 	if (sc->sc_is_atux)
268 		va = sc->sc_atu_sh + ATUX_OCCDR;
270 		va = sc->sc_atu_sh + ATUE_OCCDR;
286 		isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR);
287 		if (sc->sc_is_atux)
291 		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR, isr);
302 	struct i81342_pci_softc *sc = device_get_softc(dev);
306 	i81342_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr);
307 	bus_space_write_4(sc->sc_st, sc->sc_atu_sh, sc->sc_is_atux ?
309 	va = sc->sc_is_atux ? ATUX_OCCDR : ATUE_OCCDR;
312 		bus_space_write_1(sc->sc_st, sc->sc_atu_sh, va + (reg & 3)
316 		bus_space_write_2(sc->sc_st, sc->sc_atu_sh, va + (reg & 3)
320 		bus_space_write_4(sc->sc_st, sc->sc_atu_sh, va, data);
333 	struct i81342_pci_softc *sc = device_get_softc(bus);
341 		rm = &sc->sc_irq_rman;
344 		rm = &sc->sc_mem_rman;
345 		bt = &sc->sc_pcimem;
349 		rm = &sc->sc_io_rman;
350 		bt = &sc->sc_pciio;
351 		bh = sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
422 	struct i81342_pci_softc *sc;
426 	sc = device_get_softc(pcib);
428 	if (sc->sc_is_atux) {
474 	    sc->sc_is_atux ? "PCI-X" : "PCIe", device, pin);
481 	struct i81342_pci_softc *sc = device_get_softc(dev);
487 		*result = sc->sc_busno;
497 	struct i81342_pci_softc * sc = device_get_softc(dev);
503 		sc->sc_busno = result;