arm/ti/ti_edma3.c

125 #define ti_edma3_cc_rd_4(reg)		bus_read_4(ti_edma3_sc->mem_res[0], reg)
126 #define ti_edma3_cc_wr_4(reg, val)	bus_write_4(ti_edma3_sc->mem_res[0], reg, val)
159 	uint32_t reg;
186 	reg = ti_edma3_cc_rd_4(TI_EDMA3CC_PID);
188 	device_printf(dev, "EDMA revision %08x\n", reg);
243 	uint32_t reg;
269 		reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(i>>3));
270 		reg &= TI_EDMA3CC_DMAQNUM_CLR(i);
271 		reg |= TI_EDMA3CC_DMAQNUM_SET(i, eqn);
272 		ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(i>>3), reg);
280 		reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM);
281 		reg &= TI_EDMA3CC_QDMAQNUM_CLR(i);
282 		reg |= TI_EDMA3CC_QDMAQNUM_SET(i, eqn);
283 		ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg);
291 	uint32_t reg;
308 	uint32_t reg;
315 		reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAE(0));
316 		reg |= (0x01 << ch);
317 		ti_edma3_cc_wr_4(TI_EDMA3CC_DRAE(0), reg);
319 		reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DRAEH(0));
320 		reg |= (0x01 << (ch - 32));
321 		ti_edma3_cc_wr_4(TI_EDMA3CC_DRAEH(0), reg);
325 	reg = ti_edma3_cc_rd_4(TI_EDMA3CC_DMAQNUM(ch >> 3));
326 	reg &= TI_EDMA3CC_DMAQNUM_CLR(ch);
327 	reg |= TI_EDMA3CC_DMAQNUM_SET((ch), eqn);
328 	ti_edma3_cc_wr_4(TI_EDMA3CC_DMAQNUM(ch >> 3), reg);
331 	reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));
332 	reg &= TI_EDMA3CC_OPT_TCC_CLR;
333 	reg |= TI_EDMA3CC_OPT_TCC_SET(ch);
334 	ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);
342 	uint32_t reg;
348 	reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QRAE(0));
349 	reg |= (0x01 << ch);
350 	ti_edma3_cc_wr_4(TI_EDMA3CC_QRAE(0), reg);
353 	reg = ti_edma3_cc_rd_4(TI_EDMA3CC_QDMAQNUM);
354 	reg |= TI_EDMA3CC_QDMAQNUM_SET(ch, eqn);
355 	ti_edma3_cc_wr_4(TI_EDMA3CC_QDMAQNUM, reg);
358 	reg = ti_edma3_cc_rd_4(TI_EDMA3CC_OPT(ch));
359 	reg &= TI_EDMA3CC_OPT_TCC_CLR;
360 	reg |= TI_EDMA3CC_OPT_TCC_SET(ch);
361 	ti_edma3_cc_wr_4(TI_EDMA3CC_OPT(ch), reg);