nvidia/drm2/tegra_dc.c

296 	uint32_t val;
298 	val = (src - 1) << 12 ; /* 4.12 fixed float */
299 	val /= (dst - 1);
300 	if (val  > (maxscale << 12))
301 		val = maxscale << 12;
302 	return val;
362 	uint32_t val;
428 	val = WINDOW_A_SELECT << index;
429 	WR4(sc, DC_CMD_DISPLAY_WINDOW_HEADER, val);
462 	val = win->surface_kind;
464 		val |= SURFACE_KIND_BLOCK_HEIGHT(win->block_height);
465 	WR4(sc, DC_WINBUF_SURFACE_KIND, val);
479 	val = WIN_ENABLE;
481 		val |= CSC_ENABLE;
483 		val |= COLOR_EXPAND;
485 		val |= V_DIRECTION;
487 		val |= H_DIRECTION;
489 		val |= SCAN_COLUMN;
490 	WR4(sc, DC_WINC_WIN_OPTIONS, val);
555 	uint32_t val, idx;
569 	val = RD4(sc, DC_WINC_WIN_OPTIONS);
570 	val &= ~WIN_ENABLE;
571 	WR4(sc, DC_WINC_WIN_OPTIONS, val);
746 	uint32_t val;
760 	val = RD4(sc, DC_CMD_DISPLAY_COMMAND);
761 	val |= DISPLAY_CTRL_MODE(CTRL_MODE_C_DISPLAY);
762 	WR4(sc, DC_CMD_DISPLAY_COMMAND, val);
778 	uint32_t val;
785 	val = RD4(sc, DC_CMD_INT_MASK);
786 	val |= FRAME_END_INT;
787 	WR4(sc, DC_CMD_INT_MASK, val);
789 	val = RD4(sc, DC_CMD_INT_ENABLE);
790 	val |= FRAME_END_INT;
791 	WR4(sc, DC_CMD_INT_ENABLE, val);
848 	uint32_t val;
854 	val = RD4(sc, DC_CMD_INT_MASK);
855 	val |= VBLANK_INT;
856 	WR4(sc, DC_CMD_INT_MASK, val);
865 	uint32_t val;
871 	val = RD4(sc, DC_CMD_INT_MASK);
872 	val &= ~VBLANK_INT;
873 	WR4(sc, DC_CMD_INT_MASK, val);
986 	uint32_t val, *src, *dst;
996 		val = CURSOR_SIZE(C32x32);
999 		val = CURSOR_SIZE(C64x64);
1002 		val = CURSOR_SIZE(C128x128);
1005 		val = CURSOR_SIZE(C256x256);
1037 		val |= CURSOR_CLIP(CC_DISPLAY);
1038 		val |= CURSOR_START_ADDR(crtc->cursor_pbase);
1039 		WR4(sc, DC_DISP_CURSOR_START_ADDR, val);
1041 		val = RD4(sc, DC_DISP_BLEND_CURSOR_CONTROL);
1042 		val &= ~CURSOR_DST_BLEND_FACTOR_SELECT(~0);
1043 		val &= ~CURSOR_SRC_BLEND_FACTOR_SELECT(~0);
1044 		val |= CURSOR_MODE_SELECT;
1045 		val |= CURSOR_DST_BLEND_FACTOR_SELECT(DST_NEG_K1_TIMES_SRC);
1046 		val |= CURSOR_SRC_BLEND_FACTOR_SELECT(SRC_BLEND_K1_TIMES_SRC);
1047 		val |= CURSOR_ALPHA(~0);
1048 		WR4(sc, DC_DISP_BLEND_CURSOR_CONTROL, val);
1050 		val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS);
1051 		val |= CURSOR_ENABLE;
1052 		WR4(sc, DC_DISP_DISP_WIN_OPTIONS, val);
1054 		val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS);
1055 		val &= ~CURSOR_ENABLE;
1056 		WR4(sc, DC_DISP_DISP_WIN_OPTIONS, val);
1129 	uint32_t val;
1134 	val = enable ? CTRL_MODE_C_DISPLAY: CTRL_MODE_STOP;
1135 	WR4(sc, DC_CMD_DISPLAY_COMMAND, DISPLAY_CTRL_MODE(val));
1146 	uint32_t val;
1150 	val = RD4(sc, DC_DISP_DISP_WIN_OPTIONS);
1152 		val |= HDMI_ENABLE;
1154 		val &= ~HDMI_ENABLE;
1155 	WR4(sc, DC_DISP_DISP_WIN_OPTIONS, val);