freescale/imx/imx_gpt.c

151 	struct imx_gpt_softc *sc;
155 	sc = device_get_softc(dev);
157 	if (bus_alloc_resources(dev, imx_gpt_spec, sc->res)) {
162 	sc->sc_dev = dev;
163 	sc->sc_iot = rman_get_bustag(sc->res[0]);
164 	sc->sc_ioh = rman_get_bushandle(sc->res[0]);
171 	sc->sc_clksrc = GPT_CR_CLKSRC_IPG;
175 	switch (sc->sc_clksrc) {
193 		    sc->sc_clksrc);
203 	WRITE4(sc, IMX_GPT_CR, 0);
204 	WRITE4(sc, IMX_GPT_IR, 0);
208 	    sc->sc_clksrc |	/* Use selected clock */
214 	WRITE4(sc, IMX_GPT_CR, ctlreg);
224 	WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_SWR);
225 	while (READ4(sc, IMX_GPT_CR) & GPT_CR_SWR)
231 		sc->clkfreq = basefreq;
234 		sc->clkfreq = basefreq / prescale;
237 	WRITE4(sc, IMX_GPT_PR, prescale);
240 	WRITE4(sc, IMX_GPT_SR, GPT_IR_ALL);
243 	WRITE4(sc, IMX_GPT_CR, ctlreg | GPT_CR_EN);
247 		    sc->clkfreq / 1000, basefreq, READ4(sc, IMX_GPT_CR), READ4(sc, IMX_GPT_PR));
250 	err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_CLK, imx_gpt_intr,
251 	    NULL, sc, &sc->sc_ih);
253 		bus_release_resources(dev, imx_gpt_spec, sc->res);
266 	t1 = READ4(sc, IMX_GPT_CNT);
267 	WRITE4(sc, IMX_GPT_OCR3, 0);
268 	t2 = READ4(sc, IMX_GPT_CNT);
272 	sc->et.et_name = "iMXGPT";
273 	sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
274 	sc->et.et_quality = 800;
275 	sc->et.et_frequency = sc->clkfreq;
276 	sc->et.et_min_period = ((uint64_t)setup_ticks << 32) / sc->clkfreq;
277 	sc->et.et_max_period = ((uint64_t)0xfffffffe  << 32) / sc->clkfreq;
278 	sc->et.et_start = imx_gpt_timer_start;
279 	sc->et.et_stop = imx_gpt_timer_stop;
280 	sc->et.et_priv = sc;
281 	et_register(&sc->et);
284 	imx_gpt_timecounter.tc_frequency = sc->clkfreq;
289 	    imx_gpt_sc = sc;
297 	struct imx_gpt_softc *sc;
300 	sc = (struct imx_gpt_softc *)et->et_priv;
303 		sc->sc_period = ((uint32_t)et->et_frequency * period) >> 32;
305 		WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) + sc->sc_period);
307 		sc->ir_reg |= GPT_IR_OF2;
308 		WRITE4(sc, IMX_GPT_IR, sc->ir_reg);
312 		if ((sc->ir_reg & GPT_IR_OF3) == 0) {
313 			sc->ir_reg |= GPT_IR_OF3;
314 			WRITE4(sc, IMX_GPT_IR, sc->ir_reg);
320 		WRITE4(sc, IMX_GPT_OCR3, READ4(sc, IMX_GPT_CNT) + ticks);
332 	struct imx_gpt_softc *sc;
334 	sc = (struct imx_gpt_softc *)et->et_priv;
337 	sc->ir_reg &= ~(GPT_IR_OF2 | GPT_IR_OF3);
338 	WRITE4(sc, IMX_GPT_IR, sc->ir_reg);
339 	WRITE4(sc, IMX_GPT_SR, GPT_IR_OF2 | GPT_IR_OF3);
340 	sc->sc_period = 0;
348 	struct imx_gpt_softc *sc;
351 	sc = (struct imx_gpt_softc *)arg;
353 	status = READ4(sc, IMX_GPT_SR);
361 	WRITE4(sc, IMX_GPT_SR, status);
365 		if (sc->et.et_active) {
366 			sc->et.et_event_cb(&sc->et, sc->et.et_arg);
372 		if (sc->et.et_active)
373 			sc->et.et_event_cb(&sc->et, sc->et.et_arg);
374 		if (sc->sc_period != 0)
375 			WRITE4(sc, IMX_GPT_OCR2, READ4(sc, IMX_GPT_CNT) +
376 			    sc->sc_period);