freescale/imx/imx_epit.c

140 RD4(struct epit_softc *sc, bus_size_t offset)
143 	return (bus_read_4(sc->memres, offset));
147 WR4(struct epit_softc *sc, bus_size_t offset, uint32_t value)
150 	bus_write_4(sc->memres, offset, value);
154 WR4B(struct epit_softc *sc, bus_size_t offset, uint32_t value)
157 	bus_write_4(sc->memres, offset, value);
158 	bus_barrier(sc->memres, offset, 4, BUS_SPACE_BARRIER_WRITE);
162 epit_read_counter(struct epit_softc *sc)
169 	return (0xffffffff - RD4(sc, EPIT_CNR));
175 	struct epit_softc *sc = arg;
186 	ticks = 1 + ((uint64_t)usec * sc->clkfreq) / 1000000;
187 	curcnt = startcnt = epit_read_counter(sc);
190 		curcnt = epit_read_counter(sc);
204 epit_tc_attach(struct epit_softc *sc)
208 	WR4(sc, EPIT_LR, 0xffffffff);
209 	WR4(sc, EPIT_CR, sc->ctlreg | EPIT_CR_EN);
212 	sc->tc.tc_name          = "EPIT";
213 	sc->tc.tc_quality       = 1000;
214 	sc->tc.tc_frequency     = sc->clkfreq;
215 	sc->tc.tc_counter_mask  = 0xffffffff;
216 	sc->tc.tc_get_timecount = epit_tc_get_timecount;
217 	sc->tc.tc_priv          = sc;
218 	tc_init(&sc->tc);
222 	arm_set_delay(epit_do_delay, sc);
224 	epit_sc = sc;
232 	struct epit_softc *sc;
235 	sc = (struct epit_softc *)et->et_priv;
242 	WR4(sc, EPIT_CR, sc->ctlreg);
243 	WR4(sc, EPIT_SR, EPIT_SR_OCIF);
245 		sc->oneshot = false;
248 		sc->oneshot = true;
255 	WR4(sc, EPIT_LR, ticks);
256 	WR4B(sc, EPIT_CR, sc->ctlreg | EPIT_CR_EN);
264 	struct epit_softc *sc;
266 	sc = (struct epit_softc *)et->et_priv;
269 	WR4(sc, EPIT_CR, sc->ctlreg);
270 	WR4B(sc, EPIT_SR, EPIT_SR_OCIF);
278 	struct epit_softc *sc;
281 	sc = arg;
293 	if (sc->oneshot)
294 		WR4(sc, EPIT_CR, sc->ctlreg);
296 	status = RD4(sc, EPIT_SR);
297 	WR4B(sc, EPIT_SR, status);
302 	if (sc->et.et_active)
303 		sc->et.et_event_cb(&sc->et, sc->et.et_arg);
309 epit_et_attach(struct epit_softc *sc)
314 	sc->intres = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid,
316 	if (sc->intres == NULL) {
317 		device_printf(sc->dev, "could not allocate interrupt\n");
321 	err = bus_setup_intr(sc->dev, sc->intres, INTR_TYPE_CLK | INTR_MPSAFE,
322 	    epit_intr, NULL, sc, &sc->inthandle);
324 		device_printf(sc->dev, "unable to setup the irq handler\n");
329 	sc->ctlreg |= EPIT_CR_OCIEN;
332 	sc->et.et_name = "EPIT";
333 	sc->et.et_flags = ET_FLAGS_ONESHOT | ET_FLAGS_PERIODIC;
334 	sc->et.et_quality = 1000;
335 	sc->et.et_frequency = sc->clkfreq;
336 	sc->et.et_min_period = ((uint64_t)ET_MIN_TICKS  << 32) / sc->clkfreq;
337 	sc->et.et_max_period = ((uint64_t)ET_MAX_TICKS  << 32) / sc->clkfreq;
338 	sc->et.et_start = epit_et_start;
339 	sc->et.et_stop = epit_et_stop;
340 	sc->et.et_priv = sc;
341 	et_register(&sc->et);
418 	struct epit_softc *sc;
422 	sc = device_get_softc(dev);
423 	sc->dev = dev;
426 	sc->memres = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid,
428 	if (sc->memres == NULL) {
429 		device_printf(sc->dev, "could not allocate registers\n");
444 		sc->clkfreq = imx_ccm_ipg_hz();
447 		sc->clkfreq = imx_ccm_perclk_hz();
450 		sc->clkfreq = 32768;
458 	WR4(sc, EPIT_CR, 0);
460 	sc->ctlreg =
468 	WR4B(sc, EPIT_CR, sc->ctlreg | EPIT_CR_SWR);
469 	while (RD4(sc, EPIT_CR) & EPIT_CR_SWR)
475 	if (device_get_unit(sc->dev) == 0)
476 		err = epit_tc_attach(sc);
478 		err = epit_et_attach(sc);