freescale/imx/imx6_ipu.c

387 	struct videomode 	*sc_mode;
680 	    sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_NONE);
686 	    sc->sc_mode->htotal - 1, DI_SYNC_CLK, 0, DI_SYNC_CLK);
689 	    0, MODE_HSW(sc->sc_mode) * 2);
693 	    sc->sc_mode->vtotal - 1, DI_SYNC_COUNTER(DI_COUNTER_INT_HSYNC),
698 	    0, MODE_VSW(sc->sc_mode) * 2);
701 	IPU_WRITE4(sc, di_scr_conf, sc->sc_mode->vtotal - 1);
708 	    MODE_VSW(sc->sc_mode) + MODE_VFP(sc->sc_mode), DI_SYNC_COUNTER(DI_COUNTER_HSYNC));
710 	    sc->sc_mode->vdisplay, DI_SYNC_COUNTER(DI_COUNTER_VSYNC),
714 	    0, DI_SYNC_CLK, MODE_HSW(sc->sc_mode) + MODE_HFP(sc->sc_mode), DI_SYNC_CLK);
716 	    sc->sc_mode->hdisplay, DI_SYNC_COUNTER(DI_COUNTER_AD_0),
729 	if (sc->sc_mode->flags & VID_NHSYNC)
734 	if (sc->sc_mode->flags & VID_NVSYNC)
756 	IPU_WRITE4(sc, DC_DISP_CONF2(di), sc->sc_mode->hdisplay);
873 	stride = sc->sc_mode->hdisplay * MODE_BPP / 8;
878 	CH_PARAM_SET_FW(&param, sc->sc_mode->hdisplay - 1);
879 	CH_PARAM_SET_FH(&param, sc->sc_mode->vdisplay - 1);
986 	dma_size = round_page(sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * (MODE_BPP / 8));
1021 	sc->sc_fb_size = sc->sc_mode->hdisplay * sc->sc_mode->vdisplay * MODE_BPP / 8;
1045 	sc->sc_fb_info.fb_stride = sc->sc_mode->hdisplay * MODE_BPP / 8;
1046 	sc->sc_fb_info.fb_width = sc->sc_mode->hdisplay;
1047 	sc->sc_fb_info.fb_height = sc->sc_mode->vdisplay;
1094 	sc->sc_mode = &mode1024x768;
1097 	HDMI_SET_VIDEOMODE(hdmi_dev, sc->sc_mode);