freescale/imx/imx6_hdmi.c

80 RD1(struct imx_hdmi_softc *sc, bus_size_t off)
83 	return (bus_read_1(sc->sc_mem_res, off));
87 WR1(struct imx_hdmi_softc *sc, bus_size_t off, uint8_t val)
90 	bus_write_1(sc->sc_mem_res, off, val);
94 imx_hdmi_phy_wait_i2c_done(struct imx_hdmi_softc *sc, int msec)
98 	val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) &
105 		val = RD1(sc, HDMI_IH_I2CMPHY_STAT0) &
111 imx_hdmi_phy_i2c_write(struct imx_hdmi_softc *sc, unsigned short data,
116 	WR1(sc, HDMI_IH_I2CMPHY_STAT0,
118 	WR1(sc, HDMI_PHY_I2CM_ADDRESS_ADDR, addr);
119 	WR1(sc, HDMI_PHY_I2CM_DATAO_1_ADDR, ((data >> 8) & 0xff));
120 	WR1(sc, HDMI_PHY_I2CM_DATAO_0_ADDR, ((data >> 0) & 0xff));
121 	WR1(sc, HDMI_PHY_I2CM_OPERATION_ADDR, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE);
122 	imx_hdmi_phy_wait_i2c_done(sc, 1000);
126 imx_hdmi_disable_overflow_interrupts(struct imx_hdmi_softc *sc)
128 	WR1(sc, HDMI_IH_MUTE_FC_STAT2, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK);
129 	WR1(sc, HDMI_FC_MASK2,
134 imx_hdmi_av_composer(struct imx_hdmi_softc *sc)
141 	inv_val = ((sc->sc_mode.flags & VID_NVSYNC) ?
145 	inv_val |= ((sc->sc_mode.flags & VID_NHSYNC) ?
151 	inv_val |= ((sc->sc_mode.flags & VID_INTERLACE) ?
155 	inv_val |= ((sc->sc_mode.flags & VID_INTERLACE) ?
165 	WR1(sc, HDMI_FC_INVIDCONF, inv_val);
168 	WR1(sc, HDMI_FC_INHACTV1, sc->sc_mode.hdisplay >> 8);
169 	WR1(sc, HDMI_FC_INHACTV0, sc->sc_mode.hdisplay);
172 	WR1(sc, HDMI_FC_INVACTV1, sc->sc_mode.vdisplay >> 8);
173 	WR1(sc, HDMI_FC_INVACTV0, sc->sc_mode.vdisplay);
176 	hblank = sc->sc_mode.htotal - sc->sc_mode.hdisplay;
177 	WR1(sc, HDMI_FC_INHBLANK1, hblank >> 8);
178 	WR1(sc, HDMI_FC_INHBLANK0, hblank);
181 	vblank = sc->sc_mode.vtotal - sc->sc_mode.vdisplay;
182 	WR1(sc, HDMI_FC_INVBLANK, vblank);
185 	hbp = sc->sc_mode.htotal - sc->sc_mode.hsync_end;
186 	WR1(sc, HDMI_FC_HSYNCINDELAY1, hbp >> 8);
187 	WR1(sc, HDMI_FC_HSYNCINDELAY0, hbp);
190 	vbp = sc->sc_mode.vtotal - sc->sc_mode.vsync_end;
191 	WR1(sc, HDMI_FC_VSYNCINDELAY, vbp);
193 	hsync_len = (sc->sc_mode.hsync_end - sc->sc_mode.hsync_start);
195 	WR1(sc, HDMI_FC_HSYNCINWIDTH1, hsync_len >> 8);
196 	WR1(sc, HDMI_FC_HSYNCINWIDTH0, hsync_len);
199 	WR1(sc, HDMI_FC_VSYNCINWIDTH, (sc->sc_mode.vsync_end - sc->sc_mode.vsync_start));
203 imx_hdmi_phy_enable_power(struct imx_hdmi_softc *sc, uint8_t enable)
207 	reg = RD1(sc, HDMI_PHY_CONF0);
210 	WR1(sc, HDMI_PHY_CONF0, reg);
214 imx_hdmi_phy_enable_tmds(struct imx_hdmi_softc *sc, uint8_t enable)
218 	reg = RD1(sc, HDMI_PHY_CONF0);
221 	WR1(sc, HDMI_PHY_CONF0, reg);
225 imx_hdmi_phy_gen2_pddq(struct imx_hdmi_softc *sc, uint8_t enable)
229 	reg = RD1(sc, HDMI_PHY_CONF0);
232 	WR1(sc, HDMI_PHY_CONF0, reg);
236 imx_hdmi_phy_gen2_txpwron(struct imx_hdmi_softc *sc, uint8_t enable)
240 	reg = RD1(sc, HDMI_PHY_CONF0);
243 	WR1(sc, HDMI_PHY_CONF0, reg);
247 imx_hdmi_phy_sel_data_en_pol(struct imx_hdmi_softc *sc, uint8_t enable)
251 	reg = RD1(sc, HDMI_PHY_CONF0);
254 	WR1(sc, HDMI_PHY_CONF0, reg);
258 imx_hdmi_phy_sel_interface_control(struct imx_hdmi_softc *sc, uint8_t enable)
262 	reg = RD1(sc, HDMI_PHY_CONF0);
265 	WR1(sc, HDMI_PHY_CONF0, reg);
269 imx_hdmi_phy_test_clear(struct imx_hdmi_softc *sc, unsigned char bit)
273 	val = RD1(sc, HDMI_PHY_TST0);
277 	WR1(sc, HDMI_PHY_TST0, val);
281 imx_hdmi_clear_overflow(struct imx_hdmi_softc *sc)
287 	WR1(sc, HDMI_MC_SWRSTZ, (uint8_t)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ);
289 	val = RD1(sc, HDMI_FC_INVIDCONF);
292 		WR1(sc, HDMI_FC_INVIDCONF, val);
296 imx_hdmi_phy_configure(struct imx_hdmi_softc *sc)
301 	WR1(sc, HDMI_MC_FLOWCTRL, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS);
304 	imx_hdmi_phy_gen2_txpwron(sc, 0);
307 	imx_hdmi_phy_gen2_pddq(sc, 1);
310 	WR1(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_DEASSERT);
311 	WR1(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_ASSERT);
313 	WR1(sc, HDMI_MC_HEACPHY_RST, HDMI_MC_HEACPHY_RST_ASSERT);
315 	imx_hdmi_phy_test_clear(sc, 1);
316 	WR1(sc, HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);
317 	imx_hdmi_phy_test_clear(sc, 0);
327 	if (sc->sc_mode.dot_clock*1000 <= 45250000) {
328 		imx_hdmi_phy_i2c_write(sc, CPCE_CTRL_45_25, HDMI_PHY_I2C_CPCE_CTRL);
329 		imx_hdmi_phy_i2c_write(sc, GMPCTRL_45_25, HDMI_PHY_I2C_GMPCTRL);
330 	} else if (sc->sc_mode.dot_clock*1000 <= 92500000) {
331 		imx_hdmi_phy_i2c_write(sc, CPCE_CTRL_92_50, HDMI_PHY_I2C_CPCE_CTRL);
332 		imx_hdmi_phy_i2c_write(sc, GMPCTRL_92_50, HDMI_PHY_I2C_GMPCTRL);
333 	} else if (sc->sc_mode.dot_clock*1000 <= 185000000) {
334 		imx_hdmi_phy_i2c_write(sc, CPCE_CTRL_185, HDMI_PHY_I2C_CPCE_CTRL);
335 		imx_hdmi_phy_i2c_write(sc, GMPCTRL_185, HDMI_PHY_I2C_GMPCTRL);
337 		imx_hdmi_phy_i2c_write(sc, CPCE_CTRL_370, HDMI_PHY_I2C_CPCE_CTRL);
338 		imx_hdmi_phy_i2c_write(sc, GMPCTRL_370, HDMI_PHY_I2C_GMPCTRL);
345 	if (sc->sc_mode.dot_clock*1000 <= 54000000) {
346 		imx_hdmi_phy_i2c_write(sc, 0x091c, HDMI_PHY_I2C_CURRCTRL);
347 	} else if (sc->sc_mode.dot_clock*1000 <= 58400000) {
348 		imx_hdmi_phy_i2c_write(sc, 0x091c, HDMI_PHY_I2C_CURRCTRL);
349 	} else if (sc->sc_mode.dot_clock*1000 <= 72000000) {
350 		imx_hdmi_phy_i2c_write(sc, 0x06dc, HDMI_PHY_I2C_CURRCTRL);
351 	} else if (sc->sc_mode.dot_clock*1000 <= 74250000) {
352 		imx_hdmi_phy_i2c_write(sc, 0x06dc, HDMI_PHY_I2C_CURRCTRL);
353 	} else if (sc->sc_mode.dot_clock*1000 <= 118800000) {
354 		imx_hdmi_phy_i2c_write(sc, 0x091c, HDMI_PHY_I2C_CURRCTRL);
355 	} else if (sc->sc_mode.dot_clock*1000 <= 216000000) {
356 		imx_hdmi_phy_i2c_write(sc, 0x06dc, HDMI_PHY_I2C_CURRCTRL);
361 	imx_hdmi_phy_i2c_write(sc, 0x0000, HDMI_PHY_I2C_PLLPHBYCTRL);
362 	imx_hdmi_phy_i2c_write(sc, MSM_CTRL_FB_CLK, HDMI_PHY_I2C_MSM_CTRL);
364 	imx_hdmi_phy_i2c_write(sc, TXTERM_133, HDMI_PHY_I2C_TXTERM);
367 	imx_hdmi_phy_i2c_write(sc, CKCALCTRL_OVERRIDE, HDMI_PHY_I2C_CKCALCTRL);
369 	if (sc->sc_mode.dot_clock*1000 > 148500000) {
370 		imx_hdmi_phy_i2c_write(sc,CKSYMTXCTRL_OVERRIDE | CKSYMTXCTRL_TX_SYMON |
372 		imx_hdmi_phy_i2c_write(sc, VLEVCTRL_TX_LVL(9) | VLEVCTRL_CK_LVL(9),
375 		imx_hdmi_phy_i2c_write(sc,CKSYMTXCTRL_OVERRIDE | CKSYMTXCTRL_TX_SYMON |
377 		imx_hdmi_phy_i2c_write(sc, VLEVCTRL_TX_LVL(13) | VLEVCTRL_CK_LVL(13),
381 	imx_hdmi_phy_enable_power(sc, 1);
384 	imx_hdmi_phy_enable_tmds(sc, 0);
385 	imx_hdmi_phy_enable_tmds(sc, 1);
388 	imx_hdmi_phy_gen2_txpwron(sc, 1);
389 	imx_hdmi_phy_gen2_pddq(sc, 0);
393 	val = RD1(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
397 			device_printf(sc->sc_dev, "PHY PLL not locked\n");
400 		val = RD1(sc, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
407 imx_hdmi_phy_init(struct imx_hdmi_softc *sc)
413 		imx_hdmi_phy_sel_data_en_pol(sc, 1);
414 		imx_hdmi_phy_sel_interface_control(sc, 0);
415 		imx_hdmi_phy_enable_tmds(sc, 0);
416 		imx_hdmi_phy_enable_power(sc, 0);
419 		imx_hdmi_phy_configure(sc);
424 imx_hdmi_enable_video_path(struct imx_hdmi_softc *sc)
432 	WR1(sc, HDMI_FC_CTRLDUR, 12);
433 	WR1(sc, HDMI_FC_EXCTRLDUR, 32);
434 	WR1(sc, HDMI_FC_EXCTRLSPAC, 1);
440 	WR1(sc, HDMI_FC_CH0PREAM, 0x0B);
441 	WR1(sc, HDMI_FC_CH1PREAM, 0x16);
442 	WR1(sc, HDMI_FC_CH2PREAM, 0x21);
445 	clkdis = RD1(sc, HDMI_MC_CLKDIS) & HDMI_MC_CLKDIS_CECCLK_DISABLE;
450 	WR1(sc, HDMI_MC_CLKDIS, clkdis);
453 	WR1(sc, HDMI_MC_CLKDIS, clkdis);
457 imx_hdmi_video_packetize(struct imx_hdmi_softc *sc)
470 	WR1(sc, HDMI_VP_PR_CD, val);
472 	val = RD1(sc, HDMI_VP_STUFF);
475 	WR1(sc, HDMI_VP_STUFF, val);
477 	val = RD1(sc, HDMI_VP_CONF);
482 	WR1(sc, HDMI_VP_CONF, val);
484 	val = RD1(sc, HDMI_VP_STUFF);
487 	WR1(sc, HDMI_VP_STUFF, val);
489 	WR1(sc, HDMI_VP_REMAP, remap_size);
492 		val = RD1(sc, HDMI_VP_CONF);
499 		WR1(sc, HDMI_VP_CONF, val);
501 		val = RD1(sc, HDMI_VP_CONF);
508 		WR1(sc, HDMI_VP_CONF, val);
510 		val = RD1(sc, HDMI_VP_CONF);
517 		WR1(sc, HDMI_VP_CONF, val);
522 	val = RD1(sc, HDMI_VP_STUFF);
527 	WR1(sc, HDMI_VP_STUFF, val);
529 	val = RD1(sc, HDMI_VP_CONF);
532 	WR1(sc, HDMI_VP_CONF, val);
536 imx_hdmi_video_sample(struct imx_hdmi_softc *sc)
545 	WR1(sc, HDMI_TX_INVID0, val);
551 	WR1(sc, HDMI_TX_INSTUFFING, val);
552 	WR1(sc, HDMI_TX_GYDATA0, 0x0);
553 	WR1(sc, HDMI_TX_GYDATA1, 0x0);
554 	WR1(sc, HDMI_TX_RCRDATA0, 0x0);
555 	WR1(sc, HDMI_TX_RCRDATA1, 0x0);
556 	WR1(sc, HDMI_TX_BCBDATA0, 0x0);
557 	WR1(sc, HDMI_TX_BCBDATA1, 0x0);
561 imx_hdmi_set_mode(struct imx_hdmi_softc *sc)
564 	imx_hdmi_disable_overflow_interrupts(sc);
565 	imx_hdmi_av_composer(sc);
566 	imx_hdmi_phy_init(sc);
567 	imx_hdmi_enable_video_path(sc);
569 	imx_hdmi_video_packetize(sc);
570 	/* TODO:  imx_hdmi_video_csc(sc); */
571 	imx_hdmi_video_sample(sc);
572 	imx_hdmi_clear_overflow(sc);
578 hdmi_edid_read(struct imx_hdmi_softc *sc, uint8_t **edid, uint32_t *edid_len)
591 	if (sc->sc_i2c_xref == 0)
594 	i2c_dev = OF_device_from_xref(sc->sc_i2c_xref);
596 		device_printf(sc->sc_dev,
597 		    "no actual device for \"ddc-i2c-bus\" property (handle=%x)\n", sc->sc_i2c_xref);
601 	device_printf(sc->sc_dev, "reading EDID from %s, addr %02x\n",
606 	msg[1].buf = sc->sc_edid;
608 	result = iicbus_request_bus(i2c_dev, sc->sc_dev, IIC_INTRWAIT);
611 		device_printf(sc->sc_dev, "failed to request i2c bus: %d\n", result);
616 	iicbus_release_bus(i2c_dev, sc->sc_dev);
619 		device_printf(sc->sc_dev, "i2c transfer failed: %d\n", result);
622 		*edid_len = sc->sc_edid_len;
623 		*edid = sc->sc_edid;
649 	struct imx_hdmi_softc *sc;
651 	sc = device_get_softc((device_t)dev);
653 	if (OF_device_from_xref(sc->sc_i2c_xref) != NULL) {
654 		if (sc->eh_tag != NULL) {
656 			    sc->eh_tag);
658 		WR1(sc, HDMI_PHY_POL0, HDMI_PHY_HPD);
659 		WR1(sc, HDMI_IH_PHY_STAT0, HDMI_IH_PHY_STAT0_HPD);
660 		if ((RD1(sc, HDMI_IH_PHY_STAT0) & HDMI_IH_PHY_STAT0_HPD) != 0) {
661 			EVENTHANDLER_INVOKE(hdmi_event, sc->sc_dev,
670 	if (sc->eh_tag == NULL) {
671 		sc->eh_tag = EVENTHANDLER_REGISTER(device_attach,
679 	struct imx_hdmi_softc *sc;
681 	sc = device_get_softc(dev);
683 	if (sc->sc_mem_res != NULL)
685 		    sc->sc_mem_rid, sc->sc_mem_res);
693 	struct imx_hdmi_softc *sc;
698 	sc = device_get_softc(dev);
699 	sc->sc_dev = dev;
703 	sc->sc_mem_rid = 0;
704 	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_mem_rid,
706 	if (sc->sc_mem_res == NULL) {
714 		sc->sc_i2c_xref = 0;
716 		sc->sc_i2c_xref = i2c_xref;
718 	sc->sc_edid = malloc(EDID_LENGTH, M_DEVBUF, M_WAITOK | M_ZERO);
719 	sc->sc_edid_len = EDID_LENGTH;
723 	device_printf(sc->sc_dev, "HDMI controller %02x:%02x:%02x:%02x\n",
724 	    RD1(sc, HDMI_DESIGN_ID), RD1(sc, HDMI_REVISION_ID),
725 	    RD1(sc, HDMI_PRODUCT_ID0), RD1(sc, HDMI_PRODUCT_ID1));
766 	struct imx_hdmi_softc *sc;
768 	sc = device_get_softc(dev);
769 	memcpy(&sc->sc_mode, mode, sizeof(*mode));
770 	imx_hdmi_set_mode(sc);