Lines Matching refs:clk
139 struct at91_pmc_clock *clk;
142 clk = at91_pmc_clock_ref("udpck");
143 clk->pmc_mask = PMC_SCER_UDP_SAM9;
144 at91_pmc_clock_deref(clk);
147 clk = at91_pmc_clock_ref("uhpck");
148 clk->pmc_mask = PMC_SCER_UHP_SAM9;
149 at91_pmc_clock_deref(clk);
152 clk = at91_pmc_clock_ref("plla");
153 clk->pll_min_in = SAM9X25_PLL_A_MIN_IN_FREQ; /* 2 MHz */
154 clk->pll_max_in = SAM9X25_PLL_A_MAX_IN_FREQ; /* 32 MHz */
155 clk->pll_min_out = SAM9X25_PLL_A_MIN_OUT_FREQ; /* 400 MHz */
156 clk->pll_max_out = SAM9X25_PLL_A_MAX_OUT_FREQ; /* 800 MHz */
157 clk->pll_mul_shift = SAM9X25_PLL_A_MUL_SHIFT;
158 clk->pll_mul_mask = SAM9X25_PLL_A_MUL_MASK;
159 clk->pll_div_shift = SAM9X25_PLL_A_DIV_SHIFT;
160 clk->pll_div_mask = SAM9X25_PLL_A_DIV_MASK;
161 clk->set_outb = at91_pmc_800mhz_plla_outb;
162 at91_pmc_clock_deref(clk);
164 clk = at91_pmc_clock_ref("pllb");
165 clk->pll_min_in = SAM9X25_PLL_B_MIN_IN_FREQ; /* 2 MHz */
166 clk->pll_max_in = SAM9X25_PLL_B_MAX_IN_FREQ; /* 32 MHz */
167 clk->pll_min_out = SAM9X25_PLL_B_MIN_OUT_FREQ; /* 30 MHz */
168 clk->pll_max_out = SAM9X25_PLL_B_MAX_OUT_FREQ; /* 100 MHz */
169 clk->pll_mul_shift = SAM9X25_PLL_B_MUL_SHIFT;
170 clk->pll_mul_mask = SAM9X25_PLL_B_MUL_MASK;
171 clk->pll_div_shift = SAM9X25_PLL_B_DIV_SHIFT;
172 clk->pll_div_mask = SAM9X25_PLL_B_DIV_MASK;
173 clk->set_outb = at91_pmc_800mhz_pllb_outb;
174 at91_pmc_clock_deref(clk);