Lines Matching defs:clk
139 struct at91_pmc_clock *clk;
142 clk = at91_pmc_clock_ref("uhpck");
143 clk->pmc_mask = PMC_SCER_UHP_SAM9;
144 at91_pmc_clock_deref(clk);
147 clk = at91_pmc_clock_ref("plla");
148 clk->pll_min_in = SAM9G45_PLL_A_MIN_IN_FREQ; /* 2 MHz */
149 clk->pll_max_in = SAM9G45_PLL_A_MAX_IN_FREQ; /* 32 MHz */
150 clk->pll_min_out = SAM9G45_PLL_A_MIN_OUT_FREQ; /* 400 MHz */
151 clk->pll_max_out = SAM9G45_PLL_A_MAX_OUT_FREQ; /* 800 MHz */
152 clk->pll_mul_shift = SAM9G45_PLL_A_MUL_SHIFT;
153 clk->pll_mul_mask = SAM9G45_PLL_A_MUL_MASK;
154 clk->pll_div_shift = SAM9G45_PLL_A_DIV_SHIFT;
155 clk->pll_div_mask = SAM9G45_PLL_A_DIV_MASK;
156 clk->set_outb = at91_pmc_800mhz_plla_outb;
157 at91_pmc_clock_deref(clk);