Lines Matching defs:clk
135 struct at91_pmc_clock *clk;
138 clk = at91_pmc_clock_ref("udpck");
139 clk->pmc_mask = PMC_SCER_UDP_SAM9;
140 at91_pmc_clock_deref(clk);
143 clk = at91_pmc_clock_ref("uhpck");
144 clk->pmc_mask = PMC_SCER_UHP_SAM9;
145 at91_pmc_clock_deref(clk);
148 clk = at91_pmc_clock_ref("plla");
149 clk->pll_min_in = SAM9G20_PLL_A_MIN_IN_FREQ; /* 2 MHz */
150 clk->pll_max_in = SAM9G20_PLL_A_MAX_IN_FREQ; /* 32 MHz */
151 clk->pll_min_out = SAM9G20_PLL_A_MIN_OUT_FREQ; /* 400 MHz */
152 clk->pll_max_out = SAM9G20_PLL_A_MAX_OUT_FREQ; /* 800 MHz */
153 clk->pll_mul_shift = SAM9G20_PLL_A_MUL_SHIFT;
154 clk->pll_mul_mask = SAM9G20_PLL_A_MUL_MASK;
155 clk->pll_div_shift = SAM9G20_PLL_A_DIV_SHIFT;
156 clk->pll_div_mask = SAM9G20_PLL_A_DIV_MASK;
157 clk->set_outb = at91_pmc_800mhz_plla_outb;
158 at91_pmc_clock_deref(clk);
160 clk = at91_pmc_clock_ref("pllb");
161 clk->pll_min_in = SAM9G20_PLL_B_MIN_IN_FREQ; /* 2 MHz */
162 clk->pll_max_in = SAM9G20_PLL_B_MAX_IN_FREQ; /* 32 MHz */
163 clk->pll_min_out = SAM9G20_PLL_B_MIN_OUT_FREQ; /* 30 MHz */
164 clk->pll_max_out = SAM9G20_PLL_B_MAX_OUT_FREQ; /* 100 MHz */
165 clk->pll_mul_shift = SAM9G20_PLL_B_MUL_SHIFT;
166 clk->pll_mul_mask = SAM9G20_PLL_B_MUL_MASK;
167 clk->pll_div_shift = SAM9G20_PLL_B_DIV_SHIFT;
168 clk->pll_div_mask = SAM9G20_PLL_B_DIV_MASK;
169 clk->set_outb = at91_pmc_800mhz_pllb_outb;
170 at91_pmc_clock_deref(clk);