Lines Matching defs:clk
161 struct at91_pmc_clock *clk;
164 clk = at91_pmc_clock_ref("udpck");
165 clk->pmc_mask = PMC_SCER_UDP;
166 at91_pmc_clock_deref(clk);
169 clk = at91_pmc_clock_ref("uhpck");
170 clk->pmc_mask = PMC_SCER_UHP;
171 at91_pmc_clock_deref(clk);
174 clk = at91_pmc_clock_ref("plla");
175 clk->pll_min_in = RM9200_PLL_A_MIN_IN_FREQ; /* 1 MHz */
176 clk->pll_max_in = RM9200_PLL_A_MAX_IN_FREQ; /* 32 MHz */
177 clk->pll_min_out = RM9200_PLL_A_MIN_OUT_FREQ; /* 80 MHz */
178 clk->pll_max_out = RM9200_PLL_A_MAX_OUT_FREQ; /* 180 MHz */
179 clk->pll_mul_shift = RM9200_PLL_A_MUL_SHIFT;
180 clk->pll_mul_mask = RM9200_PLL_A_MUL_MASK;
181 clk->pll_div_shift = RM9200_PLL_A_DIV_SHIFT;
182 clk->pll_div_mask = RM9200_PLL_A_DIV_MASK;
183 clk->set_outb = at91_pll_outb;
184 at91_pmc_clock_deref(clk);
186 clk = at91_pmc_clock_ref("pllb");
187 clk->pll_min_in = RM9200_PLL_B_MIN_IN_FREQ; /* 100 KHz */
188 clk->pll_max_in = RM9200_PLL_B_MAX_IN_FREQ; /* 32 MHz */
189 clk->pll_min_out = RM9200_PLL_B_MIN_OUT_FREQ; /* 30 MHz */
190 clk->pll_max_out = RM9200_PLL_B_MAX_OUT_FREQ; /* 240 MHz */
191 clk->pll_mul_shift = RM9200_PLL_B_MUL_SHIFT;
192 clk->pll_mul_mask = RM9200_PLL_B_MUL_MASK;
193 clk->pll_div_shift = RM9200_PLL_B_DIV_SHIFT;
194 clk->pll_div_mask = RM9200_PLL_B_DIV_MASK;
195 clk->set_outb = at91_pll_outb;
196 at91_pmc_clock_deref(clk);