arm/at91/at91_pmcreg.h

69 #define PMC_SCER_PCK	(1UL << 0)	/* PCK: Processor Clock Enable */
70 #define PMC_SCER_UDP	(1UL << 1)	/* UDP: USB Device Port Clock Enable */
71 #define PMC_SCER_MCKUDP	(1UL << 2)	/* MCKUDP: Master disable susp/res */
72 #define PMC_SCER_UHP	(1UL << 4)	/* UHP: USB Host Port Clock Enable */
73 #define PMC_SCER_PCK0	(1UL << 8)	/* PCK0: Programmable Clock out en */
74 #define PMC_SCER_PCK1	(1UL << 9)	/* PCK1: Programmable Clock out en */
75 #define PMC_SCER_PCK2	(1UL << 10)	/* PCK2: Programmable Clock out en */
76 #define PMC_SCER_PCK3	(1UL << 11)	/* PCK3: Programmable Clock out en */
77 #define PMC_SCER_UHP_SAM9 (1UL << 6)	/* UHP: USB Host Port Clock Enable */
78 #define PMC_SCER_UDP_SAM9 (1UL << 7)	/* UDP: USB Device Port Clock Enable */
86 #define	CKGR_UCKR_BIASEN	(1UL << 24)
87 #define	CKGR_UCKR_UPLLEN	(1UL << 16)
90 #define CKGR_MOR_MOSCEN	(1UL << 0)	/* MOSCEN: Main Oscillator Enable */
91 #define CKGR_MOR_OSCBYPASS (1UL << 1)	/* Oscillator Bypass */
95 #define CKGR_MCFR_MAINRDY	(1UL << 16)	/* Main Clock Ready */
113 #define PMC_IER_MOSCS	(1UL << 0)	/* Main Oscillator Status */
114 #define PMC_IER_LOCKA	(1UL << 1)	/* PLL A Locked */
115 #define PMC_IER_LOCKB	(1UL << 2)	/* PLL B Locked */
116 #define PMC_IER_MCKRDY	(1UL << 3)	/* Master Clock Status */
117 #define	PMC_IER_LOCKU	(1UL << 6)	/* UPLL Locked */
118 #define PMC_IER_PCK0RDY	(1UL << 8)	/* Programmable Clock 0 Ready */
119 #define PMC_IER_PCK1RDY	(1UL << 9)	/* Programmable Clock 1 Ready */
120 #define PMC_IER_PCK2RDY	(1UL << 10)	/* Programmable Clock 2 Ready */
121 #define PMC_IER_PCK3RDY	(1UL << 11)	/* Programmable Clock 3 Ready */