arm/at91/at91_pmc.c

230 at91_pmc_set_pllb_mode(struct at91_pmc_clock *clk, int on)
250 at91_pmc_set_upll_mode(struct at91_pmc_clock *clk, int on)
270 at91_pmc_set_sys_mode(struct at91_pmc_clock *clk, int on)
274 	WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask);
276 		while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) != clk->pmc_mask)
279 		while ((RD4(sc, PMC_SCSR) & clk->pmc_mask) == clk->pmc_mask)
284 at91_pmc_set_periph_mode(struct at91_pmc_clock *clk, int on)
288 	WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask);
290 		while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) != clk->pmc_mask)
293 		while ((RD4(sc, PMC_PCSR) & clk->pmc_mask) == clk->pmc_mask)
301 	struct at91_pmc_clock *clk;
304 	clk = malloc(sizeof(*clk), M_PMC, M_NOWAIT | M_ZERO);
305 	if (clk == NULL)
309 	clk->name = malloc(buflen, M_PMC, M_NOWAIT);
310 	if (clk->name == NULL)
313 	strlcpy(clk->name, name, buflen);
314 	clk->pmc_mask = 1 << irq;
315 	clk->set_mode = &at91_pmc_set_periph_mode;
317 		clk->parent = &mck;
319 		clk->parent = parent;
323 			clock_list[i] = clk;
324 			return (clk);
328 	if (clk != NULL) {
329 		if (clk->name != NULL)
330 			free(clk->name, M_PMC);
331 		free(clk, M_PMC);
341 	struct at91_pmc_clock *clk, *alias_clk;
343 	clk = at91_pmc_clock_ref(name);
344 	if (clk)
345 		alias_clk = at91_pmc_clock_add(alias, 0, clk->parent);
347 	if (clk && alias_clk) {
348 		alias_clk->hz = clk->hz;
349 		alias_clk->pmc_mask = clk->pmc_mask;
350 		alias_clk->set_mode = clk->set_mode;
370 at91_pmc_clock_deref(struct at91_pmc_clock *clk)
372 	if (clk == NULL)
377 at91_pmc_clock_enable(struct at91_pmc_clock *clk)
379 	if (clk == NULL)
383 	if (clk->parent)
384 		at91_pmc_clock_enable(clk->parent);
385 	if (clk->refcnt++ == 0 && clk->set_mode)
386 		clk->set_mode(clk, 1);
390 at91_pmc_clock_disable(struct at91_pmc_clock *clk)
392 	if (clk == NULL)
396 	if (--clk->refcnt == 0 && clk->set_mode)
397 		clk->set_mode(clk, 0);
398 	if (clk->parent)
399 		at91_pmc_clock_disable(clk->parent);
403 at91_pmc_pll_rate(struct at91_pmc_clock *clk, uint32_t reg)
407 	freq = clk->parent->hz;
408 	div = (reg >> clk->pll_div_shift) & clk->pll_div_mask;
409 	mul = (reg >> clk->pll_mul_shift) & clk->pll_mul_mask;
421 	clk->hz = freq;
427 at91_pmc_pll_calc(struct at91_pmc_clock *clk, uint32_t out_freq)
433 	if (out_freq > clk->pll_max_out)
440 		input = clk->parent->hz / i;
441 		if (input < clk->pll_min_in)
443 		if (input > clk->pll_max_in)
447 		if (mul1 > (clk->pll_mul_mask + 1))
466 	if (clk->set_outb != NULL)
467 		ret |= clk->set_outb(out_freq);
470 		((mul - 1) << clk->pll_mul_shift) |
471 		(div << clk->pll_div_shift));