arm/allwinner/a10_gpio.c

188 	uint32_t bank, func, offset;
195 	bank = sc->padconf->pins[pin].port;
199 	func = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3));
207 	uint32_t bank, data, offset;
216 	bank = sc->padconf->pins[pin].port;
220 	data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3));
223 	A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, pin >> 3), data);
231 	uint32_t bank, offset, val;
236 	bank = sc->padconf->pins[pin].port;
240 	val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4));
248 	uint32_t bank, offset, val;
253 	bank = sc->padconf->pins[pin].port;
257 	val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4));
260 	A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pin >> 4), val);
266 	uint32_t bank, offset, val;
271 	bank = sc->padconf->pins[pin].port;
275 	val = A10_GPIO_READ(sc, A10_GPIO_GP_DRV(bank, pin >> 4));
283 	uint32_t bank, offset, val;
288 	bank = sc->padconf->pins[pin].port;
292 	val = A10_GPIO_READ(sc, A10_GPIO_GP_DRV(bank, pin >> 4));
295 	A10_GPIO_WRITE(sc, A10_GPIO_GP_DRV(bank, pin >> 4), val);
458 	uint32_t bank, data;
464 	bank = sc->padconf->pins[pin].port;
468 	data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
473 	A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
483 	uint32_t bank, reg_data;
489 	bank = sc->padconf->pins[pin].port;
493 	reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
504 	uint32_t bank, data;
510 	bank = sc->padconf->pins[pin].port;
514 	data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
519 	A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
530 	uint32_t bank, data, pin;
537 	 * We require that first_pin refers to the first pin in a bank, because
542 	bank = sc->padconf->pins[first_pin].port;
548 	data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
550 		A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank),
565 	uint32_t bank, pin;
572 	bank = sc->padconf->pins[first_pin].port;
577 	 * The configuration for a bank of pins is scattered among several
803 	/* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */