arm/allwinner/a10_dmac.c

89 #define	DMACH_READ(ch, reg)		\
90     DMA_READ((ch)->ch_sc, (reg) + (ch)->ch_regoff)
91 #define	DMACH_WRITE(ch, reg, val)	\
92     DMA_WRITE((ch)->ch_sc, (reg) + (ch)->ch_regoff, (val))
212 a10dmac_read_ctl(struct a10dmac_channel *ch)
214 	if (ch->ch_type == CH_NDMA) {
215 		return (DMACH_READ(ch, AWIN_NDMA_CTL_REG));
217 		return (DMACH_READ(ch, AWIN_DDMA_CTL_REG));
222 a10dmac_write_ctl(struct a10dmac_channel *ch, uint32_t val)
224 	if (ch->ch_type == CH_NDMA) {
225 		DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val);
227 		DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val);
234 	struct a10dmac_channel *ch = priv;
299 	if (ch->ch_type == CH_NDMA) {
305 		DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val);
315 		DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val);
322 		DMACH_WRITE(ch, AWIN_DDMA_PARA_REG,
337 	struct a10dmac_channel *ch = NULL;
352 			ch = &ch_list[index];
353 			ch->ch_callback = cb;
354 			ch->ch_callbackarg = cbarg;
357 			if (ch->ch_type == CH_NDMA)
368 	return (ch);
374 	struct a10dmac_channel *ch = priv;
375 	struct a10dmac_softc *sc = ch->ch_sc;
381 	cfg = a10dmac_read_ctl(ch);
382 	if (ch->ch_type == CH_NDMA) {
383 		sta = AWIN_DMA_IRQ_NDMA_END(ch->ch_index);
386 		sta = AWIN_DMA_IRQ_DDMA_END(ch->ch_index);
390 	a10dmac_write_ctl(ch, cfg);
394 	ch->ch_callback = NULL;
395 	ch->ch_callbackarg = NULL;
404 	struct a10dmac_channel *ch = priv;
407 	cfg = a10dmac_read_ctl(ch);
408 	if (ch->ch_type == CH_NDMA) {
412 		DMACH_WRITE(ch, AWIN_NDMA_SRC_ADDR_REG, src);
413 		DMACH_WRITE(ch, AWIN_NDMA_DEST_ADDR_REG, dst);
414 		DMACH_WRITE(ch, AWIN_NDMA_BC_REG, nbytes);
417 		a10dmac_write_ctl(ch, cfg);
422 		DMACH_WRITE(ch, AWIN_DDMA_SRC_START_ADDR_REG, src);
423 		DMACH_WRITE(ch, AWIN_DDMA_DEST_START_ADDR_REG, dst);
424 		DMACH_WRITE(ch, AWIN_DDMA_BC_REG, nbytes);
427 		a10dmac_write_ctl(ch, cfg);
436 	struct a10dmac_channel *ch = priv;
439 	cfg = a10dmac_read_ctl(ch);
440 	if (ch->ch_type == CH_NDMA) {
445 	a10dmac_write_ctl(ch, cfg);