Lines Matching refs:vcpu
289 static int vmx_getdesc(void *arg, int vcpu, int reg, struct seg_desc *desc);
290 static int vmx_getreg(void *arg, int vcpu, int reg, uint64_t *retval);
510 * Allocate a unique VPID for each vcpu from the unit number allocator.
1023 panic("vmx_vminit: vmclear error %d on vcpu %d\n",
1112 vmx_handle_cpuid(struct vm *vm, int vcpu, struct vmxctx *vmxctx)
1118 handled = x86_emulate_cpuid(vm, vcpu,
1127 vmx_run_trace(struct vmx *vmx, int vcpu)
1130 VCPU_CTR1(vmx->vm, vcpu, "Resume execution at %#lx", vmcs_guest_rip());
1135 vmx_exit_trace(struct vmx *vmx, int vcpu, uint64_t rip, uint32_t exit_reason,
1139 VCPU_CTR3(vmx->vm, vcpu, "%s %s vmexit at 0x%0lx",
1146 vmx_astpending_trace(struct vmx *vmx, int vcpu, uint64_t rip)
1149 VCPU_CTR1(vmx->vm, vcpu, "astpending vmexit at 0x%0lx", rip);
1160 vmx_invvpid(struct vmx *vmx, int vcpu, pmap_t pmap, int running)
1165 vmxstate = &vmx->state[vcpu];
1173 * This will invalidate TLB entries tagged with the vcpu's
1180 KASSERT(curthread->td_critnest > 0, ("%s: vcpu %d running outside "
1181 "critical section", __func__, vcpu));
1186 * We do this because this vcpu was executing on a different host
1193 * move the thread associated with this vcpu between host cpus.
1204 vmm_stat_incr(vmx->vm, vcpu, VCPU_INVVPID_DONE, 1);
1212 vmm_stat_incr(vmx->vm, vcpu, VCPU_INVVPID_SAVED, 1);
1217 vmx_set_pcpu_defaults(struct vmx *vmx, int vcpu, pmap_t pmap)
1221 vmxstate = &vmx->state[vcpu];
1227 vmm_stat_incr(vmx->vm, vcpu, VCPU_MIGRATIONS, 1);
1232 vmx_invvpid(vmx, vcpu, pmap, 1);
1241 vmx_set_int_window_exiting(struct vmx *vmx, int vcpu)
1244 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) == 0) {
1245 vmx->cap[vcpu].proc_ctls |= PROCBASED_INT_WINDOW_EXITING;
1246 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
1247 VCPU_CTR0(vmx->vm, vcpu, "Enabling interrupt window exiting");
1252 vmx_clear_int_window_exiting(struct vmx *vmx, int vcpu)
1255 KASSERT((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0,
1256 ("intr_window_exiting not set: %#x", vmx->cap[vcpu].proc_ctls));
1257 vmx->cap[vcpu].proc_ctls &= ~PROCBASED_INT_WINDOW_EXITING;
1258 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
1259 VCPU_CTR0(vmx->vm, vcpu, "Disabling interrupt window exiting");
1263 vmx_set_nmi_window_exiting(struct vmx *vmx, int vcpu)
1266 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_NMI_WINDOW_EXITING) == 0) {
1267 vmx->cap[vcpu].proc_ctls |= PROCBASED_NMI_WINDOW_EXITING;
1268 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
1269 VCPU_CTR0(vmx->vm, vcpu, "Enabling NMI window exiting");
1274 vmx_clear_nmi_window_exiting(struct vmx *vmx, int vcpu)
1277 KASSERT((vmx->cap[vcpu].proc_ctls & PROCBASED_NMI_WINDOW_EXITING) != 0,
1278 ("nmi_window_exiting not set %#x", vmx->cap[vcpu].proc_ctls));
1279 vmx->cap[vcpu].proc_ctls &= ~PROCBASED_NMI_WINDOW_EXITING;
1280 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
1281 VCPU_CTR0(vmx->vm, vcpu, "Disabling NMI window exiting");
1285 vmx_set_tsc_offset(struct vmx *vmx, int vcpu, uint64_t offset)
1289 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_TSC_OFFSET) == 0) {
1290 vmx->cap[vcpu].proc_ctls |= PROCBASED_TSC_OFFSET;
1291 vmcs_write(VMCS_PRI_PROC_BASED_CTLS, vmx->cap[vcpu].proc_ctls);
1292 VCPU_CTR0(vmx->vm, vcpu, "Enabling TSC offsetting");
1306 vmx_inject_nmi(struct vmx *vmx, int vcpu)
1325 VCPU_CTR0(vmx->vm, vcpu, "Injecting vNMI");
1328 vm_nmi_clear(vmx->vm, vcpu);
1332 vmx_inject_interrupts(struct vmx *vmx, int vcpu, struct vlapic *vlapic,
1339 if (vmx->state[vcpu].nextrip != guestrip) {
1342 VCPU_CTR2(vmx->vm, vcpu, "Guest interrupt blocking "
1344 vmx->state[vcpu].nextrip, guestrip);
1350 if (vm_entry_intinfo(vmx->vm, vcpu, &entryinfo)) {
1375 if (vm_nmi_pending(vmx->vm, vcpu)) {
1392 vmx_inject_nmi(vmx, vcpu);
1395 VCPU_CTR1(vmx->vm, vcpu, "Cannot inject NMI "
1399 VCPU_CTR1(vmx->vm, vcpu, "Cannot inject NMI due to "
1404 vmx_set_nmi_window_exiting(vmx, vcpu);
1407 extint_pending = vm_extint_pending(vmx->vm, vcpu);
1419 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_INT_WINDOW_EXITING) != 0) {
1420 VCPU_CTR0(vmx->vm, vcpu, "Skip interrupt injection due to "
1455 VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to "
1462 VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to "
1476 VCPU_CTR2(vmx->vm, vcpu, "Cannot inject vector %d due to "
1490 vm_extint_clear(vmx->vm, vcpu);
1504 vmx_set_int_window_exiting(vmx, vcpu);
1507 VCPU_CTR1(vmx->vm, vcpu, "Injecting hwintr at vector %d", vector);
1516 vmx_set_int_window_exiting(vmx, vcpu);
1561 vmx_emulate_xsetbv(struct vmx *vmx, int vcpu, struct vm_exit *vmexit)
1567 vmxctx = &vmx->ctx[vcpu];
1578 vm_inject_gp(vmx->vm, vcpu);
1584 vm_inject_ud(vmx->vm, vcpu);
1590 vm_inject_gp(vmx->vm, vcpu);
1595 vm_inject_gp(vmx->vm, vcpu);
1602 vm_inject_gp(vmx->vm, vcpu);
1613 vm_inject_gp(vmx->vm, vcpu);
1623 vm_inject_gp(vmx->vm, vcpu);
1637 vmx_get_guest_reg(struct vmx *vmx, int vcpu, int ident)
1641 vmxctx = &vmx->ctx[vcpu];
1682 vmx_set_guest_reg(struct vmx *vmx, int vcpu, int ident, uint64_t regval)
1686 vmxctx = &vmx->ctx[vcpu];
1743 vmx_emulate_cr0_access(struct vmx *vmx, int vcpu, uint64_t exitqual)
1751 regval = vmx_get_guest_reg(vmx, vcpu, (exitqual >> 8) & 0xf);
1781 vmx_emulate_cr4_access(struct vmx *vmx, int vcpu, uint64_t exitqual)
1789 regval = vmx_get_guest_reg(vmx, vcpu, (exitqual >> 8) & 0xf);
1801 vmx_emulate_cr8_access(struct vmx *vmx, int vcpu, uint64_t exitqual)
1812 vlapic = vm_lapic(vmx->vm, vcpu);
1816 vmx_set_guest_reg(vmx, vcpu, regnum, cr8);
1818 cr8 = vmx_get_guest_reg(vmx, vcpu, regnum);
2240 vmx_exit_process(struct vmx *vmx, int vcpu, struct vm_exit *vmexit)
2256 vmxctx = &vmx->ctx[vcpu];
2262 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_COUNT, 1);
2263 SDT_PROBE3(vmm, vmx, exit, entry, vmx, vcpu, vmexit);
2272 VCPU_CTR0(vmx->vm, vcpu, "Handling MCE during VM-entry");
2293 error = vm_exit_intinfo(vmx->vm, vcpu, exitintinfo);
2311 vmx_clear_nmi_blocking(vmx, vcpu);
2313 vmx_assert_nmi_blocking(vmx, vcpu);
2366 SDT_PROBE4(vmm, vmx, exit, taskswitch, vmx, vcpu, vmexit, ts);
2367 VCPU_CTR4(vmx->vm, vcpu, "task switch reason %d, tss 0x%04x, "
2373 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_CR_ACCESS, 1);
2374 SDT_PROBE4(vmm, vmx, exit, craccess, vmx, vcpu, vmexit, qual);
2377 handled = vmx_emulate_cr0_access(vmx, vcpu, qual);
2380 handled = vmx_emulate_cr4_access(vmx, vcpu, qual);
2383 handled = vmx_emulate_cr8_access(vmx, vcpu, qual);
2388 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_RDMSR, 1);
2391 VCPU_CTR1(vmx->vm, vcpu, "rdmsr 0x%08x", ecx);
2392 SDT_PROBE4(vmm, vmx, exit, rdmsr, vmx, vcpu, vmexit, ecx);
2393 error = emulate_rdmsr(vmx, vcpu, ecx, &retu);
2406 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_WRMSR, 1);
2411 VCPU_CTR2(vmx->vm, vcpu, "wrmsr 0x%08x value 0x%016lx",
2413 SDT_PROBE5(vmm, vmx, exit, wrmsr, vmx, vmexit, vcpu, ecx,
2415 error = emulate_wrmsr(vmx, vcpu, ecx,
2430 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_HLT, 1);
2431 SDT_PROBE3(vmm, vmx, exit, halt, vmx, vcpu, vmexit);
2441 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_MTRAP, 1);
2442 SDT_PROBE3(vmm, vmx, exit, mtrap, vmx, vcpu, vmexit);
2447 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_PAUSE, 1);
2448 SDT_PROBE3(vmm, vmx, exit, pause, vmx, vcpu, vmexit);
2452 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_INTR_WINDOW, 1);
2453 SDT_PROBE3(vmm, vmx, exit, intrwindow, vmx, vcpu, vmexit);
2454 vmx_clear_int_window_exiting(vmx, vcpu);
2468 vmx, vcpu, vmexit, intr_info);
2485 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_EXTINT, 1);
2488 SDT_PROBE3(vmm, vmx, exit, nmiwindow, vmx, vcpu, vmexit);
2490 if (vm_nmi_pending(vmx->vm, vcpu))
2491 vmx_inject_nmi(vmx, vcpu);
2492 vmx_clear_nmi_window_exiting(vmx, vcpu);
2493 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_NMI_WINDOW, 1);
2496 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_INOUT, 1);
2511 vis->index = inout_str_index(vmx, vcpu, in);
2512 vis->count = inout_str_count(vmx, vcpu, vis->inout.rep);
2514 inout_str_seginfo(vmx, vcpu, inst_info, in, vis);
2516 SDT_PROBE3(vmm, vmx, exit, inout, vmx, vcpu, vmexit);
2519 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_CPUID, 1);
2520 SDT_PROBE3(vmm, vmx, exit, cpuid, vmx, vcpu, vmexit);
2521 handled = vmx_handle_cpuid(vmx->vm, vcpu, vmxctx);
2524 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_EXCEPTION, 1);
2544 vmx_restore_nmi_blocking(vmx, vcpu);
2557 VCPU_CTR0(vmx->vm, vcpu, "Vectoring to MCE handler");
2583 VCPU_CTR2(vmx->vm, vcpu, "Reflecting exception %d/%#x into "
2586 vmx, vcpu, vmexit, intr_vec, errcode);
2587 error = vm_inject_exception(vmx->vm, vcpu, intr_vec,
2600 if (vm_mem_allocated(vmx->vm, vcpu, gpa) ||
2601 apic_access_fault(vmx, vcpu, gpa)) {
2606 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_NESTED_FAULT, 1);
2608 vmx, vcpu, vmexit, gpa, qual);
2611 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_INST_EMUL, 1);
2613 vmx, vcpu, vmexit, gpa);
2625 vmx_restore_nmi_blocking(vmx, vcpu);
2630 SDT_PROBE3(vmm, vmx, exit, eoi, vmx, vcpu, vmexit);
2634 SDT_PROBE3(vmm, vmx, exit, apicaccess, vmx, vcpu, vmexit);
2635 handled = vmx_handle_apic_access(vmx, vcpu, vmexit);
2643 vlapic = vm_lapic(vmx->vm, vcpu);
2645 vmx, vcpu, vmexit, vlapic);
2646 handled = vmx_handle_apic_write(vmx, vcpu, vlapic, qual);
2649 SDT_PROBE3(vmm, vmx, exit, xsetbv, vmx, vcpu, vmexit);
2650 handled = vmx_emulate_xsetbv(vmx, vcpu, vmexit);
2653 SDT_PROBE3(vmm, vmx, exit, monitor, vmx, vcpu, vmexit);
2657 SDT_PROBE3(vmm, vmx, exit, mwait, vmx, vcpu, vmexit);
2661 vlapic = vm_lapic(vmx->vm, vcpu);
2676 SDT_PROBE3(vmm, vmx, exit, vminsn, vmx, vcpu, vmexit);
2681 vmx, vcpu, vmexit, reason);
2682 vmm_stat_incr(vmx->vm, vcpu, VMEXIT_UNKNOWN, 1);
2719 vmx, vcpu, vmexit, handled);
2847 vmx_run(void *arg, int vcpu, register_t rip, pmap_t pmap,
2863 vmcs = &vmx->vmcs[vcpu];
2864 vmxctx = &vmx->ctx[vcpu];
2865 vlapic = vm_lapic(vm, vcpu);
2866 vmexit = vm_exitinfo(vm, vcpu);
2872 vmx_msr_guest_enter(vmx, vcpu);
2887 vmx_set_pcpu_defaults(vmx, vcpu, pmap);
2912 vmx_inject_interrupts(vmx, vcpu, vlapic, rip);
2915 * Check for vcpu suspension after injecting events because
2916 * vmx_inject_interrupts() can suspend the vcpu due to a
2921 vm_exit_suspended(vmx->vm, vcpu, rip);
2927 vm_exit_rendezvous(vmx->vm, vcpu, rip);
2933 vm_exit_reqidle(vmx->vm, vcpu, rip);
2937 if (vcpu_should_yield(vm, vcpu)) {
2939 vm_exit_astpending(vmx->vm, vcpu, rip);
2940 vmx_astpending_trace(vmx, vcpu, rip);
2950 if ((vmx->cap[vcpu].proc_ctls & PROCBASED_USE_TPR_SHADOW) != 0) {
2971 vmx_run_trace(vmx, vcpu);
2987 vmx->state[vcpu].nextrip = rip;
2990 vmx_exit_handle_nmi(vmx, vcpu, vmexit);
2992 handled = vmx_exit_process(vmx, vcpu, vmexit);
2998 vmx_exit_trace(vmx, vcpu, rip, exit_reason, handled);
3013 vmm_stat_incr(vm, vcpu, VMEXIT_USERSPACE, 1);
3015 VCPU_CTR1(vm, vcpu, "returning from vmx_run: exitcode %d",
3019 vmx_msr_guest_exit(vmx, vcpu);
3121 vmx_get_intr_shadow(struct vmx *vmx, int vcpu, int running, uint64_t *retval)
3126 error = vmcs_getreg(&vmx->vmcs[vcpu], running,
3133 vmx_modify_intr_shadow(struct vmx *vmx, int vcpu, int running, uint64_t val)
3140 * Forcing the vcpu into an interrupt shadow is not supported.
3147 vmcs = &vmx->vmcs[vcpu];
3155 VCPU_CTR2(vmx->vm, vcpu, "Setting intr_shadow to %#lx %s", val,
3182 vmx_getreg(void *arg, int vcpu, int reg, uint64_t *retval)
3187 running = vcpu_is_running(vmx->vm, vcpu, &hostcpu);
3189 panic("vmx_getreg: %s%d is running", vm_name(vmx->vm), vcpu);
3192 return (vmx_get_intr_shadow(vmx, vcpu, running, retval));
3194 if (vmxctx_getreg(&vmx->ctx[vcpu], reg, retval) == 0)
3197 return (vmcs_getreg(&vmx->vmcs[vcpu], running, reg, retval));
3201 vmx_setreg(void *arg, int vcpu, int reg, uint64_t val)
3208 running = vcpu_is_running(vmx->vm, vcpu, &hostcpu);
3210 panic("vmx_setreg: %s%d is running", vm_name(vmx->vm), vcpu);
3213 return (vmx_modify_intr_shadow(vmx, vcpu, running, val));
3215 if (vmxctx_setreg(&vmx->ctx[vcpu], reg, val) == 0)
3222 error = vmcs_setreg(&vmx->vmcs[vcpu], running, reg, val);
3232 vmcs_getreg(&vmx->vmcs[vcpu], running,
3238 vmcs_setreg(&vmx->vmcs[vcpu], running,
3247 error = vmcs_setreg(&vmx->vmcs[vcpu], running,
3253 * Invalidate the guest vcpu's TLB mappings to emulate
3259 pmap = vmx->ctx[vcpu].pmap;
3260 vmx_invvpid(vmx, vcpu, pmap, running);
3268 vmx_getdesc(void *arg, int vcpu, int reg, struct seg_desc *desc)
3273 running = vcpu_is_running(vmx->vm, vcpu, &hostcpu);
3275 panic("vmx_getdesc: %s%d is running", vm_name(vmx->vm), vcpu);
3277 return (vmcs_getdesc(&vmx->vmcs[vcpu], running, reg, desc));
3281 vmx_setdesc(void *arg, int vcpu, int reg, struct seg_desc *desc)
3286 running = vcpu_is_running(vmx->vm, vcpu, &hostcpu);
3288 panic("vmx_setdesc: %s%d is running", vm_name(vmx->vm), vcpu);
3290 return (vmcs_setdesc(&vmx->vmcs[vcpu], running, reg, desc));
3294 vmx_getcap(void *arg, int vcpu, int type, int *retval)
3302 vcap = vmx->cap[vcpu].set;
3336 vmx_setcap(void *arg, int vcpu, int type, int val)
3339 struct vmcs *vmcs = &vmx->vmcs[vcpu];
3354 pptr = &vmx->cap[vcpu].proc_ctls;
3363 pptr = &vmx->cap[vcpu].proc_ctls;
3372 pptr = &vmx->cap[vcpu].proc_ctls;
3381 pptr = &vmx->cap[vcpu].proc_ctls2;
3390 pptr = &vmx->cap[vcpu].proc_ctls2;
3422 vmx->cap[vcpu].set |= (1 << type);
3424 vmx->cap[vcpu].set &= ~(1 << type);
3470 * modified if the vcpu is running.
3615 ("vmx_set_tmr: vcpu cannot be running"));
3690 * once in the context of vcpu 0.