Lines Matching refs:i16
339 case MVT::i16:
509 case MVT::i16: Opc = X86::MOV16mr; break;
674 case MVT::i16: Opc = X86::MOV16mi; break;
1226 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
1348 case MVT::i16: return X86::CMP16rr;
1374 case MVT::i16:
1546 case MVT::i16: MovInst = X86::MOVZX32rr16; break;
1559 } else if (DstVT == MVT::i16) {
1560 // i8->i16 doesn't exist in the autogenerated isel table. Need to zero
1566 ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, /*Kill=*/true,
1605 if (DstVT == MVT::i16) {
1606 // i8->i16 doesn't exist in the autogenerated isel table. Need to sign
1612 ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, /*Kill=*/true,
1718 case MVT::i16: TestOpc = X86::TEST16ri; break;
1850 const static unsigned NumTypes = 4; // i8, i16, i32, i64
1893 }, // i16
1918 case MVT::i16: TypeIndex = 1; break;
1959 if (VT == MVT::i16) {
2021 if (RetVT < MVT::i16 || RetVT > MVT::i64)
2289 case MVT::i16: Opc = X86::CMOV_GR16; break;
2583 VT = MVT::i16;
2645 ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, true, RegIdx);
2649 InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::SIGN_EXTEND, InputReg,
3252 // If this is a constant i1/i8/i16 argument, promote to i32 to avoid an extra
3698 case MVT::i16:
3699 return fastEmitInst_extractsubreg(MVT::i16, SrcReg, /*Kill=*/true,
3720 case MVT::i16: Opc = X86::MOV16ri; break;