Target/SystemZ/SystemZFrameLowering.cpp

1 //===-- SystemZFrameLowering.cpp - Frame lowering for SystemZ -------------===//
27   { SystemZ::R2D,  0x10 },
28   { SystemZ::R3D,  0x18 },
29   { SystemZ::R4D,  0x20 },
30   { SystemZ::R5D,  0x28 },
31   { SystemZ::R6D,  0x30 },
32   { SystemZ::R7D,  0x38 },
33   { SystemZ::R8D,  0x40 },
34   { SystemZ::R9D,  0x48 },
35   { SystemZ::R10D, 0x50 },
36   { SystemZ::R11D, 0x58 },
37   { SystemZ::R12D, 0x60 },
38   { SystemZ::R13D, 0x68 },
39   { SystemZ::R14D, 0x70 },
40   { SystemZ::R15D, 0x78 },
41   { SystemZ::F0D,  0x80 },
42   { SystemZ::F2D,  0x88 },
43   { SystemZ::F4D,  0x90 },
44   { SystemZ::F6D,  0x98 }
52   // Due to the SystemZ ABI, the DWARF CFA (Canonical Frame Address) is not
60   RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
88   unsigned HighGPR = SystemZ::R15D;
96         if (SystemZ::GR64BitRegClass.contains(Reg) && StartSPOffset > Offset) {
115       if (FirstGPR < SystemZ::NumArgGPRs) {
116         unsigned Reg = SystemZ::ArgGPRs[FirstGPR];
131       if (SystemZ::GR64BitRegClass.contains(Reg)) {
187     for (unsigned I = MFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
188       SavedRegs.set(SystemZ::ArgGPRs[I]);
192     SavedRegs.set(SystemZ::R6D);
193     SavedRegs.set(SystemZ::R7D);
199     SavedRegs.set(SystemZ::R11D);
204     SavedRegs.set(SystemZ::R14D);
213     if (SystemZ::GR64BitRegClass.contains(Reg) && SavedRegs.test(Reg)) {
214       SavedRegs.set(SystemZ::R15D);
228   Register GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
252   SystemZ::GPRRegs SpillGPRs = ZFI->getSpillGPRRegs();
258     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
265     MIB.addReg(SystemZ::R15D).addImm(SpillGPRs.GPROffset);
271       if (SystemZ::GR64BitRegClass.contains(Reg))
277       for (unsigned I = ZFI->getVarArgsFirstGPR(); I < SystemZ::NumArgGPRs; ++I)
278         addSavedGPR(MBB, MIB, SystemZ::ArgGPRs[I], true);
284     if (SystemZ::FP64BitRegClass.contains(Reg)) {
287                                &SystemZ::FP64BitRegClass, TRI);
289     if (SystemZ::VR128BitRegClass.contains(Reg)) {
292                                &SystemZ::VR128BitRegClass, TRI);
316     if (SystemZ::FP64BitRegClass.contains(Reg))
318                                 &SystemZ::FP64BitRegClass, TRI);
319     if (SystemZ::VR128BitRegClass.contains(Reg))
321                                 &SystemZ::VR128BitRegClass, TRI);
326   SystemZ::GPRRegs RestoreGPRs = ZFI->getRestoreGPRRegs();
335     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
342     MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
349           SystemZ::GR64BitRegClass.contains(Reg))
400       Opcode = SystemZ::AGHI;
402       Opcode = SystemZ::AGFI;
458     if (MBBI != MBB.end() && MBBI->getOpcode() == SystemZ::STMG)
466       if (SystemZ::GR64BitRegClass.contains(Reg)) {
502       BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR))
503         .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
507     emitIncrement(MBB, MBBI, DL, SystemZ::R15D, Delta, ZII);
517       BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::STG))
518         .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0)
524     BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
525       .addReg(SystemZ::R15D);
528     unsigned HardFP = MRI->getDwarfRegNum(SystemZ::R11D, true);
538       I->addLiveIn(SystemZ::R11D);
545     if (SystemZ::FP64BitRegClass.contains(Reg)) {
547           (MBBI->getOpcode() == SystemZ::STD ||
548            MBBI->getOpcode() == SystemZ::STDY))
552     } else if (SystemZ::VR128BitRegClass.contains(Reg)) {
554           MBBI->getOpcode() == SystemZ::VST)
598     if (Opcode != SystemZ::LMG)
621     emitIncrement(MBB, MBBI, DL, SystemZ::R15D, StackSize, ZII);
655   case SystemZ::ADJCALLSTACKDOWN:
656   case SystemZ::ADJCALLSTACKUP: