RISCV/AsmParser/RISCVAsmParser.cpp

85   void emitToStreamer(MCStreamer &S, const MCInst &Inst);
98   void emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
101   void emitLoadAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
105   void emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
109   void emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
112   void emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
119   bool checkPseudoAddTPRel(MCInst &Inst, OperandVector &Operands);
125   bool processInstruction(MCInst &Inst, SMLoc IDLoc, OperandVector &Operands,
699   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
706       Inst.addOperand(MCOperand::createImm(Imm));
708       Inst.addOperand(MCOperand::createExpr(Expr));
712   void addRegOperands(MCInst &Inst, unsigned N) const {
714     Inst.addOperand(MCOperand::createReg(getReg()));
717   void addImmOperands(MCInst &Inst, unsigned N) const {
719     addExpr(Inst, getImm());
722   void addFenceArgOperands(MCInst &Inst, unsigned N) const {
738     Inst.addOperand(MCOperand::createImm(Imm));
741   void addCSRSystemRegisterOperands(MCInst &Inst, unsigned N) const {
743     Inst.addOperand(MCOperand::createImm(SysReg.Encoding));
757   void addFRMArgOperands(MCInst &Inst, unsigned N) const {
759     Inst.addOperand(MCOperand::createImm(getRoundingMode()));
813   MCInst Inst;
817     MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
823     return processInstruction(Inst, IDLoc, Operands, Out);
1634 void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
1636   bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
1639   S.EmitInstruction((Res ? CInst : Inst), getSTI());
1648   for (RISCVMatInt::Inst &Inst : Seq) {
1649     if (Inst.Opc == RISCV::LUI) {
1651           Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm));
1654           Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm(
1655                    Inst.Imm));
1691 void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
1699   MCOperand DestReg = Inst.getOperand(0);
1700   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
1705 void RISCVAsmParser::emitLoadAddress(MCInst &Inst, SMLoc IDLoc,
1716   MCOperand DestReg = Inst.getOperand(0);
1717   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
1731 void RISCVAsmParser::emitLoadTLSIEAddress(MCInst &Inst, SMLoc IDLoc,
1739   MCOperand DestReg = Inst.getOperand(0);
1740   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
1746 void RISCVAsmParser::emitLoadTLSGDAddress(MCInst &Inst, SMLoc IDLoc,
1754   MCOperand DestReg = Inst.getOperand(0);
1755   const MCExpr *Symbol = Inst.getOperand(1).getExpr();
1760 void RISCVAsmParser::emitLoadStoreSymbol(MCInst &Inst, unsigned Opcode,
1770   MCOperand DestReg = Inst.getOperand(0);
1773   MCOperand TmpReg = Inst.getOperand(TmpRegOpIdx);
1774   const MCExpr *Symbol = Inst.getOperand(SymbolOpIdx).getExpr();
1779 bool RISCVAsmParser::checkPseudoAddTPRel(MCInst &Inst,
1781   assert(Inst.getOpcode() == RISCV::PseudoAddTPRel && "Invalid instruction");
1782   assert(Inst.getOperand(2).isReg() && "Unexpected second operand kind");
1783   if (Inst.getOperand(2).getReg() != RISCV::X4) {
1792 bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
1795   Inst.setLoc(IDLoc);
1797   switch (Inst.getOpcode()) {
1801     Register Reg = Inst.getOperand(0).getReg();
1802     const MCOperand &Op1 = Inst.getOperand(1);
1812     int64_t Imm = Inst.getOperand(1).getImm();
1822     emitLoadLocalAddress(Inst, IDLoc, Out);
1825     emitLoadAddress(Inst, IDLoc, Out);
1828     emitLoadTLSIEAddress(Inst, IDLoc, Out);
1831     emitLoadTLSGDAddress(Inst, IDLoc, Out);
1834     emitLoadStoreSymbol(Inst, RISCV::LB, IDLoc, Out, /*HasTmpReg=*/false);
1837     emitLoadStoreSymbol(Inst, RISCV::LBU, IDLoc, Out, /*HasTmpReg=*/false);
1840     emitLoadStoreSymbol(Inst, RISCV::LH, IDLoc, Out, /*HasTmpReg=*/false);
1843     emitLoadStoreSymbol(Inst, RISCV::LHU, IDLoc, Out, /*HasTmpReg=*/false);
1846     emitLoadStoreSymbol(Inst, RISCV::LW, IDLoc, Out, /*HasTmpReg=*/false);
1849     emitLoadStoreSymbol(Inst, RISCV::LWU, IDLoc, Out, /*HasTmpReg=*/false);
1852     emitLoadStoreSymbol(Inst, RISCV::LD, IDLoc, Out, /*HasTmpReg=*/false);
1855     emitLoadStoreSymbol(Inst, RISCV::FLW, IDLoc, Out, /*HasTmpReg=*/true);
1858     emitLoadStoreSymbol(Inst, RISCV::FLD, IDLoc, Out, /*HasTmpReg=*/true);
1861     emitLoadStoreSymbol(Inst, RISCV::SB, IDLoc, Out, /*HasTmpReg=*/true);
1864     emitLoadStoreSymbol(Inst, RISCV::SH, IDLoc, Out, /*HasTmpReg=*/true);
1867     emitLoadStoreSymbol(Inst, RISCV::SW, IDLoc, Out, /*HasTmpReg=*/true);
1870     emitLoadStoreSymbol(Inst, RISCV::SD, IDLoc, Out, /*HasTmpReg=*/true);
1873     emitLoadStoreSymbol(Inst, RISCV::FSW, IDLoc, Out, /*HasTmpReg=*/true);
1876     emitLoadStoreSymbol(Inst, RISCV::FSD, IDLoc, Out, /*HasTmpReg=*/true);
1879     if (checkPseudoAddTPRel(Inst, Operands))
1884   emitToStreamer(Out, Inst);