Target/NVPTX/NVPTXISelLowering.cpp

377   addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
398                  MVT::i16, MVT::i32, MVT::i64}) {
407   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
429   setOperationAction(ISD::ROTL, MVT::i16, Expand);
430   setOperationAction(ISD::ROTR, MVT::i16, Expand);
433   setOperationAction(ISD::BSWAP, MVT::i16, Expand);
495   for (const auto& Ty : {MVT::i16, MVT::i32, MVT::i64}) {
506   setOperationAction(ISD::CTTZ, MVT::i16, Expand);
1334       // i8 types in IR will be i16 types in SDAG
1336               (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
1486           // size. FP16 is loaded/stored using i16, so it's handled
1529           StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1614         theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1795         EltType = MVT::i16;
2247 // v1 = ld i8* addr (-> i16)
2248 // v = trunc i16 to i1
2256   SDValue newLD = DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
2341     // stored type to i16 and propagate the "real" type as the memory type.
2388           ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
2409 // v1 = zxt v to i16
2410 // st.u8 i16, addr
2419   Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2609             // into an i16 register)
2706       RetVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, RetVal);
4111     Info.memVT = MVT::i16;
4467   // The type legalizer turns a vector load of i8 values into a zextload to i16
4687     DemotedVT = MVT::i16;
4831   // loaded type to i16 and propagate the "real" type as the memory type.
4834     EltVT = MVT::i16;
4938       // loaded type to i16 and propagate the "real" type as the memory type.
4941         EltVT = MVT::i16;
5029       // Force output to i16
5030       SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);